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CN104282558B - Junction-free nanowire FinFET and manufacturing method thereof - Google Patents

Junction-free nanowire FinFET and manufacturing method thereof Download PDF

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CN104282558B
CN104282558B CN201310275445.6A CN201310275445A CN104282558B CN 104282558 B CN104282558 B CN 104282558B CN 201310275445 A CN201310275445 A CN 201310275445A CN 104282558 B CN104282558 B CN 104282558B
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semiconductor substrate
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fin
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CN104282558A (en
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黄新运
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Semiconductor Manufacturing International Shanghai Corp
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H01L29/7854—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection with rounded corners

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Abstract

The invention relates to a junction-free nanowire FinFET semiconductor device and a manufacturing method thereof, wherein the method comprises the following steps: providing a semiconductor substrate; forming an epitaxial layer on the semiconductor substrate; patterning the epitaxial layer and a portion of the semiconductor substrate to form a fin structure and a nanowire structure on the fin structure; a gate structure is formed over the fin structure and the nanowire structure. According to the junction-free nanowire FinFET semiconductor device formed by the invention, when the device is in an open state, the current is larger, when the device is in an off state, the current is smaller, the performance of the junction-free nanowire FinFET semiconductor device is greatly improved, the on-off ratio of the junction-free nanowire FinFET semiconductor device is larger than that of a planar device, the whole process is completely compatible with the prior process, the preparation method of the transistor is suitable for a small-sized semiconductor substrate, and the preparation cost of the transistor is lower than that of a nanowire cylinder full-surrounding gate junction-free field effect transistor, so that the preparation process of the transistor is simpler, and the process cost is reduced at the same time.

Description

Junction-free nanowire FinFET and manufacturing method thereof
Technical Field
The present invention relates to semiconductor manufacturing processes, and more particularly, to a semiconductor device combining a fin field effect transistor (FinFET) and a junction-less nanowire field effect transistor and a method of manufacturing the same.
Background
Integrated Circuits (ICs) have evolved from a small number of interconnected devices fabricated on a single silicon chip to millions of devices. Current ICs offer performance and complexity far beyond original imagination. To achieve improvements in complexity and circuit density (i.e., the number of devices that can be packaged onto a given chip area), the size of the smallest device features, also referred to as the device "geometry," has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features that span less than a quarter of a micron.
With the continuous development of semiconductor technology, the performance of integrated circuits is improved mainly by the continuous reduction of the size of integrated circuit devices to increase the speed thereof. Currently, as the semiconductor industry has progressed to the point of nanotechnology process in pursuit of high device density, high performance, and low cost, the fabrication of semiconductor devices is limited by various physical limits.
Challenges from manufacturing and design aspects as CMOS devices continue to shrink have prompted the development of three-dimensional designs such as fin field effect transistors (finfets). Compared with the existing planar transistor, the FinFET device has more excellent performance in the aspects of channel control, shallow trench effect reduction and the like; a planar gate structure is disposed over the channel, and in finfets the gate is disposed around the fin, thus allowing static control from three sides, with more outstanding performance in static control.
Fig. 1A to 1C show a prior art FinFET forming method, where fig. 1A and 1C are schematic diagrams along a YY 'direction, and fig. 1B is a schematic diagram along an X1X 1' direction, in fig. 1A to 1C, where the YY 'and X1X 1' directions are shown as upper right small diagrams. As shown in fig. 1A-1B, a well 101 is first formed in the semiconductor substrate 100, as shown in fig. 1A, then a semiconductor material layer 102 is formed on the well, the semiconductor material layer is patterned to obtain a fin pattern, a gate structure is formed on the fin pattern, as shown in fig. 1B, then a spacer is formed, ion implantation is performed, and finally an electrical connection is formed. As shown in fig. 1C, which is a schematic structural diagram of a FinTFET device, the FinTFET device includes: a semiconductor substrate 100; a well 101 in the semiconductor substrate 100; a fin 102 located over the well; a gate structure 103 surrounding the fin; the lightly doped source electrode doping area and the lightly doped drain electrode doping area are positioned on two sides of the grid structure and are different from the well doping type; raised source 105 and raised drain 104 of the same doping type located in the lightly doped source doping region and the lightly doped drain doping region. Compared with a planar high-K metal gate structure, the FinFET has more excellent performance which can be improved by 10-20%, but along with the reduction of devices and the improvement of technology, the 10-20% performance improvement is far from enough.
Finfet devices have not met the needs of device development, and the continuous scaling of semiconductor device feature sizes has faced new challenges, as the various processes used in integrated circuit fabrication may have certain limitations. That is, a given process typically only works down to a certain feature size, thus requiring changes to the process or layout of the device.
The nanowire cylinder fully-wrapped-gate junction-free field effect transistor (GAAC JLFET) that has been developed at present can solve the challenges faced by the prior art, such as large doping concentration gradient, low thermal budget, and the like. The nanowire all-around gate junction-free field effect transistor has a larger on-off ratio (lager on-off ratio) compared to a conventional tri-gate (tri-gate) effect transistor. However, the manufacturing cost of the all-around gate junction-free field effect transistor is far higher than that of the traditional gate fin-shaped field effect transistor.
Therefore, the nanowire cylinder fully-surrounding-gate junction-free field effect transistor structure is applied to the multi-gate fin-shaped field effect transistor, so that the problems of the traditional multi-gate fin-shaped field effect transistor are reduced, the performance of the device is improved, the scaling capability is improved, and the manufacturing cost of the device is reduced.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In order to effectively solve the above problems, the present invention provides a method for manufacturing a junction-free nanowire FinFET, comprising: providing a semiconductor substrate; forming an epitaxial layer on the semiconductor substrate; patterning the epitaxial layer and a portion of the semiconductor substrate to form a fin structure and a nanowire structure on the fin structure; a gate structure is formed over the fin structure and the nanowire structure.
Preferably, the material of the epitaxial layer is SiGe or SiC.
Preferably, the thickness of the epitaxial layer is 5-10 nm.
Preferably, the fin structures have a width of less than 8 nm.
Preferably, the doping type of the epitaxial layer is different from the doping type of the fin structure.
Preferably, the epitaxial layer is formed using an in-situ doping process or a shallow junction doping process.
Preferably, a well is formed in the semiconductor substrate.
Preferably, the semiconductor substrate is Si.
Preferably, the gate structure is a high-K metal gate structure.
Preferably, the method further comprises the step of forming shallow trench isolations on the semiconductor substrate on both sides of the fin structure before forming the gate structure.
Preferably, after forming the gate structure, the method further comprises the steps of: performing LDD ion implantation; forming a first gap wall on the side wall of the gate structure; epitaxially growing a first semiconductor material layer to form a raised source drain; forming a second spacer on the first spacer; performing ion implantation, forming source and drain regions on two sides of the grid structure, and performing rapid annealing; and forming a silicide layer on the source and drain regions, and then forming an electrical connection.
Preferably, the first semiconductor material layer is a Si, SiGe or SiC material layer.
Preferably, the method of patterning the epitaxial layer and a portion of the semiconductor substrate comprises: forming a patterned photoresist layer on the epitaxial layer to define patterns of the fin structures and the nanowire structures; etching the epitaxial layer and a part of the semiconductor substrate by taking the photoresist layer as a mask to form the fin structure and the nanowire structure positioned on the fin structure; and removing the photoresist layer.
Preferably, the doping type of the epitaxial layer is the same as that of the source and drain regions.
The invention also provides a junction-free nanowire FinFET semiconductor device, comprising: a semiconductor substrate; a fin structure on the semiconductor substrate and a nanowire structure on the fin structure; a gate structure surrounding the fin structure and the nanowire structure.
Preferably, the material of the nanowire structure is SiGe or SiC.
Preferably, the gate structure is a high-K metal gate structure.
Preferably, the doping type of the nanowire structure is different from the doping type of the fin structure.
In the semiconductor device and the manufacturing method, the junction-free nanowire transistor and the FinFET are combined to form the junction-free nanowire FinFET in the preparation process in order to avoid the problems of high doping concentration gradient, low thermal budget and the like of the transistor in the prior art. According to the transistor formed by the invention, when the device is in an open state, the current is larger, when the device is in an open state, the current is smaller, the performance of the transistor and a FinFET is greatly improved, and the transistor has a larger on-off ratio (large on-off ratio) compared with a planar device, the whole process is completely compatible with the prior process, and the preparation method of the transistor is suitable for a small-sized semiconductor substrate, and the preparation cost of the transistor is lower than that of a nanowire cylinder full-surrounding gate junction-free field effect transistor (GAAC JLFET), so that the preparation process of the transistor is simpler, and the process cost is reduced.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings, there is shown in the drawings,
FIGS. 1A-1C are schematic cross-sectional views of a process for preparing FinTFET according to the prior art;
fig. 2A-2C are schematic cross-sectional views of a process for preparing N-type FinTFET according to an embodiment of the invention;
fig. 3A-3C are schematic cross-sectional views of a process for preparing a P-type FinTFET according to another embodiment of the invention;
FIG. 4 is a process flow diagram for preparing FinTFET according to another embodiment of the invention
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
In order to provide a thorough understanding of the present invention, a detailed description will be given in the following description to illustrate the method for improving particle defects upon thin film deposition according to the present invention. It will be apparent that the invention may be practiced without limitation to specific details that are within the skill of one of ordinary skill in the semiconductor arts. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the invention. As used herein, the singular is intended to include the plural unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Exemplary embodiments according to the present invention will now be described in more detail with reference to the accompanying drawings. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It is to be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity, and the same elements are denoted by the same reference numerals, and thus the description thereof will be omitted.
In order to overcome the defects in the prior art, the preparation processes of the junction-free nanowire transistors (junction-free nanowire transistors) and the fin field effect transistors (FinFETs) are fused, a junction-free nanowire layer is prepared in the process of the fin field effect transistors (FinFETs), and the junction-free nanowire field effect transistors are obtained.
The following detailed description of the embodiments of the present invention will be made with reference to fig. 2A-2C and fig. 3A-3C, wherein fig. 2A-2C are schematic cross-sectional views illustrating the preparation process of N-type FinTFET; fig. 3A-3C are schematic cross-sectional views of the process for preparing P-type FinTFET. In fig. 2A-2C and 3A-3C, fig. 2A, 2C, 3A and 3C are schematic views along the YY ' direction, and fig. 2B and 3B are schematic views along the X1X1 ' direction, wherein the YY, X1X1 ' directions are as shown in the upper right small figure.
In order to overcome the problems in the prior art, the invention provides a preparation method of a junction-free nanowire FinFET semiconductor device, which comprises the following steps:
providing a semiconductor substrate;
depositing and forming an epitaxial layer on the semiconductor substrate;
patterning the epitaxial layer and the semiconductor substrate to form a fin structure and a nanowire structure on the fin structure;
forming a gate structure over the fin structure and the nanowire structure.
The method for manufacturing the semiconductor device according to the present invention will be described in detail with reference to fig. 2A-2C, and the semiconductor device may be an N-type junction-free nanowire finfet in an embodiment of the present invention.
As shown in fig. 2A, a semiconductor substrate 200 is provided, in which a well 201 is formed in the semiconductor substrate 200;
the semiconductor substrate may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. In addition, an active region may be defined on the semiconductor substrate.
In an embodiment of the present invention, a well 201 is formed in the semiconductor substrate, and in an embodiment of the present invention, the substrate is an N-type substrate, and specifically, an N-type substrate commonly used in the art may be selected by a person skilled in the art, and then a P-well is formed in the N-type substrate.
Preferably, the thickness of the semiconductor substrate 200 is 10-100nm, preferably 30-50 nm.
An epitaxial layer 202, which may be SiGe or SiC, is grown on the semiconductor substrate 200. Preferably, the epitaxial layer 202 is SiGe, the thickness of the epitaxial layer 202 is 1-50nm, preferably 5-10nm in a specific embodiment of the present invention, and the Si material layer 200 and the epitaxial layer 202 are not limited to the above numerical range, which is merely exemplary and can be selected by one skilled in the art as needed. Preferably, the content of Ge in the SiGe material layer is 15-45 wt%.
The epitaxial layer 202 may be formed by in-situ doping (in-situ doping) or ultra-shallow junction doping (ultra-shallow junction doping). In a specific embodiment of the present invention, an in-situ doping method is selected to form the SiGe material layer 202, and specifically, when a chemical vapor deposition method or a gas source molecular beam epitaxy method is used to grow N-type silicon, silane or disilane is used as a silicon source, phosphane is used as an N-type doping gas, and a certain amount of germane is added at the same time. For example, GeH is selected4And SiH2Cl2As a reaction gas and selecting H2As the carrier gas, the flow ratio of the reaction gas and the carrier gas is 0.01-0.1, the deposition temperature is 300-1000 ℃, preferably 650-750 ℃, and the gas pressure is 1-50Torr, preferably 20-40 Torr.
In one embodiment of the present invention, the epitaxial growth technique is used to grow the semiconductor substrate at 1000-Forming epitaxial SiC on the bottom, the source gas used in epitaxial growth is SiH4And C3H8Introduction of H during the epitaxy process2，N2As carrier gas, n-type in-situ doping is realized at the same time, the typical growth temperature is 1500-1600 ℃, and then annealing is further carried out at 1600-1700 ℃.
Next, a fin structure and a nanowire structure located on the fin structure are formed on the semiconductor substrate 200, as shown in fig. 2B, the device structure is formed by forming a patterned mask layer, such as a photoresist mask layer, on the epitaxial layer 202, the photoresist mask layer defines the width, length, position, and the like of the fin structure and the nanowire structure, then etching the semiconductor substrate 200 and the epitaxial layer 202 with the photoresist mask layer as a mask, forming a fin structure 203 and a nanowire structure 204 on the semiconductor substrate, where the nanowire structure 204 is formed on the top of the fin structure after the epitaxial layer 202 is etched, and then removing the photoresist mask layer, where the method for removing the photoresist mask layer may be an oxidation ashing method. It is noted that the formation of the fin structures and nanowire structures is merely exemplary and not limited to this method.
In one embodiment of the present invention, the patterned photoresist layer is used as a mask, and CF is introduced4And CHF3Etching a portion of the semiconductor substrate 200 and the epitaxial layer 202 under the etching conditions of (1), wherein the etching pressure: 50-150 mTorr; power: 300-800W; time: 5-15 s; wherein the gas flow rate is as follows: CF (compact flash)4，10-30sccm；CHF310-30sccm, it should be noted that the above etching method is only exemplary and not limited to this method, and those skilled in the art can select other commonly used methods.
In a specific embodiment of the present invention, Si is deposited on the semiconductor substrate as a preferred implementation manner, and lightly doping and P-type doping may be performed while depositing Si, where the doping type is different from the doping type in the source/drain region in the subsequent process, and then a fin is further formed, where the fin is a P-type fin and the lightly doping type of the fin is the same as the doping type of the well. As an example, the epitaxial layer is doped to obtain a uniform and highly doped epitaxial layer, which is doped N-type, but with the same doping type as the fin structure or the silicon substrate, but with the subsequent source/drain regions.
Then, an isolation structure 205 is formed on the semiconductor substrate, for example, a shallow trench isolation or a local oxide layer is formed on the semiconductor substrate, in an embodiment of the present invention, a shallow trench isolation structure is preferably formed, and the formation method of the shallow trench isolation may be a method commonly used in the prior art, for example, first, an oxide layer is deposited on the semiconductor substrate 200, and then the oxide layer is etched back to form a shallow trench isolation structure with a top lower than the fin.
Then, a gate structure 206 is formed on the fin structure, the gate structure 206 surrounds the fin structure and the nanowire structure to form a surrounding gate structure 206, the fin structure and the nanowire structure are located below the gate structure, the nanowire structure is used as a channel after the surrounding gate structure 206 is formed, and the surrounding gate structure 206 has more excellent performance in the aspects of channel control, shallow trench effect reduction and the like compared with the existing planar transistor; a planar gate structure is disposed over the channel, and in finfets the gate is disposed around the fin, thus allowing static control from three sides, with more outstanding performance in static control. Meanwhile, the junction-free nanowire FinFET has a relatively narrow fin structure, in a specific embodiment of the present invention, the width critical dimension of the fin structure is less than 8nm, and the junction-free nanowire layer is a depletion layer as seen from the energy band diagram of the FinFET when the junction-free nanowire FinFET is in an off state.
In a specific embodiment of the present invention, the gate structure 206 is a polysilicon gate structure, and the polysilicon gate structure is formed by first forming a dielectric layer on the fin structure and the nanowire structure, and forming a gate oxide layer on the dielectric layer, preferably, the gate oxide layer is made of silicon dioxide, and can be formed by thermal oxidation.
In the present invention, a polysilicon gate structure is preferably formed, and a method for forming the polysilicon layer may be a Low Pressure Chemical Vapor Deposition (LPCVD) process. The process conditions for forming the polysilicon layer include: the reaction gas is silane (SiH4), and the flow rate of the silane can be 100-200 cubic centimeters per minute (sccm), such as 150 sccm; the temperature in the reaction cavity can be 700-750 ℃; the pressure in the reaction chamber can be 250 to 350 milli-millimeter mercury (mTorr), such as 300 mTorr; the reaction gas may further include a buffer gas, the buffer gas may be helium (He) or nitrogen, and the flow rate of the helium and the nitrogen may range from 5 to 20 liters per minute (slm), such as 8slm, 10slm, or 15 slm.
And then patterning to form a polysilicon gate structure 206 on the fin structure and the nanowire structure, wherein the patterning method comprises first forming a patterned photoresist layer, etching the polysilicon layer and the gate oxide layer by using the photoresist layer as a mask, and finally ashing to remove the photoresist layer, but the patterning method of the polysilicon gate structure is not limited to the above example.
Preferably, in order to further improve the performance of the device, the gate structure 206 is a metal gate structure or a high-K metal gate structure, and in an embodiment of the present invention, the metal gate structure is formed by forming a polysilicon gate structure on the fin structure and the junction-free nanowire structure as a dummy gate, removing the dummy gate to form a trench, forming a U-shaped gate dielectric layer on the bottom and the sidewall of the trench, and preferably, the gate dielectric layer is a high-K dielectric layer to form the gate dielectric layer, such as for HfO2And high-K materials obtained by introducing elements such as Si, Al, N, La, and Ta and optimizing the ratio of the elements. The method of forming the high-K dielectric layer may be a physical vapor deposition process or an atomic layer deposition process. And filling a plurality of film stacks on the gate dielectric layer in the groove, wherein the films comprise a work function metal layer, a barrier layer and a conductive layer. The barrier layer comprises TaN, TiN, TaC, TaSiN, WN, TiAl, TiAlN, or combinations thereof. The above-mentionedNon-limiting examples of methods for depositing the barrier layer include Chemical Vapor Deposition (CVD) such as Low Temperature Chemical Vapor Deposition (LTCVD), Low Pressure Chemical Vapor Deposition (LPCVD), rapid thermal chemical vapor deposition (LTCVD), plasma chemical vapor deposition (PECVD). And finally forming a high-k metal gate structure. Etching away the dummy gate to form the metal gate structure is a common technique for those skilled in the art and will not be discussed in detail here.
Performing LDD ion implantation on two sides of the gate structure to form a lightly doped region. The method of forming the LDD may be an ion implantation process or a diffusion process. The ion type of the LDD implantation is determined according to the electrical property of a semiconductor device to be formed, namely the formed device is an NMOS device, and the impurity ions doped in the LDD implantation process are one or the combination of phosphorus, arsenic, antimony and bismuth; in one embodiment of the present invention, the device formed is a PMOS device and the implanted impurity ions are boron. The ion implantation process may be performed in one or more steps depending on the desired concentration of impurity ions. Alternatively, the subsequent fabrication process may be performed without performing the LDD ion implantation process, and the LDD doping process is not necessary.
After the ion implantation is finished, in order to eliminate the defects caused by the collision of high-energy incident ions with atoms on a semiconductor crystal lattice and the displacement of crystal lattice atoms, the device is annealed at a certain temperature to recover the structure of the crystal and eliminate the defects. The annealing temperature is 200-800 ℃.
A first spacer is formed on the gate structure 206, and the material of the first spacer is, for example, an insulating material such as silicon nitride, silicon oxide, or silicon oxynitride. As the size of the device is further reduced, the channel length of the device is smaller and smaller, the particle injection depth of the source electrode and the drain electrode is also smaller and smaller, and the first gap wall is used for improving the channel length of the formed transistor and reducing the short-channel effect and the hot carrier effect caused by the short-channel effect. The first spacer may be formed on both sides of the gate structure 206 by a process such as chemical vapor deposition, and the thickness of the first spacer may be as small as 80 angstroms in this embodiment.
Preferably, the first semiconductor material layer is a Si, SiGe or SiC material layer, so as to form raised source- drain regions 207a and 207b on two sides of the gate structure 206, as shown in fig. 2, the Si material layer is undoped Si, and has a thickness of 10-30nm, preferably 20nm, in a specific embodiment of the present invention, the Si material layer epitaxy method is: hydrogen (H)2) Gas-borne silicon tetrachloride (SiCl)4) Or trichlorosilane (SiHCl)3) Silane (SiH)4) Or dichlorosilane (SiH)2Cl2) And the silicon atoms enter a reaction chamber provided with a silicon substrate, high-temperature chemical reaction is carried out in the reaction chamber, the silicon-containing reaction gas is reduced or thermally decomposed, and the generated silicon atoms are epitaxially grown on the surface of the substrate silicon. In the step, 98.5% high dilution ratio can be selected, the reaction temperature is 1500-.
Forming a second spacer (spacer) on the first spacer; the second spacer may be made of one of silicon oxide, silicon nitride, and silicon oxynitride, or a combination thereof. As an optimized implementation manner of this embodiment, the second spacer is composed of silicon oxide and silicon nitride, and the specific process includes: a first silicon oxide layer, a first silicon nitride layer and a second silicon oxide layer are formed on a semiconductor substrate, and then a spacer is formed by an etching method.
A second spacer is formed on the gate structure 206. The second spacer, comprising a nitride, an oxynitride or a combination thereof, is formed by deposition and etching. The second spacer structure may have a different thickness, but the thickness of the second spacer structure is typically 10nm to 30nm, measured from the bottom surface.
The second spacer structure may comprise at least one oxide layer and/or at least one nitride layer. It should be noted that the spacer structure is optional and not necessary, and is mainly used to protect the sidewalls of the gate structure 206 from being damaged during the subsequent etching or ion implantation.
Preferably, after the gate structure 206 is formed, a step of forming source and drain regions 208a and 208b on both sides of the gate may be further included, specifically, the source and drain regions may be formed by ion implantation or diffusion, and as a further preference, a step of thermal annealing may be further included after the ion implantation or diffusion.
The annealing step is generally to place the substrate under the protection of high vacuum or high purity gas, heat to a certain temperature and perform a rapid temperature rise annealing (RTA) process, in the invention, the high purity gas is preferably nitrogen or inert gas, the temperature of the rapid temperature rise annealing process step is 800-. As a further preferred option, the rapid thermal annealing selected in the present invention may be selected in one of the following ways: pulsed laser rapid annealing, pulsed electron beam rapid annealing, ion beam rapid annealing, continuous wave laser rapid annealing, and incoherent broadband light source (e.g., halogen lamp, arc lamp, graphite heating) rapid annealing, to name but not limited to.
And finally, forming an electrical connection on the raised source drain, depositing a conductive material on the raised source drain, and then flattening the conductive material for electrical connection, wherein the conductive material can be formed by Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD) or other advanced deposition techniques. Preferably, the conductive material is a tungsten material. In another embodiment, the conductive material may be cobalt (Co), molybdenum (Mo), titanium nitride (TiN), and a conductive material containing tungsten, or a combination thereof.
Preferably, in one embodiment, in order to reduce the contact resistance, a silicidation process (silicidation) for forming a silicide layer is further included before filling the conductive material, specifically, a metal layer, such as a nickel metal layer, is sputtered on the surface of the semiconductor substrate, and then a Rapid Thermal Annealing (RTA) process is performed to react a portion of the metal layer contacting the gate and the source/drain regions into a silicide layer, thereby completing the silicidation process (silicidation).
The formation of the silicide region begins with the deposition of a metal layer, which may comprise nickel (nickel), cobalt (cobalt), and platinum (platinum) or combinations thereof. The substrate is then heated, causing silicidation of the metal layer and the underlying silicon layer, thereby forming a region of the metal silicide layer. An etchant is then used that attacks the metal layer but does not attack the silicide region to remove the unreacted metal layer. As shown in fig. 2C, a schematic structural diagram of the formed junction-free nanowire FinTFET device
In addition, fig. 3A-3C illustrate a schematic process of forming a P-type junction-free nanowire FinTFET, in which an N-well is formed in the P-type substrate, an epitaxial layer of SiGe or SiC is formed on the P-type substrate, the epitaxial layer and the semiconductor substrate are etched according to a mask layer to form a fin structure and a nanowire structure, a gate structure is formed on the fin structure and the nanowire, and a first spacer is formed on a sidewall of the gate structure; epitaxially growing a first semiconductor material layer to form a raised source drain; forming a second spacer on the first spacer; and forming P-type light doping on the drain region, forming P-type doping on the source region, annealing, forming a silicide layer on the source region, and forming electrical connection. The specific forming method may refer to a forming method of the N-type junction-free nanowire FinTFET, and is not described herein again. For the sake of distinction from fig. 2, the numbering is adjusted in fig. 3, in particular as follows the semiconductor substrate 300, the well 301, the epitaxial layer 302, the fin structure 303, the nanowire structure 304, the shallow trench isolation 305, the gate structure 306, the source 308a and the drain 308b, the raised drain 307b and the raised source 307 a.
Fig. 4 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, which specifically includes the following steps:
step 401 provides a semiconductor substrate;
step 402, forming an epitaxial layer on the semiconductor substrate;
step 403, patterning the epitaxial layer and the semiconductor substrate to form a fin structure and a junction-free nanowire structure;
step 404 forming shallow trench isolation on the semiconductor substrate;
step 405 forming a gate structure over the fin structure and the junction-less nanowire structure;
step 406 performs LDD ion implantation;
step 407, forming a first spacer on a sidewall of the gate structure;
step 408, epitaxially growing a first semiconductor material layer to form a raised source drain;
step 409 forming a second spacer on the first spacer;
step 410, performing ion implantation, forming source and drain regions on two sides of the grid structure, and annealing;
step 411 forms a silicide layer on the source and drain regions and then forms an electrical connection.
In addition, the invention provides a preparation method of the junction-free nanowire FinFET device, and also provides a semiconductor device, which comprises the following steps:
a semiconductor substrate;
a well in the semiconductor substrate;
a fin structure located on the well and a junction-free nanowire structure located on the fin structure;
a gate structure surrounding the fin structure and the nanowire structure;
the device comprises a substrate, a well, a fin structure, a non-junction nanowire structure, a source electrode, a drain electrode and a device, wherein the well is an N well, the fin structure is an N type, the non-junction nanowire structure is a P type, the source electrode and the drain electrode are P types, and the device is a P type non-junction nanowire fin field effect transistor; or the trap is a P trap, the fin structure is a P type, the junction-free nanowire structure is an N type, the source and drain are N types, and the device is an N type junction-free nanowire fin field effect transistor.
As a further preference, the device further comprises:
a first spacer and a second spacer on the gate structure;
shallow trench isolation positioned at two sides of the grid structure;
source and drain regions located at two sides of the gate structure;
an electrical connection element on the gate structure.
In the semiconductor device and the preparation method, the junction-free nanowire transistor and the FinFET are combined to form the junction-free nanowire FinFET in the preparation process in order to avoid the problems of high doping concentration gradient, low thermal budget and the like of the transistor in the prior art. According to the transistor formed by the invention, when the device is in an open state, the current is larger, when the device is in an open state, the current is smaller, the performance of the transistor and a FinFET is greatly improved, and the transistor has a larger on-off ratio (large on-off ratio) compared with a planar device, the whole process is completely compatible with the prior process, and the preparation method of the transistor is suitable for a small-sized semiconductor substrate, and the preparation cost of the transistor is lower than that of a nanowire cylinder full-surrounding gate junction-free field effect transistor (GAAC JLFET), so that the preparation process of the transistor is simpler, and the process cost is reduced.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed.

Claims (16)

1. A method for fabricating a junction-free nanowire FinFET, comprising:
providing a semiconductor substrate;
forming an epitaxial layer on the semiconductor substrate, wherein the doping type of the epitaxial layer is different from that of the fin structure;
patterning the epitaxial layer and a portion of the semiconductor substrate to form a fin structure and a nanowire structure on the fin structure;
a gate structure is formed over the fin structure and the nanowire structure.
2. The method of claim 1, wherein the epitaxial layer is SiGe or SiC.
3. The method of claim 1, wherein the epitaxial layer is 5-10nm thick.
4. The method of claim 1, wherein the fin structures have a width of less than 8 nm.
5. The method of claim 1, wherein the epitaxial layer is formed using an in-situ doping process or a shallow junction doping process.
6. The method of claim 1, wherein a well is formed in the semiconductor substrate.
7. The method of claim 1, wherein the semiconductor substrate is Si.
8. The method of claim 1, wherein the gate structure is a high-K metal gate structure.
9. The method of claim 1, further comprising the step of forming shallow trench isolations on the semiconductor substrate on both sides of the fin structure prior to forming the gate structure.
10. The method of claim 1, wherein after forming the gate structure, the method further comprises:
performing LDD ion implantation;
forming a first gap wall on the side wall of the gate structure;
epitaxially growing a first semiconductor material layer to form a raised source drain;
forming a second spacer on the first spacer;
performing ion implantation, forming source and drain regions on two sides of the grid structure, and performing rapid annealing;
and forming a silicide layer on the source and drain regions, and then forming an electrical connection.
11. The method of claim 10, wherein the first layer of semiconductor material is a layer of Si, SiGe or SiC material.
12. The method of claim 1, wherein patterning the epitaxial layer and a portion of the semiconductor substrate comprises:
forming a patterned photoresist layer on the epitaxial layer to define patterns of the fin structures and the nanowire structures;
etching the epitaxial layer and a part of the semiconductor substrate by taking the photoresist layer as a mask to form the fin structure and the nanowire structure positioned on the fin structure;
and removing the photoresist layer.
13. The method according to claim 10, wherein the doping type of the epitaxial layer is the same as the doping type of the source drain region.
14. A junction-free nanowire FinFET semiconductor device, comprising:
a semiconductor substrate;
the semiconductor device comprises a fin structure positioned on the semiconductor substrate and a nanowire structure positioned on the fin structure, wherein the doping type of the nanowire structure is different from that of the fin structure;
a gate structure surrounding the fin structure and the nanowire structure.
15. The device of claim 14, wherein the material of the nanowire structure is SiGe or SiC.
16. The device of claim 14, wherein the gate structure is a high-K metal gate structure.
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