CN104252854A - Array substrate, driving method thereof, display panel and display device - Google Patents
Array substrate, driving method thereof, display panel and display device Download PDFInfo
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- CN104252854A CN104252854A CN201410510750.3A CN201410510750A CN104252854A CN 104252854 A CN104252854 A CN 104252854A CN 201410510750 A CN201410510750 A CN 201410510750A CN 104252854 A CN104252854 A CN 104252854A
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Abstract
The invention relates to an array substrate, a driving method thereof, a display panel and a display device. The array substrate comprises a plurality of rows of gate lines, a plurality of columns of data lines and a plurality of pixel units; the pixel units are respectively arranged between each two neighboring columns of data lines, the gate line of the 2n minus 1th row and the gate line of the 2nth row; n is a positive integer, and 2n is less than or equal to the total row number of the gate lines of the array substrate; each pixel unit comprises a first sub-pixel and a second sub-pixel which are arranged in the same row; the first sub-pixel is connected with the data line neighboring the right side of the first sub-pixel through a first transistor, and the grid of the first transistor is connected with the gate line of the 2n minus 1th row neighboring the first sub-pixel; the second sub-pixel is connected with the data line neighboring the left side of the second sub-pixel through a second transistor, and the grid of the second transistor is connected with the gate line of the 2nth row neighboring the second sub-pixel; among the neighboring pixel units, the arrangement order of the first sub-pixels and the arrangement order of the second sub-pixels are opposite along the gate line direction. The invention can reduce power consumption when a pint driving mode needs to be adopted.
Description
Technical field
The present invention relates to display technique field, particularly relate to a kind of array base palte and driving method, display panel and display device.
Background technology
Existing array base palte comprises multirow grid line, multi-column data line and multiple pixel cell; Described pixel cell is arranged at adjacent two column data lines, between the capable grid line of 2n-1 and the capable grid line of 2n; N is positive integer, and 2n is less than or equal to total line number of the grid line that described array base palte comprises; Each described pixel cell comprises the first sub-pix and second sub-pix of colleague's setting; Described first sub-pix is connected by the first transistor and the data line the most adjacent with this first sub-pix, and grid and the next line grid line adjacent with this first sub-pix of this first transistor are connected; Described second sub-pix is connected by transistor seconds and the data line the most adjacent with this second sub-pix, and grid and the lastrow grid line adjacent with this second sub-pix of this transistor seconds are connected; In all pixel cells, described first sub-pix is contrary all identical along putting in order of grid line direction with described second sub-pix.
As shown in Figure 1, existing array base palte comprises N-th row grid line GN, the capable grid line GN+1 of N+1, the capable grid line GN+2 of N+2, the capable grid line GN+3 of N+3, M-2 column data line DM-2, M-1 column data line DM-1, M column data line DM, M+1 column data line DM+1, M+2 column data line DM+2, be arranged at GN, four pixel cells between GN+1 and adjacent column data line, and be arranged at GN+2, four pixel cells between GN+3 and adjacent data line, wherein N is positive integer, M be greater than 2 positive integer, the first sub-pix that each pixel cell comprises is arranged at left side, the second sub-pix that each pixel cell comprises is provided with right side, red sub-pixel is designated R in FIG, green sub-pixels is designated G, blue subpixels is designated B, time then as adopted the display panel of array base palte as shown in Figure 1 need adopt a some type of drive, data line need adopt the type of drive of row upset, namely when showing same frame picture, charge polarity when opening every a line grid line on each data line all can overturn, thus causes power consumption large.
Summary of the invention
Fundamental purpose of the present invention is to provide a kind of array base palte and driving method, display panel and display device, to solve in prior art when adopting some type of drive because data line need adopt the type of drive of row upset and the large problem of the power consumption that causes.
In order to achieve the above object, the invention provides a kind of array base palte, comprise multirow grid line, multi-column data line and multiple pixel cell; Described pixel cell is arranged at adjacent two column data lines, between the capable grid line of 2n-1 and the capable grid line of 2n; N is positive integer, and 2n is less than or equal to total line number of the grid line that described array base palte comprises;
Each described pixel cell comprises the first sub-pix and second sub-pix of colleague's setting;
Described first sub-pix, is connected by the first transistor with data line adjacent on the right side of this first sub-pix, and grid and the 2n-1 capable grid line adjacent with this first sub-pix of this first transistor are connected;
Described second sub-pix, is connected by transistor seconds with data line adjacent on the left of this second sub-pix, and grid and the 2n capable grid line adjacent with this second sub-pix of this transistor seconds are connected;
In adjacent pixel cell, described first sub-pix is contrary along putting in order of grid line direction with described second sub-pix.
Present invention also offers a kind of driving method of array base palte, be applied to above-mentioned array base palte, described driving method comprises:
When showing each frame picture, multirow grid line is opened successively;
When the capable grid line of 2n-1 is opened, the first transistor that grid is connected with the capable grid line of this 2n-1 is opened, and the data line be connected with this first transistor sends the electric charge of the first polarity to connected first sub-pix;
When the capable grid line of 2n is opened, the transistor seconds that grid is connected with the capable grid line of this 2n is opened, and the data line be connected with this transistor seconds sends the electric charge of the second polarity to connected second sub-pix.
Concrete, when needs adopt some type of drive, the first polarity is contrary with the second polarity, and contrary in the polarity of the electric charge of front and back two frame picture same data lines output.
Present invention also offers a kind of display panel, comprise above-mentioned array base palte.
Present invention also offers a kind of display device, comprise above-mentioned display panel.
Compared with prior art, array base palte of the present invention and driving method, display panel and display device, when needs adopt some type of drive, when showing same frame picture, charge polarity on each data line all remains unchanged, namely data line need adopt the type of drive of row upset, and power consumption reduces greatly.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of existing array base palte;
Fig. 2 is the schematic diagram of the array base palte described in the present invention one specific embodiment;
Fig. 3 A is the positive-negative polarity schematic diagram of the array base palte each sub-pix when display one frame picture described in this specific embodiment of the present invention;
Fig. 3 B is the positive-negative polarity schematic diagram of the array base palte each sub-pix when showing next frame picture described in this specific embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Array base palte described in the embodiment of the present invention, comprises multirow grid line, multi-column data line and multiple pixel cell; Described pixel cell is arranged at adjacent two column data lines, between the capable grid line of 2n-1 and the capable grid line of 2n; N is positive integer, and 2n is less than or equal to total line number of the grid line that described array base palte comprises;
Each described pixel cell comprises the first sub-pix and second sub-pix of colleague's setting;
Described first sub-pix, is connected by the first transistor with data line adjacent on the right side of this first sub-pix, and grid and the 2n-1 capable grid line adjacent with this first sub-pix of this first transistor are connected;
Described second sub-pix, is connected by transistor seconds with data line adjacent on the left of this second sub-pix, and grid and the 2n capable grid line adjacent with this second sub-pix of this transistor seconds are connected;
In adjacent pixel cell, described first sub-pix is contrary along putting in order of grid line direction with described second sub-pix.
In the array base palte described in the embodiment of the present invention, adjacent pixel cell refers to along pixel cell adjacent on grid line direction and along pixel cell adjacent on data line direction.
The driving method of the array base palte described in the embodiment of the present invention, is applied to above-mentioned array base palte, and described driving method comprises:
When showing each frame picture, multirow grid line is opened successively;
When the capable grid line of 2n-1 is opened, the first transistor that grid is connected with the capable grid line of this 2n-1 is opened, and the data line be connected with this first transistor sends the electric charge of the first polarity to connected first sub-pix;
When the capable grid line of 2n is opened, the transistor seconds that grid is connected with the capable grid line of this 2n is opened, and the data line be connected with this transistor seconds sends the electric charge of the second polarity to connected second sub-pix.
Concrete, when needs adopt some type of drive, the first polarity is contrary with the second polarity, and contrary in the polarity of the electric charge of front and back two frame picture same data lines output.
When adopting the display panel needs of the array base palte comprised described in this embodiment of the invention to adopt some type of drive, when showing same frame picture, charge polarity on each data line all remains unchanged, namely data line need adopt the type of drive of row upset, compares and adopts the display panel power consumption of existing array base palte greatly to reduce.
The structure of the array base palte described in this embodiment of the invention is described according to a specific embodiment below.
As shown in Figure 2, array base palte described in the present invention one specific embodiment comprises N-th row grid line GN, the capable grid line GN+1 of N+1, N+2 capable grid line GN+2, the capable grid line GN+3 of N+3, M-2 column data line DM-2, M-1 column data line DM-1, M column data line DM, M+1 column data line DM+1, M+2 column data line DM+2, is arranged at four pixel cells between GN, GN+1 and adjacent column data line, and four pixel cells be arranged between GN+2, GN+3 and adjacent data line, wherein N is positive integer, M be greater than 2 positive integer;
In fig. 2, red sub-pixel is designated R, and green sub-pixels is designated G, and blue subpixels is designated B;
In the pixel cell that pixel cell and second row the 4th of the pixel cell of the first row first row of Fig. 2, the tertial pixel cell of the first row, the second row secondary series arrange, the first sub-pix is positioned at left side, and the second sub-pix is positioned at right side;
At the pixel cell of the first row secondary series of Fig. 2, in the pixel cell that the first row the 4th arranges, the pixel cell of the second row first row and the tertial pixel cell of the second row, the first sub-pix is positioned at right side, and the second sub-pix is positioned at left side;
When display one frame picture, the charge polarity on DM-1 and the charge polarity on DM+1 are just, the charge polarity on the charge polarity on DM-2, the charge polarity on DM and DM+2 is negative;
As shown in Figure 3A, when GN opens, DM-1 fills positive electricity to the first row first sub-pix, and DM fills negative electricity to the first row the 4th sub-pix, and DM+1 fills positive electricity to the first row the 5th sub-pix, and DM+2 fills negative electricity to the first row the 8th sub-pix;
When GN+1 opens, DM-2 fills negative electricity to the first row second sub-pix, and DM-1 fills positive electricity to the first row the 3rd sub-pix, and DM fills negative electricity to the first row the 6th sub-pix, and DM+1 fills positive electricity to the first row the 7th sub-pix;
When GN+2 opens, DM-1 fills positive electricity to the second row second sub-pix, and DM fills negative electricity to the second row the 3rd sub-pix, and DM+1 fills positive electricity to the second row the 6th sub-pix, and DM+2 fills negative electricity to the second row the 7th sub-pix;
When GN+3 opens, DM-2 fills negative electricity to the second row first sub-pix, and DM-1 fills positive electricity to the second row the 4th sub-pix, and DM fills negative electricity to the second row the 5th sub-pix, and DM+1 fills positive electricity to the first row the 8th sub-pix;
When showing next frame picture, the charge polarity on DM-1 and the charge polarity on DM+1 are negative, and the charge polarity on the charge polarity on DM-2, the charge polarity on DM and DM+2 is just;
As shown in Figure 3 B, when GN opens, DM-1 fills negative electricity to the first row first sub-pix, and DM fills positive electricity to the first row the 4th sub-pix, and DM+1 fills negative electricity to the first row the 5th sub-pix, and DM+2 fills positive electricity to the first row the 8th sub-pix;
When GN+1 opens, DM-2 fills positive electricity to the first row second sub-pix, and DM-1 fills negative electricity to the first row the 3rd sub-pix, and DM fills positive electricity to the first row the 6th sub-pix, and DM+1 fills negative electricity to the first row the 7th sub-pix;
When GN+2 opens, DM-1 fills negative electricity to the second row second sub-pix, and DM fills positive electricity to the second row the 3rd sub-pix, and DM+1 fills negative electricity to the second row the 6th sub-pix, and DM+2 fills positive electricity to the second row the 7th sub-pix;
When GN+3 opens, DM-2 fills positive electricity to the second row first sub-pix, and DM-1 fills negative electricity to the second row the 4th sub-pix, and DM fills positive electricity to the second row the 5th sub-pix, and DM+1 fills negative electricity to the first row the 8th sub-pix;
When showing next frame picture, the charge polarity on DM-1 and the charge polarity on DM+1 overturn again as just, and the charge polarity on the charge polarity on DM-2, the charge polarity on DM and DM+2 overturns again as negative, the like.
From the driving process of the array base palte described in this specific embodiment of the present invention, only need make the polarity upset of the electric charge exported in the same data lines of front and back two frame picture, namely take the type of drive arranging upset, namely can realize a driving.
Display panel described in the embodiment of the present invention, comprises above-mentioned array base palte.
Display device described in the embodiment of the present invention, comprises above-mentioned display panel.
Described display device can comprise liquid crystal indicator, such as liquid crystal panel, LCD TV, mobile phone, liquid crystal display.Except liquid crystal indicator, described display device can also comprise the display device of organic light emitting display or other types, such as electronic reader etc.
The above is only embodiments of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (5)
1. an array base palte, is characterized in that, comprises multirow grid line, multi-column data line and multiple pixel cell; Described pixel cell is arranged at adjacent two column data lines, between the capable grid line of 2n-1 and the capable grid line of 2n; N is positive integer, and 2n is less than or equal to total line number of the grid line that described array base palte comprises;
Each described pixel cell comprises the first sub-pix and second sub-pix of colleague's setting;
Described first sub-pix, is connected by the first transistor with data line adjacent on the right side of this first sub-pix, and grid and the 2n-1 capable grid line adjacent with this first sub-pix of this first transistor are connected;
Described second sub-pix, is connected by transistor seconds with data line adjacent on the left of this second sub-pix, and grid and the 2n capable grid line adjacent with this second sub-pix of this transistor seconds are connected;
In adjacent pixel cell, described first sub-pix is contrary along putting in order of grid line direction with described second sub-pix.
2. a driving method for array base palte, is applied to array base palte as claimed in claim 1, it is characterized in that, described driving method comprises:
When showing each frame picture, multirow grid line is opened successively;
When the capable grid line of 2n-1 is opened, the first transistor that grid is connected with the capable grid line of this 2n-1 is opened, and the data line be connected with this first transistor sends the electric charge of the first polarity to connected first sub-pix;
When the capable grid line of 2n is opened, the transistor seconds that grid is connected with the capable grid line of this 2n is opened, and the data line be connected with this transistor seconds sends the electric charge of the second polarity to connected second sub-pix.
3. the driving method of array base palte as claimed in claim 2, is characterized in that, when needs adopt some type of drive, the first polarity is contrary with the second polarity, and contrary in the polarity of the electric charge of front and back two frame picture same data lines output.
4. a display panel, is characterized in that, comprises array base palte as claimed in claim 1.
5. a display device, is characterized in that, comprises display panel as claimed in claim 4.
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| CN201410510750.3A CN104252854A (en) | 2014-09-28 | 2014-09-28 | Array substrate, driving method thereof, display panel and display device |
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| CN201410510750.3A CN104252854A (en) | 2014-09-28 | 2014-09-28 | Array substrate, driving method thereof, display panel and display device |
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| CN104900207A (en) * | 2015-06-24 | 2015-09-09 | 京东方科技集团股份有限公司 | Array substrate, drive method thereof and display device |
| CN105425491A (en) * | 2016-01-05 | 2016-03-23 | 重庆京东方光电科技有限公司 | Double-gate type pixel structure, display panel and display device |
| CN105629611A (en) * | 2016-03-11 | 2016-06-01 | 京东方科技集团股份有限公司 | Array substrate, display device and drive method thereof |
| CN106648261A (en) * | 2017-03-06 | 2017-05-10 | 京东方科技集团股份有限公司 | Array substrate and display panel, display device |
| CN109215609A (en) * | 2018-11-12 | 2019-01-15 | 合肥京东方显示技术有限公司 | Display base plate, display panel and its driving method |
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| CN104900207A (en) * | 2015-06-24 | 2015-09-09 | 京东方科技集团股份有限公司 | Array substrate, drive method thereof and display device |
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| CN109215609A (en) * | 2018-11-12 | 2019-01-15 | 合肥京东方显示技术有限公司 | Display base plate, display panel and its driving method |
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