CN104243330B - A kind of network on three-dimensional chip router towards low-density perpendicular interconnection - Google Patents

Abstract

The present invention relates to a kind of network on three-dimensional chip router towards low-density perpendicular interconnection, including inner control logic, cross bar switch and five horizontal direction ports and two vertical direction ports, the network-on-chip includes some network-on-chip nodes, each network node includes a processing unit with network interface or memory cell and a router, each processing unit or memory cell pass through the network interface and corresponding router communication, the output channel of the vertical direction port of the router goes here and there out shift-register circuit using being incorporated to, input channel uses SI PO shift register circuit.Have the beneficial effect that：It is respectively adopted to be incorporated to by the output channel and input channel in network on three-dimensional chip router vertical direction port and goes here and there out shift register and SI PO shift register, realizes the purpose that data are effectively and reliably transmitted in the case where network on three-dimensional chip vertical join line density reduces.

Description

A 3D Network-on-Chip Router for Low-Density Vertical Interconnects

technical field

The invention relates to a three-dimensional on-chip network router, in particular to a three-dimensional on-chip network router facing low-density vertical interconnection.

Background technique

With the increasing integration density on the chip, the traditional design method based on bus interconnection has to face a severe communication bottleneck. design method. On the other hand, with the progress of the technology, the long delay of the global connection has become an important factor limiting the performance of the chip, and the three-dimensional integration technology has emerged as the times require. The combination of 3D integration technology and on-chip network provides a direction for the design of multi-core chips in the future.

The three-dimensional network on chip has the advantages of scalability, high integration density, short global connection, small chip area, and good performance, but it also has disadvantages such as high manufacturing cost and poor heat dissipation.

Three-dimensional integration technology is to stack chips vertically. Traditional packaging technologies include system-in-package (SiP) and package-on-package (PoP). Recently, more research has been done on Through-Silicon-Via (TSV) technology. The vertical interconnection technology made by through-silicon via technology interconnects chips vertically by drilling holes in silicon and then injecting conductive materials. The main driving force for the development of TSV technology is that the length of TSV wires is short, and the resistance and inductance are lower, which can increase the transmission speed of signals. Under the trend of miniaturization, these are the most critical performance factors. 3D integration requires some additional processing steps compared to 2D integration, including TSV formation, wafer thinning, and wafer bonding. Compared with other packaging technologies, TSV vertical wires are shorter, the transmission speed is faster, and the power consumption is lower. However, the manufacturing process of TSV is more complicated and more expensive. Compared with logic devices, TSV occupies a relatively large chip area. , while reducing the yield of chips, which are closely related to the number of TSVs.

The number of connections between the vertical ports of the existing three-dimensional network-on-chip router is the same as the number of connections between the horizontal ports. High TSV technology, such a design greatly increases the area and cost of the chip.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies of the above prior art, and provide a three-dimensional on-chip network router for low-density vertical interconnection, which is specifically realized by the following technical solutions:

The three-dimensional on-chip network router for low-density vertical interconnection includes internal control logic, a crossbar switch, five horizontal ports and two vertical ports, and the five horizontal ports are east, west, south, north and Local port, two vertical direction ports, respectively upper and lower ports, is characterized in that the network on chip includes several network nodes on chip, and each network node includes a processing unit or storage unit with a network interface and a router , each of the processing units or storage units communicates with the corresponding router through the network interface, and the upper port and the lower port in the vertical direction are respectively connected to the input channel and the output channel, and the input channel adopts serial input and output A bit register circuit, the output channel adopts a parallel-in serial-out shift register circuit.

The further design of the low-density vertical interconnection-oriented three-dimensional network-on-chip router is that the network-on-chip is formed by stacking multiple layers of chips, and each layer of chips contains the same number of network nodes, and the network nodes in the same layer are connected to each other. They are connected by horizontal wires and arranged in a matrix grid topology, and the network nodes at corresponding positions between the two adjacent layers are connected by vertical wires made by TSV technology.

The further design of the low-density vertical interconnection-oriented three-dimensional network-on-chip router is that the parallel-in and serial-out shift register circuit is composed of several parallel-in and serial-out shift registers, and the number of parallel-in and serial-out shift registers is The number of vertical connections made by TSV technology in the vertical direction is equal to the number of vertical connections made by TSV technology, and the parallel-in-serial-output shift register adopts cross interval input, and the interval period is equal to the number of vertical connections made by TSV technology.

A further design of the low-density vertical interconnection-oriented three-dimensional network-on-chip router is that the output port of the vertical port of the router is connected with a FIFO memory.

The further design of the low-density vertical interconnection-oriented three-dimensional network-on-chip router is that the serial-in-parallel shift register circuit is composed of a number of serial-in-parallel shift registers, and the number of the serial-in-parallel shift registers is the same as the number of serial-in-parallel shift registers. The number of vertical connections made by TSV technology is equal.

The advantages of the present invention are as follows:

In the present invention, the output channel of the vertical direction port adopts the parallel input and serial output shift register circuit, so that the data transmitted from the horizontal direction port is input in parallel and serially output, and the data bits from the horizontal direction port to the vertical direction port are realized. wide conversion. For the transmission of multi-bit data, a set of parallel-in serial-out shift registers is used, and the number of shift registers is equal to the number of vertical connections made by TSV technology. For the parallel-in-serial-out shift register, a cross-interval input is adopted, and the period of the interval is equal to the number of vertical connections made by TSV technology. In the present invention, the output channel and the input channel of the vertical direction port of the three-dimensional on-chip network router respectively adopt the parallel-in-serial-out shift register and the serial-in-parallel-out shift register, thereby realizing the efficient operation under the condition that the vertical connection density of the three-dimensional on-chip network is reduced. , Reliable data transmission, and improve the yield of the chip, reduce the area of the chip and reduce the cost of the chip and three-dimensional bonding, has a good application prospect.

Description of drawings

FIG. 1 is a schematic diagram of a three-dimensional mesh network-on-chip adopted in the present invention.

FIG. 2 is a side view of the schematic diagram of the three-dimensional mesh network-on-chip shown in FIG. 1 .

FIG. 3 is a schematic diagram of the parallel-in-serial-out shift register.

Figure 4(a) is the input of the parallel-in-serial-out shift register.

Figure 4(b) is a schematic diagram of a module incorporating a serial-output shift register.

FIG. 5( a ) is a diagram of the internal structure of the serial-in-parallel-out shift register.

Figure 5(b) is a block diagram of a serial-in-parallel-out shift register.

Fig. 6 is a schematic diagram of the port in the vertical direction.

detailed description

The solution of the present invention will be described in detail below in conjunction with the accompanying drawings.

Example 1

The three-dimensional network-on-chip router for low-density vertical interconnection provided in this embodiment includes internal control logic, a crossbar switch, five horizontal ports and two vertical ports, as shown in FIG. 1 . The above-mentioned five horizontal ports are respectively east, west, south, north and local ports; the two vertical ports are respectively upper and lower ports.

The on-chip network provided by this embodiment includes several on-chip network nodes, each network node includes a processing unit with a network interface and a router, each processing unit communicates with the corresponding router through the network interface, and the output of the vertical port of the router The channel adopts a parallel-in and serial-out shift register circuit, and the input channel adopts a serial-in parallel-out shift register circuit. There are a total of 32 on-chip network nodes, which are stacked from upper and lower layers. Each layer includes 16 network nodes. The network nodes in the same layer are connected to each other through horizontal connections, and are arranged in a 4*4 matrix grid Arranged in a topological manner, network nodes at corresponding positions between the two layers are connected through vertical connections made by TSV technology. The side view of the three-dimensional network on a chip is shown in Figure 2. In this example, the number of horizontal wires (Wire) between the routing nodes in the horizontal direction is 128, and the vertical wires between the routing nodes in the vertical direction are made of through-silicon via technology. The number of wires (TSV) is 64, so data needs to be divided into two parts and serially transmitted when being transmitted on the vertical port.

In order to solve this problem, this embodiment redesigns the ports in the vertical direction of the router. Figure 3 is the design of the output channel of the vertical port of the router. The basic unit is a two-input parallel in serial out (Parallel InSerial Out, PISO) shift register. The basic function is to serially output data from two parallel inputs.

The output channel of the vertical port of the router adopts 64 identical parallel-in and serial-out shift registers. There is an interval of 64 bits between the two inputs of the parallel input to the serial output shift register, for example: the 0th bit and the 64th bit are input to the first parallel input to the serial output shift register, and the 1st bit and the 65th bit are input to the second parallel In and out of the shift register, and so on, the 63rd bit and the 127th bit are input into the 64th register, as shown in Figure 4(a). This design realizes 128-bit data parallel input, high 64-bit and low 64-bit sequential serial output, and effectively realizes the conversion of the data bit width from the horizontal direction port to the vertical direction port. Figure 4(b) is a modular schematic diagram of the parallel-in and serial-out shift register.

Figure 5(a) is the design of the input channel of the vertical port of the router, and the basic unit is a two-input serial in parallel out (Serial In Parallel Out, SIPO) shift register. The basic function is to output the data of two serial inputs in parallel. The input channel of the vertical direction port of the router adopts 64 identical serial input and parallel output shift registers to realize the functions of two 64-bit data serial input, 128-bit data parallel output, and data transfer from the vertical direction port to the horizontal direction port Bit width conversion. See Figure 5(b) for the modular diagram of the serial-in-parallel-out shift register.

FIG. 6 is a schematic diagram of the overall design of ports in the vertical direction of the router. The 128-bit data is input in parallel through the output channel, and then divided into two 64-bit data for serial transmission through TSV. It takes 4 cycles for the data to be output in parallel on the receiving channel at the same time. In this embodiment, the pipeline can be used to output a 128-bit flit every 2 cycles, so the input data needs to be temporarily registered. Therefore, a depth of 4 and a width of 128 bits is added to the output port of the vertical direction port of the route. FIFO memory.

In the present invention, the output channel and the input channel of the vertical direction port of the three-dimensional on-chip network router respectively adopt the parallel-in-serial-out shift register and the serial-in-parallel-out shift register, thereby realizing the efficient operation under the condition that the vertical connection density of the three-dimensional on-chip network is reduced. , Reliable data transmission, and improve the yield of the chip, reduce the area of the chip and reduce the cost of the chip and three-dimensional bonding, has a good application prospect.

Example 2

The three-dimensional network-on-chip router for low-density vertical interconnection provided in this embodiment includes internal control logic, a crossbar switch, five horizontal ports and two vertical ports, as shown in FIG. 1 . The above-mentioned five horizontal ports are respectively east, west, south, north and local ports; the two vertical ports are respectively upper and lower ports.

The on-chip network provided by this embodiment includes several on-chip network nodes, each network node includes a storage unit with a network interface and a router, each storage unit communicates with the corresponding router through the network interface, and the output of the vertical port of the router The channel adopts a parallel-in and serial-out shift register circuit, and the input channel adopts a serial-in parallel-out shift register circuit. There are a total of 32 on-chip network nodes, which are stacked from upper and lower layers. Each layer includes 16 network nodes. The network nodes in the same layer are connected to each other through horizontal connections, and are arranged in a 4*4 matrix grid Arranged in a topological manner, network nodes at corresponding positions between the two layers are connected through vertical connections made by TSV technology. The side view of the three-dimensional network on a chip is shown in Figure 2. In this example, the number of horizontal wires (Wire) between the routing nodes in the horizontal direction is 128, and the vertical wires between the routing nodes in the vertical direction are made of through-silicon via technology. The number of wires (TSV) is 64, so data needs to be divided into two parts and serially transmitted when being transmitted on the vertical port. The remaining technical solutions of this implementation are as described in Embodiment 1 and will not be repeated here.

Claims (3)

1. a kind of network on three-dimensional chip router towards low-density perpendicular interconnection, including inner control logic, cross bar switch with And five horizontal direction ports and two vertical direction ports, five horizontal direction ports, it is East, West, South, North and sheet respectively Ground port, two vertical direction ports, it is upper and lower port respectively, it is characterised in that if the network-on-chip is surfed the Net including dry plate Network node, each network node include a processing unit with network interface or memory cell and a router, Each processing unit or memory cell by the network interface and corresponding router communication, the vertical direction it is upper Port, lower port are connected respectively input channel and output channel, and the input channel uses SI PO shift register Circuit, the output channel go here and there out shift-register circuit using being incorporated to；

The network-on-chip is stacked by multilayer chiop and formed, and each layer of chip includes the network node of identical quantity, same Network node is connected by horizontal line between each other in layer, and is arranged by the network topology mode of matrix, the adjacent two layers Between correspondence position network node by made of silicon perforation technology vertical join line connect；

Described be incorporated to goes here and there out shift-register circuit and is gone here and there out shift register by some be incorporated to and formed, and described be incorporated to is gone here and there out displacement and posted The vertical join line quantity made of silicon perforation technology is equal with vertical direction for storage number, and described be incorporated to is gone here and there out shift register and adopted Inputted with transpostion interval, the cycle at interval with made of silicon perforation technology vertical join line quantity it is equal.

2. the network on three-dimensional chip router according to claim 1 towards low-density perpendicular interconnection, it is characterised in that institute The output channel for stating router vertical direction port is connected with FIFO memory.

3. the network on three-dimensional chip router according to claim 1 towards low-density perpendicular interconnection, it is characterised in that string Enter and go out shift-register circuit and be made up of some SI PO shift registers, the SI PO shift register number with Vertical join line quantity is equal made of silicon perforation technology.