CN104218001B - A manufacturing method of flash memory gate - Google Patents
A manufacturing method of flash memory gate Download PDFInfo
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- CN104218001B CN104218001B CN201310210343.6A CN201310210343A CN104218001B CN 104218001 B CN104218001 B CN 104218001B CN 201310210343 A CN201310210343 A CN 201310210343A CN 104218001 B CN104218001 B CN 104218001B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 65
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 57
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 57
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 46
- 229920005591 polysilicon Polymers 0.000 claims abstract description 46
- 230000007547 defect Effects 0.000 claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 14
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 13
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 11
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 9
- 238000005468 ion implantation Methods 0.000 claims abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 48
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 22
- 239000000377 silicon dioxide Substances 0.000 claims description 22
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 18
- 229910052721 tungsten Inorganic materials 0.000 claims description 18
- 239000010937 tungsten Substances 0.000 claims description 18
- 238000001259 photo etching Methods 0.000 claims description 13
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 11
- 239000001301 oxygen Substances 0.000 claims description 11
- 229910052760 oxygen Inorganic materials 0.000 claims description 11
- 230000008021 deposition Effects 0.000 claims description 8
- 229910052796 boron Inorganic materials 0.000 claims description 7
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 239000011513 prestressed concrete Substances 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 2
- 239000007792 gaseous phase Substances 0.000 claims 1
- 239000013049 sediment Substances 0.000 claims 1
- 108091006146 Channels Proteins 0.000 description 4
- 229910003978 SiClx Inorganic materials 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 239000004567 concrete Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 210000003205 muscle Anatomy 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention discloses a manufacturing method of flash memory gate. The manufacturing method comprises the following steps: forming shallow trench field oxide in order to isolate an active region; forming a well region of the flash memory by ion implantation; growing an ONO layer and a polysilicon layer sequentially on the surface of the silicon substrate and doping the polysilicon layer; depositing a layer of tungsten silicide on the surface of the polysilicon layer; growing the fourth and the fifth silicon nitride layers sequentially by using the processes of furnace tube and chemical vapor deposition, and stacking them to form the gate hard mask layer; and by means of photolithographic etching process, etching the gate hard mask layer, tungsten silicide layer and polysilicon layer in sequence to form the gate of the flash memory. The inventive method is capable of enabling the gate to maintain better morphology, better repairing the ONO defect of the flash memory to prolong the lifespan thereof and eliminate the durability test problem caused by forming the silicon nitride layer only using chemical vapor deposition, and preventing effectively the depletion of the polysilicon.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit method of manufacturing technology, more particularly to a kind of manufacture of flash memory grid
Method.
Background technology
As shown in figure 1, being the top view of the flash memory that existing method is formed；As shown in Fig. 2 being the flash memory of the AA ' line along along Fig. 1
Sectional view.Existing method comprises the steps when forming the grid of flash memory：
Step one, form shallow trench using lithographic etch process on silicon substrate 101, active area is defined by shallow trench；
In shallow trench, filling silica forms shallow trench field oxygen 103, by shallow trench field oxygen 103, active area is isolated.
Step 2, silicon substrate 101 surfaces of active regions grow one layer of sacrificial oxide layer.
Carry out the well region 102 that ion implanting forms flash memory, the ion implanting of well region 102 passes through sacrificial oxide layer.Flash memory
Well region 102 includes for including N-type well region or P type trap zone, and N-type well region is located in the flash area that channel type is P-type channel,
P type trap zone is located in the flash area that channel type is N-type channel.
Well region 102 removes sacrificial oxide layer using wet-etching technology after being formed.
Step 3, silicon substrate 101 surface grow ground floor silica, second layer silicon nitride and third layer oxygen successively
SiClx, forms ONO layer 104 by the superposition of ground floor silica, second layer silicon nitride and third layer silica, in 4ONO layer 104 table
Deposit one layer of polysilicon layer 105 on face, and p-type or n-type doping are carried out to polysilicon layer 105 using ion implantation technology；Contraposition
Carry out p-type doping in channel type is for the polysilicon layer 105 in the flash area of P-type channel, being pointed to channel type is N-type
Carry out n-type doping in described polysilicon layer in the flash area of raceway groove.
Step 4, in polysilicon layer 105 surface deposited metal tungsten silicide layer 106.
Step 5, using furnace process in metal silication tungsten layer 106 surface deposition one silicon nitride layer 107 and by this silicon nitride
Layer 107 composition grid hard mask layer 107.
Step 6, photoetching offset plate figure is formed using photoetching process and is defined the grid figure of flash memory by this photoetching offset plate figure
Shape；Grid hard mask layer 107 is performed etching for mask using photoetching offset plate figure, using photoetching offset plate figure and grid hard mask layer
107 perform etching and are formed with grid hard mask layer, metal silication tungsten successively for mask to metal silication tungsten layer and polysilicon layer
Layer and the grid of polysilicon layer superposition formation flash memory.
The grid hard mask layer being made up of silicon nitride layer in existing semiconductor flash memory grid technology method is typically to utilize
Boiler tube mode grows；The benefit of the grid hard mask layer that boiler tube mode grows is during grid etch, grid hard mask layer
Grid can be provided and protect well, keep the gate topography after etching.But at the high warm of long furnace process
Comprehend and cause the boron ion of p-type polysilicon layer to be diffused into metal silication tungsten layer, so that the boron ion concentration of p-type polysilicon layer subtracts
Light, cause, during transistor work, depletion of polysilicon occurs.
Silicon nitride layer in existing method also can be using the relatively low chemical vapor deposition method growth of technological temperature, if adopted
Although it can be avoided that furnace process produces if doing grid hard mask layer with the silicon nitride layer being formed by chemical vapor deposition method
The boron ion of p-type polysilicon layer be diffused into the defect of metal silication tungsten layer, but due to the ONO layer existing defects in flash memory,
Chemical vapor deposition method cannot eliminate the defect in ONO layer, and the presence of these defects can reduce service life the meeting of flash memory
Cause the durability test problem of flush memory device.
Content of the invention
The technical problem to be solved is to provide a kind of manufacture method of flash memory grid, and grid can be made to keep good
Good pattern, can eliminate durability test problem, can effectively prevent depletion of polysilicon.
For solving above-mentioned technical problem, the manufacture method of the flash memory grid that the present invention provides comprises the steps：
Step one, form shallow trench on a silicon substrate using lithographic etch process, active area is defined by described shallow trench；
In described shallow trench, filling silica forms shallow trench field oxygen, by described shallow trench field oxygen, described active area is isolated.
Step 2, carry out ion implanting formed well region.
Step 3, grow ground floor silica, second layer silicon nitride and third layer oxygen successively on the surface of described silicon substrate
SiClx, removes described ground floor silica outside flash area, described second layer silicon nitride and described third layer silica, by protecting
The described ground floor silica in described flash area, described second layer silicon nitride and the superposition of described third layer silica is stayed to be formed
ONO layer；Described surface of silicon outside described flash area forms the gate dielectric layer with the integrated cmos device of flash memory, in institute
State one layer of polysilicon layer of deposition on ONO layer and described gate dielectric layer surface, and using ion implantation technology to described polysilicon layer
Carry out p-type or n-type doping.
Step 4, in described polysilicon layer surface deposited metal tungsten silicide layer.
Step 5, using furnace process in described metal silication tungsten layer surface deposition the 4th silicon nitride layer；Using chemical gas
Phase depositing technics in described 4th silicon nitride layer surface deposition the 5th silicon nitride layer, by described 4th silicon nitride layer and the described 5th
Silicon nitride layer superposition forms grid hard mask layer；The temperature conditionss of the furnace process of described 4th silicon nitride layer can be to described ONO
The boundary defect of the silicon nitride of layer and silica carries out repairing and can make the boron ion of the described polysilicon layer of p-type doping to expand
It is scattered in described metal silication tungsten layer, under conditions of described grid hard mask layer gross thickness is constant, described 4th silicon nitride layer
It is set to the thickness of described 5th silicon nitride layer：Enable to described in the furnace process time of described 4th silicon nitride layer
Under conditions of the boundary defect of ONO layer is fully repaired, the thickness of described 4th silicon nitride layer gets over Bao Yuehao.
Step 6, define the gate patterns of described flash memory using photoetching process；Gate patterns according to lithographic definition according to
Secondary described grid hard mask layer, described metal silication tungsten layer and described polysilicon layer are performed etching, etching post tensioned unbonded prestressed concrete region outside
Described grid hard mask layer, described metal silication tungsten layer and described polysilicon layer be all removed, by remaining in described gate regions
The described grid hard mask layer in domain, described metal silication tungsten layer and the superposition of described polysilicon layer form the grid of described flash memory.
Further improvement is that the thickness of the 4th silicon nitride layer described in step 5 is 300～600, described 5th nitrogen
The thickness of SiClx layer is 900～1200.
Further improvement is that well region described in step 2 includes N-type well region or P type trap zone, and N-type well region is located at described
In PMOS device region in cmos device, the NMOS device that P type trap zone is located in described flash area and described cmos device
In part region.
Further improvement is to be pointed to the nmos device in described flash area and described cmos device in step 3
Carry out n-type doping in described polysilicon layer in region, be pointed to described in the PMOS device region in described cmos device
Carry out p-type doping in polysilicon layer.
Further improvement is that furnace process described in step 5 is LPCVD, and described chemical vapor deposition method is
PECVD.
Further improvement is that the temperature of described furnace process is 720 DEG C, and the temperature of described chemical vapor deposition method is
400℃.
Further improvement be, the abundant reparation of the boundary defect of ONO layer described in step 5 is by meeting durability test
It is defined.
Further improvement is that the condition meeting durability test is：Under 55 DEG C of temperature conditionss, described flash memory is entered
After the circulation erase and program operations that row is 110K time, flash memory can normally run.
The present invention by by the grid being made up of silicon nitride layer hard mask layer be divided into two-layer and successively adopt furnace process and
Chemical vapor deposition method is formed, and grid hard mask layer can carry out good protection to grid in grid etch, so as to
The pattern of enough good holding grids；Simultaneously the inventive method using furnace process can be good at the silicon nitride to ONO layer and
The boundary defect of silica is repaired, it is possible to increase the service life of flash memory simultaneously eliminates and individually adopts chemical vapor deposition method
Form the durability test problem brought during silicon nitride layer；Then it is avoided that long-time boiler tube is high using chemical vapor deposition method
In p-type polysilicon layer caused by temperature, boron is diffused into the defect in metal silication tungsten layer, can effectively prevent depletion of polysilicon.
Brief description
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description：
Fig. 1 is the top view of the flash memory that existing method is formed；
Fig. 2 is the sectional view of the flash memory of AA ' line along along Fig. 1；
Fig. 3 is the flow chart of present invention method；
Fig. 4 is the profile of flash memory in present invention method；
Fig. 5 is the profile of the flash memory of BB ' line along along Fig. 4.
Specific embodiment
As shown in figure 3, being the flow chart of present invention method；As shown in figure 4, being to dodge in present invention method
The profile deposited；As shown in figure 5, being the profile of the flash memory of BB ' line along along Fig. 4.The manufacture of embodiment of the present invention flash memory grid
Method comprises the steps：
Step one, using lithographic etch process, shallow trench is formed on silicon substrate 1, defined by described shallow trench active
Area；In described shallow trench, filling silica forms shallow trench field oxygen 3, by described shallow trench field oxygen 3, described active area is carried out
Isolation；
Step 2, carry out ion implanting formed flash memory well region 2.In the embodiment of the present invention flash memory and for flash memory periphery electricity
The cmos device on road integrates making, and cmos device includes PMOS device and nmos device two types.Described well region 2 wraps
Include N-type well region 2 or P type trap zone 2, N-type well region 2 is located in PMOS device region, and P type trap zone 2 is located at flash area and NMOS device
In part region.
Step 3, grow ground floor silica, second layer silicon nitride and third layer oxygen successively on the surface of described silicon substrate 1
SiClx, using etching technics remove flash area outside described ground floor silica, described second layer silicon nitride and the described 3rd
Layer silica, by the described ground floor silica, described second layer silicon nitride and the described third layer that remain in described flash area
Silica superposition forms ONO layer 4；The grid that described silicon substrate 1 surface outside described flash area forms described cmos device are situated between
Matter layer, deposits one layer of polysilicon layer 5 on described ONO layer and described gate dielectric layer surface, and using ion implantation technology to institute
State polysilicon layer 5 and carry out p-type or n-type doping.Concrete doped region is to be pointed to described flash area and described cmos device
In nmos device region in described polysilicon layer in carry out n-type doping, be pointed to the PMOS device in described cmos device
Carry out p-type doping in described polysilicon layer in region.
Step 4, in described polysilicon layer 5 surface deposited metal tungsten silicide layer 6.
Step 5, using furnace process in described metal silication tungsten layer 6 surface deposition the 4th silicon nitride layer 7, described boiler tube
Technique is LPCVD, and technological temperature is 720 DEG C.Using chemical vapor deposition method in described 4th silicon nitride layer 7 surface deposition
Five silicon nitride layers 8, described chemical vapor deposition method is PECVD, and technological temperature is 400 DEG C.By described 4th silicon nitride layer 7 He
Described 5th silicon nitride layer 8 superposition forms grid hard mask layer.The temperature conditionss meeting of the furnace process of described 4th silicon nitride layer 7
The defect of described ONO layer 4 is carried out repairing and can make the boron ion of the described polysilicon layer 5 of p-type doping to be diffused into described gold
Belong in tungsten silicide layer 6, under conditions of described grid hard mask layer gross thickness is constant, described 4th silicon nitride layer 7 and described the
The thickness of five silicon nitride layers 8 is set to：Enable to described ONO layer 4 in the furnace process time of described 4th silicon nitride layer 7
Under conditions of defect is fully repaired, the thickness of described 4th silicon nitride layer 7 gets over Bao Yuehao；The filling of the boundary defect of described ONO layer 4
Point repair and to be defined by meeting durability test；The condition meeting durability test is：Under 55 DEG C of temperature conditionss, to described sudden strain of a muscle
After depositing into the circulation erase and program operations of row 110K time, flash memory can normally run.Preferably, the thickness of described 4th silicon nitride layer
Spend for 300～600, the thickness of described 5th silicon nitride layer is 900～1200.
Step 6, using photoetching process formed photoetching offset plate figure, defined in described flash area by described photoetching offset plate figure
Go out the gate patterns of described flash memory, described photoetching offset plate figure also defines described cmos device in described cmos device region simultaneously
Gate patterns；The hard mask pattern of formation is performed etching for mask with described photoetching offset plate figure to described grid hard mask layer, by
Described photoetching offset plate figure and described hard mask pattern be mask or individually with described hard mask pattern for mask successively to described gold
Belong to tungsten silicide layer 6 and described polysilicon layer 5 performs etching, the described grid hard mask layer outside etching post tensioned unbonded prestressed concrete region, described gold
Belong to tungsten silicide layer 6 and described polysilicon layer 5 is all removed, by the described grid hard mask layer, the institute that remain in described area of grid
State metal silication tungsten layer 6 and described polysilicon layer 5 forms institute in described flash area and the superposition of described cmos device region respectively
State flash memory and the grid of described cmos device.
Above by specific embodiment, the present invention is described in detail, but these have not constituted the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art also can make many deformation and improve, and these also should
It is considered as protection scope of the present invention.
Claims (7)
1. a kind of manufacture method of flash memory grid is it is characterised in that comprise the steps：
Step one, form shallow trench on a silicon substrate using lithographic etch process, active area is defined by described shallow trench；Institute
State filling silica in shallow trench and form shallow trench field oxygen, by described shallow trench field oxygen, described active area is isolated；
Step 2, carry out ion implanting formed well region；
Step 3, grow ground floor silica, second layer silicon nitride and third layer silica successively on the surface of described silicon substrate,
Remove described ground floor silica outside flash area, described second layer silicon nitride and described third layer silica, by remaining in
The described ground floor silica of described flash area, described second layer silicon nitride and the superposition of described third layer silica form ONO
Layer；Described surface of silicon outside described flash area forms the gate dielectric layer with the integrated cmos device of flash memory, described
Deposit one layer of polysilicon layer on ONO layer and described gate dielectric layer surface, and using ion implantation technology, described polysilicon layer is entered
Row p-type or n-type doping；
It is pointed to carry out N in the described polysilicon layer in the nmos device region in described flash area and described cmos device
Type adulterates, and is pointed to carry out p-type doping in the described polysilicon layer in the PMOS device region in described cmos device；
Step 4, in described polysilicon layer surface deposited metal tungsten silicide layer；
Step 5, using furnace process in described metal silication tungsten layer surface deposition the 4th silicon nitride layer；Formed sediment using chemical gaseous phase
Long-pending technique, in described 4th silicon nitride layer surface deposition the 5th silicon nitride layer, is nitrogenized by described 4th silicon nitride layer and the described 5th
Silicon layer superposition forms grid hard mask layer；The temperature conditionss of the furnace process of described 4th silicon nitride layer can be to described ONO layer
The boundary defect of silicon nitride and silica carries out repairing and can make the boron ion of the described polysilicon layer of p-type doping to be diffused into
In described metal silication tungsten layer, under conditions of described grid hard mask layer gross thickness is constant, described 4th silicon nitride layer and institute
The thickness stating the 5th silicon nitride layer is set to：Enable to described ONO layer in the furnace process time of described 4th silicon nitride layer
Boundary defect fully repair under conditions of, the thickness of described 4th silicon nitride layer gets over Bao Yuehao；
Step 6, define the gate patterns of described flash memory using photoetching process；Right successively according to the gate patterns of lithographic definition
Described grid hard mask layer, described metal silication tungsten layer and described polysilicon layer perform etching, the institute outside etching post tensioned unbonded prestressed concrete region
State grid hard mask layer, described metal silication tungsten layer and described polysilicon layer to be all removed, by remaining in described area of grid
Described grid hard mask layer, described metal silication tungsten layer and the superposition of described polysilicon layer form the grid of described flash memory.
2. flash memory grid as claimed in claim 1 manufacture method it is characterised in that：4th silicon nitride layer described in step 5
Thickness beThe thickness of described 5th silicon nitride layer is
3. flash memory grid as claimed in claim 1 manufacture method it is characterised in that：Described in step 2, well region includes N-type
Well region or P type trap zone, N-type well region is located in the PMOS device region in described cmos device, and P type trap zone is located at described flash memory area
In nmos device region in domain and described cmos device.
4. flash memory grid as claimed in claim 1 manufacture method it is characterised in that：Described in step 5, furnace process is
LPCVD, described chemical vapor deposition method is PECVD.
5. the flash memory grid as described in claim 1 or 4 manufacture method it is characterised in that：The temperature of described furnace process is
720 DEG C, the temperature of described chemical vapor deposition method is 400 DEG C.
6. flash memory grid as claimed in claim 1 manufacture method it is characterised in that：The interface of ONO layer described in step 5
The abundant reparation of defect is defined by meeting durability test.
7. flash memory grid as claimed in claim 6 manufacture method it is characterised in that：The condition meeting durability test is：
Under 55 DEG C of temperature conditionss, after described flash memory is carried out with the circulation erase and program operations of 110K time, flash memory can normally run.
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| CN102956492A (en) * | 2011-08-24 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and manufacture method thereof and MOS (metal oxide semiconductor) transistor and manufacture method thereof |
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2013
- 2013-05-30 CN CN201310210343.6A patent/CN104218001B/en active Active
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|---|---|---|---|---|
| CN101099236A (en) * | 2004-12-22 | 2008-01-02 | 桑迪士克股份有限公司 | Eeprom array with self-aligned shallow-trench isolation |
| CN102054675A (en) * | 2009-11-02 | 2011-05-11 | 中芯国际集成电路制造(上海)有限公司 | Method for forming offset side wall and MOS (metal oxide semiconductor) transistor |
| CN102097308A (en) * | 2009-12-15 | 2011-06-15 | 中芯国际集成电路制造(上海)有限公司 | Side wall etching method |
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