CN104199635A - Pseudo-random number generator integrating CRC (cyclic redundancy check) circuit - Google Patents
Pseudo-random number generator integrating CRC (cyclic redundancy check) circuit Download PDFInfo
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Abstract
The invention discloses a pseudo-random number generator integrating a CRC (cyclic redundancy check) circuit and belongs to the technical field of pseudo-random number generators. The pseudo-random number generator is characterized in that on basis of the CRC circuit, a disturbing module, a status register module, a mapping circuit and a sampling circuit are added, and the pseudo-random number generator can output more reliable pseudo-random numbers, basis is provided for the development of pseudo-random number circuits, and normal execution of CRC has no effect on original functions; meanwhile, few hardware resources are added, efficacy maximization is achieved on the premise of lowest cost, and benefit of the pseudo-random number generator is improved accordingly.
Description
Technical field
The present invention relates to a kind of pseudorandom number generator, relate in particular to a kind of pseudorandom number generator of integrated CRC check circuit.
Background technology
CRC identifying code is cyclic redundancy check (CRC) code, is extensively present in data communication field, and its effect is for checking data.The essence that CRC identifying code produces is the polynomial division of mould 2, the remainder that the check code of generation is division.The generation of its check code can constantly be carried out subtraction and displacement to a generator polynomial by data.In actual applications, for the multiple choices mode of having chosen of generator polynomial.Specifically select which kind of polynomial expression, depend on the regulation of agreement.Such as, in USB3.0 communication protocol, just exist 3 kinds of CRC check codes, for the CRC-16 in packet header, for the CRC-5 of link control word, and for the CRC-32 of data division, this polynomial expression is respectively 100Bh, 00101b and 04C11DB7h.Such as 00101b, represent respectively polynomial expression everybody coefficient from high to low, corresponding polynomial expression is x
5+ x
2+ 1.
The subtraction of mould 2 is xor operation, can with circuit, realize very easily like this.In actual applications, there are serial or parallel implementation.A bit of the each deal with data of serial mode, is used linear feedback shift register (Linear Feedback Shift Registers, LFSR) conventionally.As shown in Figure 1, Fig. 1 is the electrical block diagram of CRC-5 shift register to CRC-5 shift-register circuit in USB3.0.USB3.0 agreement has been stipulated the create-rule of CRC, and when verification calculate to start, register initial value is set as entirely 1, and data start to calculate from low level, and will after result negate, be inverted high-low-position, thereby obtain terminal check code.
For generation of the pseudorandom number generator of pseudo random number, conventionally adopt LFSR to produce and there is macrocyclic random number.This LFSR comprises a plurality of series connection registers and an XOR circuit, and wherein, the output data of predetermined register are fed back to first register by this XOR circuit.Due to XOR circuit being provided in feedback path, thereby make linear feedback shift register produce the random number with longer cycle.
Using pseudo random number to produce in the encrypted circuit etc. of password, if show pseudo-random number sequence or pseudorandom logic, an original plaintext of ciphertext reduction that can obtain from one, thus it is extremely important to make effectively to produce uncertain random number sequence.
Hence one can see that, and pseudorandom number generator of the prior art can not provide relatively pseudo random number reliably, thereby be unfavorable for the circuit exploitation etc. of pseudorandom number generator.
Summary of the invention
Problem for above-mentioned existence, the invention provides a kind of pseudorandom number generator of integrated CRC check circuit, to overcome pseudorandom number generator of the prior art, can not provide the problem of pseudo random number comparatively reliably, thereby both provided pseudo random number comparatively reliably, for the circuit exploitation of pseudorandom number generator provides the foundation, guaranteed again the normal execution of CRC checking, simultaneously, employing hardware resource is few, on the basis of minimum cost, accomplish function maximization, improved product benefit.
To achieve these goals, the technical scheme that the present invention takes is:
A pseudorandom number generator for integrated CRC check circuit, wherein, comprising:
Load module, it is configured to input data to be verified;
CRC check circuit, it is connected to described load module and is configured to data to be tested described in verification;
Interference module, it is configured to input interfering data;
Mapping circuit, it is connected to described interference module and described CRC check circuit, and the state that is configured to shine upon described CRC check circuit then carries out XOR computing with described interfering data;
State is kept in module, and it is connected to described mapping circuit and described CRC check circuit, and is written into described CRC check circuit after being configured to obtain described XOR operation result;
Sampling circuit, it is exported after being connected to described mapping circuit and being configured to extract described XOR operation result.
The pseudorandom number generator of above-mentioned integrated CRC check circuit, wherein, described CRC check circuit is linear feedback shift register.
The pseudorandom number generator of above-mentioned integrated CRC check circuit, wherein, described linear feedback shift register comprises a plurality of registers and a plurality of logical operation door.
The pseudorandom number generator of above-mentioned integrated CRC check circuit, wherein, described logical operation door is exclusive or logic gate.
The pseudorandom number generator of above-mentioned integrated CRC check circuit, wherein, described mapping circuit is comprised of one or more exclusive or logic gates.
The pseudorandom number generator of above-mentioned integrated CRC check circuit, wherein, the temporary module of described state is formed of registers.
The pseudorandom number generator of above-mentioned integrated CRC check circuit, wherein, described sampling circuit is a register.
The pseudorandom number generator of above-mentioned integrated CRC check circuit, wherein, the r of the clock frequency that the clock frequency of described mapping circuit is described sampling circuit times, and r > 1.
Technique scheme tool has the following advantages or beneficial effect:
The pseudorandom number generator of a kind of integrated CRC check circuit provided by the invention, on the basis at CRC check circuit, increase interference module, state temporary module, mapping circuit and sampling circuit, thereby the pseudorandom number generator that has guaranteed this integrated CRC check circuit can be exported pseudo random number comparatively reliably, for the circuit exploitation of pseudorandom number generator provides the foundation, can make again the normal execution of CRC checking, not affect its original function; Meanwhile, the hardware resource of increase is considerably less, thereby on the basis of minimum cost, has accomplished function maximization, and then has improved the product benefit of the pseudorandom number generator of this integrated CRC check circuit.
Accompanying drawing explanation
By reading the detailed description of non-limiting example being done with reference to the following drawings, the present invention and feature thereof, profile and advantage will become more apparent.In whole accompanying drawings, identical mark is indicated identical part.Deliberately proportionally do not draw accompanying drawing, focus on illustrating purport of the present invention.
Fig. 1 is the electrical block diagram of CRC-5 shift register in prior art;
Fig. 2 is the structural representation of the pseudorandom number generator of the integrated CRC check circuit that provides of the embodiment of the present invention 1;
Fig. 3 is the effect schematic diagram of the pseudorandom number generator output random number of the integrated CRC check circuit that provides of the application embodiment of the present invention 1.
Embodiment
Embodiment 1:
Fig. 2 is the structural representation of the pseudorandom number generator of the integrated CRC check circuit that provides of the embodiment of the present invention 1, as shown in the figure, the pseudorandom number generator of the integrated CRC check circuit that the embodiment of the present invention 1 provides comprises: in order to input the load module of data to be verified, the CRC check circuit of the data to be tested that are connected with load module and input in order to verification, in order to input the interference module of interfering data, the mapping circuit being all connected with CRC check circuit with interference module, and this mapping circuit then carries out XOR computing with interfering data in order to shine upon the state of CRC check circuit, the temporary module of state being all connected with CRC check circuit with mapping circuit, the temporary module of this state is written into CRC check circuit after obtaining XOR operation result, be connected with mapping circuit and in order to extract the sampling circuit of exporting after XOR operation result.
In the pseudorandom number generator of the integrated CRC check circuit providing in the embodiment of the present invention 1, CRC check circuit is linear feedback shift register, this linear feedback shift register comprises a plurality of registers and a plurality of logical operation door, and this logical operation door is exclusive or logic gate, adopting this linear feedback shift register is CRC check circuit, the data that can guarantee input are accurately verified, thereby have been guaranteed the normal execution that CRC verifies.
In the pseudorandom number generator of the integrated CRC check circuit providing in the embodiment of the present invention 1, mapping circuit is comprised of one or more exclusive or logic gates, introduce mapping circuit, state to CRC check circuit shines upon, simultaneously together with interference module, obtain the pseudorandom output of a single-bit, the meaning of interference module has been to introduce extra enchancement factor, and output is played to perturbation action.
In the pseudorandom number generator of the integrated CRC check circuit providing in the embodiment of the present invention 1, the temporary module of state is formed of registers, sampling circuit is a register, and the r of the clock frequency that the clock frequency of mapping circuit is sampling circuit doubly, and r > 1, if r is 1.5,2.5,4,7.5,8 etc.; In the non-checking data stage, the temporary module of state is obtained the XOR operation result of output from mapping circuit, and send this XOR operation result to CRC check circuit, after the displacement of CRC check circuit, send mapping circuit to, simultaneously, mapping circuit also obtains interfering data from interference module, carry out by sampling circuit, exporting after logic XOR, thereby obtain pseudo random number, and can export comparatively pseudo random number reliably, for the circuit exploitation of pseudorandom number generator provides the foundation.
When the pseudorandom number generator of the integrated CRC check circuit that the application embodiment of the present invention 1 provides carries out work, needing the data time section of verification, CRC check circuit carries out work in normal mode, when data time section starts, according to protocol requirement, it is complete 1 that linear shift register is set to, and then carries out CRC computing, completes the work of verification; And in other data segment of non-verification or the free time of countless certificates, and the external control module of the pseudorandom number generator of whole integrated CRC check circuit enable signal when effective, this CRC check circuit works on, from the temporary module of state of the present invention, move into data, and input to mapping circuit with the interfering data of interference module output, mapping circuit carries out after corresponding computing to continue to produce random number, thereby reliable pseudo random number is provided.
Below elaborate the principle of work of the pseudorandom number generator of the integrated CRC check circuit that the embodiment of the present invention 1 provides.
In the linear shift register of CRC-m, contain m register, its state is designated as Sti (i=1,2, ..., m), and 1 vector of m bit is designated as to Fm, the state transition function of CRC-m is designated as fcrc, state in the temporary module of state is Ss, Ss is m position, and the temporary choice function of the temporary module of state is fs, is m position, wherein, i position is that 1 expression selects the data of corresponding position in Ss to be written into linear shift register.In the Ss of m position, only having small part position is 1, thus when realizing, Ss only corresponding 1 position need be provided with to register, to save hardware resource.
The computing of n state is designated as,
(1) multiplication in formula represents logical and, addition presentation logic XOR.
Mapping circuit is that the state of CRC check circuit is shone upon, and simultaneously, with together with the interfering data of interference module, obtains the pseudorandom output of a single-bit.The meaning of interference module is to introduce extra enchancement factor, and output is played to perturbation action.The interfering data of interference module is obtained by other and the incoherent node of CRC computing of circuit, is single-bit, is designated as Dn.Mapping function f produces single-bit output from the state of shift register and interference module, comprises m bit, be designated as fi (i=1,2 ... m).In order to keep the harmony of sequence unaffected, mapping circuit adopts XOR computing, thereby obtains XOR operation result.It exports expression formula,
(2) multiplication in formula represents logical and, addition presentation logic XOR.
The effect of the temporary module of state is that the register in the temporary module of state that its Ss represents when non-checking data section is initial is written into shift register by formula (1), and in non-checking data section, other moves into data to Ss from the output of mapping circuit constantly.In checking data section, the data of the temporary module of state are locked, do not change.
So, according to formula (1), non-checking data section, the initial value of the state of CRC check circuit is determined jointly by the final value of last checking data and the final value of last non-checking data section.Avoided so non-checking data section to be directly subject to the impact of checking data, because checking data is communication data, its value is normally completely predictable, and is written into the data of non-verification section last time, just can guarantee the continuity of different non-checking data sections, increase unpredictability.
Sampling circuit is sampled to the output of mapping circuit, and exports random number with the frequency of sampling clock.The sampling clock of sampling circuit is set to be slower than the clock of mapping circuit, interference module, the temporary module of state, CRC check circuit, these modules of load module, the clock of the temporary module of mapping circuit, interference module, state, CRC check circuit, these modules of load module is consistent, and is r times between the sampling circuit module consistent with these.Exporting k position random number can be expressed as,
O(k)＝B(r×k) (3)
From the above, the temporary module of load module, interference module, CRC check circuit, mapping circuit and state works in the master clock frequency of CRC check; Sampling circuit works in sampling clock frequency.
The present invention is applicable to the various occasions of CRC serial circuit, and the selection of m can be worked for the mode that any number or CRC-m are any agreement defined.But, in order to make the variation of random number larger, suitably select that m value is larger, the interfering data of data and interference module changes greatly, can be conducive to strengthen the quality of random number.
The pseudorandom number generator of the integrated CRC check circuit that the embodiment of the present invention 1 provides, based on CRC check circuit, increase a small amount of logic gate, can be applied to does not have absolute requirement to unpredictability, the occasion that does not need true random number, needed filler etc. while need to, send data as the middle supply of SoC (SOC (system on a chip)) embedded software, hardware algorithm.
Fig. 3 is the effect schematic diagram of the pseudorandom number generator output random number of the integrated CRC check circuit that provides of the application embodiment of the present invention 1; As shown in the figure, select the CRC-32 of USB3.0 agreement regulation.Each parameter is selected following f=1010 0,000 0,000 1,000 0,000 0,000 1,000 0000, fs=0000,0,000 0,000 1,111 0,000 0,000 0,000 1111, r=4, selection check data segment 72 bits, free segment 128 bits.
Draw the Two dimensional Distribution of continuous 16 bit random numbers, as shown in the figure.(a) for directly obtain the result of 40000 Bit datas from CRC check circuit and mapping circuit; (b) for adding the result after the temporary module of state; (c) result for adding that the temporary module of state and load module are changed by 0.05 probability; (d), for adding that state keeps in module, load module and interference module change with 0.05 probability, and the result after sampling.
Simultaneously we calculate the entropy of the design data of exporting with the quality of quantitative analysis random number, and its computing formula is,
Wherein i represents that unit of account is i bit, so have 2
iindividual symbol, n is total number of symbols, n
jbe the number of j symbol, H
iresult of calculation more approaches that 1 expression is unreasonable to be thought.
Result while obtaining i=1-6 is 0.9999,0.9988,0.9993,0.9983,0.9953,0.9966.The quality of visible sequence is very good, can meet application requirements.
In Fig. 3, can also see, when without any processing and introducing enchancement factor, data are fixed; The introducing of the temporary module of state makes data become many in the redirect of state space; And as long as introduce very small changing factor in load module and interference module, the random number of the pseudorandom number generator of the integrated CRC check circuit that the embodiment of the present invention 1 provides output can reach very high quality.
The data that obtain in figure are more conservative, and in practical application, the variation probability of load module and interference module is generally greater than 0.05, so result of practical application should, than better in figure, can meet the demands completely.
So, the pseudorandom number generator of the integrated CRC check circuit that the embodiment of the present invention 1 provides, on the basis at CRC check circuit, increase interference module, state temporary module, mapping circuit and sampling circuit, thereby the pseudorandom number generator that has guaranteed this integrated CRC check circuit can be exported pseudo random number comparatively reliably, for the circuit exploitation of pseudorandom number generator provides the foundation, can make again the normal execution of CRC checking, do not affect its original function; Meanwhile, the hardware resource of increase is considerably less, thereby on the basis of minimum cost, has accomplished function maximization, and then has improved the product benefit of the pseudorandom number generator of this integrated CRC check circuit.
It should be appreciated by those skilled in the art that those skilled in the art can realize described variation example in conjunction with prior art and above-described embodiment, do not repeat them here.Such variation example does not affect flesh and blood of the present invention, does not repeat them here.
Above preferred embodiment of the present invention is described.It will be appreciated that, the present invention is not limited to above-mentioned specific implementations, and the equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Any those of ordinary skill in the art, make many possible changes and modification not departing from technical solution of the present invention, or are revised as the equivalent embodiment of equivalent variations, and this does not affect flesh and blood of the present invention.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (8)
1. a pseudorandom number generator for integrated CRC check circuit, is characterized in that, comprising:
Load module, it is configured to input data to be verified;
CRC check circuit, it is connected to described load module and is configured to data to be tested described in verification;
Interference module, it is configured to input interfering data;
Mapping circuit, it is connected to described interference module and described CRC check circuit, and the state that is configured to shine upon described CRC check circuit then carries out XOR computing with described interfering data;
State is kept in module, and it is connected to described mapping circuit and described CRC check circuit, and is written into described CRC check circuit after being configured to obtain described XOR operation result;
Sampling circuit, it is exported after being connected to described mapping circuit and being configured to extract described XOR operation result.
2. the pseudorandom number generator of integrated CRC check circuit as claimed in claim 1, is characterized in that, described CRC check circuit is linear feedback shift register.
3. the pseudorandom number generator of integrated CRC check circuit as claimed in claim 2, is characterized in that, described linear feedback shift register comprises a plurality of registers and a plurality of logical operation door.
4. the pseudorandom number generator of integrated CRC check circuit as claimed in claim 3, is characterized in that, described logical operation door is exclusive or logic gate.
5. the pseudorandom number generator of integrated CRC check circuit as claimed in claim 1, is characterized in that, described mapping circuit is comprised of one or more exclusive or logic gates.
6. the pseudorandom number generator of integrated CRC check circuit as claimed in claim 1, is characterized in that, the temporary module of described state is formed of registers.
7. the pseudorandom number generator of integrated CRC check circuit as claimed in claim 1, is characterized in that, described sampling circuit is a register.
8. the pseudorandom number generator of integrated CRC check circuit as claimed in claim 1, is characterized in that, the r of the clock frequency that the clock frequency of described mapping circuit is described sampling circuit times, and r > 1.
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