CN104155035A - Pressure sensor forming method - Google Patents
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- CN104155035A CN104155035A CN201410425363.XA CN201410425363A CN104155035A CN 104155035 A CN104155035 A CN 104155035A CN 201410425363 A CN201410425363 A CN 201410425363A CN 104155035 A CN104155035 A CN 104155035A
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Abstract
A pressure sensor forming method includes the steps that a semiconductor substrate is provided; a bottom electrode layer is formed on the semiconductor substrate; a sacrificial layer is formed on the semiconductor substrate, and the bottom electrode layer is covered with the sacrificial layer; a top electrode layer is formed, and the top face and the side faces of the sacrificial layer and part of the semiconductor substrate are covered with the top electrode layer; the top electrode layer is processed through laser annealing; after the laser processing, an opening penetrating through the top electrode layer in the thickness direction is formed in the top electrode layer, and the sacrificial layer is exposed out of the opening; the sacrificial layer is removed through the opening. Through the pressure sensor forming method, the performance of a formed pressure sensor can be improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of formation method of pressure transducer.
Background technology
Along with the development of MEMS (micro electro mechanical system) (Micro-Electro-Mechanical-System, MEMS) technology, various sensors have been realized microminaturization.
In the sensor of current various microminaturizations, applying more one is MEMS pressure transducer, MEMS pressure transducer can utilize the sensitive thin film in MEMS to receive external pressure information, treated the signal converting circuit is amplified, thereby measure concrete pressure information.MEMS pressure transducer is widely used in automotive electronics such as TPMS (system for monitoring pressure in tyre), and consumer electronics are such as tire gauge, sphygmomanometer, and industrial electronic is such as fields such as digital pressure gauge, digital stream scale, industrial batching weighings.
According to the difference of pressure transducer principle of work, pressure transducer can be divided into three kinds of condenser types, piezoelectric type, pressure resistance type.Wherein, the pressure measurement parts of capacitance pressure transducer, are sensitive thin film, this sensitive thin film is in order to the cavity of overburden pressure sensor self, in other words, cavity pressure is born on a surface of this sensitive thin film, outside pressure is born on another surface, correspondingly, its principle that realizes pressure measurement is: sensitive thin film and a parallel electrode composition capacity plate antenna with it, in the time that ambient pressure changes, sensitive thin film deforms because the pressure in outside pressure and self cavity there are differences, thereby the capacitance size of capacity plate antenna is changed, can calculate the size of ambient pressure by measuring the capacitance variations of capacity plate antenna.
But the pressure transducer performance that the formation method of existing pressure transducer forms is not good.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of pressure transducer, the performance of the pressure transducer being formed to improve.
For addressing the above problem, the invention provides a kind of formation method of pressure transducer, comprising:
Semiconductor base is provided;
On described semiconductor base, form bottom electrode layer;
On described semiconductor base, form sacrifice layer, described sacrifice layer covers described bottom electrode layer;
Form top electrode layer, described top electrode layer covers the described semiconductor base of end face, side and part of described sacrifice layer;
Described top electrode layer is carried out to laser annealing processing;
After described laser treatment, in described top electrode layer, form the opening that runs through described top electrodes layer thickness, described opening exposes described sacrifice layer;
Remove described sacrifice layer by described opening.
Optionally, the material of described top electrode layer is poly-SiGe.
Optionally, the thickness range of described top electrode layer is
Optionally, the laser power scope of described laser annealing processing employing is 0.5J/cm
2～10J/cm
2.
Optionally, it is pulse laser that the laser adopting is processed in described laser annealing, and each recurrence interval of described pulse laser comprises laser duration and interval time, and the described laser duration is 1ns～200ns, and be 10ns～1000ns described interval time.
Optionally, described laser annealing is processed and is carried out at ambient temperature, and carries out under the atmospheric condition of nitrogen or argon gas.
Optionally, the length range of described top electrode layer is 40 μ m～100 μ m, and width range is 40 μ m～100 μ m.
Optionally, adopt Low Pressure Chemical Vapor Deposition to form described top electrode layer.
Optionally, forming the temperature range that described top electrode layer adopts is 420 DEG C～440 DEG C.
Optionally, described semiconductor base comprises control circuit, the first interconnection structure and the second interconnection structure, described bottom electrode layer is electrically connected described control circuit by described the first interconnection structure, and described top electrode layer is electrically connected described control circuit by described the second interconnection structure.
Compared with prior art, technical scheme of the present invention has the following advantages:
In technical scheme of the present invention, after forming top electrode layer, top electrode layer is carried out to laser annealing processing, laser annealing processing can make top electrode layer reach higher annealing temperature, thereby top electrode layer is annealed fully, make the internal stress of top electrode layer be reduced to fully little level, eliminate the adverse effect that internal stress is brought; Reduce on the other hand the resistivity of the top electrode layer forming, improve the electric conductivity of top electrode layer.Therefore, two aspects can both improve the performance of formed pressure transducer.And described laser annealing processing can only be annealed to top electrode layer, and can not cause adverse effect to the other parts of pressure transducer.
Further, the laser power scope that laser annealing processing adopts is 0.5J/cm
2～10J/cm
2.Laser power is selected relevant to the thickness of top electrode layer.If laser power is greater than 10J/cm
2, laser may see through top electrode layer, circuit devcie is below caused damage, and if laser power is less than 0.5J/cm
2, cannot fully anneal to top electrode layer, and then cannot make formed top electrode layer meet corresponding internal stress level and resistivity level.
Brief description of the drawings
Fig. 1 to Figure 10 is the structural representation corresponding to the each step of formation method of the pressure transducer that provides of the embodiment of the present invention.
Embodiment
As described in background, the pressure transducer performance that existing method forms is not good.Further analyze reason, originally, existing method, in the time of the top electrode layer of mineralization pressure sensor, conventionally adopt boiler tube technique to form, but the top electrode layer internal stress that boiler tube technique forms is larger, and resistivity is also larger.And top electrode layer is as cavity (cavity is between bottom electrode and the top electrodes) top crown of senses change in pressure, what require that its internal stress tries one's best is low, to can obtain change value of pressure accurately, what require that its resistance tries one's best is low simultaneously, to can obtain better conductive characteristic.And if top electrode layer internal stress is larger, itself easily splits, and pressure transducer was lost efficacy.Even if top electrode layer does not split, also easily produce bending or warpage, thereby cavity capacitance is changed, and then it is inaccurate to cause the pressure measured to change, be i.e. pressure transducer hydraulic performance decline.
For addressing the above problem, the invention provides a kind of formation method of pressure transducer, described method provides semiconductor base, on described semiconductor base, form bottom electrode layer, on described semiconductor base, form sacrifice layer, described sacrifice layer covers described bottom electrode layer, form top electrode layer, described top electrode layer covers the end face of described sacrifice layer, the described semiconductor base of side and part, described top electrode layer is carried out to laser annealing processing, after described laser treatment, in described top electrode layer, form the opening that runs through described top electrodes layer thickness, described opening exposes described sacrifice layer, remove described sacrifice layer by described opening.Described method is after forming top electrode layer, top electrode layer is carried out to laser annealing processing, make on the one hand the internal stress of top electrode layer be reduced to fully little level, eliminate the adverse effect that internal stress is brought, reduce on the other hand the resistivity of the top electrode layer forming, thereby improve the performance of pressure transducer.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
The embodiment of the present invention provides a kind of formation method of pressure transducer, incorporated by reference to referring to figs. 1 to Figure 10.
Please refer to Fig. 1, semiconductor base is provided, described semiconductor base comprises Semiconductor substrate (not shown) and is positioned at the dielectric layer 100 in described Semiconductor substrate.
In the present embodiment, described semiconductor base also comprises control circuit (not shown), the first interconnection structure and the second interconnection structure.In Fig. 1, show that the first interconnection structure comprises interconnection line 101 and connector 102, interconnection line 101 and connector 102 are electrically connected, and interconnection line 101 is electrically connected to described control circuit.The second interconnection structure comprises interconnection line 104, interconnection line 107, connector 105 and connector 108.Interconnection line 104 is electrically connected connector 105, and interconnection line 107 is electrically connected connector 108, and interconnection line 104 is electrically connected described control circuit, and interconnection line 107 is electrically connected described control circuit.
Described Semiconductor substrate can be silicon substrate, germanium substrate, III-group Ⅴ element compound substrate, silicon carbide substrates or its rhythmo structure, also can be silicon on insulated substrate or diamond substrate, can also be to well known to a person skilled in the art other semiconductive material substrate.In the present embodiment, described Semiconductor substrate is specially silicon substrate.
In the present embodiment, in described semiconductor base, can also comprise other device architectures, such as amplifier, D/A, analog processing circuit and/or digital processing circuit, interface circuit etc., the formation method of these device architectures can be all CMOS technique.
In the present embodiment, described control circuit can be cmos circuit, and the material of dielectric layer can be monox, and the material of interconnection line can be aluminium or copper, and the material of connector can be copper or tungsten.The formation method of dielectric layer, interconnection line and connector, by those skilled in the art are known, does not repeat them here.
In the present embodiment, between each connector and dielectric layer 100, can also form diffusion impervious layer (not mark).Diffusion impervious layer can prevent that the metal material in each connector from diffusing in dielectric layer 100.
Please continue to refer to Fig. 1, on described semiconductor base, form bottom electrode layer 103, interconnection line 106 and interconnection line 109, wherein, bottom electrode layer 103 is electrically connected to described control circuit by the interconnection line 101 in the first interconnection structure and connector 102.And interconnection line 106 and interconnection line 109 belong to a part for described the second interconnection structure.
In the present embodiment, bottom electrode layer 103, interconnection line 106 and interconnection line 109 are all surrounded by dielectric layer 100.In fact, dielectric layer 100 can be sandwich construction, and can adopt multiple processing steps to form, thereby bottom electrode layer 103, interconnection line 106 and interconnection line 109 are enclosed in dielectric layer 100.
In the present embodiment, the material of bottom electrode layer 103 can be the combination in any of aluminium, titanium, zinc, silver, gold, copper, tungsten, cobalt, nickel, tantalum, these metals of platinum one of them or they; Or, can be also nonmetal or their combination in any of these conductions (doping) of polysilicon, amorphous silicon, poly-SiGe, amorphous germanium silicon; Or, be selected from described metal, conductive non-metals one of them and theys' combination in any, and be not limited to these materials, the other materials that also can be known to the skilled person.
In the present embodiment, the material of interconnection line 106 and interconnection line 109 can be identical with the material of bottom electrode layer 103, and they can adopt identical technique together to form, thereby save processing step.
Please refer to Fig. 2, etching dielectric layer 100 is to expose interconnection line and interconnection line.
In the present embodiment, can first on dielectric layer 100, form the photoresist (not shown) of patterning, again taking photoresist as mask, adopt reactive ion etching (Reactive Ion Etching, RIE) technique etching dielectric layer 100, to expose interconnection line 106 and interconnection line 109.
Please refer to Fig. 3, form sacrifice layer 110 on described semiconductor base, sacrifice layer 110 covers bottom electrode layer 103.
In the present embodiment, the end face of bottom electrode layer 103 and side are enclosed in that in dielectric layer 100, (end face and the side that are bottom electrode layer 103 are covered by dielectric layer, whole bottom electrode layer 103 is positioned at dielectric layer 100 inside), therefore, can be by form sacrifice layer 110 on dielectric layer 100, thereby make sacrifice layer 110 cover described bottom electrode layer 103, as shown in Figure 3.
It should be noted that, in other embodiments of the invention, after described bottom electrode layer is formed on semiconductor base, if while all coming out in the end face of bottom electrode layer and side, also can form sacrifice layer at the end face of described bottom electrode layer and side, sacrifice layer directly covers side and the end face of bottom electrode layer.
It should be noted that, in other embodiments of the invention, after described bottom electrode layer is formed on semiconductor base, if while all coming out in the end face of bottom electrode layer and side, also can form other dielectric layer and only cover the side of described bottom electrode layer, and the end face of bottom electrode layer is exposed (being that dielectric layer upper surface flushes with the end face of bottom electrode layer), now can directly on the end face of described bottom electrode layer, form sacrifice layer, and described sacrifice layer is dielectric layer described in cover part simultaneously, it is the area of plane that the area of plane of described sacrifice layer is greater than described bottom electrode layer.
In the present embodiment, the material of sacrifice layer 110 can be amorphous carbon, but is not limited to amorphous carbon, the other materials that also can be known to the skilled person, such as photoresist or polyimide (PI) etc.Can utilize chemical gaseous phase depositing process depositing amorphous carbon, cover in bottom electrode layer 103, utilize afterwards photoetching, etching technics to remove part amorphous carbon, residue covers the amorphous carbon of bottom electrode layer 103, forms sacrifice layer 110.
Please refer to Fig. 4, form top electrode layer 111, cover end face, side and the part semiconductor substrate of sacrifice layer 110, part semiconductor substrate is specially part dielectric layer 100 (being top electrode layer 111 cover part dielectric layers 100) in Fig. 4.And top electrode layer 111 is electrically connected interconnection line 106 and interconnection line 109 that abovementioned steps exposes, and be electrically connected to described control circuit by described the second interconnection structure being formed by each interconnection line and connector.
In the present embodiment, it is low that the material require of top electrode layer 111 meets formation temperature, internal stress low (being less than 20Mpa) and the feature conducting electricity very well.Therefore can be chosen as poly-SiGe.It should be noted that, in other embodiments of the invention, it is low that top electrode layer 111 also can select other to meet formation temperature, internal stress low (being less than 20Mpa) and the material conducting electricity very well.
In the present embodiment, can adopt Low Pressure Chemical Vapor Deposition (Low Pressure Chemical Vapor Deposition, LPCVD) to form top electrode layer 111.Described Low Pressure Chemical Vapor Deposition can carry out in boiler tube (Furnace) equipment.LPCVD major advantage is to have excellent film equality, and gradient coating performance preferably, and chip that can depositing large-area.Concrete, the forming process of top electrode layer 111 can be: depositing conducting layer (not shown), described conductive layer covers end face and side and the part dielectric layer 100 of sacrifice layer 110, then utilizes photoetching process to carry out graphically described conductive layer, forms top electrode layer 111.
In the present embodiment, the temperature range that formation top electrode layer 111 adopts is 420 DEG C～440 DEG C.Because while forming top electrode layer 111, (CMOS) circuit above forms, in order to ensure that circuit is not subject to temperatures involved, require technological temperature to be below no more than 450 DEG C, and simultaneously in order to retain certain process window (to ensure that formation temperature can have fixed domain of walker), temperature is controlled at below 440 DEG C.But on the other hand,, for adopting LPCVD deposition to form required top electrode layer 111, need to ensure that temperature is more than 420 DEG C.
In the present embodiment, in order to ensure that top electrode layer 111 meets the making requirement of pressure transducer, the thickness range that top electrode layer 111 is set is
the length range of top electrode layer 111 is 40 μ m～100 μ m, and the width range of top electrode layer 111 is 40 μ m～100 μ m, the area of top electrode layer 111 can be (40 μ m × 40 μ m)～(100 μ m × 100 μ m).
Incorporated by reference to reference to figure 4 and Fig. 5, top electrode layer 111 shown in Fig. 4 is carried out to laser annealing and process, until form top electrode layer 112 shown in Fig. 5.
In the present embodiment, it can be pulse laser that the laser (as shown in the arrow in Fig. 4, not mark) adopting is processed in laser annealing, and in each recurrence interval, the laser duration can be 1ns～200ns, and can be 10ns～1000ns interval time.Laser duration and interval time, design parameter was determined by the thickness of top electrode layer 111 not damage circuit devcie (cmos device) below as prerequisite.In the present embodiment, the thickness range of top electrode layer 111 is
therefore the laser duration can be 1ns～200ns, is increased to corresponding annealing temperature with the top electrode layer 111 that ensures respective thickness.Ensure that top electrode layer 111 experiences enough annealing times under corresponding annealing temperature condition interval time, thereby ensured that the quality of the top electrode layer 112 forming after annealing reaches necessary requirement.
In the present embodiment, it is 0.5J/cm that the laser power scope adopting is processed in laser annealing
2～10J/cm
2.Laser power is selected relevant to the thickness of top electrode layer 111.If laser power is greater than 10J/cm
2, laser may see through top electrode layer 111, cmos device is below caused damage, and if laser power is less than 0.5J/cm
2, cannot fully anneal to top electrode layer 111, and then cannot make formed top electrode layer 111 meet corresponding internal stress level and resistivity level.
In the present embodiment, the annealing temperature of laser annealing processing is by laser power (0.5J/cm
2～10J/cm
2) determine.It can be 200nm～600nm that the laser wavelength range adopting is processed in laser annealing.In the time that the power of sharp light wavelength and laser annealing processing is fixed, annealing temperature is just substantially fixing.This enforcement is specifically by controlling power and the wavelength of laser, can make the annealing temperature of top electrode layer 111 reach 1000 DEG C～1300 DEG C, thereby make top electrode layer 111 obtain sufficient annealing in process, ensure that final top electrode layer 111 internal stresss and the resistivity forming is all reduced to comparatively desirable level.And, adopting laser annealing to process and also have a very important reason, i.e. laser annealing processing can be carried out separately top electrode layer 111, and except top electrode layer 111, other structure is the impact of Stimulated Light annealing in process not.
In the present embodiment, laser annealing processing can be carried out at ambient temperature, and can under nitrogen or argon gas atmosphere condition, carry out, and nitrogen or argon gas can prevent that the oxidizing gas such as top electrode layer 111 and oxidation of high temperature in annealing process from reacting.
Please refer to Fig. 6, on top electrode layer 112, form adhesion layer 113.
In the present embodiment, the material of adhesion layer 113 can be silicon nitride, because silicon nitride can strengthen the adhesive attraction between the dielectric layer 116 (please refer to Fig. 9) of top electrode layer 112 and follow-up formation.That is to say, forming adhesion layer 113 objects is the adhesivenesses between the dielectric layer 116 in order to increase top electrode layer 112 and follow-up formation.If there is no adhesion layer 113, the adhesiveness between top electrode layer 112 and dielectric layer is poor, and in the pressure transducer course of work, dielectric layer 116 may depart from top electrode layer 112, affects performance and the durability of pressure transducer.
It should be noted that, in other embodiments of the invention, if good adhesion between top electrode layer and the dielectric layer of follow-up formation, without forming adhesion layer.And if adhesiveness is bad, need to select suitable material as adhesion layer between the two between the two.
Please refer to Fig. 7, in adhesion layer and top electrode layer 112, form opening 114, opening 114 exposes sacrifice layer 110.
In the present embodiment, the forming process of opening 114 is specifically as follows: utilize photoetching and etching technics etching adhesion layer 113 and top electrode layer 112, to form the opening 114 running through in adhesion layer 113 and top electrode layer 112.
Please refer to Fig. 8, remove sacrifice layer 110 by opening 114, between adhesion layer 113 and top electrode layer 112 and bottom electrode layer 103, form cavity 115.
In the present embodiment, the material of sacrifice layer 110 is amorphous carbon, and the method for therefore removing sacrifice layer 110 can be: the oxygen of the ionizations such as employing forms oxygen plasma, more described oxygen plasma is passed into opening 114, be under the condition of 150 DEG C～450 DEG C in temperature range, amorphous carbon described in ashing.The condition that the present embodiment is 150 DEG C～450 DEG C in temperature range is gone down except amorphous carbon, can ensure that control circuit and the interconnection structure in semiconductor base is injury-free.
Please refer to Fig. 9, form dielectric layer 116 and cover top electrode layer 112 and dielectric layer 110.
In the present embodiment, the material of dielectric layer 116 can be silicon dioxide equally, and it forms technique and is well known to those skilled in the art, and does not repeat them here.
Please refer to Figure 10, on dielectric layer 116, form the top electrode layer isolating 112 parts between 117, two openings 117 of two openings as pressure sensing district.
In the formation method of the pressure transducer that the present embodiment provides, after forming top electrode layer 111, top electrode layer 111 is carried out to laser annealing processing, thereby after making on the one hand laser annealing process, the internal stress of top electrode layer 112 is reduced to fully little level, eliminate the adverse effect that internal stress is brought, reduce on the other hand the resistivity of the top electrode layer 112 forming, thereby improve the performance of pressure transducer.
Concrete, the formation method of the pressure transducer that employing the present embodiment provides can make the internal stress of top electrode layer 112 be controlled at below 5MPa, even close to zero internal stress, and resistivity is controlled at below 1m Ω cm, thereby corresponding pressure transducer performance is significantly improved.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a formation method for pressure transducer, is characterized in that, comprising:
Semiconductor base is provided;
On described semiconductor base, form bottom electrode layer;
On described semiconductor base, form sacrifice layer, described sacrifice layer covers described bottom electrode layer;
Form top electrode layer, described top electrode layer covers the described semiconductor base of end face, side and part of described sacrifice layer;
Described top electrode layer is carried out to laser annealing processing;
After described laser treatment, in described top electrode layer, form the opening that runs through described top electrodes layer thickness, described opening exposes described sacrifice layer;
Remove described sacrifice layer by described opening.
2. formation method as claimed in claim 1, is characterized in that, the material of described top electrode layer is poly-SiGe.
3. formation method as claimed in claim 2, is characterized in that, the thickness range of described top electrode layer is
4. formation method as claimed in claim 3, is characterized in that, it is 0.5J/cm that the laser power scope adopting is processed in described laser annealing
2～10J/cm
2.
5. formation method as claimed in claim 4, it is characterized in that, it is pulse laser that the laser adopting is processed in described laser annealing, each recurrence interval of described pulse laser comprises laser duration and interval time, the described laser duration is 1ns～200ns, and be 10ns～1000ns described interval time.
6. formation method as claimed in claim 1, is characterized in that, described laser annealing is processed and carried out at ambient temperature, and carries out under the atmospheric condition of nitrogen or argon gas.
7. formation method as claimed in claim 1, is characterized in that, the length range of described top electrode layer is 40 μ m～100 μ m, and width range is 40 μ m～100 μ m.
8. formation method as claimed in claim 1, is characterized in that, adopts Low Pressure Chemical Vapor Deposition to form described top electrode layer.
9. formation method as claimed in claim 1, is characterized in that, the temperature range that forms described top electrode layer employing is 420 DEG C～440 DEG C.
10. formation method as claimed in claim 1, it is characterized in that, described semiconductor base comprises control circuit, the first interconnection structure and the second interconnection structure, described bottom electrode layer is electrically connected described control circuit by described the first interconnection structure, and described top electrode layer is electrically connected described control circuit by described the second interconnection structure.
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