CN104143992B - LDPC encoding method based on bit stuffing - Google Patents

Abstract

An LDPC encoding method based on bit stuffing is characterized by comprising the steps that (1) synchronous head and information bit extraction is performed on received AOS standard frame data, and n bit parallel information bit data flow capable of performing parallel encoding is obtained through information bit sorting and bit stuffing; (2) extension is performed to generate a matrix; (3) LDPC parallel encoding is performed to generate a check bit; (4) sorting is performed to form AOS standard frame format data flow for output. The LDPC encoding method based on bit stuffing has the advantages of being low in hardware overhead, high in processing speed and applicability, easy to implement in an engineering mode, stable and reliable; besides, the design method has obvious advantages in application in the aerospace field.

Description

A kind of LDPC coded methods based on bit padding

Technical field

The invention belongs to satellite remote sensing technology field, more particularly to a kind of LDPC coded methods based on bit padding.

Background technology

With the high speed development of satellite remote sensing technology, LDPC encoder must in real time complete all kinds of payload mass datas Process and transmission, carried out the development of spaceborne high-speed LDPC encoder of new generation for this, spaceborne high-speed LDPC coding of new generation Device requires that the data rate that can be completed is 5Gbps, and the LDPC encoder of traditional serial process can not meet such height The processing requirement of fast data.

Error correcting code is a key equipment for ensureing remote sensing satellite data transmission subsystem reliability, main in current telecommunication satellite Using error correcting code be CCSDS131.1-O-2 standard recommendations 7/8 code check (8176,7154) code shortening code form LDPC (8160,7136) code, the error correcting code has the advantages that resources occupation rate is relatively low, coding and decoding is relatively easy and error correcting capability is stronger.

This kind of LDPC code that CCSDS recommends is encoded according to AOS standard frame formats to load forward data.AOS Standard frame be 1024 bytes (8192 bits, remove 32 bit frame heads after remaining 8160 bit), detail parameters referring to CCSDS mark It is accurate.

LDPC (8176, it is 7154) linear block codes, most basic coded method is realized with the serial mode of list bit , its cataloged procedure is represented by following matrix multiplication：

C_1×n=m_1×kG_k×n

Wherein, C_1×nFor the code word after LDPC codings, m_1×kFor information bit, G_k×nFor generator matrix.

The generator matrix G of the LDPC code_qcForm is as follows：

Wherein, B_i,jBe size be 511 × 511 circular matrix, matrix P_7154×1022By B_i,jTheory of Circular Matrix piecemeal, has r =14 rows, c=2 row, block length is represented with L=511.So, check bit can be written as：

Information bit is divided into into the sub-block of 14 a length of 511, i.e. m_1×7154=(M₁ M₂…M₁₄), then check bit is：

Using partitioning of matrix characteristic, long vector (1 × 7154) can be decomposed with the multiplication of big matrix (7154 × 1022) For 14 × 2 511bit vectors and 511 × 511 multiplications of matrices and 14 × 2 vector additions.So far, computing is further divided Solve as the inner product of two 511bits vector, so as to further be simplified.

The remote sensing satellite of early stage is single due to load categories, and data rate is relatively low, corresponds, early stage LDPC encoder Method for designing it is relatively simple.After receiving the AOS standard frame formats of single bit serials, using the basic serial code knots of LDPC Structure, this kind of coded system is referred to herein as coded system one.

In coded system one, the AOS standard frames that the data flow of coding processing device is generally the serial of list bit are sent in front Formatted data stream, concrete form is as shown in figure 4, the flow chart of data processing of coded system one is as shown in Figure 5.This single bit serials Coded method is used in actual FPGA realizations, and clock frequency highest is capable of achieving 200MHz or so, and maximum real-time coding speed is 200Mbps。

With the development of satellite remote sensor, the LDPC encoder method for designing of early stage cannot meet remote sensing of new generation and defend The demand of star, the data output rate of remote sensor of new generation is in more than 5Gbps, it is impossible to which real-time coding is processed；In order to improve coding The processing speed of device, existing Conventional solutions are：On the basis of coded system one it is data cached using FIFO by the way of, It is n roads with single-pass data stream caching, is then worked simultaneously with n roads serial LDPC encoder, after the completion of coding, then is cached with FIFO N circuit-switched datas are cached back again original single-pass data stream by data, and this kind of processing mode is referred to as into coded system two.

High-speed data process under, front send into coding processing device data flow be generally n bit (n=2,4,8,16, 32....) parallel AOS standard frame format data flows, concrete form is as shown in fig. 6, handling process such as Fig. 7 of coded system two Shown, code rate can be risen to original n times by the method for designing, although meet real-time coding rate requirement in theory. But the design has several clearly disadvantageous parts：First, handling process is numerous and diverse, considerably increases the complexity of coding； Second, introducing FIFO carries out data buffer storage, has both added the Read-write Catrol logic of FIFO, also substantially increases during subchannel The error probability of data processing.3rd, parallel serial conversion is carried out to input data, the problem of cross clock domain can be so introduced, increase Plus metastable risk and unnecessary clock and the wasting of resources；4th, resource occupation is more, has used substantial amounts of FIFO to provide Source, and n list bit serial encoders work simultaneously, the logical resource for using is at least n times of list bit serial encoders.

The content of the invention

It is an object of the invention to overcome the shortcomings of two kinds of common coded systems, there is provided a kind of LDPC based on bit padding Coded method, the method is realized using parallel LDPC codings, disclosure satisfy that high-speed data process and realization is simple, to reach hardware Resource is few, and design complexity is low, realization is simple, the characteristics of reliability is high.

The above-mentioned purpose of the present invention is achieved by following technical proposals：

A kind of LDPC coded methods based on bit padding, comprise the following steps：

(1) data of the AOS standard frames of 8192bit to receiving, extract 32bit synchronous heads, and whole through information bit Reason and bit padding obtain the information bit of 7168bit, and concrete methods of realizing is as follows：

A () extracts 32bit synchronous heads in the AOS standard frames of 8192bit, respectively and shortens the 7136bit letters of code form Breath position；

B () fills the data 0 of 18bit before step (a) extracts the 7136bit information bits for obtaining, described information position is whole Manage the 7154bit information bits for standard code form；

C 7154bit information bits that () obtains step (b) are divided into 14 sections, and 511bit numbers are included in each described section According to, fill the data 0 of 1bit after last bit data in 14 sections respectively, the 7154bit information bits are filled For 7168bit information bits；

(2) extend LDPC (8176,7154) code generator matrix, will 7154*1022 dimension matrix P expand to 7168*1022 Dimension matrix P ', concrete methods of realizing is as follows：

(8176,7154) code generator matrix G=[I P], wherein I are the list of 7154*7154 dimensions to LDPC in CCSDS standards Bit matrix, P is that the 7154*1022 being made up of 28 circular matrixes ties up matrix：

Wherein, B_i,jCircular matrix, i.e. matrix B are tieed up for 511*511_i,jThe second row to last column data, before being it Data line circulates to the right 1 and obtains：

I=1～14 are positive integer, j=1,2

By the circular matrix B_i,jLast column data circulate one to the right and obtain data line, by a line number According to being added on matrix B_i,jLast column after, form 512*511 dimensional expansions exhibition matrix B '_i,j：

I=1～14 are positive integer, j=1,2

By the extended matrix B '_i,jComposition 7168*1022 dimension matrix P '：

(3) LDPC parallel encodings are carried out, will step (1) it is collated and the 7168bit information bits that obtain of filling adopt n positions Parallel input mode is input into, and is multiplied with the matrix P ', generates the check bit of 1022bit, and the 1022bit check bit that will be generated 2bit data 0 are filled below, 1024bit check bit is obtained, and n is encoder bit wide and n=2^k, k is 1～9 natural number；

(4) the 1024bit check bit that the 7168bit information bits and step (3) for being obtained using step (1) is obtained, Yi Jibu Suddenly the 32bit synchronous heads for directly extracting from AOS standard frames in (1), the LDPC for obtaining the AOS standard frame formats of 8192bit is compiled Code device output frame, concrete methods of realizing is as follows：

A the 7168bit information bits that step (1) is obtained averagely are divided into 14 sections by (), include in each section 512bit data, respectively delete last bit data 0 in 14 sections, are to be reduced to by the 7168bit information 7154bit information bits；

The data 0 of b 7154bit information bits foremost 18bit that () obtains step (a) reduction are deleted, by described information Position is reduced to shorten the 7136bit information bits of code form；

C the 32bit synchronous heads directly extracted from AOS standard frames in step (1) are filled in the 7136bit information bits by () Before, and by the 1024bit check bit that step (3) is obtained it is filled in after the 7136bit information bits, obtains 8192bit's AOS standard frames, and the standard frame is exported using nbit parallel modes.

In the above-mentioned LDPC coded methods based on bit padding, step (3) carries out LDPC parallel encodings, will step (1) 7168bit information bits=[c that collated and filling is obtained₁、c₂、c₃、…、c₇₁₆₈] be input into using n parallel-by-bits input mode, It is multiplied with the matrix P ', generates the check bit of 1022bit, the calculating process adopts two circulating registers by Group B1, B2 and two depositors a1, a2 deposit data：

Wherein, two circulating register groups B1, B2, each circulating register group is posted including n cyclic shift Storage, the length of the circulating register is 511bit, n circulating register in circulating register group B1 The data of preservation are respectively designated as：[η_1,1、η_1,2、…、η_1,511]、[η_2,1、η_2,2、…、η_2,511]、…、[η_{N, 1}、η_{N, 2}、…、 η_{N, 511}]；The data that n circulating register in circulating register group B2 is preserved are respectively designated as：[γ_1,1、 γ_1,2、…、γ_1,511]、[γ_2,1、γ_2,2、…、γ_2,511]、…、[γ_{N, 1}、γ_{N, 2}、…、γ_{N, 511}]；

Two depositors a1 and a2, the wherein length of each shift register are 511bit；Preserve in depositor a1 Data be denoted as：[α₁、α₂、…、α₅₁₁]；The data preserved in depositor a2 are denoted as：[β₁、β₂、…、β₅₁₁]；

The concrete methods of realizing of the calculating process is as follows：

During (1) first clock cycle, parallel input nbit information bits：[c₁、c₂、…、c_n]；

Extended matrix B ' is stored respectively with n circulating register in circulating register group B1_1,1 1 row～line n, n circulating register in circulating register group B2 stores respectively extended matrix B '_1,2's 1 row～line n, and be zero by the preservation data initialization in the depositor a1 and a2, i.e. α_l=0, β_l=0, wherein l=1 ～511 is positive integer；

(2) by step (1) parallel input nbit information bits respectively with the data storage phase of circulating register group B1 Take advantage of and add up and be stored in depositor a1：The l positions of wherein depositor a1 preserve dataL=1,2 ..., 511 is positive integer；

The nbit information bits of the parallel input are multiplied simultaneously respectively with the data stored in circulating register group B2 It is cumulative to be stored in depositor a2：The l positions of wherein depositor a2 preserve dataL=1,2 ..., 511 are Positive integer；

During (3) second clock cycle, parallel input nbit information bits：[c_n+1、c_n+2、…、c_2n]；

And by the n circulating register difference in circulating register group B1 to the right cyclic shift n position, i.e. B1 N circulating register store extended matrix B ' respectively_1,1The (n+1)th row～the 2n rows, update η_{I, j}(i=1～n, j=1 ～value 511)；

And n circulating register in circulating register group B2 is distinguished into cyclic shift n position to the right, circulation is moved N circulating register in bit register group B2 stores respectively extended matrix B '_1,2The (n+1)th row～the 2n rows, update γ_{I, j}(the value of i=1～n, j=1～511)；

(4) by step (3) parallel input nbit information bits respectively with the data storage phase of circulating register group B1 Take advantage of and add up, the accumulation result updates the preservation data in depositor a1 after being added with data storage in depositor a1：Wherein The l positions of depositor a1 preserve data(l=1,2 ..., 511 is positive integer)；

The nbit information bits that step (3) is input into parallel are multiplied simultaneously respectively with the data storage of circulating register group B2 Cumulative, the accumulation result updates the preservation data in depositor a2 after being added with data storage in depositor a2：Wherein deposit The l positions of device a2 preserve data(l=1,2 ..., 511 is positive integer)；

(5) the like, after the 512/n clock cycle, the data vector preserved in depositor a1 is [c₁、c₂、 c₃、…、c₅₁₂]B′_1,1, the data vector preserved in depositor a2 is [c₁、c₂、c₃、…、c₅₁₂]B′_1,2；

During (6) 512/n+1 clock cycle, parallel input nbit information bits：[c₅₁₂₊₁、c₅₁₂₊₂、…、c_512+n]；

Extended matrix B ' is stored respectively with n circulating register in circulating register group B1_2,1 1 row～line n, n circulating register in circulating register group B2 stores respectively extended matrix B '_2,2's 1 row～line n；

According to the calculating process of step (1)～(5), after the 1024/n clock cycle, the data preserved in depositor a1 For [c₁、c₂、c₃、…、c₅₁₂]B′_1,1+[c₅₁₂₊₁、c₅₁₂₊₂、c₅₁₂₊₃、…、c₁₀₂₄]B′_2,1；The data of preservation are in depositor a2: [c₁、c₂、c₃、…、c₅₁₂]B′_1,2+[c₅₁₂₊₁、c₅₁₂₊₂、c₅₁₂₊₃、…、c₁₀₂₄]B′_2,2；

(7) the like, after the 7168/n clock cycle, the data preserved in depositor a1 areDeposit The data of preservation are in device a2Wherein：

M_i=[c_(i-1)*512+1,c_(i-1)*512+2,…,c_{(i-1)*512+512}], i=1～14 are positive integer；

(8) connect the 511bit data that depositor a2 is preserved after the 511bit data that depositor a1 is preserved, obtain 1022bit Check bit.

The present invention has the advantage that compared with prior art：

(1) LDPC coded methods of the invention, using nbit parallel encoding modes, the serial code mode phase with single bit Than, the real-time processing speed of data can be greatly improved, data processing rate is improve into n times, disclosure satisfy that current satellite leads to The mission requirements of Large Copacity, high speed data transfers in letter, comply with the development trend of real time data processing.

(2) LDPC coded methods of the invention, without the need for becoming to front input parallel data format in parallel encoding Change, coder module can be directly invoked, complete parallel encoding process.Handling process is simple, easily realizes, greatly reduces using volume The complexity of code device.

(3) LDPC coded methods of the invention, it is not necessary to data are cached, going out in data handling procedure is reduced Wrong probability, it is to avoid occur wrong frame, the phenomenon of falling frame during data cached using FIFO/RAM.

(4) LDPC coded methods of the invention, can real-time processing data, there is no real time data process of caching, it is to avoid Partial data is detained in the buffer in prior art coded system two (recording in the introduction) the drawbacks of.

(5) LDPC coded methods of the invention, only need to a kind of clock frequency in whole cataloged procedure, it is to avoid serial data And change and branch during introduce multiple clock frequencies caused by cross clock domain problem, reduce metastable risk with not Necessary clock sources are wasted.

(6) LDPC coded methods of the invention, have saved resource and have used, relative to prior art coded system two, we Method can reduce FIFO resource usage amounts, and reduce the usage amount of logical resource, wherein, encoder word width n economizes on resources more greatly effect Fruit is more obvious.

Description of the drawings

Fig. 1. implement process chart for LDPC coded methods of the present invention；

Fig. 2. for the process chart of LDPC coded methods of the present invention；

Fig. 3. for the SRAA circuit diagrams that LDPC parallel encodings of the present invention are realized；

Fig. 4. for coding processing device AOS standard frame format data-stream form in coded system one；

Fig. 5. for the flow chart of data processing figure of coded system one；

Fig. 6. for the parallel AOS standard frame format data-stream forms of coded system two；

Fig. 7. for the flow chart of data processing figure of coded system two；

Specific embodiment

Below in conjunction with the accompanying drawings the present invention is described in further detail with specific embodiment：

In the method LDPC coding be to carry out by frame, to data flow in each frame data do with process, therefore Only the processing procedure of a frame data is explained in invention, specified otherwise is no longer done in follow-up elaboration, as shown in Fig. 2 parallel Input nbit AOS standard frame format data flows, using the LDPC coded methods based on bit padding of the present invention, can be parallel AOS standard frame format data flows after output nbit codings.

LDPC coded method of the present invention based on bit padding, implements process chart as shown in figure 1, specifically including The following steps：

(1) to the data of the AOS standard frames of 8192bit, 32bit synchronous heads are extracted, and is arranged and bit through information bit Filling obtains the information bit of 7168bit, and concrete methods of realizing is as follows：

A () extracts 32bit synchronous heads in the AOS standard frames of 8192bit, respectively and shortens the 7136bit letters of code form Breath position；

In the present embodiment, encoder bit wide n=4, the AOS standard frames of 8192bit are：

From the standard frame extracting data to 7136bit information bits be：

From the standard frame extracting data to 32bit synchronous heads be：

B () fills the data 0 of 18bit before step (a) extracts the 7136bit information bits for obtaining, described information position is whole Manage the 7154bit information bits for standard code form；

In the embodiment of encoder bit wide n=4, the 7154bit information bits are：

If (c) encoder bit wide n=2^k, k is 1～9 natural number, works as k>When 1, the 7154bit letters that step (b) is obtained Breath bit length is not the integral multiple of n, in order to encode it is convenient need to carry out bit padding to the information bit, will step (b) obtain 7154bit information bits be divided into 14 sections, 511bit data are included in each described section, respectively in 14 sections most The data 0 of 1bit are filled after latter bit data, the 7154bit information bits are filled to into 7168bit information bits, wherein, 7168 For encoder bit wide n=2^kThe integral multiple of (k is 1～9 natural number)；

In the embodiment of encoder bit wide n=4, the 7168bit information bits are：

(2) in order to corresponding with the information bit after bit padding, need to extend LDPC (8176,7154) code generate square Battle array, will 7154*1022 dimension matrix P expand to 7168*1022 dimension matrix P ', concrete methods of realizing is as follows：

(8176,7154) code generator matrix G=[I P], wherein I are the list of 7154*7154 dimensions to LDPC in CCSDS standards Bit matrix, P is that the 7154*1022 being made up of 28 circular matrixes ties up matrix：

Wherein, B_i,jCircular matrix, i.e. matrix B are tieed up for 511*511_i,jThe second row to last column data, before being it Data line circulates to the right 1 and obtains：

I=1～14 are positive integer, j=1,2

By the circular matrix B_i,jLast column data circulate one to the right and obtain data line, by a line number According to being added on matrix B_i,jLast column after, form 512*511 dimensional expansions exhibition matrix B '_i,j：

I=1～14 are positive integer, j=1,2

By the extended matrix B '_i,jComposition 7168*1022 dimension matrix P '：

(3) LDPC parallel encodings are carried out, will step (1) it is collated and the 7168bit information bits that obtain of filling adopt n positions Parallel mode is input into, and is multiplied with the matrix P ', generates behind the check bit of 1022bit, and the 1022bit check bit that will be generated Filling 2bit data 0, obtain 1024bit check bit, and n is encoder bit wide and n=2^k, k is 1～9 natural number；

In the present embodiment, the 1024bit check bit of 4 parallel-by-bits output is：

(4) the 1024bit check bit that the 7168bit information bits and step (3) for being obtained using step (1) is obtained, Yi Jibu Suddenly the 32bit synchronous heads for directly extracting from AOS standard frames in (1), the LDPC for obtaining the AOS standard frame formats of 8192bit is compiled Code device output frame, concrete methods of realizing is as follows：

A the 7168bit information bits that step (1) is obtained averagely are divided into 14 sections by (), include in each section 512bit data, respectively delete last bit data 0 in 14 sections, are to be reduced to by the 7168bit information 7154bit information bits；

The data 0 of b 7154bit information bits foremost 18bit that () obtains step (a) reduction are deleted, by described information Position is reduced to shorten the 7136bit information bits of code form；

C the 32bit synchronous heads directly extracted from AOS standard frames in step (1) are filled in the 7136bit information bits by () Before, and by the 1024bit check bit that step (3) is obtained it is filled in after the 7136bit information bits, obtains 8192bit's AOS standard frames, and the standard frame is exported using nbit parallel modes.

In the present embodiment, the standard frame for encoding output is：

In the LDPC coded methods based on bit padding of the present invention, step (3) carries out LDPC parallel encodings, will step (1) 7168bit information bits=[c that collated and filling is obtained₁、c₂、c₃、…、c₇₁₆₈] be input into using n parallel-by-bits input mode, It is multiplied with the matrix P ', generates the check bit of 1022bit, the parallel SRAA circuits that it is implemented is as shown in Figure 3.

Wherein, two circulating register groups B1, B2, wherein each described circulating register group include that n is followed Ringed shift register, the length of the circulating register is 511bit；

Wherein, the data that n circulating register in circulating register group B1 is preserved are respectively designated as： [η_1,1、η_1,2、…、η_1,511]、[η_2,1、η_2,2、…、η_2,511]、…、[η_{N, 1}、η_{N, 2}、…、η_{N, 511}]；

Wherein, the data that n circulating register in circulating register group B2 is preserved are respectively designated as： [γ_1,1、γ_1,2、…、γ_1,511]、[γ_2,1、γ_2,2、…、γ_2,511]、…、[γ_{N, 1}、γ_{N, 2}、…、γ_{N, 511}]；

Two depositors a1 and a2, the wherein length of each shift register are 511bit；

Wherein, the data for preserving in depositor a1 are denoted as：[α₁、α₂、…、α₅₁₁]；

Wherein, the data for preserving in depositor a2 are denoted as：[β₁、β₂、…、β₅₁₁]；

Concrete methods of realizing is as follows：

During (1) first clock cycle, parallel input nbit information bits：[c₁、c₂、…、c_n]；

Extended matrix B ' is stored respectively with n circulating register in circulating register group B1_1,1 1 row～line n, n circulating register in circulating register group B2 stores respectively extended matrix B '_1,2's 1 row～line n, and be zero by the preservation data initialization in the depositor a1 and a2, i.e. α_l=0, β_l=0, wherein l=1 ～511 is positive integer；

(2) by step (1) parallel input nbit information bits respectively with the data storage phase of circulating register group B1 Take advantage of and add up and be stored in depositor a1：The l positions of wherein depositor a1 preserve dataL=1,2 ..., 511 is positive integer；

The nbit information bits of the parallel input are multiplied simultaneously respectively with the data stored in circulating register group B2 It is cumulative to be stored in depositor a2：The l positions of wherein depositor a2 preserve dataL=1,2 ..., 511 are Positive integer；

During (3) second clock cycle, parallel input nbit information bits：[c_n+1、c_n+2、…、c_2n]；

And by the n circulating register difference in circulating register group B1 to the right cyclic shift n position, i.e. B1 N circulating register store extended matrix B ' respectively_1,1The (n+1)th row～the 2n rows, update η_{I, j}(i=1～n, j=1 ～value 511)；

And n circulating register in circulating register group B2 is distinguished into cyclic shift n position to the right, circulation is moved N circulating register in bit register group B2 stores respectively extended matrix B '_1,2The (n+1)th row～the 2n rows, update γ_{I, j}(the value of i=1～n, j=1～511)；

(4) by step (3) parallel input nbit information bits respectively with the data storage phase of circulating register group B1 Take advantage of and add up, the accumulation result updates the preservation data in depositor a1 after being added with data storage in depositor a1：Wherein The l positions of depositor a1 preserve data(l=1,2 ..., 511 is positive integer)；

The nbit information bits that step (3) is input into parallel are multiplied simultaneously respectively with the data storage of circulating register group B2 Cumulative, the accumulation result updates the preservation data in depositor a2 after being added with data storage in depositor a2：Wherein deposit The l positions of device a2 preserve data(l=1,2 ..., 511 is positive integer)；

(5) the like, after the 512/n clock cycle, the data vector preserved in depositor a1 is [c₁、c₂、 c₃、…、c₅₁₂]B′_1,1, the data vector preserved in depositor a2 is [c₁、c₂、c₃、…、c₅₁₂]B′_1,2；

During (6) 512/n+1 clock cycle, parallel input nbit information bits：[c₅₁₂₊₁、c₅₁₂₊₂、…、c_512+n]；

Extended matrix B ' is stored respectively with n circulating register in circulating register group B1_2,1 1 row～line n, n circulating register in circulating register group B2 stores respectively extended matrix B '_2,2's 1 row～line n；

According to the calculating process of step (1)～(5), after the 1024/n clock cycle, the data preserved in depositor a1 For [c₁、c₂、c₃、…、c₅₁₂]B′_1,1+[c₅₁₂₊₁、c₅₁₂₊₂、c₅₁₂₊₃、…、c₁₀₂₄]B′_2,1；The data of preservation are in depositor a2: [c₁、c₂、c₃、…、c₅₁₂]B′_1,2+[c₅₁₂₊₁、c₅₁₂₊₂、c₅₁₂₊₃、…、c₁₀₂₄]B′_2,2；

(7) the like, after the 7168/n clock cycle, the data preserved in depositor a1 areDeposit The data of preservation are in device a2Wherein：

M_i=[c_(i-1)*512+1,c_(i-1)*512+2,…,c_{(i-1)*512+512}], i=1～14 are positive integer；

(8) connect the 511bit data that depositor a2 is preserved after the 511bit data that depositor a1 is preserved, obtain 1022bit Check bit.

In the case that following table is encoder bit wide n=4, with the FPGA product realities of xilinx companies 5vfx130tff1738-1 Now, prior art coded system two and resource service condition of the invention：

The above, optimal specific embodiment only of the invention, but protection scope of the present invention is not limited thereto, Any those familiar with the art the invention discloses technical scope in, the change or replacement that can be readily occurred in, All should be included within the scope of the present invention.

The content not being described in detail in description of the invention belongs to the known technology of professional and technical personnel in the field.

Claims (2)

1. a kind of LDPC coded methods based on bit padding, it is characterised in that comprise the following steps：

(1) to the data of the AOS standard frames of 8192bit, 32bit synchronous heads are extracted, and is arranged and bit padding through information bit The information bit of 7168bit is obtained, concrete methods of realizing is as follows：

A () extracts 32bit synchronous heads and shortens the 7136bit information bits of code form in the AOS standard frames of 8192bit, respectively；

B () fills the data 0 of 18bit before step (a) extracts the 7136bit information bits for obtaining, be by the arrangement of described information position The 7154bit information bits of standard code form；

C 7154bit information bits that () obtains step (b) are divided into 14 sections, and 511bit data are included in each described section, point The data 0 of 1bit are not filled after last bit data in 14 sections, the 7154bit information bits are filled to 7168bit information bits；

(2) extend LDPC (8176,7154) code generator matrix, will 7154*1022 dimension matrix P expand to 7168*1022 dimension square Battle array P ', concrete methods of realizing is as follows：

(8176,7154) code generator matrix G=[I P], wherein I are the unit square of 7154*7154 dimensions to LDPC in CCSDS standards Battle array, P is that the 7154*1022 being made up of 28 circular matrixes ties up matrix：

$P=\left[\begin{array}{cc}{B}_{1,1}& B_{2,1}\\ B_{2,1}& B_{2,2}\\ .& .\\ .& .\\ .& .\\ B_{14,1}& B_{14,2}\end{array}\right]$

Wherein, B_i,jCircular matrix, i.e. matrix B are tieed up for 511*511_i,jThe second row to last column data, be its previous row Data circulate to the right 1 and obtain：

I=1～14 are positive integer, j=1,2

By the circular matrix B_i,jLast column data circulate one to the right and obtain data line, the data line is added It is added in matrix B_i,jLast column after, form 512*511 dimensional expansions exhibition matrix B '_i,j：

I=1～14 are positive integer, j=1,2

By the extended matrix B '_i,jComposition 7168*1022 dimension matrix P '：

$P^{\′}=\left[\begin{array}{cc}{B}_{1,1}^{\′}& B_{2,1}^{\′}\\ B_{2,1}^{\′}& B_{2,2}^{\′}\\ .& .\\ .& .\\ .& .\\ B_{14,1}^{\′}& B_{14,1}^{\′}\end{array}\right];$

(3) LDPC parallel encodings are carried out, will step (1) it is collated and the 7168bit information bits that obtain of filling adopt n parallel-by-bits Mode is input into, and is multiplied with the matrix P ', generates and filled behind the check bit of 1022bit, and the 1022bit check bit that will be generated 2bit data 0, obtain 1024bit check bit, and n is encoder bit wide and n=2^k, k is 1～9 natural number；

(4) the 1024bit check bit that the 7168bit information bits and step (3) for being obtained using step (1) is obtained, and step (1) In the 32bit synchronous heads that directly extract from AOS standard frames, the LDPC encoder for obtaining the AOS standard frame formats of 8192bit is defeated Go out frame, concrete methods of realizing is as follows：

A the 7168bit information bits that step (1) is obtained averagely are divided into 14 sections by (), 512bit numbers are included in each section According to, last bit data 0 in 14 sections are deleted respectively, the 7168bit information bits are reduced to into 7154bit letters Breath position；

The data 0 of b 7154bit information bits foremost 18bit that () obtains step (a) reduction are deleted, by described information position also Originally it was the 7136bit information bits for shortening code form；

(c) by the 32bit synchronous heads directly extracted from AOS standard frames in step (1) be filled in the 7136bit information bits it Before, and the 1024bit check bit that step (3) is obtained is filled in after the 7136bit information bits, obtain the AOS of 8192bit Standard frame, and the standard frame is exported using nbit parallel modes.

2. a kind of LDPC coded methods based on bit padding according to claim 1, it is characterised in that：Step (3) is entered Row LDPC parallel encodings, will the collated 7168bit information bits=[c obtained with filling of step (1)₁、c₂、c₃、…、c₇₁₆₈] It is input into using n parallel-by-bits input mode, is multiplied with the matrix P ', generate the check bit of 1022bit, two is adopted in calculating process Individual circulating register group B1, B2 and two depositors a1, a2 deposit data：

Wherein, two circulating register groups B1, B2, each circulating register group includes n circulating register, The length of the circulating register is 511bit, and n circulating register in circulating register group B1 is preserved Data be respectively designated as：[η_1,1、η_1,2、…、η_1,511]、[η_2,1、η_2,2、…、η_2,511]、…、[η_{N, 1}、η_{N, 2}、…、η_{N, 511}]；Follow The data that n circulating register in ringed shift register group B2 is preserved are respectively designated as：[γ_1,1、γ_1,2、…、 γ_1,511]、[γ_2,1、γ_2,2、…、γ_2,511]、…、[γ_{N, 1}、γ_{N, 2}、…、γ_{N, 511}]；

Two depositors a1 and a2, the wherein length of each shift register are 511bit；The number preserved in depositor a1 According to being denoted as：[α₁、α₂、…、α₅₁₁]；The data preserved in depositor a2 are denoted as：[β₁、β₂、…、β₅₁₁]；

The concrete methods of realizing of the calculating process is as follows：

During (1) first clock cycle, parallel input nbit information bits：[c₁、c₂、…、c_n]；

Extended matrix B ' is stored respectively with n circulating register in circulating register group B1_1,1The 1st row ～line n, n circulating register in circulating register group B2 stores respectively extended matrix B '_1,2The 1st Row～line n, and be zero by the preservation data initialization in the depositor a1 and a2, i.e. α_l=0, β_l=0, wherein l=1～ 511 is positive integer；

(2) the nbit information bits that step (1) is input into parallel are multiplied simultaneously respectively with the data storage of circulating register group B1 It is cumulative to be stored in depositor a1：The l positions of wherein depositor a1 preserve dataL=1,2 ..., 511 are Positive integer；

The nbit information bits of the parallel input are multiplied and are added up with the data stored in circulating register group B2 respectively It is stored in depositor a2：The l positions of wherein depositor a2 preserve dataL=1,2 ..., 511 is just whole Number；

During (3) second clock cycle, parallel input nbit information bits：[c_n+1、c_n+2、…、c_2n]；

And n circulating register in circulating register group B1 is distinguished into the n in cyclic shift n position, i.e. B1 to the right Individual circulating register stores respectively extended matrix B '_1,1The (n+1)th row～the 2n rows, update η_{I, j}(i=1～n, j=1～ 511) value；

And n circulating register in circulating register group B2 is distinguished into cyclic shift n position to the right, cyclic shift is posted N circulating register in storage group B2 stores respectively extended matrix B '_1,2The (n+1)th row～the 2n rows, update γ_{I, j}(i The value of=1～n, j=1～511)；

(4) the nbit information bits that step (3) is input into parallel are multiplied simultaneously respectively with the data storage of circulating register group B1 Cumulative, the accumulation result updates the preservation data in depositor a1 after being added with data storage in depositor a1：Wherein deposit The l positions of device a1 preserve data(l=1,2 ..., 511 is positive integer)；

The nbit information bits that step (3) is input into parallel are multiplied and are tired out with the data storage of circulating register group B2 respectively Plus, the accumulation result updates the preservation data in depositor a2 after being added with data storage in depositor a2：Wherein depositor The l positions of a2 preserve data(l=1,2 ..., 511 is positive integer)；

(5) the like, after the 512/n clock cycle, the data vector preserved in depositor a1 is [c₁、c₂、c₃、…、 c₅₁₂]B′_1,1, the data vector preserved in depositor a2 is [c₁、c₂、c₃、…、c₅₁₂]B′_1,2；

During (6) 512/n+1 clock cycle, parallel input nbit information bits：[c₅₁₂₊₁、c₅₁₂₊₂、…、c_512+n]；

Extended matrix B ' is stored respectively with n circulating register in circulating register group B1_2,1The 1st row ～line n, n circulating register in circulating register group B2 stores respectively extended matrix B '_2,2The 1st Row～line n；

According to the calculating process of step (1)～(5), after the 1024/n clock cycle, the data preserved in depositor a1 are [c₁、 c₂、c₃、…、c₅₁₂]B′_1,1+[c₅₁₂₊₁、c₅₁₂₊₂、c₅₁₂₊₃、…、c₁₀₂₄]B′_2,1；The data of preservation are in depositor a2:[c₁、c₂、 c₃、…、c₅₁₂]B′_1,2+[c₅₁₂₊₁、c₅₁₂₊₂、c₅₁₂₊₃、…、c₁₀₂₄]B′_2,2；

(7) the like, after the 7168/n clock cycle, the data preserved in depositor a1 areIn depositor a2 The data of preservation areWherein：

M_i=[c_(i-1)*512+1,c_(i-1)*512+2,…,c_{(i-1)*512+512}], i=1～14 are positive integer；

(8) connect the 511bit data that depositor a2 is preserved after the 511bit data that depositor a1 is preserved, obtain the school of 1022bit Test position.