CN104143983B - Continuous Approximation formula analog-digital converter and its method - Google Patents
Continuous Approximation formula analog-digital converter and its method Download PDFInfo
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Abstract
A kind of Continuous Approximation formula analog-digital converter and its method, especially during each position in during last several determine is determined, first current potential and the second current potential in sampling and D/A conversion circuit repeatedly compared to obtain multiple comparative results using comparator is continuous, then again by Continuous Approximation formula controls circuit to produce corresponding carry-out bit according to obtained multiple comparative results.
Description
Technical field
The present invention relates to a kind of Analog-digital Converter technology, more particularly to a kind of Continuous Approximation formula analog-digital converter
（SAR ADC）And its method.
Background technology
Analog-digital converter（analog-to-digital converter；ADC）There are a variety of frameworks, for example：Flash type
（flash）ADC, pipeline type（pipelined）ADC, Continuous Approximation formula（successive-approximation-register；
SAR）ADC etc..The each have their own advantage of these frameworks, it will usually selected according to different application demands.Wherein, Continuous Approximation formula
ADC is compared with other frameworks consumption lower-wattage, compared with small area and lower cost.
Traditionally, SAR ADC are to use binary search algorithm（binary search algorithm）Come obtain with it is defeated
Enter the digital output code that signal matches.In transfer process, according to the comparative result of comparator each time, in SAR ADC
D/A conversion circuit is generally required for adding deduct the voltage of a binary scale, to last bit period（bit
cycle）After end, the gap of input signal and reference voltage will be less than a least significant bit（least
significant bit；LSB）.However, when input signals are small, it is easily by noise jamming（This interference include comparator,
Chip system in itself, the interference of power supply etc.）, and then cause to judge by accident.
The content of the invention
In one embodiment, a kind of Continuous Approximation formula analog-digital conversion method includes：By being carried out to an analog signal
Sample to produce one first current potential, recur according on first current potential and the D/A conversion circuit using a comparator
Multiple second current potentials sequentially produce multiple carry-out bits and export a data signal based on this little carry-out bit.In this, this little
Two current potentials correspond respectively to these carry-out bits.Wherein, the generation step of last carry-out bit using a comparator to first
The second current potential that current potential occurs with last time is carried out continuously and repeatedly compared, with obtain multiple first comparative results and according to
This little first comparative result produces last carry-out bit.
In another embodiment, a kind of Continuous Approximation formula analog-digital conversion method includes：By entering to an analog signal
Row samples to produce one first current potential, continuously send out according on first current potential and the D/A conversion circuit using a comparator
Raw multiple second current potentials sequentially produce multiple carry-out bits and export a data signal based on this little carry-out bit.Wherein, this is a little
The generation step of last j carry-out bit in carry-out bit includes：The first current potential occurs with last time using a comparator
Second current potential, which is carried out continuously, repeatedly to be compared, to respectively obtain multiple first comparative results and according to these the first comparative results
Produce last j carry-out bit.In this, j is the integer more than 1.
In another embodiment, a kind of Continuous Approximation formula analog-digital converter includes：One sampling and digital-to-analogue conversion
Circuit, a comparator and Continuous Approximation formula control circuit.One Continuous Approximation formula control circuit includes：One first determines mould
Block, at least one second decision module and an output logic.First decision module correspond to multiple determine during in it is last
One of during one position is determined, and during each second decision module is determined corresponding to remaining position.
Sampling and D/A conversion circuit produce one first current potential by being sampled to an analog signal.In last
During one position is determined, comparator is carried out continuously to the first current potential with one second current potential in sampling and D/A conversion circuit
Repeatedly compare to respectively obtain multiple first comparative results, and the first decision module produces one according to this little first comparative result
The last carry-out bit of group.During each decision in during remaining decision, comparator enters to the first current potential with the second current potential
Row once compares to obtain corresponding second comparative result, and corresponding second decision module compares knot according to corresponding second
Fruit controls sampling and D/A conversion circuit to produce a carry-out bit according to corresponding second comparative result, to adjust
The second current potential in sampling and D/A conversion circuit.Logic is exported according to an at least carry-out bit and one group of last carry-out bit
To export a data signal.
To sum up, according to the Continuous Approximation formula analog-digital converter of the present invention（SAR ADC）And its method is for last several
Individual position increases the number of comparisons of comparator during determining, effectively to be reduced in the case where not increasing the situation of signal supervisory instrument of complexity
Noise（For example:The noise jamming of comparator, chip system, produced by power supply etc. in itself）To SAR ADC signal noise ratio
Influence.Furthermore, can come further using majority rule, average carry or specific coded system again for multiple comparative result
Reduce the energy of noise.
Brief description of the drawings
Fig. 1 is the Continuous Approximation formula analog-digital converter according to one embodiment of the invention（SAR ADC）Schematic diagram.
Fig. 2 and Fig. 3 is the Continuous Approximation formula according to one embodiment of the invention（SAR）The stream summary of analog-digital conversion method
Cheng Tu.
Fig. 4 be Fig. 1 in the first decision module an embodiment schematic diagram.
Fig. 5 is the partial process view of the SAR analog-digital conversion methods according to another embodiment of the present invention.
Fig. 6 is the schematic diagram of the SAR ADC according to another embodiment of the present invention.
Fig. 7 be Fig. 6 in the first decision module an embodiment schematic diagram.
Fig. 8 and Fig. 9 is the partial process view of the SAR analog-digital conversion methods according to further embodiment of this invention.
Figure 10 controls the partial schematic diagram of another embodiment of circuit for the Continuous Approximation formula in Fig. 1.
Figure 11 is the partial schematic diagram of the SAR ADC according to another embodiment of the present invention.
Figure 12 be Figure 11 in system clock, clock signal and control clock an embodiment timing diagram.
【Symbol description】
10 Continuous Approximation formula analog-digital converters（SAR ADC）
110 samplings and D/A conversion circuit
130 comparators
150 Continuous Approximation formulas control circuit
151 input logics
153-1~153-N decision modules
154 generation units
154-1~154-3 generation units
155 identifying units
157 output logics
1571 logic elements
1573 output units
B1~B（N+j-1）Carry-out bit
B[1:N] data signal
B（N-1）_ a digital codes
B（N-1）_ b digital codes
B（N-1）_ c digital codes
BN_a digital codes
BN_b digital codes
BN_c digital codes
CKc controls clock
CKs system clocks
CK1~CK（N+4）Clock signal
OUT_p comparative results
OUT_n comparative results
Sc digital controlled signals
Valid useful signals
Vin analog signals
VDD supplies voltage
The current potentials of V1 first
The current potentials of V2 second
S21 is sampled and preserved to sampled analog signals
S23 produces the second current potential according to the digital controlled signal received
S25 is to the in the first current potential in sampling and D/A conversion circuit and sampling and D/A conversion circuit
The progress of two current potentials once compares to obtain a comparative result
S27 produces a carry-out bit according to this comparative result
S29 exports digital controlled signal to sampling and D/A conversion circuit according to this comparative result
S33 produces the second current potential according to the digital controlled signal received
S35 is to the in the first current potential in sampling and D/A conversion circuit and sampling and D/A conversion circuit
The progress of two current potentials once compares to obtain a comparative result
S37 produces a digital code according to this comparative result
S38 produces a carry-out bit according to the digital code of this little comparative result of correspondence
S39 exports digital controlled signal to sampling and D/A conversion circuit according to this little comparative result
S43 produces the second current potential according to the digital controlled signal received
S45 is to the in the first current potential in sampling and D/A conversion circuit and sampling and D/A conversion circuit
The progress of two current potentials once compares to obtain a comparative result
S47 produces a digital code according to this comparative result
S48 produces last carry-out bit according to the digital code of this little comparative result of correspondence
S48 ' produces multiple carry-out bits according to the digital code of this little comparative result of correspondence
S51 exports a data signal based on all carry-out bits
Embodiment
Fig. 1 is the Continuous Approximation formula analog-digital converter according to one embodiment of the invention（SAR ADC）Summary signal
Figure.Fig. 2 and Fig. 3 is the Continuous Approximation formula according to one embodiment of the invention（SAR）The outline flowchart of analog-digital conversion method.
Reference picture 1, SAR ADC10 include a sampling and D/A conversion circuit 110, a comparator 130 and one connect
Continuous approximant control circuit 150.
Sampling and D/A conversion circuit 110 are coupled to two inputs of comparator 130, the output of comparator 130
End is coupled to Continuous Approximation formula control circuit 150 and Continuous Approximation formula control circuit 150 is coupled to sampling and digital simulation turns
Change the control end of circuit 110.
Reference picture 2, SAR ADC10 running starts from sample phase（sampling phase）.During sample phase, even
Continuous approximant control circuit 150 controls sampling and D/A conversion circuit 110 with digital controlled signal Sc, with cause sampling and
D/A conversion circuit 110 is sampled and preserved to sampled analog signals Vin（Step S21）.In other words, sampling and numeral
Analog conversion circuit 110 produces one first current potential V1 by sampled analog signals Vin.
Then, SAR ADC10 enter the position cycle stage（bit-cycling phase）, that is, the stage is changed, to determine numeral
The conversion output of output.The position cycle stage include sequentially connect N number of determine during.Wherein, N is the integer more than 1.Every
During individual position is determined, sampling and D/A conversion circuit 110 can change a position and produce one second current potential V2.In this, take
Sample and D/A conversion circuit 110 only change a position during same position is determined, and by most significant digit（most
significant bit；MSB）Start conversion to least significant bit (LSB)（least significant bit；LSB）.
In certain embodiments, Continuous Approximation formula control circuit 150 includes N number of decision module 153-1~153N and one
Export logic 157.
Decision module 153-1~153（N-1）It is respectively coupled to sampling and digital simulation turn in the output end of comparator 130
Change between the control end of circuit 110.Also, decision module 153-1~153（N-1）Output end be connected to output logic 157.Certainly
Cover half block 153-1~153（N-1）Each of be coupled to next decision module.
During N number of decision module 153-1~153N corresponds respectively to N number of decision, and during everybody determines, correspondence
Decision module one carry-out bit is determined according to output OUT_p, OUT_n of comparator 130.
Describe for convenience, decision module 153-N is referred to as the first decision module 153-N below, and remaining determines mould
Block 153-1~153-（N-1）Referred to as the second decision module 153-1~153-（N-1）.
During the 1st determines, Continuous Approximation formula controls circuit 150 to export digital controlled signal Sc to sampling and numeral
Analog conversion circuit 110.In certain embodiments, Continuous Approximation formula control circuit 150 according to the second decision module 153-1~
153（N-1）Output（That is, carry-out bit B1~B（N-1））Produce digital controlled signal Sc.
Sampling and D/A conversion circuit 110 produce the second current potential V2 further according to the digital controlled signal Sc received
（Step S23）.In this, digital controlled signal Sc highest（First）Position is " 1 ", and remaining position is " 0 ".
Then, 130 pairs of samplings of comparator and the first current potential V1 and sampling and digital mould on D/A conversion circuit 110
The the second current potential V2 intended on change-over circuit 110 is once compared to obtain the 1st comparative result OUT_p, OUT_n（Step
S25）.In this, comparative result OUT_p, OUT_n are a differential wave.
Second decision module 153-1 produces a carry-out bit B1 according to this comparative result OUT_p, OUT_n（Step S27）.
As an example it is assumed that the first current potential V1 is input signal Vin, and the second current potential V2 is the simulation after digital controlled signal Sc conversions
Output（VDAC）.Now, when comparative result OUT_p, OUT_n of comparator 130 are that simulation output VDAC is less than input signal Vin
When, carry-out bit B1 value is set as " 1 " by the second decision module 153-1, i.e. output signal B [1:N] the 1st be 1.Conversely,
When comparative result OUT_p, OUT_n of comparator 130 are more than or equal to input signal Vin for simulation output VDAC, second determines
Carry-out bit B1 is set as " 0 " by cover half block 153-1, i.e. output signal B [1:N] the 1st be 0.
Also, Continuous Approximation formula controls circuit 150 to control sampling and digital mould according to this comparative result OUT_p, OUT_n
Intend change-over circuit 110（Step S29）, to adjust the second current potential V2 in sampling and D/A conversion circuit 110.Change speech
It, Continuous Approximation formula controls carry-out bit B1 of the circuit 150 according to produced by the second decision module 153-1 to adjust and by new number
Word control signal Sc is exported to sampling and D/A conversion circuit 110, to cause sampling and D/A conversion circuit 110
The second current potential V2 is produced according to new digital controlled signal Sc（Step S23）.Using the 1st comparative result OUT_p, OUT_n as simulation
VDAC is exported to be less than exemplified by input signal Vin, now, digital controlled signal Sc highest（First）Position be maintained " 1 ", it is secondary high
（Second）Position is changed by " 0 " is set to " 1 ", and remaining position is also maintained " 0 ".And sample and the then basis of D/A conversion circuit 110
New digital controlled signal Sc produces the second current potential V2.Similarly, if defeated using the 1st comparative result OUT_p, OUT_n to simulate
Go out VDAC to be not less than exemplified by input signal Vin, digital controlled signal Sc highest（First）Position then change be set to " 0 ", it is secondary high（The
Two）Position is changed by " 0 " is set to " 1 ", and remaining position is also maintained " 0 ".
Comparator 130 is again to the first current potential V1 on sampling and D/A conversion circuit 110 and sampling and digital mould
The progress for intending the second current potential V2 on change-over circuit 110 is once compared, to obtain the 2nd comparative result OUT_p, OUT_n（Step
S25）.
Second decision module 153-1 is produced further according to this comparative result OUT_p, OUT_n（Setting）Corresponding carry-out bit
B2, i.e. output signal B [1:N] the 2nd（Step S27）.
Also, Continuous Approximation formula controls circuit 150 to control to sample again according to this comparative result OUT_p, OUT_n and number
Word analog conversion circuit 110（Step S29）, to adjust the second current potential in sampling and D/A conversion circuit 110 again
V2。
That is, by sequentially performing repeatedly（Step S23）、（Step S25）、（Step S27）And（Step S29）, directly
During the decision of second-to-last position is completed.Now, the second decision module 153-1~153（N-1）Produce respectively（Setting）It is defeated
Go out a B1~B（N-1）, i.e. output signal B [1:N] the 1st to N-1.
During n-th position is determined（That is, during last position is determined）, the repetition of comparator 130 is to the first current potential V1 and second
Current potential V2 is compared to obtain multiple comparative result OUT_p, OUT_n, i.e. continuously the first current potential V1 is entered with the second current potential V2
Row repeatedly compares.Describe for convenience, comparative result OUT_p, OUT_n produced by during n-th position is determined are referred to as the
One comparative result OUT_p, OUT_n, and comparative result OUT_p, OUT_n produced by during remaining decision are referred to as the second ratio
Compared with result OUT_p, OUT_n.In other words, during last position is determined, comparator 130, which is carried out continuously, to be compared for m time and obtains m individual the
One comparative result OUT_p, OUT_n.In this, m is the integer more than 1.During last position is determined, comparator 130 compares completion
Afterwards, Continuous Approximation formula control circuit 150 will not turn according to each comparative result OUT_p, OUT_n control sampling and digital simulation
Change circuit 110 and remove to adjust the second current potential V2 thereon, that is to say, that during last position is determined, Continuous Approximation formula control circuit
150 will not change exported digital controlled signal Sc, to cause repeatedly relatively more used second current potential V2 to remain unchanged.
In other words, in the same position cycle stage, the first multiple comparative results of decision module continuous processing, and second determines
Cover half block then only handles a comparative result.
In certain embodiments, the first decision module 153-N includes the m identifying unit 155 of generation unit 154 and one.m
Individual generation unit 154 is respectively coupled between the output end of comparator 130 and the input of identifying unit 155.
M generation unit corresponds respectively to m first comparative result OUT_p, OUT_n, and according to the corresponding first ratio
Corresponding digital code is produced compared with result OUT_p, OUT_n.
Fig. 4 be Fig. 1 in the first decision module 153-N an embodiment schematic diagram.
Continuously to compare 3 times（That is, m=3）Exemplified by, collocation reference picture 3 and Fig. 4, the first decision module 153-N include 3 productions
Raw unit 154-1,154-2,154-3 and an identifying unit 155.Generation unit 154-1,154-2,154-3 are respectively coupled to
Between the output end of comparator 130 and the input of identifying unit 155.The output end of identifying unit 155 is connected to sampling and number
The control end and output logic 157 of word analog conversion circuit 110.
During n-th position is determined, sampling and D/A conversion circuit 110 are produced according to new digital controlled signal Sc
Second current potential V2（Step S43）.Then, comparator 130 compare for the 1st time（The n-th of whole position cycle stage compares）, i.e.,
Compare the first current potential V1 and the second current potential V2 to obtain the 1st first comparative result OUT_p, OUT_n（Step S45）.Produce single
First 154-1 produces a digital code B3_a according to this first comparative result OUT_p, OUT_n（Step S47）.
Then, comparator 130 carries out the 2nd time and compared again（The N+1 times of whole position cycle stage is compared）, that is, compare first
Current potential V1 and the second current potential V2 to obtain the 2nd first comparative result OUT_p, OUT_n again（Step S45）.Generation unit 154-2
A digital code B3_b is produced further according to this first comparative result OUT_p, OUT_n（Step S47）.
Then, comparator 130 carries out the 3rd time and compared again（The N+2 times of whole position cycle stage is compared）, that is, compare first
Current potential V1 and the second current potential V2 to obtain the 3rd first comparative result OUT_p, OUT_n again（Step S45）.Generation unit 154-3
A digital code B3_c is produced further according to this first comparative result OUT_p, OUT_n（Step S47）.
In after the number of comparisons for completing to set, identifying unit 155 is according to correspondence this 3 times first comparative results OUT_p, OUT_
N digital code B3_a, B3_b, B3_c is produced（Setting）Last carry-out bit BN（Step S48）.
Then, output logic 157 is used as a data signal B [1 using all carry-out bit B1~BN set:N], and will
This data signal B [1:N] export circuit to next stage（Step S51）.
Fig. 5 is the partial process view of the SAR analog-digital conversion methods according to another embodiment of the present invention.According to Fig. 6
The SAR ADC of another embodiment of the present invention schematic diagram.
In certain embodiments, reference picture 5 and Fig. 6, the first decision module 153-N can be according to m the first comparative results
OUT_p, OUT_n digital code produce multiple carry-out bit BN~B（N+j-1）（Step S48 '）.Wherein, j is the integer more than 1.
Now, output logic 157 is i.e. with all carry-out bit B1~B（N+j-1）It is used as a data signal B [1:N+j-1],
And by this data signal B [1:N+j-1] export to next stage（Step S51）.
Fig. 7 be Fig. 6 in the first decision module 153-N an embodiment schematic diagram.
Exemplified by continuously comparing 2 times and produce 2 carry-out bits, reference picture 7 of arranging in pairs or groups, the first decision module 153-N includes 2
Generation unit 154-1,154-2 and an identifying unit 155.Generation unit 154-1,154-2 are respectively coupled in comparator 130
Between the input of output end and identifying unit 155.The output end of identifying unit 155 is connected to sampling and digital-to-analogue conversion electricity
The control end and output logic 157 on road 110.
During n-th position is determined, comparator 130 is carried out continuously 2 times and compared（The N of whole position cycle stage and N+1 times
Compare）And sequentially obtain 2 first comparative results OUT_p, OUT_n.Generation unit 154-1 is according to the 1st the first comparative result
OUT_p, OUT_n produce a digital code B3_a, and generation unit 154-2 is according to the 2nd first comparative result OUT_p, OUT_n
Produce a digital code B3_b（Step S47）.Then, it is determined that unit 155 is using a conversion table（Such as following table one）According to digital code
BN_a, BN_b obtain most latter two carry-out bit BN, B（N+1）（Step S48 '）.
Table one
| BN_a | BN_b | BN | B（N+1） |
| 0 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 0 |
In certain embodiments, can be during last several determine, each comparator 130 is all carried out continuously multiple ratio
Compared with using further lifting SAR ADC10 signal noise ratio（signal-to-noise ratio；SNR）.
In other words ,+2 positions of kth reciprocal decision module 153- corresponding during being determined during determining to n-th position（N-k
+1）Each of~153-N includes multiple identifying units 155 of generation unit 154 and one.Describe for convenience, below
Decision module 153-N is referred to as the first decision module 153-N, by decision module 153-（N-k+1）~153-（N-1）Referred to as
3rd decision module 153-（N-k+1）~153-（N-1）, and by remaining decision module 153-1~153-（N-1）Referred to as second
Decision module 153-1~153-（N-1）.Also, following comparative result OUT_p by produced by during n-th position is determined,
OUT_n is referred to as the first comparative result OUT_p, OUT_n, by during being determined during+2 positions decisions of kth reciprocal to the N-1 position
Produced comparative result OUT_p, OUT_n is referred to as the 3rd comparative result OUT_p, OUT_n, and institute during remaining position is determined
Comparative result OUT_p, OUT_n of generation are referred to as second comparative result OUT_p, OUT_n.
Fig. 8 and Fig. 9 is the partial process view of the SAR analog-digital conversion methods according to further embodiment of this invention.Yu Tu
In formula, k is integer, and k+2 is less than the sum of carry-out bit.Figure 10 controls another reality of circuit 150 for the Continuous Approximation formula in Fig. 1
Apply the partial schematic diagram of example.
Reference picture 8, Fig. 9 and Figure 10, it is assumed that during SAR ADC10 are designed as last 2 positions decision（That is, k in schema=
0）Comparator 130 respectively compare for 3 times（That is, m=0 in schema）.
During second-to-last position is determined（That is, during the N-1 position is determined）When, sample and D/A conversion circuit
110 produce the second current potential V2 according to new digital controlled signal Sc（Step S33）.Then, comparator 130 carries out the N-1 position
Compare for the 1st time during decision, that is, compare the first current potential V1 and the second current potential V2 with obtain one the 3rd comparative result OUT_p,
OUT_n（Step S35）.3rd decision module 153-（N-1）In generation unit 154-1 according to this 3rd comparative result
OUT_p, OUT_n produce a digital code B（N-1）_a（Step S37）.
Then, carry out again during the N-1 position is determined the 2nd time of comparator 130 is compared, that is, compares the first current potential V1 and the
Two current potential V2 to obtain one the 3rd comparative result OUT_p, OUT_n again（Step S35）.3rd decision module 153-（N-1）In
Generation unit 154-2 produces a digital code B according to this 3rd comparative result OUT_p, OUT_n（N-1）_b（Step S37）.
Then, carry out again during the N-1 position is determined the 3rd time of comparator 130 is compared, that is, compares the first current potential V1 and the
Two current potential V2 to obtain one the 3rd comparative result OUT_p, OUT_n again（Step S35）.3rd decision module 153-（N-1）In
Generation unit 154-3 produces a digital code B according to this 3rd comparative result OUT_p, OUT_n（N-1）_c（Step S37）.
Before number of comparisons set during completing this decision, Continuous Approximation formula control circuit 150 will not change
The digital controlled signal Sc exported, to cause repeatedly relatively more used second current potential V2 to remain unchanged.
In complete setting number of comparisons after, the 3rd decision module 153-（N-1）In identifying unit 155 according to correspondence this
The digital code B of the 3rd comparative result OUT_p, OUT_n produced by 3 comparisons（N-1）_a、B（N-1）_b、B（N-1）_ c is produced
（Setting）The N-1 carry-out bit B（N-1）（Step S38）.
Continuous Approximation formula controls circuit 150 to control to sample again according to this little 3rd comparative result OUT_p, OUT_n and number
Word analog conversion circuit 110（Step S39）, to adjust the second current potential in sampling and D/A conversion circuit 110 again
V2（Step 43）.In other words, Continuous Approximation formula control circuit 150 is based on the 3rd decision module 153-（N-1）In identifying unit
The N-1 carry-out bit B set by 155（N-1）Turn to adjust and export digital controlled signal Sc to sampling and digital simulation
Change circuit 110.
During n-th position is determined, collocation reference picture 3 or Fig. 5, sampling and D/A conversion circuit 110 are according to new
Digital controlled signal Sc adjusts the second current potential V2（Step 43）Afterwards, 130 couple of first current potential V1 of comparator and the second current potential V2
It is carried out continuously 3 times to compare, to obtain three first comparative results OUT_p, OUT_n（Step 45）.Also, the first decision module
Generation unit 154-1,154-2,154-3 in 153-N produce number according to this little first comparative result OUT_p, OUT_n respectively
Character code BN_a, BN_b, BN_c（Step 47）.Then, the identifying unit 155 in the 3rd decision module 153-N further according to corresponding to
Digital code BN_a, BN_b, BN_c of first comparative result OUT_p, OUT_n produced by this 3 comparisons is produced（Setting）N-th
Carry-out bit BN（Step S48）Or produce N and N+1 carry-out bit BN, B（N+1）（Step S48 '）.
In other words, in the same position cycle stage, the first decision module and the 3rd decision module handle multiple comparisons
As a result, and the second decision module then only handle a comparative result.Furthermore, multiple generation units difference in same decision module
Multiple comparative results produced by during being determined corresponding to same position.Also, it is many for being set as during being determined except last position
During the secondary position compared is determined, before number of comparisons set during completing this decision, Continuous Approximation formula control circuit
150 all without exported digital controlled signal Sc is changed, to cause repeatedly relatively more used second current potential V2 to remain unchanged.
In certain embodiments, during last several determine, each comparator 130, which is all carried out continuously, repeatedly to be compared
When, comparator 130 performed during each decision the number of times that compares can all same, different or part is identical and part not
Together.As an example it is assumed that k=0, SAR ADC10 in Fig. 8 can be such as the design of above-mentioned example, but SAR ADC10 can also be set
It is calculated as comparator 130 and is carried out continuously 2 times during the N-1 position is determined comparing（That is, there are the 3rd decision module 2 to produce list
Member）, and be carried out continuously 3 times during n-th position is determined and compare（That is, the first decision module has 3 generation units）.
In step S38 or step S48, identifying unit 155 can be in the way of majority rule or in the way of average carry again
To obtain corresponding carry-out bit.
During n-th position is determined and exemplified by m=3, identifying unit 155 carries out corresponding digital code BN_a, BN_b, BN_c
Majority rule to obtain last carry-out bit BN, such as following table two.
Table two
| BN_a | BN_b | BN_c | BN |
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 1 |
In other words, when the mode using majority rule, m is necessary for odd number, i.e. comparator 130 is during this decision
Number of comparisons is odd number.
Again during n-th position is determined and exemplified by m=3, identifying unit 155 carries out corresponding digital code BN_a, BN_b, BN_
C average carry again（Decimal fractions round up）To obtain last carry-out bit BN, such as following table three.
Table three
| BN_a | BN_b | BN_c | It is average | BN |
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0.33 | 0 |
| 0 | 1 | 0 | 0.33 | 0 |
| 0 | 1 | 1 | 0.67 | 1 |
| 1 | 0 | 0 | 0.33 | 0 |
| 1 | 0 | 1 | 0.67 | 1 |
| 1 | 1 | 0 | 0.67 | 1 |
| 1 | 1 | 1 | 1 | 1 |
Figure 11 is the partial schematic diagram of the SAR ADC according to another embodiment of the present invention.
By taking N=3 as an example, reference picture 11, in this embodiment, comparator 130 carries out 1 respectively during the 1st and 2 position is determined
It is secondary to compare, and comparator 130 compare for 3 times during the 3rd position is determined.
Continuous Approximation formula control circuit 150 includes input logic 151, the second decision module 153-1,153-2, the first decision
Module and output logic.First decision module includes three generation units 154-1,154-2,154-3 and an identifying unit
155.Exporting logic includes a logic module 1571 and an output unit 1573.Two inputs coupling of input logic 151
The positive output end and negative output terminal of comparator 130.
Second decision module 153-1,153-2 and generation unit 154-1,154-2,154-3 can be by the flip-flop DFF that connect
Realize.In this, each of second decision module 153-1,153-2 and generation unit 154-1,154-2,154-3 include
Two flip-flop DFF（For convenience of description, referred to as the first flip-flop DFF and the second flip-flop DFF individually below）.
The first flip-flop DFF's in second decision module 153-1,153-2 and generation unit 154-1,154-2,154-3
Set end or reset end and receive system clock CKs, and set or reset according to system clock CKs.
Each first flip-flop DFF output end is coupled to the second flip-flop corresponding to identical bits or same numbers code
DFF control end and corresponding to next bit or the first flip-flop DFF of next digital code input.And the second decision module
153-1 the first flip-flop DFF input is then coupled to feeder ear（Supply voltage VDD）.
In other words, the second decision module 153-1 the first flip-flop DFF output end is coupled to the second decision module 153-
The input of 1 the second flip-flop DFF control end and the second decision module 153-2 the first flip-flop DFF.Second determines
Module 153-2 the first flip-flop DFF output end is coupled to the second decision module 153-2 the second flip-flop DFF control
End and generation unit 154-1 the first flip-flop DFF input.Generation unit 154-1 the first flip-flop DFF output
End is coupled to generation unit 154-1 the second flip-flop DFF control end and generation unit 154-2 the first flip-flop DFF
Input.And generation unit 154-3 the first flip-flop DFF output end is then being coupled to the second of generation unit 154-3 just
Anti- device DFF control end and the first input end of logic module 1571.
Each second flip-flop DFF input is coupled to the positive output end of comparator 130.Generation unit 154-1,154-
2nd, 154-3 the second flip-flop DFF output end is connected to the input of identifying unit 155.Second decision module 153-1,
153-2 the second flip-flop DFF output end and the output end of identifying unit 155 are coupled to the output of output unit 1573
End, and it is electrically connected to sampling and D/A conversion circuit 110.
The output end of input logic 151 is coupled to each first flip-flop DFF control end and logic module 1571
Second input.3rd input reception system clock CKs of logic element 1571.The output end of logic module 1571 is connected to
The control end of output unit 1573.
Input logic 151 receives anode and the negative terminal output of comparator 130（Comparative result OUT_p, OUT_n）, and enter
Row comparative result OUT_p, OUT_n logical operation are so that useful signal Valid is exported to each first flip-flop DFF control
End and the input of logic module 1571.In certain embodiments, input logic 151 can be a NAND gate（NAND gate）.
Second decision module 153-1 the first flip-flop DFF is produced according to useful signal Valid and supply voltage VDD
One clock signal CK1.Second decision module 153-1 the second flip-flop DFF believes further according to anode comparative result OUT_p and clock
Number CK1 sets the 1st carry-out bit B1.Also, the second decision module 153-1 the first flip-flop DFF is also by this clock signal CK1
The second decision module 153-2 the first flip-flop DFF is supplied to, using the first flip-flop DFF as the second decision module 153-2
Input data.
Second decision module 153-2 the first flip-flop DFF is produced according to useful signal Valid and clock signal CK1
One clock signal CK2.Second decision module 153-1 the second flip-flop DFF believes further according to anode comparative result OUT_p and clock
Number CK2 sets the 2nd carry-out bit B2.Also, the second decision module 153-2 the first flip-flop DFF is also by this clock signal CK2
Generation unit 154-1 the first flip-flop DFF is supplied to, using the input number of the first flip-flop DFF as generation unit 154-1
According to.
Generation unit 154-1 produces clock signal CK3 according to useful signal Valid and clock signal CK2.Generation unit
154-1 the second flip-flop DFF exports a digital code B3_a further according to anode comparative result OUT_p and clock signal CK3.And
And, this clock signal CK5 is also supplied to logic module 1571 by generation unit 154-1 the first flip-flop DFF.
Generation unit 154-2 produces clock signal CK4 according to useful signal Valid and clock signal CK2.Generation unit
154-2 the second flip-flop DFF exports a digital code B3_b further according to anode comparative result OUT_p and clock signal CK4.And
And, this clock signal CK4 is also supplied to generation unit 154-3's first positive and negative by generation unit 154-2 the first flip-flop DFF
Device DFF, using the input data of the first flip-flop DFF as generation unit 154-3.
Generation unit 154-3 produces clock signal CK5 according to useful signal Valid and clock signal CK4.Generation unit
154-3 the second flip-flop DFF exports a digital code B3_c further according to anode comparative result OUT_p and clock signal CK5.And
And, this clock signal CK5 is also supplied to logic module 1571 by generation unit 154-1 the first flip-flop DFF.
Identifying unit 155 then sets the 3rd carry-out bit B3 according to digital code B3_a, B3_b, B3_c.In this, identifying unit
155 can determine the 3rd carry-out bit B3 with majority rule or the average mode such as carry again.
Logic element 1571 is produced during a control according to system clock CKs, useful signal Valid and clock signal CK5
Clock CKc, the 1st carry-out bit B1, the 2nd carry-out bit B2 and the 3rd output are read according to control clock CKc to cause output unit 1573
Position B3 is simultaneously output it as an output signal B [1:3].In certain embodiments, logic element 1571 can be with OR gate（OR gate）
Realize.
In this embodiment, system clock CKs, clock signal CK1~CK5 and control clock CKc sequential relationship are such as
Shown in Figure 12.
Wherein, sampling and D/A conversion circuit 110 consist essentially of multiple switch and multiple electric capacity.This little electric capacity
First end be connected to an input of comparator 130, and the second end then optionally receives a reference voltage by switch.Even
Continuous approximant control circuit 150 is coupled to the control end of these switches, and by controlling the running that this is switched a bit to determine this
The current potential of the first end of a little electric capacity（Such as, the second current potential V2）.In certain embodiments, sampling and D/A conversion circuit 110
It may include that sampling preserves circuit and digital analog converter, or be a capacitance digital analog converter.Due to sampling and counting
The implementation aspect of word analog conversion circuit and Detailed Operation system are well known to those skilled in the art, therefore are repeated no more in this.
To sum up, according to the Continuous Approximation formula analog-digital converter of the present invention（SAR ADC）And its method is for last several
Individual position increases the number of comparisons of comparator during determining, effectively to be reduced in the case where not increasing the signal supervisory instrument of complexity
Noise（For example:The noise jamming of comparator, chip system, produced by power supply etc. in itself）To SAR ADC signal noise ratio
Influence.Furthermore, can come further using majority rule, average carry or specific coded system again for multiple comparative result
Reduce the energy of noise.
Although the present invention is disclosed as above with above-described embodiment, these right embodiments are not limited to the present invention, for this
For any those of ordinary skill in field, without departing from the spirit and scope of the present invention, variation and modification, therefore this can be made
The scope of patent protection of invention must be defined by this specification appended claims and is defined.
Claims (18)
1. a kind of Continuous Approximation formula analog-digital conversion method, including：
One first current potential is produced by being sampled to an analog signal；
Using a comparator according to multiple second current potentials recurred on first current potential and D/A conversion circuit
Multiple carry-out bits are sequentially produced, wherein, second current potential corresponds respectively to the carry-out bit；And
One data signal is exported based on the carry-out bit；
Wherein, the generation step of last carry-out bit in the carry-out bit includes：
The second current potential occurred using the continuous last time in first current potential and second current potential of the comparator
Repeatedly compared, to obtain multiple first comparative results；And
Last carry-out bit according to being produced first comparative result.
2. Continuous Approximation formula analog-digital conversion method according to claim 1, wherein, according to first comparative result
The step of producing last described carry-out bit includes：
Multiple digital codes are produced according to first comparative result of the comparator respectively；And
To the carry out majority rule of the digital code to obtain last described carry-out bit.
3. Continuous Approximation formula analog-digital conversion method according to claim 1, wherein, according to first comparative result
Include to produce the step of last corresponding described carry-out bit：
Multiple digital codes are produced according to first comparative result of the comparator respectively；And
Average carry again is carried out to the digital code to obtain last described carry-out bit.
4. Continuous Approximation formula analog-digital conversion method according to claim 1, wherein, reciprocal the in the carry-out bit
The generation step of 2 each carry-out bit into k-th of carry-out bit reciprocal includes：
Continuously first current potential is repeatedly compared with corresponding second current potential using the comparator, it is many to obtain
Individual 3rd comparative result；
The D/A conversion circuit is controlled according to the 3rd comparative result, to adjust on the D/A conversion circuit
Second current potential；And
The corresponding carry-out bit is produced according to the 3rd comparative result；
Wherein, k is integer, and k+2 is less than the sum of the carry-out bit.
5. Continuous Approximation formula analog-digital conversion method according to claim 4, wherein, according to the 3rd comparative result
The step of to produce the corresponding carry-out bit, includes：
Multiple digital codes are produced according to the 3rd comparative result respectively；And
The digital code is carried out majority rule to obtain the corresponding carry-out bit.
6. Continuous Approximation formula analog-digital conversion method according to claim 4, wherein, according to the 3rd comparative result
The step of to produce the corresponding carry-out bit, includes：
Multiple digital codes are produced according to the 3rd comparative result respectively；And
Average carry again is carried out to the digital code to obtain the corresponding carry-out bit.
7. Continuous Approximation formula analog-digital conversion method according to any one of claim 1 to 6, wherein, the output
The generation step of each carry-out bit in remaining carry-out bit in position includes：
First current potential is once compared with corresponding second current potential using the comparator, to obtain one second
Comparative result；
The D/A conversion circuit is controlled according to second comparative result of the comparator, to adjust the numeral
Second current potential on analog conversion circuit；And
The corresponding carry-out bit is produced according to second comparative result.
8. a kind of Continuous Approximation formula analog-digital conversion method, including：
One first current potential is produced by being sampled to an analog signal；
Using a comparator according to multiple second current potentials recurred on first current potential and D/A conversion circuit
Sequentially produce multiple carry-out bits；And
One data signal is exported based on the carry-out bit；
Wherein, the generation step of the last j carry-out bit in the carry-out bit includes：
The second current potential that first current potential occurs with the last time in second current potential is entered using a comparator is continuous
Row repeatedly compares, to respectively obtain multiple first comparative results；And
The last j carry-out bit is produced according to first comparative result of the comparator, wherein, j is whole more than 1
Number.
9. Continuous Approximation formula analog-digital conversion method according to claim 8, wherein, according to first comparative result
Producing the step of the last j carry-out bit includes：
At least three digital codes are produced according to first comparative result respectively；And
The last j carry-out bit is determined according to the digital code using a conversion table.
10. Continuous Approximation formula analog-digital conversion method according to claim 8 or claim 9, wherein, in second current potential
The 1st carry-out bit that second current potential of the 1st generation to the second current potential of -1 generation of jth sequentially corresponds in the carry-out bit is extremely
- 1 carry-out bit of jth, and the generation step of each carry-out bit of the 1st carry-out bit into described -1 carry-out bit of jth
Including：
First current potential is once compared with corresponding second current potential using the comparator, to obtain one second
Comparative result；
The D/A conversion circuit is controlled according to second comparative result, to adjust the D/A conversion circuit
On second current potential；And
The corresponding carry-out bit is produced according to second comparative result.
11. a kind of Continuous Approximation formula analog-digital converter, including：
One sampling and D/A conversion circuit, to produce one first current potential by being sampled to an analog signal；
One comparator, in multiple determine during in last position determine during, continuously to first current potential with
One second current potential in the sampling and D/A conversion circuit repeatedly compare compares knot to respectively obtain multiple first
Really, and during remaining position is determined, first current potential is once compared to obtain with the progress of second current potential respectively
Corresponding second comparative result；And
One Continuous Approximation formula controls circuit, including：
One first decision module, during last described position is determined, one group is produced according to first comparative result
Last carry-out bit；
At least one second decision module, each described second decision module correspond to during remaining described decision wherein it
One, so that during corresponding institute's rheme is determined, a carry-out bit is produced according to corresponding second comparative result, and according to correspondence
Second comparative result control the sampling and D/A conversion circuit, turned with adjusting the sampling and digital simulation
Second current potential changed on circuit；And
One output logic, to export a data signal according to the carry-out bit and described group of last carry-out bit.
12. Continuous Approximation formula analog-digital converter according to claim 11, wherein, the position of described group of last carry-out bit
Number is positive integer, and less than or equal to the number of comparisons of the comparator.
13. Continuous Approximation formula analog-digital converter according to claim 11, wherein, described group of last carry-out bit is one
Last carry-out bit, and first decision module includes：
Multiple generation units, correspond respectively to first comparative result, and each described generation unit is used to according to corresponding
First comparative result produces a digital code；And
One identifying unit, to obtain the last carry-out bit to digital code progress majority rule.
14. Continuous Approximation formula analog-digital converter according to claim 11, wherein, described group of last carry-out bit is one
Last carry-out bit, and first decision module includes：
Multiple generation units, correspond respectively to first comparative result, and each described generation unit is used to according to corresponding
First comparative result produces a digital code；And
One identifying unit, to obtain the last carry-out bit to the average carry again of digital code progress.
15. Continuous Approximation formula analog-digital converter according to claim 11, wherein, described group of last carry-out bit is many
Individual last carry-out bit, and first decision module includes：
Multiple generation units, correspond respectively to first comparative result, and each described generation unit is used to according to corresponding
First comparative result produces a digital code；And
One identifying unit, to export the last carry-out bit according to the digital code using a conversion table.
16. Continuous Approximation formula analog-digital converter according to claim 11, wherein, the comparator is also used in
During each position in during the 2nd to k-th decision of number is determined, the progress to first current potential and second current potential
Repeatedly compare to respectively obtain multiple 3rd comparative results, and Continuous Approximation formula control circuit also includes：
At least one the 3rd decision module, during corresponding respectively to the 2nd to k-th decision reciprocal, with corresponding described
During position is determined, corresponding carry-out bit is produced according to the 3rd comparative result of the comparator.
17. Continuous Approximation formula analog-digital converter according to claim 16, wherein, each described 3rd decision mould
Block includes：
Multiple generation units, the 3rd comparative result corresponded respectively to produced by during same institute's rheme is determined, each
The generation unit is used to produce a digital code according to corresponding 3rd comparative result；And
One identifying unit, to obtain the corresponding carry-out bit to digital code progress majority rule.
18. Continuous Approximation formula analog-digital converter according to claim 16, wherein, each described 3rd decision mould
Block includes：
Multiple generation units, the 3rd comparative result produced by during corresponding respectively to the same decision, each institute
Generation unit is stated to produce a digital code according to corresponding 3rd comparative result；And
One identifying unit, to obtain the corresponding carry-out bit to the average carry again of digital code progress.
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| CN106712772B (en) * | 2015-11-18 | 2020-03-24 | 瑞昱半导体股份有限公司 | Test method and test circuit of successive approximation type analog-digital converter |
| CN106817128B (en) * | 2015-12-01 | 2020-07-10 | 瑞昱半导体股份有限公司 | Method for self-adaptive regulating coding mode and its digital correcting circuit |
| CN107306135B (en) * | 2016-04-22 | 2020-03-10 | 瑞昱半导体股份有限公司 | Correction circuit and correction method for digital-to-analog converter |
| TWI594579B (en) * | 2016-06-13 | 2017-08-01 | 瑞昱半導體股份有限公司 | Successive approximation register analog to digital converter and analog to digital conversion method thereof |
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