CN104134460A - Nonvolatile memory reading circuit based on dynamic reference - Google Patents
Nonvolatile memory reading circuit based on dynamic reference Download PDFInfo
- Publication number
- CN104134460A CN104134460A CN201410340513.7A CN201410340513A CN104134460A CN 104134460 A CN104134460 A CN 104134460A CN 201410340513 A CN201410340513 A CN 201410340513A CN 104134460 A CN104134460 A CN 104134460A
- Authority
- CN
- China
- Prior art keywords
- dynamic reference
- data
- voltage
- reference cells
- data cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015654 memory Effects 0.000 title claims abstract description 53
- 238000013500 data storage Methods 0.000 claims description 7
- 230000000694 effects Effects 0.000 claims description 6
- 230000003321 amplification Effects 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 230000005611 electricity Effects 0.000 claims description 2
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 2
- 150000004706 metal oxides Chemical class 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 11
- 238000000034 method Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
Landscapes
- Read Only Memory (AREA)
Abstract
The invention relates to a nonvolatile memory reading circuit based on dynamic reference. The nonvolatile memory reading circuit consists of load circuits PR0 and PR1, a dynamic reference unit, NMOS (N-Channel Metal Oxide Semiconductor) clamp transistors NC0 and NC1, a bit line selection switch MUX and a voltage comparison amplifier VC, wherein source electrodes of the NMOS clamp transistors are connected to a dynamic reference unit and a nonvolatile memory data unit to be read through the bit line selection switch MUX, grid electrodes of the NMOS clamp transistors are controlled by V<G_clamp> signals, and drain electrodes of the NMOS clamp transistors are connected with a drain electrode of a load transistor; a source electrode of the load transistor is connected with a voltage source Vdd, and a grid electrode of the load transistor is controlled by the V<G_clamp> signals; a branch circuit of the data unit and a branch circuit of the dynamic reference unit read voltage in a position of the source electrode of the load transistor and are connected with two input ends of the voltage comparison amplifier; and meanwhile, the V<data> is also connected with grid electrodes of two transistors of the dynamic reference unit and is used for controlling the resistance of the dynamic reference unit. The nonvolatile memory reading circuit has the advantages that the problem of parameter deviation of a nonvolatile memory is solved, and the reading judgment margin is improved, so that the reliability of the nonvolatile memory reading circuit is improved.
Description
Technical field
The present invention relates to a kind of nonvolatile memory reading circuit based on dynamic reference, for improving the reading reliability of nonvolatile memory, belong to nonvolatile memory technical field.
Background technology
Novel nonvolatile memory technology in recent years, as spin-transfer torque magnetic RAM (Spin Transfer Torque Magnetic Random Access Memory, STT-MRAM), resistive formula random access memory (Resistive Random Access Memory, RRAM), with developments such as phase-change random access memories (Phase Change Random Access Memory, PCRAM), progressively start to enter actual production and application stage.The basic storage principle of these nonvolatile memory technology is the resistance states by changing its storage unit, makes it can be at high-resistance state R
hwith low resistance state R
lbetween switch, thereby utilize this character store digital information, as R
hcorresponding data bit " 1 ", R
lcorresponding data bit " 0 ", or vice versa.Typical storage unit is divided and (is had R by data store
lwith R
htwo kinds of Resistance states, can be expressed as a variable resistor R
x) form with access control part (NMOS word line options transistor), be called 1R1T structure, as shown in Figure 1.Generally speaking, a storer comprises two kinds of storage unit, and one is data cell, and its resistance states is variable, is designated as R
data, for stores binary data; Another kind is reference unit, and its resistance states is known, is designated as R
ref, during for reading out data, provide judgement reference to data cell.When reading out data, detect their corresponding voltage (or electric current) by apply identical electric current (or voltage) to data cell and reference unit simultaneously, then contrast, can judge canned data in data cell, as shown in Figure 2.More specifically, if data cell is low resistance state R
l, the voltage V of data cell can be detected
data=V
l, it is less than the voltage V of reference unit
ref, adjudicate data bit for " 0 "; If data cell is high-resistance state R
h, the voltage V of data cell can be detected
data=V
h, it is greater than the voltage V of reference unit
ref, adjudicate data bit for " 1 ", or vice versa.
Ideally, all storage unit in same storer all have identical resistance value R in the time of high-resistance state
h_ideal, and in the time of low resistance state, all there is identical resistance value R
l_idealnow adjudicate allowance (Sensing Margin (SM) in order to obtain best reading, be defined as the minimum value of the absolute value of the difference of reference unit voltage (or electric current) and data cell voltage (or electric current)), the resistance value R of reference unit
ref_idealmust meet R
ref_ideal=(R
h_ideal+ R
l_ideal)/2.But, in actual conditions, due to the existence of technological parameter deviation, especially under deep submicron process, R
h, R
land R
refthe actual value design load that may depart from objectives, reduce thereby cause reading judgement allowance.When reading judgement allowance can not overcome the input mismatch of reading circuit itself time, may produce read error, affect the data reading reliability of storer.
Summary of the invention
One, goal of the invention:
Cause reading the problem that judgement allowance reduces for the nonvolatile memory of mentioning in above-mentioned background because of parameter error, the present invention proposes a kind of nonvolatile memory reading circuit based on dynamic reference, it has overcome the deficiencies in the prior art, solve the parameter error problem that nonvolatile memory exists, that improves nonvolatile memory reads judgement allowance, thereby improves its reliability.
Two, technical scheme:
The technical scheme of a kind of nonvolatile memory reading circuit based on dynamic reference of the present invention is, a kind of nonvolatile memory reading circuit based on dynamic reference, as shown in Figure 4.It is characterized in that, this reading circuit reads voltage V according to data cell
dataadjust the grid voltage of nmos pass transistor in dynamic reference cells, thereby change the resistance of dynamic reference cells, what acquisition was maximum reads judgement allowance.This reading circuit is by load circuit (PR0 and PR1), dynamic reference cells, NMOS clamp transistor (NC0 and NC1), bit line selector switch (MUX) and voltage comparison amplifier (VC) composition.Position annexation between them and signal trend are: the source electrode of NMOS clamp transistor connects nonvolatile memory data cell and dynamic reference cells to be read through bit line selector switch (MUX), and the grid of NMOS clamp transistor is by V
g_clampsignal is controlled, and its drain electrode connects the drain electrode of load transistor, and load transistor source electrode meets voltage source V dd, and grid is by V
g_loadsignal is controlled, and data cell branch road and dynamic reference cells branch road, at the voltage that reads at load transistor source electrode place, are designated as respectively V
datawith V
ref, they access two input ends of voltage comparison amplifier simultaneously, simultaneously V
dataalso connect two transistorized grids in dynamic reference cells, for controlling the resistance of dynamic reference cells.While carrying out read operation, have electric current from Vdd, through load circuit, NMOS clamp transistor, bit line selector switch, nonvolatile memory data cell and dynamic reference cells, finally flow to electronegative potential Vss.Because data cell is different from the resistance of dynamic reference cells, therefore can produce different electric currents at two branch roads, be designated as respectively I
datawith I
refthereby, under the effect of load circuit, can between load circuit and NMOS clamp transistor, produce different voltage, i.e. V
datawith V
ref, they receive the input end of two of voltage comparison amplifier simultaneously, compare and amplify, final binary data output signal.Because data cell has different resistance states, i.e. R
lwith R
h, therefore V
dataalso there are two different values, i.e. V
lwith V
h.When the resistance states of data cell is low resistance state R
ltime, corresponding voltage value V
data=V
l, therefore, in the time that this voltage is received in dynamic reference cells transistorized grid, dynamic reference cells has higher resistance, thereby makes its corresponding reference voltage V
refincrease; Otherwise, when the resistance states of data cell is high-impedance state R
htime, corresponding voltage value V
data=V
h, now dynamic reference cells has lower resistance, thereby makes its corresponding reference voltage V
refreduce, as shown in accompanying drawing 5-2, can see that this reading circuit can, according to the resistance sizes of the resistance states adjustment dynamic reference cells of data cell, read judgement allowance thereby increase.
Described load circuit is PR0 and PR1, by V
g_loadsignal is controlled, for the conversion to voltage of data cell and dynamic reference cells electric current is provided; It also can use other resistive devices, and specific implementation is not construed as limiting.
Described NMOS clamp transistor is NC0 and NC1, by V
g_clampsignal is controlled, and for clamping down on the bit-line voltage of data cell and dynamic reference cells, avoids mistake write operation, prevents that data cell and dynamic reference cells from damaging because bit-line voltage is excessive simultaneously.
Described bit line selector switch (MUX) is for selecting data cell to be read and dynamic reference cells.Its embodiment is not construed as limiting.
Described voltage amplification comparer, for the data cell voltage corresponding with dynamic reference cells is compared and amplified, is exported final binary data signal, and its embodiment is not construed as limiting.
Described dynamic reference cells is the core of a kind of nonvolatile memory reading circuit based on dynamic reference of the present invention, and as shown in Fig. 3-2, it forms (RN1-RN4) by 4 data storage areas (M1-M4) and 4 nmos pass transistors.Wherein M1, M3 are configured to low resistance state, and M2, M4 are configured to high-impedance state, or M1, M2 be configured to low resistance state, and M3, M4 are configured to high-impedance state, can obtain thus that high low resistance state storage unit electricity is led or the arithmetic mean value of resistance.The grid of RN1-RN2 (or RN3-RN4) meets word line WL, and for the access control of dynamic reference cells, and the grid of RN3-RN4 (or RN1-RN2) meets V
data, for controlling the resistance of dynamic reference cells.Wherein the configuration of the resistance states of M1-M4 is not construed as limiting.Accompanying drawing 3-2 is only the schematic diagram of the dynamic reference cells that is listed as of two the most basic row two, and can be any number combine according to storage area and a nmos pass transistor arbitrarily dynamic reference cells.
Three, advantage and effect:
The present invention proposes a kind of nonvolatile memory reading circuit based on dynamic reference, can solve the device mismatch problem that nonvolatile memory causes due to technological parameter deviation, thus improve nonvolatile memory read judgement allowance, improve data reliability.
Brief description of the drawings
Fig. 1 is nonvolatile memory 1R1T memory cell structure schematic diagram.
Fig. 2 is traditional reading circuit embodiment schematic diagram of nonvolatile memory.
Fig. 3-1 is traditional reference unit schematic diagram of nonvolatile memory.
The dynamic reference cells schematic diagram that Fig. 3-2 propose for the present invention.
Fig. 4 is a kind of nonvolatile memory reading circuit schematic diagram based on dynamic reference that the present invention proposes.
What Fig. 5-1 was traditional static reading circuit reads judgement allowance schematic diagram.
Fig. 5-2 are adjudicated allowance schematic diagram for what the present invention proposed based on reading of dynamic reference.
Wherein, Fig. 1 to the parameter-definition in Fig. 5 is:
BL: representing bit line, is the abbreviation of Bit-Line;
WL: representing word line, is the abbreviation of Word-Line;
SL: representing source line, is the abbreviation of Source-Line;
SM: representing to read judgement allowance, is the abbreviation of Sensing Margin;
R
x: represent memory cell data storage area, be expressed as a variable resistor;
R
h: represent the resistance value of memory cell data storage area in the time of high-resistance state;
R
l: represent the resistance value of memory cell data storage area in the time of low resistance state;
NMOS: representing N-type metal-oxide semiconductor (MOS), is the abbreviation of N-Mental-Oxide-Semiconductor; VC: representing voltage comparison amplifier, is the abbreviation of Voltage Comparator;
Vdd: represent supply voltage;
Vss: represent source electrode line voltage;
R
data: representing the Resistance states of data unit data storage area, can be R
lor R
h;
R
ref: represent the Resistance states of virtual reference cell data storage area, ideal value is (R
h+ R
l)/2;
I
data: the electric current that represents to flow through data cell;
V
data: represent voltage corresponding to data cell branch road;
V
ref: represent voltage corresponding to reference unit branch road;
I
ref: the electric current that represents to flow through reference unit branch road;
S0-S1: represent bit line selector switch;
NA0-NA1: represent NMOS word line options transistor;
NC0-NC1: represent NMOS clamp transistor;
PR0-PR1: represent PMOS load transistor;
V
l-V
h: represent that respectively data cell is in R
lstate and R
hthe magnitude of voltage corresponding to branch road of state;
V
g_clamp: represent clamp transistor grid-control voltage;
V
g_load: represent load transistor gate control voltage;
V
g_access: represent word line transistors grid-control voltage;
M1-M4: represent that in reference unit, data store is divided;
RN1-RN4: represent the nmos pass transistor in reference unit;
Embodiment
With reference to accompanying drawing, further illustrate the substantive distinguishing features of a kind of nonvolatile memory read method based on dynamic reference of the present invention.At this, detailed exemplary embodiment is disclosed, its specific CONSTRUCTED SPECIFICATION and function detail are only the objects that represents to describe example embodiment, therefore, can implement the present invention with many selectable forms, and the present invention should not be understood to only be confined to the example embodiment in this proposition, but should cover all changes, equivalent and the refill that fall in the scope of the invention.In addition, will can not describe in detail and maybe will omit well-known element of the present invention, device and electronic circuit, in order to avoid obscure the correlative detail of embodiments of the invention.
Fig. 1 is nonvolatile memory 1R1T memory cell structure schematic diagram.It (is variable resistor R that nonvolatile memory 1R1T unit is divided by data store
x) form wherein R with access control part (nmos pass transistor)
xcan be at high-resistance state R
hwith low resistance state R
lbetween switch, thereby utilize this character store digital information, as R
hcorresponding data bit " 1 ", R
lcorresponding data bit " 0 ", or vice versa.Nmos pass transistor is for memory unit access control, and its grid meets word line WL (Word-Line), and drain electrode (or source electrode) is via R
xafter meet bit line BL (Bit-Line), source electrode (or drain electrode) meets source electrode line SL (Source-Line).Can control the switching of nmos pass transistor by the voltage of control word line, thereby whether the selection of control nonvolatile memory cell, more specifically, in the time that word line is high level, nmos pass transistor is in conducting state, and storage unit is addressable, can carry out read-write operation to it, and in the time that word line is low level, nmos pass transistor is in nonconducting state, storage unit inaccessible.
Fig. 2 is the traditional static reading circuit embodiment schematic diagram of nonvolatile memory.It is by voltage comparison amplifier, load circuit (PR0 and PR1), NMOS clamp transistor (NC0 and NC1) composition.While carrying out read operation, memory controller is selected data cell to be read (its resistance states R by word line and bit line selector switch (S0 and S1)
datathe unknown is R
hor one in RL) with corresponding reference unit, simultaneously by clamp transistor grid-control voltage V
g_clampcontrol bit-line voltage, prevent that data cell and reference unit from damaging or causing mistake write operation because bit-line voltage is too high.Under the effect of bit-line voltage, can produce the electric current (I that flows through data cell
data) with flow through the electric current (I of reference unit
ref).Then (remember that its pull-up resistor value is R at load circuit
load) effect under, I
datawith I
refbe converted into the voltage V of corresponding data cell
data=I
data× R
loadvoltage V with reference unit
ref=I
ref× R
load, because data cell and reference unit have different resistance values, therefore I
data≠ I
refthereby, V
data=I
data× R
load≠ V
ref=I
ref× R
load.Last V
datawith V
reftwo input ends that simultaneously accessed voltage comparison amplifier, compare and amplify, and export final binary data signal.More specifically, if data cell is low resistance state R
l, V
data=V
l<V
ref, output data " 0 "; If instead data cell is high-resistance state R
h, V
data=V
h>V
ref, output data " 1 ".
Under deep submicron process, owing to thering is larger fabrication process parameters deviation, between storage unit and between each transistor, all there is device mismatch (for example R
h, R
land R
refthe actual value design load that may depart from objectives, the load transistor resistance value of data cell branch road and reference unit branch road is unequal), also there is input mismatch etc. in voltage comparison amplifier, what these device parameters mismatches had a strong impact on reading circuit reads judgement allowance, when reading judgement allowance can not overcome the input mismatch of voltage comparison amplifier time, just may cause read error, affect the reliability of nonvolatile memory.
Fig. 3-1 is respectively traditional reference unit of nonvolatile memory and the dynamic reference cells schematic diagram that the present invention proposes with Fig. 3-2.In traditional reference unit, after M1-M4 connection in series-parallel, to connect with a nmos pass transistor again, its resistance states cannot change.Ideal value is R
nMOS+ (R
h+ R
l)/2, wherein R
nMOSfor the resistance value of nmos pass transistor.And dynamic reference cells of the present invention, wherein the grid of RN1-RN2 (or RN3-RN4) meets V
data, therefore its resistance states can be adjusted according to the resistance value of data cell to be read, reads judgement allowance thereby can dynamically improve.
Below in conjunction with accompanying drawing 4 and accompanying drawing 5, describe the embodiment of a kind of nonvolatile memory reading circuit based on dynamic reference of the present invention in detail.
As shown in Figure 4, a kind of nonvolatile memory reading circuit based on dynamic reference of the present invention, it is by load circuit (PR0 and PR1), dynamic reference cells, NMOS clamp transistor (NC0 and NC1), bit line selector switch (MUX) and voltage comparison amplifier (VC) composition.Position annexation between them and signal trend are: the source electrode (or drain electrode) of NMOS clamp transistor connects nonvolatile memory data cell and reference unit to be read through bit line selector switch (MUX), and the grid of NMOS clamp transistor is by V
g_clampcontrol, its drain electrode (or source electrode) connects the drain electrode (or source electrode) of load transistor, and load transistor source electrode (or drain electrode) meets voltage source V dd, and grid is by V
g_loadcontrol, what data cell branch road and reference unit branch road were located at load transistor source electrode (or drain electrode) reads voltage, is designated as respectively V
datawith V
ref, they access two input ends of voltage comparison amplifier simultaneously, simultaneously V
dataalso connect the grid of two transistors (as RN1 and RN2) in dynamic reference cells, for dynamically controlling the resistance of reference unit.While carrying out read operation, have electric current from Vdd, through load circuit, NMOS clamp transistor, bit line selector switch, nonvolatile memory data cell and reference unit, finally flow to electronegative potential Vss.Because data cell is different from the resistance of reference unit, therefore can produce different electric currents at two branch roads, be designated as respectively I
datawith I
refthereby, under the effect of load circuit, can between load circuit and NMOS clamp transistor, produce different voltage, i.e. V
datawith V
ref, they receive two input ends of voltage comparison amplifier simultaneously, compare and amplify, final binary data output signal.Because data cell has different resistance states, i.e. R
lwith R
h, therefore V
dataalso there are two different values, i.e. V
lwith V
h.When the resistance states of data cell is low resistance state R
ltime, corresponding low voltage value V
data=V
l, therefore, in the time that this voltage is received the grid of transistor in dynamic reference cells (as RN1 and RN2), reference unit shows higher resistance, thereby makes its corresponding reference voltage V
refincrease; Otherwise, when the resistance states of data cell is high-impedance state R
htime, corresponding high-voltage value V
data=V
h, therefore, in the time that this voltage is received the grid of transistor in dynamic reference cells (as RN1 and RN2), reference unit shows lower resistance, thereby makes its corresponding reference voltage V
refreduce.
Compared to conventional readout scheme, a kind of nonvolatile memory reading circuit based on dynamic reference of the present invention, can be according to data cell read voltage V
datadynamically adjust the reference voltage V of reference unit
refsize, read judgement allowance thereby increase.In conventional readout scheme, reference voltage V
refbe changeless, read judgement allowance and be completely and read voltage V by data cell
datavariation and determine, as shown in accompanying drawing 5-1.In dynamic reference scheme proposed by the invention, reference voltage V
refto read voltage V with data cell
dataand dynamic change, and its variation tendency contrary reads voltage V in data cell
datavariation tendency, as shown in accompanying drawing 5-2.More specifically, along with data cell reads voltage V
dataincrease, reference voltage V
refreduce; On the contrary, when data cell reads voltage V
datawhile reducing, reference voltage V
refincrease.In other words, pass through V
datato the control of transistor in dynamic reference cells (as RN1 and RN2) grid voltage, make V
dataand V
refbetween there is contrary variation tendency, thereby impel all the time voltage difference between the two constantly to increase, therefore increased and read judgement allowance compared with traditional scheme, improved the reading reliability of nonvolatile memory.
Claims (1)
1. the nonvolatile memory reading circuit based on dynamic reference, is characterized in that: this reading circuit is by load circuit PR0 and PR1, dynamic reference cells, NMOS clamp transistor NC0 and NC1, bit line selector switch MUX and voltage comparison amplifier VC composition; The source electrode of NMOS clamp transistor connects nonvolatile memory data cell and dynamic reference cells to be read through bit line selector switch MUX, and the grid of NMOS clamp transistor is by V
g_clampsignal is controlled, and its drain electrode connects the drain electrode of load transistor, and load transistor source electrode meets voltage source V dd, and grid is by V
g_clampsignal is controlled, and data cell branch road and dynamic reference cells branch road, at the voltage that reads at load transistor source electrode place, are designated as respectively V
datawith V
ref, they access two input ends of voltage comparison amplifier simultaneously, simultaneously V
dataalso connect two transistorized grids in dynamic reference cells, for controlling the resistance of dynamic reference cells; While carrying out read operation, have electric current from Vdd, through load circuit, NMOS clamp transistor, bit line selector switch, nonvolatile memory data cell and dynamic reference cells, finally flow to electronegative potential Vss; Because data cell is different from the resistance of dynamic reference cells, therefore can produce different electric currents at two branch roads, be designated as respectively I
datawith I
refthereby, under the effect of load circuit, can between load circuit and NMOS clamp transistor, produce different voltage, i.e. V
datawith V
ref, they receive the input end of two of voltage comparison amplifier simultaneously, compare and amplify, final binary data output signal; Because data cell has different resistance states, i.e. R
lwith R
h, therefore V
dataalso there are two different values, i.e. V
lwith V
h, when the resistance states of data cell is low resistance state R
ltime, corresponding voltage value V
data=V
l, therefore, in the time that this voltage is received in dynamic reference cells transistorized grid, dynamic reference cells has higher resistance, thereby makes its corresponding reference voltage V
refincrease; Otherwise, when the resistance states of data cell is high-impedance state R
htime, corresponding voltage value V
data=V
h, now dynamic reference cells has lower resistance, thereby makes its corresponding reference voltage V
refreduce, this reading circuit is dynamically adjusted the resistance sizes of dynamic reference cells according to the resistance states of data cell, reads judgement allowance thereby increase;
Described load circuit is PR0 and PR1, by V
g_loadsignal is controlled, for the conversion to voltage of data cell and dynamic reference cells electric current is provided; It can substitute with other resistive device, and specific implementation is not construed as limiting;
Described NMOS clamp transistor is NC0 and NC1, by V
g_clampsignal is controlled, and for clamping down on the bit-line voltage of data cell and dynamic reference cells, avoids mistake write operation, prevents that data cell and dynamic reference cells from damaging because bit-line voltage is excessive simultaneously;
Described bit line selector switch MUX is for selecting data cell to be read and dynamic reference cells;
Described voltage amplification comparer, for the data cell voltage corresponding with dynamic reference cells is compared and amplified, is exported final binary data signal;
Described dynamic reference cells is the core of this reading circuit, it forms RN1-RN4 by 4 data storage area M1-M4 and 4 nmos pass transistors, wherein M1, M3 are configured to low resistance state, M2, M4 are configured to high-impedance state, or M1, M2 are configured to low resistance state, M3, M4 are configured to high-impedance state, obtain thus that high low resistance state storage unit electricity is led or the arithmetic mean value of resistance; The grid of RN1-RN2 or RN3-RN4 meets word line WL, and for the access control of dynamic reference cells, and the grid of RN3-RN4 or RN1-RN2 meets V
data, for controlling the resistance of dynamic reference cells; Wherein the configuration of the resistance states of M1-M4 is not construed as limiting.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410340513.7A CN104134460B (en) | 2014-07-17 | 2014-07-17 | A kind of nonvolatile memory reading circuit based on dynamic reference |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410340513.7A CN104134460B (en) | 2014-07-17 | 2014-07-17 | A kind of nonvolatile memory reading circuit based on dynamic reference |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104134460A true CN104134460A (en) | 2014-11-05 |
| CN104134460B CN104134460B (en) | 2017-12-26 |
Family
ID=51807108
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410340513.7A Active CN104134460B (en) | 2014-07-17 | 2014-07-17 | A kind of nonvolatile memory reading circuit based on dynamic reference |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104134460B (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104778963A (en) * | 2015-04-01 | 2015-07-15 | 山东华芯半导体有限公司 | RRAM sensitive amplifier |
| CN107039062A (en) * | 2015-10-30 | 2017-08-11 | 台湾积体电路制造股份有限公司 | Memory device and its operating method |
| CN108257633A (en) * | 2016-12-28 | 2018-07-06 | 上海磁宇信息科技有限公司 | A kind of read method of MRAM chip and its storage unit |
| CN109192235A (en) * | 2018-10-17 | 2019-01-11 | 上海华虹宏力半导体制造有限公司 | The reference current control circuit of memory |
| WO2020177202A1 (en) * | 2019-03-07 | 2020-09-10 | 北京航空航天大学合肥创新研究院 | Memory computing system and memory computing method based on skyrmion racetrack memory |
| CN111724830A (en) * | 2019-03-18 | 2020-09-29 | 中芯国际集成电路制造(上海)有限公司 | Voltage enhancement type reading amplifying circuit |
| CN111755058A (en) * | 2019-03-27 | 2020-10-09 | 中芯国际集成电路制造(上海)有限公司 | Dynamic feedback reading amplifying circuit |
| CN113517008A (en) * | 2020-04-10 | 2021-10-19 | 中国科学院微电子研究所 | Dynamic clamping memory computing circuit, memory and electronic equipment |
| WO2022127428A1 (en) * | 2020-12-15 | 2022-06-23 | 浙江驰拓科技有限公司 | Magnetic random access memory and read circuit thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012149569A1 (en) * | 2011-04-29 | 2012-11-01 | Qualcomm Incorporated | Self-body biasing sensing circuit for resistance-based memories |
| CN103811059A (en) * | 2014-02-28 | 2014-05-21 | 北京航空航天大学 | Reference calibration circuit of non-volatile memorizer and calibration method of reference calibration circuit |
| CN103811073A (en) * | 2014-02-28 | 2014-05-21 | 北京航空航天大学 | High-reliability read circuit of non-volatile memory |
-
2014
- 2014-07-17 CN CN201410340513.7A patent/CN104134460B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012149569A1 (en) * | 2011-04-29 | 2012-11-01 | Qualcomm Incorporated | Self-body biasing sensing circuit for resistance-based memories |
| CN103811059A (en) * | 2014-02-28 | 2014-05-21 | 北京航空航天大学 | Reference calibration circuit of non-volatile memorizer and calibration method of reference calibration circuit |
| CN103811073A (en) * | 2014-02-28 | 2014-05-21 | 北京航空航天大学 | High-reliability read circuit of non-volatile memory |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104778963A (en) * | 2015-04-01 | 2015-07-15 | 山东华芯半导体有限公司 | RRAM sensitive amplifier |
| WO2016155476A1 (en) * | 2015-04-01 | 2016-10-06 | 山东华芯半导体有限公司 | Sense amplifier and resistive random access memory comprising same |
| US11848040B2 (en) | 2015-10-30 | 2023-12-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory device and reference circuit thereof |
| US10157654B2 (en) | 2015-10-30 | 2018-12-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory device and reference circuit thereof |
| US10515680B2 (en) | 2015-10-30 | 2019-12-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory device and reference circuit thereof |
| CN107039062A (en) * | 2015-10-30 | 2017-08-11 | 台湾积体电路制造股份有限公司 | Memory device and its operating method |
| CN107039062B (en) * | 2015-10-30 | 2020-10-30 | 台湾积体电路制造股份有限公司 | Memory device and method of operating the same |
| US11211106B2 (en) | 2015-10-30 | 2021-12-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory device and reference circuit thereof |
| CN108257633A (en) * | 2016-12-28 | 2018-07-06 | 上海磁宇信息科技有限公司 | A kind of read method of MRAM chip and its storage unit |
| CN108257633B (en) * | 2016-12-28 | 2020-10-23 | 上海磁宇信息科技有限公司 | MRAM chip and reading method of memory cell thereof |
| CN109192235A (en) * | 2018-10-17 | 2019-01-11 | 上海华虹宏力半导体制造有限公司 | The reference current control circuit of memory |
| WO2020177202A1 (en) * | 2019-03-07 | 2020-09-10 | 北京航空航天大学合肥创新研究院 | Memory computing system and memory computing method based on skyrmion racetrack memory |
| US11151439B2 (en) | 2019-03-07 | 2021-10-19 | Hefei Innovation Research Institute, Beihang University | Computing in-memory system and method based on skyrmion racetrack memory |
| CN111724830A (en) * | 2019-03-18 | 2020-09-29 | 中芯国际集成电路制造(上海)有限公司 | Voltage enhancement type reading amplifying circuit |
| CN111724830B (en) * | 2019-03-18 | 2022-07-26 | 中芯国际集成电路制造(上海)有限公司 | Voltage enhancement type reading amplification circuit |
| CN111755058A (en) * | 2019-03-27 | 2020-10-09 | 中芯国际集成电路制造(上海)有限公司 | Dynamic feedback reading amplifying circuit |
| CN113517008A (en) * | 2020-04-10 | 2021-10-19 | 中国科学院微电子研究所 | Dynamic clamping memory computing circuit, memory and electronic equipment |
| CN113517008B (en) * | 2020-04-10 | 2024-06-11 | 中国科学院微电子研究所 | Dynamic clamping in-memory computing circuit, memory and electronic equipment |
| WO2022127428A1 (en) * | 2020-12-15 | 2022-06-23 | 浙江驰拓科技有限公司 | Magnetic random access memory and read circuit thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104134460B (en) | 2017-12-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11164635B2 (en) | Operations on memory cells | |
| CN104134460A (en) | Nonvolatile memory reading circuit based on dynamic reference | |
| US11430511B2 (en) | Comparing input data to stored data | |
| Chou et al. | An N40 256K× 44 embedded RRAM macro with SL-precharge SA and low-voltage current limiter to improve read and write performance | |
| CN103811073B (en) | A kind of high reliability reading circuit of nonvolatile memory | |
| US8947924B2 (en) | Data readout circuit of phase change memory | |
| JP7471422B2 (en) | Tri-state programming of memory cells | |
| CN103811059B (en) | A kind of nonvolatile memory reference calibrations circuit and method | |
| US9548131B1 (en) | Reduced power read sensing for one-time programmable memories | |
| US9025367B1 (en) | Method and apparatus for sensing tunnel magneto-resistance | |
| US10304529B2 (en) | Reading circuit for resistive memory | |
| US10726914B2 (en) | Programmable resistive memories with low power read operation and novel sensing scheme | |
| CN108630270A (en) | Nonvolatile semiconductor memory device | |
| CN103811046A (en) | Novel high-reliability read circuit | |
| WO2021051551A1 (en) | Memristor memory chip and operation method therefor | |
| JP5542222B2 (en) | Semiconductor device and control method thereof | |
| CN104134461A (en) | Reading circuit structure of HMC | |
| US20160343433A1 (en) | Sensing circuit for resistive memory array | |
| US20200350031A1 (en) | One-time programmable memories with low power read operation and novel sensing scheme | |
| US20180190351A1 (en) | Read circuit of storage class memory | |
| Baek et al. | A reliable cross-point MLC ReRAM with sneak current compensation | |
| CN204667887U (en) | Memory device | |
| JP6163817B2 (en) | Nonvolatile memory cell and nonvolatile memory | |
| CN107017020A (en) | A kind of data of nonvolatile storage read method | |
| CN112447226A (en) | Programmable resistive device memory and method for the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20210220 Address after: 100191 rooms 504a and 504b, 5th floor, 23 Zhichun Road, Haidian District, Beijing Patentee after: Zhizhen storage (Beijing) Technology Co.,Ltd. Address before: 100191 No. 37, Haidian District, Beijing, Xueyuan Road Patentee before: BEIHANG University |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20231217 Address after: Room 1605, Building 1, No. 117 Yingshan Red Road, Huangdao District, Qingdao City, Shandong Province, 266400 Patentee after: Qingdao Haicun Microelectronics Co.,Ltd. Address before: 100191 rooms 504a and 504b, 5th floor, 23 Zhichun Road, Haidian District, Beijing Patentee before: Zhizhen storage (Beijing) Technology Co.,Ltd. |
|
| TR01 | Transfer of patent right |