CN104122715A - Thin film transistor substrate and LCD panel - Google Patents
Thin film transistor substrate and LCD panel Download PDFInfo
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- CN104122715A CN104122715A CN201310303563.3A CN201310303563A CN104122715A CN 104122715 A CN104122715 A CN 104122715A CN 201310303563 A CN201310303563 A CN 201310303563A CN 104122715 A CN104122715 A CN 104122715A
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- film transistor
- base plate
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Abstract
Disclosed is a thin film transistor substrate. The thin film transistor substrate comprises a plurality of parallel scanning lines, a plurality of parallel data lines, a common electrode wire, a first electrode and thin film transistors. The scanning lines and the data lines intersect in an insulation mode, and any two adjacent scanning lines and any two adjacent data lines define a pixel region. The thin film transistors are arranged at the junction positions of the scanning lines and the data lines in the pixel regions. The first electrode is placed in the pixel regions, the first electrode is provided with slits, and each slit comprises two supporting parts which are unfolded at a predetermined angle and a corner which is formed by intersecting of the two supporting parts in the middle of the corresponding pixel region. The common electrode wire comprises a body and flanges which symmetrically extend respectively from the two opposite sides of the body, the body extends in the directions of the scanning lines and is arranged corresponding to the corners of the slits, and the flanges correspond to the supporting parts of the slits. The invention further provides an LCD panel. By means of the thin film transistor substrate and the LCD panel, the aperture opening ratio can be increased, dark fringes are reduced, and meanwhile the stability of a display picture can be improved.
Description
Technical field
The present invention relates to a kind of thin film transistor base plate and use the display panels of this thin film transistor base plate.
Background technology
The thin film transistor base plate of available liquid crystal display panel generally includes orthogonal sweep trace and data line, and is being provided with near the position of data line for increasing memory capacitance to improve the public electrode wire of exhibit stabilization.But because described public electrode wire is arranged on the aperture opening ratio that conventionally can affect display panels in the viewing area of pixel, can cause easily producing dark line in the region near public electrode wire simultaneously, affect display quality.
Summary of the invention
Given this, be necessary to provide a kind of thin film transistor base plate.This thin film transistor base plate comprises many sweep traces that are parallel to each other, many data lines that are parallel to each other, public electrode wire, the first electrode and thin film transistor (TFT)s.Described sweep trace is crossing with data line insulation, and two adjacent sweep trace data lines adjacent with two define a pixel region.Described thin film transistor (TFT) is arranged at the intersection of the interior described sweep trace of described pixel region and data line.Described the first electrode is positioned at described pixel region.On described the first electrode, offer slit.Described slit comprises and is two branches that predetermined angular launches and Gai Liang branch the formed turning that intersects in pixel region middle part.Described public electrode wire comprises main body and the relative both sides symmetrical flange extending respectively by main body.Described main body is extended the also turning of corresponding described slit along the direction of described sweep trace and is arranged, and described flange is corresponding with the branch of described slit.
Also being necessary provides a kind of display panels, comprises described thin film transistor base plate, subtend substrate and is clipped in the liquid crystal layer between described two substrates.
Compared to prior art, thin film transistor base plate of the present invention and the display panels that uses this thin film transistor base plate are by changing shape and the position of traditional public electrode wire, can increase the aperture opening ratio of display panels, reduce dark line, can also improve memory capacitance simultaneously to increase the stability of display frame.
Brief description of the drawings
Fig. 1 is the schematic diagram of display panels of the present invention.
Fig. 2 is the part plan structural representation of thin film transistor base plate in Fig. 1.
Fig. 3 is the sectional structure schematic diagram along V-V line of thin film transistor base plate shown in Fig. 2.
Main element symbol description
Following embodiment further illustrates the present invention in connection with above-mentioned accompanying drawing.
Embodiment
As shown in Figure 1, the display panels 1 that the specific embodiment of the invention provides comprises thin film transistor base plate 100, the subtend substrate 200 being oppositely arranged and is clipped in the liquid crystal layer 300 between described two substrates.In the present embodiment, described subtend substrate 200 is colored filter substrates.
See also Fig. 2 and Fig. 3, the thin film transistor base plate 100 that the specific embodiment of the invention provides comprises transparency carrier 20, sweep trace 110, public electrode wire 130, gate insulator 30, data line 120, thin film transistor (TFT) 10, the first electrode 150, passivation layer 40 and the second electrode 160.
Described sweep trace 110 is crossing with data line 120 insulation.Any two adjacent sweep traces 110 define a pixel region 140 with any two adjacent data lines 120.The data line 120 of each pixel region 140 both sides is all towards same direction bending.Described thin film transistor (TFT) 10 is arranged at a sweep trace 110 and data line 120 intersections in each pixel region 140.
Described thin film transistor (TFT) 10 comprises grid 11, source electrode 12, drain 13 and channel layer 14.Described grid 11 is connected with described sweep trace 110.Described source electrode 12 is connected with described data line 120.The two ends of described channel layer 14 are connected with drain 13 with described source electrode 12 respectively.
Described the second electrode 160 is electrically connected with described thin film transistor (TFT) 10 by drain 13.Described the second electrode 160 covers pixel region 140.The described pixel region 140 of described the first electrode 150 same covering, and separate by passivation layer 40 with described the second electrode 160.On described the first electrode 150, offer multiple slits that are arranged parallel to each other 151.Each slit 151 comprises two 151a of branch and a turning 151b.Described two 151a of branch are the strip that a predetermined angular launches, and are intersected in the 151b place, described turning that is positioned at pixel region 140 middle parts.Its contiguous data line 120 of the 151a of Gai Liang branch almost parallel.Wherein, the material of described the first electrode 150 and the second electrode 160 is tin indium oxide (Indium tin oxide, ITO).In the present embodiment, described the first electrode 150 is public electrode, and described the second electrode 160 is pixel electrode.In other embodiments, described the first electrode 150 can be also pixel electrode, and described the second electrode 160 can be also public electrode.
Described public electrode wire 130 extends along the direction that is parallel to described sweep trace 110, and arranges and insulation with described sweep trace 110 intervals.Described public electrode wire 130 is simultaneously crossing with described data line 120 insulation.Described public electrode wire 130 comprises main body 131 and the relative both sides symmetrical multipair flange 132 extending respectively by this main body.Particularly, described main body 131 is extended along the direction that is parallel to sweep trace 110, and crossing with data line 120 insulation.The position while of described main body 131 is corresponding with the position of multiple turning 151b of described slit 151.In other words, described main body 131 be arranged in the multiple turning 151b of this first electrode 150 under.The position of every pair of flanges 132 is corresponding with two 151a of branch of described slit 151.In the present embodiment, the width of the width of described flange 132 and the branch 151a corresponding with its position is identical.In other embodiments, the width of described flange 132 also can be greater than or less than the width of the branch 151a corresponding with its position.
Observe from section, described grid 11, sweep trace 110 and public electrode wire 130 are formed on described transparency carrier 20.Described gate insulator 30 is formed on described transparency carrier 20, and covers described grid 11, sweep trace 110 and public electrode wire 130.Described channel layer 14 is formed on described gate insulator 30, and just to described grid 11.Described data line 120 is formed on described gate insulator 30.Described source electrode 12 and drain 13 are formed on described gate insulator 30 and described channel layer 14, and each interval is to expose described channel layer 14.Described the second electrode 160 is formed on described gate insulator 30, and is electrically connected with described drain 13.Described passivation layer 40 is formed on described gate insulator 30, and covers described data line 120, source electrode 12, channel layer 14, drain 13 and the second electrode 160.Described the first electrode 150 is formed on described passivation layer 40, and between described the first electrode 150 and described the second electrode 160, has described passivation layer 40 the two interval is separated.
Due in display panels 1, near the 151a of the branch 151b place, turning of this V-shape slit 151 and turning 151b is non-luminous dark line region, the public electrode wire 130 that affects aperture opening ratio can be arranged on position that should region, with the opaque impact on aperture opening ratio being produced of this public electrode wire 130 of maximized reduction, can also reduce near the impact that public electrode wire 130, easily the dark line of generation brings simultaneously., described public electrode wire 130 is arranged on position that should region meanwhile, can also maximizedly makes public electrode wire 130 be covered by this second electrode 160, to improve memory capacitance, and then improve the stability of display frame.
Above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can modify or be equal to replacement technical scheme of the present invention, and not depart from the spirit and scope of technical solution of the present invention.
Claims (9)
1. a thin film transistor base plate, comprising:
Many the sweep traces that are parallel to each other, many the data lines that are parallel to each other, public electrode wire, the first electrode and thin film transistor (TFT), described sweep trace is crossing with data line insulation, and the data line that two adjacent sweep trace is adjacent with two defines a pixel region, described thin film transistor (TFT) is arranged at the intersection of the interior described sweep trace of described pixel region and data line, described the first electrode is positioned at described pixel region, on described the first electrode, offer slit, described slit comprises and is two branches that predetermined angular launches and Gai Liang branch the formed turning that intersects in pixel region middle part, described public electrode wire comprises main body and the relative both sides symmetrical flange extending respectively by main body, described main body is extended the also turning of corresponding described slit along the direction of described sweep trace and is arranged, described flange is corresponding with the branch of described slit.
2. thin film transistor base plate as claimed in claim 1, is characterized in that: the data line of described pixel region both sides is all towards same direction bending, its contiguous data line of described branch almost parallel.
3. thin film transistor base plate as claimed in claim 1, is characterized in that: the width of the width of described flange and the branch corresponding with its position is identical.
4. thin film transistor base plate as claimed in claim 1, it is characterized in that: described thin film transistor base plate also comprises the second electrode, described thin film transistor (TFT) comprises grid, source electrode, drain and channel layer, described grid is connected with described sweep trace, described source electrode is connected with described data line, the two ends of described channel layer are connected with drain with described source electrode respectively, and described the second electrode is electrically connected with described thin film transistor (TFT) by drain.
5. thin film transistor base plate as claimed in claim 4, it is characterized in that: described thin film transistor base plate also comprises transparency carrier, the first insulation course and the second insulation course, described grid, sweep trace and public electrode wire are formed on described transparency carrier, described the first insulation course is formed on described transparency carrier, and cover described grid, sweep trace and public electrode wire, described channel layer is formed on described the first insulation course, and just to described grid, described data line is formed on described the first insulation course, described source electrode and drain are formed on described the first insulation survey and described channel layer, and each interval is to expose described channel layer, described the first electrode is formed on described the first insulation course, and be electrically connected with described drain, described the second insulation course is formed on described the first insulation course, and cover described data line, source electrode, channel layer, drain and the first electrode, described the second electrode is formed on described the second insulation course, described the first electrode and described the second electrode are spaced apart by described the second insulation course.
6. thin film transistor base plate as claimed in claim 5, is characterized in that: described the first insulation course is gate insulator, and described the second insulation course is passivation layer.
7. thin film transistor base plate as claimed in claim 4, is characterized in that: the material of described the first electrode and the second electrode is tin indium oxide.
8. thin film transistor base plate as claimed in claim 4, is characterized in that: described the first electrode is public electrode, and described the second electrode is pixel electrode.
9. a display panels, comprise thin film transistor base plate, the subtend substrate as described in any one in claim 1 to 8 and be clipped in as described in liquid crystal layer between two substrates.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310303563.3A CN104122715A (en) | 2013-07-19 | 2013-07-19 | Thin film transistor substrate and LCD panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310303563.3A CN104122715A (en) | 2013-07-19 | 2013-07-19 | Thin film transistor substrate and LCD panel |
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| Publication Number | Publication Date |
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| CN104122715A true CN104122715A (en) | 2014-10-29 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201310303563.3A Pending CN104122715A (en) | 2013-07-19 | 2013-07-19 | Thin film transistor substrate and LCD panel |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105093727A (en) * | 2015-09-24 | 2015-11-25 | 京东方科技集团股份有限公司 | Array substrate, curved surface display panel and curved surface display device |
| CN107272287A (en) * | 2016-04-04 | 2017-10-20 | 三星显示有限公司 | Display device |
| CN109633997A (en) * | 2018-12-21 | 2019-04-16 | 惠科股份有限公司 | Substrate and display panel |
| CN112147823A (en) * | 2019-06-26 | 2020-12-29 | 群创光电股份有限公司 | Display device |
| US11088177B2 (en) * | 2018-07-23 | 2021-08-10 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Array substrate and manufacturing method thereof |
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| CN1779536A (en) * | 2004-11-19 | 2006-05-31 | 奇美电子股份有限公司 | Liquid-crystal display device and storage capacitor |
| KR20070001652A (en) * | 2005-06-29 | 2007-01-04 | 엘지.필립스 엘시디 주식회사 | Fringe field switching mode liquid crystal display device |
| CN101620346A (en) * | 2008-07-02 | 2010-01-06 | 爱普生映像元器件有限公司 | Liquid crystal display panel |
| KR20110066491A (en) * | 2009-12-11 | 2011-06-17 | 엘지디스플레이 주식회사 | Thin film transistor liquid crystal display device |
| CN102998863A (en) * | 2011-09-09 | 2013-03-27 | 乐金显示有限公司 | Array substrate for fringe field switching mode liquid crystal display device and method of fabricating the same |
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| CN1779536A (en) * | 2004-11-19 | 2006-05-31 | 奇美电子股份有限公司 | Liquid-crystal display device and storage capacitor |
| KR20070001652A (en) * | 2005-06-29 | 2007-01-04 | 엘지.필립스 엘시디 주식회사 | Fringe field switching mode liquid crystal display device |
| CN101620346A (en) * | 2008-07-02 | 2010-01-06 | 爱普生映像元器件有限公司 | Liquid crystal display panel |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105093727A (en) * | 2015-09-24 | 2015-11-25 | 京东方科技集团股份有限公司 | Array substrate, curved surface display panel and curved surface display device |
| US10014323B2 (en) | 2015-09-24 | 2018-07-03 | Boe Technology Group Co., Ltd. | Array substrate, curved display panel and curved display device |
| CN105093727B (en) * | 2015-09-24 | 2018-11-06 | 京东方科技集团股份有限公司 | A kind of array substrate, curved face display panel, curved-surface display device |
| CN107272287A (en) * | 2016-04-04 | 2017-10-20 | 三星显示有限公司 | Display device |
| US11088177B2 (en) * | 2018-07-23 | 2021-08-10 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Array substrate and manufacturing method thereof |
| CN109633997A (en) * | 2018-12-21 | 2019-04-16 | 惠科股份有限公司 | Substrate and display panel |
| CN112147823A (en) * | 2019-06-26 | 2020-12-29 | 群创光电股份有限公司 | Display device |
| CN112147823B (en) * | 2019-06-26 | 2024-04-12 | 群创光电股份有限公司 | Display apparatus |
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Application publication date: 20141029 |