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CN104112102A - Multi-DDR access control method and device supporting address intersection scheme configuration - Google Patents

Multi-DDR access control method and device supporting address intersection scheme configuration Download PDF

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Publication number
CN104112102A
CN104112102A CN201410307056.1A CN201410307056A CN104112102A CN 104112102 A CN104112102 A CN 104112102A CN 201410307056 A CN201410307056 A CN 201410307056A CN 104112102 A CN104112102 A CN 104112102A
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address
interleaved scheme
ddr
scheme
address interleaved
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CN104112102B (en
Inventor
刘胜
陈海燕
万江华
陈胜刚
陈书明
郭阳
葛磊磊
雷元武
马胜
王耀华
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National University of Defense Technology
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National University of Defense Technology
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

The invention discloses a multi-DDR access control method and device supporting address intersection scheme configuration. The method includes the steps that address intersection schemes, distributed among multiple DDR controllers, of external memory address space are configured as high address intersection schemes or low address intersection schemes or schemes combining the high address intersection schemes and the low address intersection schemes; when access to DDR space is requested, according to the configured address intersection schemes, a memory address of a request source is mapped in a final stage Cache sub-body corresponding to the target DDR controller. The device comprises an address intersection scheme configuration module corresponding to the method and an access route selection module. The multi-DDR access control method and device have the advantages that the method is simple, access efficiency is high, hardware cost is low, and the address intersection schemes can be flexibly configured according to actual requirements.

Description

Support many DDR access control method and the device of address interleaved scheme configuration
Technical field
The present invention relates to DDR (Double Data Rate SDRAM, Double Data Rate synchronous dynamic random access memory) controller technology field, relate in particular to a kind of many DDR access control method and device of supporting address interleaved scheme configuration.
Background technology
The current development along with application and the continuous progress of ic manufacturing technology, a plurality of traditional processor cores are integrated in same chip and make its collaborative polycaryon processor of organizing work efficiently, be widely used in a plurality of fields such as general-purpose computations, high-performance calculation, embedded calculating.The general integrated a plurality of DDR controllers of polycaryon processor are to make chip have larger memory bandwidth, also can make the chip can integrated more more jumbo memory grains simultaneously.The DDR controller of current main-stream is 3.0 versions, and more the DDR controller IP of highest version is also about to release.
How external memory address space distributes and to be called address interleaved scheme between a plurality of DDR controllers, high address interleaved scheme and low order address interleaved scheme are two kinds of address interleaved scheme commonly using, wherein high address interleaved scheme is which DDR controller the request that adopts the high position of memory access address to distinguish request source falls into, and it has advantages of easy expansion, good reliability.If programmer can be mapped to the data of a plurality of tasks respectively on nearest DDR controller, each task can operate on different DDR controllers by ensuring escapement from confliction, the resources such as the shared network on sheet, Cache are efficient access partly also, if yet single task program is mapped in the interleaved scheme system of high address, there will be the situation that a period of time only has a DDR controller to be used effectively, cause the waste of DDR controller effective bandwidth.Low order address interleaved scheme is to adopt the low level of memory access address to determine which DDR controller the request of request source falls into, same task will be mapped in different DDR controllers the access of continuation address, the Memory accessing delay of a plurality of DDR controllers will be piled up, thereby is conducive to give full play to the bandwidth with a plurality of DDR controllers.If yet some DDR controllers exist fault in low order address interleaved scheme, can expand to whole system, and also can cause the problems such as memory conflict increase when a plurality of task run.
In traditional multi-core processor system, between a plurality of DDR controllers, conventionally adopt fixing a kind of address interleaved scheme, in the M3000 server family of Ru Fujitsu company, adopted low order address interleaved scheme, the Niagara series processors of Sun Microsystems has also adopted similar low order address interleaved scheme.Although it is simple that fixing address interleaved scheme hardware is realized, exist use dumb and make the shortcomings such as some application program execution efficiency step-down.
In polycaryon processor often there is different memory access features in different application programs, also not identical to the demand of the address interleaved scheme between a plurality of DDR; Even in the different operation phase of same application program, its data memory access is also inconsistent to the demand of the address interleaved scheme between a plurality of DDR.This difference to the demand of address interleaved scheme between DDR, is in fact implying the difference that DDR, final stage Cache (Last Level Cache, LLC) and network-on-chip " sharing " and " privately owned " required.In addition, in low order address interleaved scheme, only can be more favourable to the utilization of memory bandwidth in some applications as minimum data cross granularity using the Cache line width of final stage Cache, the data granularity that different application is intersected to low order address often has different demands.
In sum, need to be by interleaved scheme configurable scheme in address between the many DDR of a kind of support be provided, make programmer the address interleaved scheme between different DDR is set neatly according to the differences different or the application execute phase of application, and then can utilize efficiently the resources such as DDR, final stage Cache, network-on-chip, make the fault-resistant ability of system also be strengthened simultaneously.
Summary of the invention
The technical problem to be solved in the present invention is just: the technical matters existing for prior art, the invention provides that a kind of implementation method is simple, access efficiency is high, hardware spending is little, can be according to different application programs and actual demand many DDR access control method and the device of the support address interleaved scheme configuration of configuration address interleaved scheme neatly.
For solving the problems of the technologies described above, the technical scheme that the present invention proposes is:
Support many DDR access control method of address interleaved scheme configuration, concrete implementation step is:
1) address interleaved scheme external memory address space being distributed between a plurality of DDR controllers is configured to high address interleaved scheme, low order address interleaved scheme or high address interleaved scheme and low order address interleaved scheme integrated mode;
2), when request access DDR space, the memory access address of request source being accessed to DDR space according to the described address interleaved scheme of configuration maps in the final stage Cache daughter that target DDR controller is corresponding.
As the further improvement of the inventive method, step 1) concrete implementation step be:
1.1) judge whether current application needs to enable high address interleaved scheme, if yes, is set to enable high address interleaved scheme, proceed to execution step 1.2); If NO, be set to not enable high address interleaved scheme and the address interleaved scheme of all external memory address spaces is configured to low order address interleaved scheme, proceeding to execution step 1.3);
1.2) judge whether current application also needs to enable low order address interleaved scheme, if yes, address interleaved scheme is configured to high address interleaved scheme and low order address interleaved scheme integrated mode and pattern configurations value N is set and N is not 0, wherein in external memory address space 1/2 nthe address interleaved scheme of address space be configured to high address interleaved scheme, all the other (1-1/2 n) the address interleaved scheme of address space be configured to low order address interleaved scheme, proceed to execution step 1.3); If NO, the pattern configurations value N that high address interleaved scheme and low order address interleaved scheme integrated mode are set is 0, and the address interleaved scheme of all external memory address spaces is configured to high address interleaved scheme, proceeds to execution step 2);
1.3) the interval unit of external memory address space between two adjacent DDR controllers in low order address interleaved scheme is set, proceeds to execution step 2).
Further improvement as the inventive method, described step 1) specific implementation method is: whether definition comprises for arranging needs the high address intersection of enabling high address interleaved scheme to make energy gap, the address interleaved scheme configuration register that territory is set and territory is set for the low level cross grain of low order address interleaved scheme external memory address space interval unit between two adjacent DDR controllers is set for the integrated mode of high address interleaved scheme and low order address interleaved scheme integrated mode pattern configurations value N is set, and configure described address interleaved scheme by described address interleaved scheme configuration register.
Further improvement as the inventive method, the described specific implementation method that configures described address interleaved scheme by described address interleaved scheme configuration register is: while being if desired configured to low order address interleaved scheme, high address being set and intersecting that to make the value of energy gap be 0; While being if desired configured to high address interleaved scheme, high address being set and intersecting that to make the value of energy gap be 1 and by integrated mode, territory be set pattern configurations value N is set is 0; While being if desired configured to high address interleaved scheme and low order address interleaved scheme integrated mode, high address being set and intersecting that to make the value of energy gap be 1 and by integrated mode, arrange that territory arranges pattern configurations value N and N is not 0; By low level cross grain, territory is set the interval unit of external memory address space between two adjacent DDR controllers in low order address interleaved scheme is set.
As the further improvement of the inventive method, described step 2) concrete implementation step be:
2.1) determining step 1) the middle address interleaved scheme configuring, and generate for carrying out the route judgement address BJA of target DDR controller route judgement according to the address A that seeks of request source, A be comprise 0～H-1 position request source seek address and width is H, when wherein if the address interleaved scheme of configuration is low order address interleaved scheme, proceed to execution step 2.2); If during the interleaved scheme of high address, proceed to execution step 2.3); If when high address interleaved scheme and low order address interleaved scheme integrated mode, proceed to execution step 2.4);
2.2) route judgement address BJA=A[L-1+log 2w:L], proceed to execution step 2.5);
2.3) route judgement address BJA=A[H-1:H-log2W], proceed to execution step 2.5);
2.4) if A[H-1:H-N]=0, route judges address BJA=A[H-N-1:H-N-log 2w]; If A[H-1:H-N] ≠ 0, route judges address BJA=A[L-1+log 2w:L], proceed to execution step 2.5);
2.5) according to the address realm of seeking address of request source and mapping function, route is judged to address BJA maps to the final stage Cache daughter that target DDR controller is corresponding;
Wherein W is the number of the daughter that comprises of final stage Cache, N is pattern configurations value, LOI_Grain is external memory address space interval unit between two adjacent DDR controllers in low order address interleaved scheme, and M is a capable byte number comprising of Cache in final stage Cache, and L=LOI_Grain+log 2m.
Further improvement as the inventive method, described step 2.5) specific implementation method is: the address realm of seeking address in judgement current request source, if address realm is in being configured to the address section of high address interleaved scheme, the value of described route judgement address BJA, with the final stage Cache daughter of DDR controller connection corresponding mapping one by one; If address realm is in being configured to the address section of low order address interleaved scheme, the value of described route judgement address BJA, the final stage Cache daughter that is connected with DDR controller are numbered and are shone upon according to cyclic module T, shine upon formula as follows:
Wherein W is the total number of final stage Cache daughter, and P is the number of the final stage Cache daughter that each DDR controller is corresponding.
As the further improvement of the inventive method, also comprise the address interleaved scheme switching flow while carrying out next task, step is:
3.1) result data of a upper task in DDR space is moved to non-DDR space, proceeded to execution step 3.2);
3.2) by the Cache that comprises DDR space copy in Cache system capable be set to invalid, proceed to execution step 3.3);
3.3) address interleaved scheme corresponding to configuration next task, proceeds to execution step 3.4);
3.4) program of next task is moved to corresponding DDR space according to the address interleaved scheme of configuration, and the address of program in DDR space described in mark, proceed to execution step 3.5);
3.5) jump to the address of described program in DDR space, the data-moving of next task, to DDR space, is completed to handoff procedure and starts and execute the task.
Support an access control apparatus between many DDR of address interleaved scheme configuration, comprising:
Address interleaved scheme configuration module, is configured to high address interleaved scheme, low order address interleaved scheme or high address interleaved scheme and low order address interleaved scheme integrated mode for the address interleaved scheme that external memory address space is distributed between a plurality of DDR controllers;
Access routing selecting module, for when the request access DDR space, the memory access address of request source being accessed to DDR space according to the described address interleaved scheme configuring maps in the final stage Cache daughter that target DDR controller is corresponding.
Further improvement as apparatus of the present invention: described address interleaved scheme configuration module comprises that high-order the intersection enables setting unit, integrated mode setting unit and low level cross grain setting unit; Described high-order the intersection enables setting unit setting and whether needs to enable high address interleaved scheme, described integrated mode setting unit arranges pattern configurations value N in high address interleaved scheme and low order address interleaved scheme integrated mode, and described low level cross grain is for arranging the interval unit of low order address interleaved scheme external memory address space between two adjacent DDR controllers.
Further improvement as apparatus of the present invention: described access routing selecting module comprises route judgement scalar/vector and route map unit, described route judgement scalar/vector generates route judgement address according to the address interleaved scheme of the memory access address of request source and the configuration of described address interleaved scheme configuration module; Route map unit judges that by route address BJA maps in the final stage Cache daughter that corresponding target DDR controller is corresponding according to the address realm of seeking address of request source and mapping function.
Compared with prior art, the invention has the advantages that:
1) in the present invention, adopt variable address interleaved scheme, by configuration, make user different address interleaved scheme to be set according to the demand of application, thus make application program sooner, the resource such as high bandwidth accessing DDR, final stage Cache, network-on-chip more; Address interleaved scheme can be configured to high address interleaved scheme, low order address interleaved scheme or high address interleaved scheme and low order address interleaved scheme integrated mode; make it possible to have concurrently the advantage of high address interleaved scheme and low order address interleaved scheme; even and the some DDR particles in multi-core processor system or DDR controller be when break down, system storage path still can continue normal work.
2) the present invention is by an address interleaved scheme configuration register configuration address interleaved scheme, only need to just can be configured according to a certain position of flow process modified address interleaved scheme configuration register or several, and collocation method is easy and flexible.
3) the logic expense while adopting variable address interleaved scheme only to increase the expense of address interleaved scheme configuration (as address interleaved scheme configuration register) and network-on-chip in the present invention, according to the configuration of address interleaved scheme, message or request are carried out to Route Selection, and the logic expense of address interleaved scheme configuration overhead and Route Selection is comprised of trigger or the small-scale selection logic of less width, therefore required hardware area and power consumption expense are less and do not affect the critical path time delay of system, be highly suitable in the multi-core processor system of a plurality of DDR controllers of current employing.
Accompanying drawing explanation
Fig. 1 is many DDR access control method schematic flow sheet that the present embodiment is supported address interleaved scheme configuration.
Fig. 2 is address interleaved scheme configuration register AISR structural representation in the present embodiment.
Fig. 3 is the present invention's realization flow schematic diagram that executive address interleaved scheme is switched in concrete application.
Fig. 4 is the multi-core processor system structural representation with a plurality of DDR controllers adopting in the specific embodiment of the invention.
Fig. 5 is many DDR access control method principle schematic of supporting address interleaved scheme configuration in the specific embodiment of the invention.
Fig. 6 is route judgement address BJA generating principle schematic diagram in the specific embodiment of the invention.
Fig. 7 is route judgement address BJA and the target device mapping relations schematic diagram of high address interleaved scheme in the specific embodiment of the invention.
Fig. 8 is route judgement address BJA and the target device mapping relations schematic diagram of low order address interleaved scheme in the specific embodiment of the invention.
Embodiment
Below in conjunction with Figure of description, the invention will be further described with concrete preferred embodiment, but protection domain not thereby limiting the invention.
As shown in Figure 1, the present embodiment is supported many DDR access control method of address interleaved scheme configuration, and concrete implementation step is:
1) address interleaved scheme external memory address space being distributed between a plurality of DDR controllers is configured to high address interleaved scheme, low order address interleaved scheme or high address interleaved scheme and low order address interleaved scheme integrated mode;
2), when request access DDR space, the memory access address of request source being accessed to DDR space according to the described address interleaved scheme of configuration maps in the final stage Cache daughter that target DDR controller is corresponding.
By configurable address interleaved scheme, can suitable address interleaved scheme be set according to application program and actual demand; thereby make application program sooner, the resource such as high bandwidth accessing DDR, final stage Cache, network-on-chip more; configurable address interleaved scheme is compared with traditional fixed address interleaved scheme; can have the advantage of high address interleaved scheme and low order address interleaved scheme concurrently; even and the some DDR particles in multi-core processor system or DDR controller be when break down, system storage path still can continue normal work.
In the present embodiment, step 1) concrete implementation step is:
1.1) judge whether current application needs to enable high address interleaved scheme, if yes, is set to enable high address interleaved scheme, proceed to execution step 1.2); If NO, be set to not enable high address interleaved scheme and the address interleaved scheme of all external memory address spaces is configured to low order address interleaved scheme, proceeding to execution step 1.3);
1.2) judge whether current application also needs to enable low order address interleaved scheme, if yes, address interleaved scheme is configured to high address interleaved scheme and low order address interleaved scheme integrated mode and pattern configurations value N is set and N is not 0, wherein in external memory address space 1/2 nthe address interleaved scheme of address space be configured to high address interleaved scheme, all the other (1-1/2 n) the address interleaved scheme of address space be configured to low order address interleaved scheme, proceed to execution step 1.3); If NO, the pattern configurations value N that high address interleaved scheme and low order address interleaved scheme integrated mode are set is 0, and the address interleaved scheme of all external memory address spaces is configured to high address interleaved scheme, proceeds to execution step 2);
1.3) the interval unit of external memory address space between two adjacent DDR controllers in low order address interleaved scheme is set, proceeds to execution step 2).
In the present embodiment, step 1) specifically by one, having high address intersects and to make energy gap, integrated mode that the address interleaved scheme configuration register (Address Interleaving Scheme Register, AISR) that territory and low level cross grain arrange territory is set to realize.As shown in Figure 2, address interleaved scheme configuration register AISR structure in the present embodiment, comprise that high address intersection makes energy gap (En), integrated mode that territory (Mode) is set and low level cross grain arranges territory (LOI-Grain), all the other positions are for retaining position (Reserved), and the overall width of register is identical with the machine word-length of processor (being assumed to 32 bits).
In the present embodiment, high address intersects makes energy gap for enabling high address interleaved scheme, and when high address intersection makes energy gap En be set to 0, all external memory address spaces distribute between a plurality of DDR controllers according to low order address interleaved scheme; When high address intersection makes energy gap En be set to 1, the part in external memory address space is set to adopt high address interleaved scheme to distribute, and remaining part is set to adopt low order address interleaved scheme to distribute.Integrated mode arranges territory Mode for high address interleaved scheme and low order address interleaved scheme integrated mode pattern configurations value N are set, and by pattern configurations value N, is determined and is adopted the intersection space, high address of high address interleaved scheme to account for the ratio in whole external space; Particularly, the value N that territory Mode is set when integrated mode is set to respectively 0,1,2 ..., during N, intersection space, corresponding high address occupies respectively the whole of whole external space, and 1/2,1/4 ..., 1/2 n.Low level cross grain arranges territory LOI-Grain and is used for arranging the interval unit between two adjacent DDR controllers in the low order address intersection space that adopts low level interleaved scheme; The line width of the final stage Cache of supposing the system is M byte, when low level cross grain arranges territory LOI-Grain, is set to respectively 0,1,2 ..., during T, the interval unit in corresponding low order address intersection space is respectively M, 2M, and 4M ..., 2 tm byte.In the time of need to carrying out address interleaved scheme configuration, user only need to, according to a certain or several of flow process modified address interleaved scheme configuration register AISR, just can be configured the address interleaved scheme between many DDR.
In the present embodiment, the specific implementation method by address interleaved scheme configuration register configuration address interleaved scheme is: while being if desired configured to low order address interleaved scheme, high address being set and intersecting that to make the value of energy gap En be 0; While being if desired configured to high address interleaved scheme, high address being set and intersecting that to make the value of energy gap En be 1 and by integrated mode, arrange that territory Mode arranges pattern configurations value N and N is 0; While being if desired configured to the address interleaved scheme of high address interleaved scheme and low order address interleaved scheme combination, high address being set and intersecting and make the value of energy gap En be 1, by integrated mode, arrange that territory Mode arranges pattern configurations value N and N is not 0; If while being configured to low order address interleaved scheme, the value that low level cross grain arranges territory LOI-Grain is set, can meet the different demands of different application to the data granularity of low order address intersection., when high address intersection makes energy gap En be set to 0, address interleaved scheme is configured to low order address interleaved scheme; When high address intersection makes energy gap En be set to 1, enable high address interleaved scheme, pattern configurations value N be not 0 o'clock for being configured to high address interleaved scheme and low order address interleaved scheme integrated mode, pattern configurations value N is 0 o'clock, address interleaved scheme is configured to high address interleaved scheme.
In the present embodiment, the request source in each access DDR space is through the final stage Cache daughter corresponding to target DDR controller of the concrete access of route mapping judgement, the value that the concrete methods of realizing of route mapping is arranged by address interleaved scheme configuration register AISR determines, according to the address interleaved scheme of concrete configuration, carries out route mapping.Step 2) the concrete implementation step that according to the address interleaved scheme of configuration, the memory access address of request source is mapped to the final stage Cache daughter that target DDR controller is corresponding is:
2.1) determining step 1) the middle address interleaved scheme configuring, according to the address A that seeks of request source, generate for carrying out the route judgement address BJA of target DDR controller route judgement, A be comprise 0～H-1 position request source seek address and width is H, when wherein if the address interleaved scheme of configuration is low order address interleaved scheme (En=0), proceed to execution step 2.2); If during the interleaved scheme of high address (En=1, N=0), proceed to execution step 2.3); If when high address interleaved scheme and low order address interleaved scheme integrated mode (En=1, N ≠ 0), proceed to execution step 2.4);
2.2) route judgement address BJA=A[L-1+log 2w:L], proceed to execution step 2.5);
2.3) route judgement address BJA=A[H-1:H-log2W], proceed to execution step 2.5);
2.4) if A[H-1:H-N]=0, route judges address BJA=A[H-N-1:H-N-log 2w]; If A[H-1:H-N] ≠ 0, route judges address BJA=A[L-1+log 2w:L], proceed to execution step 2.5);
2.5) according to the address realm of seeking address of request source and mapping function, route is judged to address BJA maps to the final stage Cache daughter that target DDR controller is corresponding.
Wherein W is the number of the daughter that comprises of LLC; Pattern configurations value N is the value in AISR register Mode territory; LOI_Grain is the value in AISR register LOI_Grain territory; M is the capable byte number comprising of Cache of final stage Cache; L=LOI_Grain+log 2m; En is the value in AISR register En territory.
In the present embodiment, step 2.1) determining step 1 in), the specific implementation method of the address interleaved scheme of configuration is: judge that high address intersection makes whether the value of energy gap En is 1, if not 1 o'clock, judgement address interleaved scheme is low order address interleaved scheme, and all external memory address spaces distribute according to low order address interleaved scheme between a plurality of DDR controllers; If 1, continue judgment model Configuration Values N, if pattern configurations value N is 0 o'clock, judgement address interleaved scheme is high address interleaved scheme, all external memory address spaces distribute according to high address interleaved scheme between a plurality of DDR controllers, if pattern configurations value N is not 0 o'clock, judgement address interleaved scheme is high address interleaved scheme and low order address interleaved scheme integrated mode, in external memory address space 1/2 nthe address interleaved scheme that distributes between a plurality of DDR controllers of address space be high address interleaved scheme, all the other (1-1/2 n) the address interleaved scheme of address space be low order address interleaved scheme.
Step 2.5 in the present embodiment) specific implementation method is: the address realm of seeking address in judgement current request source, if address realm is in being configured to the address section of high address interleaved scheme, the value of route judgement address BJA, with the final stage Cache daughter of DDR controller connection corresponding mapping one by one, if address realm is in being configured to the address section of low order address interleaved scheme, the value of route judgement address BJA, the final stage Cache daughter that is connected with DDR controller are numbered and are shone upon according to cyclic module T, shine upon formula and are: wherein W is the total number of final stage Cache daughter, and P is the number of the final stage Cache daughter that each DDR controller is corresponding.
In the present embodiment, if need to switch address interleaved scheme between a upper task and new task in application program, as shown in Figure 3, the specific implementation flow process of switching address interleaved scheme is as follows:
1. the result data of a upper task in DDR space is moved to non-DDR space;
2. check whether move completely, if move completely, go to 3., otherwise return to execution 1.;
3. by the Cache that comprises DDR space copy in Cache system (comprising the final stage Cache that is connected with DDR controller and other Cache) capable be set to invalid;
4. check whether setting completed, if setting completed, go to 5., otherwise return to execution 3.;
5. program jumps to the non-DDR space (as flash space etc.) of system, and the value of new address interleaved scheme configuration register AISR is set;
6. the program of new task is moved to DDR space, and the address in DDR space is designated as E by new procedures;
7. check whether move completely, if move complete going to 8., otherwise return to execution 6.;
8. program jumps to the entry address E of new task in DDR space;
9. by the data-moving of new task to DDR space;
10. check whether move completely, if move completely, complete handoff procedure and start the execution of new task, otherwise return to execution 9..
During work, user only need to be according to a certain or several of the flow process coding of above-mentioned switching address interleaved scheme, modified address interleaved scheme register, just can configure and change the address interleaved scheme between DDR controller, carry out the access control between many DDR controller.
Take below in multi-core processor system and the present invention to be further described as example by 4 DDR controllers of 8 final stage Cache daughters access.
As shown in Figure 4, the multi-core processor system in the specific embodiment of the invention with a plurality of DDR controllers, comprise polycaryon processor core (Core0, Core1,, Core7), network-on-chip (Network on Chip, NoC), final stage Cache and 4 DDR controller (DDRC0, DDRC1, DDRC2 and DDRC3), polycaryon processor core (Core0, Core1 wherein, Core7) by network-on-chip NoC final stage Cache, be connected, final stage Cache adopts distributed design approach and by a plurality of daughter LLC0, LLC1,, LLC7 forms; The final stage Cache other end and DDR controller (DDRC0, DDRC1, DDRC2 and DDRC3) are connected and every two LLC daughters have been connected a DDR controller.
As shown in Figure 5, in the specific embodiment of the invention (4 DDR controllers), support many DDR access control method principle of address interleaved scheme configuration, system request is by 4 DDR controller (DDRC0 of 8 LLC access, DDRC1, DDRC2 and DDRC3), the address of supposing the access DDR of request source is A, and the address width of A is to be total to H position from 0 to H-1; In the interleaved scheme configuration register AISR of address, integrated mode arranges territory Mode and comprises two, and L=LOI_Grain+log 2m, wherein M is the byte number of the line width of final stage Cache.Address interleaved scheme can be configured to high address interleaved scheme, low order address interleaved scheme and high address interleaved scheme and low order address interleaved scheme integrated mode, therefore in whole DDR space, exist the high address transposition section that adopts high address interleaved scheme and two regions of low order address transposition section that adopt low order address interleaved scheme, when the capacity configuration of a high position or low order address transposition section is zero, DDR space is according to single low level or high address interleaved scheme distribution external memory address space.
In the present embodiment, intersection space, high address intersects space rear at front, low order address, and certainly in other embodiments, the position of high address transposition section and low order address transposition section also can be other organizational forms.As shown in Figure 5, in the transposition section of high address, adopt high address interleaved scheme, the front 1/4 continuous space of whole high address transposition section (0,1 ..., M0-1) continuous distribution in DDR0 controller; Ensuing 1/4 continuous space (M0, M+1 ..., M1-1) continuous distribution in DDR1 controller; Again 1/4 continuous space (M1, M1+1 ..., M2-1) continuous distribution in DDR2 controller; Last 1/4 continuous space (M2, M2+1 ..., M3-1) continuous distribution in DDR3 controller, makes continuous address form broken line (as shown in the broken line arrow that dotted line in figure represents) longitudinally at high address transposition section.In low order address transposition section, adopt low order address interleaved scheme, address space be take fundamental block as continuous being distributed on 4 DDR controllers of unit (in figure one fill shaded block be a fundamental block), and the size of fundamental block low level cross grain in the interleaved scheme configuration register AISR of address arranges territory LOI_Grain and determines (byte number=2 that fundamental block comprises tm, T is the value of LOI_Grain, M is the capable byte number comprising of Cache of final stage Cache), the distribution mode of fundamental block as shown in the figure, fundamental block M3 distributes in DDR0 controller, next fundamental block M3+1 distributes in DDR1 controller, next fundamental block M3+2 distributes in DDR2 controller, next fundamental block M3+3 distributes in DDR3 controller, next fundamental block M3+4 distributes in DDR0 controller ..., make continuous address form horizontal broken line (as shown in the lateral arrows that dotted line in figure represents) at low order address transposition section.
In the present embodiment, the request source in each request access DDR space generates route judgement address BJA according to the value of address interleaved scheme configuration register AISR, as shown in Figure 6, detailed process is as follows: first judge that high address intersection makes whether the value of energy gap En is 1, if be not 1, route judges address BJA=A[L+2:L], otherwise the value that territory Mode is set according to integrated mode further judges, if and integrated mode arranges territory Mode=2 ' b00, be pattern configurations value N=0, whole DDR space is all according to high address interleaved scheme tissue, route judges address BJA=A[H-1:H-3], if Mode=2 ' is b01, be pattern configurations value N=1, front 1/2 of whole DDR space according to high address interleaved scheme tissue, rear 1/2 according to low order address interleaved scheme tissue, if and A[H-1] be 0, route judges address BJA=A[H-2:H-4], otherwise route judgement address BJA=A[L+2:L], if integrated mode arranges territory Mode=2 ' b10, be pattern configurations value N=2, front 1/4 of whole DDR space according to high address interleaved scheme tissue, rear 3/4 according to low order address interleaved scheme tissue, if and A[H-1:H-2] be 0, route judges address BJA=A[H-3:H-5], otherwise route judgement address BJA=A[L+2:L], if integrated mode arranges territory Mode=2 ' b11, be pattern configurations value N=3, front 1/8 of whole DDR according to high address interleaved scheme tissue, rear 7/8 according to low order address interleaved scheme tissue, if and A[H-1:H-3] be 0, route judges address BJA=A[H-4:H-6], otherwise route judgement address BJA=A[L+2:L].
In the present embodiment, route judgement address BJA maps to according to concrete mapping function the final stage Cache daughter that target DDR controller is corresponding, as shown in Figure 7,8.The route mapping relationship of route judgement address BJA and target device LLC daughter in the present embodiment, if high address transposition section is dropped in current request address, as shown in Figure 7, the value of the numbering of LLC daughter and route judgement address BJA is corresponding completely one by one; If low order address transposition section is dropped in current request address, as shown in Figure 8, the value of route judgement address BJA is 0,1 ..., 7 o'clock, the numbering of LLC daughter was respectively: 0,2,4,6,1,3,5,7.
In the present embodiment multi-core processor system, LLC daughter and polycaryon processor core Core all carry out interconnected as the node of network-on-chip NoC, every two LLC daughters have connected a DDR controller, certainly between LLC daughter in other embodiments, polycaryon processor core Core, network-on-chip NoC and DDR controller, also can adopt other to be connected and organizational form, the corresponding route mapping policy of different connections or organizational form is slightly different, and its principle is with above-mentioned consistent.
Adopt such scheme, logic expense while adopting expense, network-on-chip that configurable address interleaved scheme only increased address interleaved scheme configuration register AISR, according to address interleaved scheme configuration register AISR, message or request are carried out to Route Selection etc., these hardware are comprised of trigger or the small-scale selection logic of less width, and required hardware area and power consumption expense are less and do not affect the critical path time delay of system.
The present embodiment also provides access control apparatus between a kind of many DDR that support the configuration of address interleaved scheme, comprising:
Address interleaved scheme configuration module, is configured to high address interleaved scheme, low order address interleaved scheme or high address interleaved scheme and low order address interleaved scheme integrated mode for the address interleaved scheme that external memory address space is distributed between a plurality of DDR controllers;
Access routing selecting module, for when the request access DDR space, the memory access address of request source being accessed to DDR space according to the described address interleaved scheme configuring maps in the final stage Cache daughter that target DDR controller is corresponding.
In the present embodiment, address interleaved scheme configuration module comprises that high-order the intersection enables setting unit, integrated mode setting unit and low level cross grain setting unit; High-order intersection enables setting unit and enables high address interleaved scheme, integrated mode setting unit arranges pattern configurations value N in high address interleaved scheme and low order address interleaved scheme integrated mode, and low level cross grain is for arranging the interval unit of low order address interleaved scheme external memory address space between two adjacent DDR controllers.
In the present embodiment, address interleaved scheme configuration module intersects and to make energy gap En, integrated mode that the address interleaved scheme configuration register AISR that territory Mode and low level cross grain arrange territory LOI-Grain is set to realize by having high address, and address interleaved scheme configuration register AISR structure as mentioned above.
In the present embodiment, access routing selecting module comprises route judgement scalar/vector and route map unit, route judgement scalar/vector generates route judgement address BJA according to the address interleaved scheme of the memory access address according to request source and the configuration of described address interleaved scheme configuration module, and route judgement address BJA is used for carrying out Route Selection; Route map unit judges that by route address BJA maps to the final stage Cache daughter that corresponding target DDR controller is corresponding according to the address realm of seeking address of request source and mapping function.
Between many DDR that between many DDR of the present embodiment support address interleaved scheme configuration, access control apparatus configures with above-mentioned support address interleaved scheme, access control method is corresponding, it is consistent that it has structure and principle of work that between the many DDR that configure with above-mentioned support address interleaved scheme, access control method is corresponding, do not repeat them here.
Above-mentioned is preferred embodiment of the present invention, not the present invention is done to any pro forma restriction.Although the present invention discloses as above with preferred embodiment, yet not in order to limit the present invention.Any those of ordinary skill in the art, in the situation that not departing from technical solution of the present invention scope, can utilize the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solution of the present invention,, all should drop in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to the technology of the present invention essence.

Claims (10)

1. many DDR access control method of supporting address interleaved scheme configuration, is characterized in that, concrete implementation step is:
1) address interleaved scheme external memory address space being distributed between a plurality of DDR controllers is configured to high address interleaved scheme, low order address interleaved scheme or high address interleaved scheme and low order address interleaved scheme integrated mode;
2), when request access DDR space, the memory access address of request source being accessed to DDR space according to the described address interleaved scheme of configuration maps in the final stage Cache daughter that target DDR controller is corresponding.
2. many DDR access control method of support according to claim 1 address interleaved scheme configuration, is characterized in that step 1) concrete implementation step be:
1.1) judge whether current application needs to enable high address interleaved scheme, if yes, is set to enable high address interleaved scheme, proceed to execution step 1.2); If NO, be set to not enable high address interleaved scheme and the address interleaved scheme of all external memory address spaces is configured to low order address interleaved scheme, proceeding to execution step 1.3);
1.2) judge whether current application also needs to enable low order address interleaved scheme, if yes, address interleaved scheme is configured to high address interleaved scheme and low order address interleaved scheme integrated mode and pattern configurations value N is set and N is not 0, wherein in external memory address space 1/2 nthe address interleaved scheme of address space be configured to high address interleaved scheme, all the other (1-1/2 n) the address interleaved scheme of address space be configured to low order address interleaved scheme, proceed to execution step 1.3); If NO, the pattern configurations value N that high address interleaved scheme and low order address interleaved scheme integrated mode are set is 0, and the address interleaved scheme of all external memory address spaces is configured to high address interleaved scheme, proceeds to execution step 2);
1.3) the interval unit of external memory address space between two adjacent DDR controllers in low order address interleaved scheme is set, proceeds to execution step 2).
3. many DDR access control method that support according to claim 2 address interleaved scheme configures, it is characterized in that, described step 1) specific implementation method is: whether definition comprises for arranging needs the high address intersection of enabling high address interleaved scheme to make energy gap, the address interleaved scheme configuration register that territory is set and territory is set for the low level cross grain of low order address interleaved scheme external memory address space interval unit between two adjacent DDR controllers is set for the integrated mode of high address interleaved scheme and low order address interleaved scheme integrated mode pattern configurations value N is set, and configure described address interleaved scheme by described address interleaved scheme configuration register.
4. many DDR access control method that support according to claim 3 address interleaved scheme configures, it is characterized in that, the described specific implementation method that configures described address interleaved scheme by described address interleaved scheme configuration register is: while being if desired configured to low order address interleaved scheme, high address being set and intersecting that to make the value of energy gap be 0; While being if desired configured to high address interleaved scheme, high address being set and intersecting that to make the value of energy gap be 1 and by integrated mode, territory be set pattern configurations value N is set is 0; While being if desired configured to high address interleaved scheme and low order address interleaved scheme integrated mode, high address being set and intersecting that to make the value of energy gap be 1 and by integrated mode, arrange that territory arranges pattern configurations value N and N is not 0; By low level cross grain, territory is set the interval unit of external memory address space between two adjacent DDR controllers in low order address interleaved scheme is set.
5. according to many DDR access control method of the support address interleaved scheme configuration described in claim 2 or 3 or 4, it is characterized in that described step 2) concrete implementation step be:
2.1) determining step 1) the middle address interleaved scheme configuring, and generate for carrying out the route judgement address BJA of target DDR controller route judgement according to the address A that seeks of request source, A be comprise 0～H-1 position request source seek address and width is H, when wherein if the address interleaved scheme of configuration is low order address interleaved scheme, proceed to execution step 2.2); If during the interleaved scheme of high address, proceed to execution step 2.3); If when high address interleaved scheme and low order address interleaved scheme integrated mode, proceed to execution step 2.4);
2.2) route judgement address BJA=A[L-1+log 2w:L], proceed to execution step 2.5);
2.3) route judgement address BJA=A[H-1:H-log2W], proceed to execution step 2.5);
2.4) if A[H-1:H-N]=0, route judges address BJA=A[H-N-1:H-N-log 2w]; If A[H-1:H-N] ≠ 0, route judges address BJA=A[L-1+log 2w:L], proceed to execution step 2.5);
2.5) according to the address realm of seeking address of request source and mapping function, route is judged to address BJA maps to the final stage Cache daughter that target DDR controller is corresponding;
Wherein W is the total number of the daughter that comprises of final stage Cache, N is pattern configurations value, LOI_Grain is external memory address space interval unit between two adjacent DDR controllers in low order address interleaved scheme, and M is a capable byte number comprising of Cache in final stage Cache, and L=LOI_Grain+log 2m.
6. many DDR access control method that support according to claim 5 address interleaved scheme configures, it is characterized in that, described step 2.5) specific implementation method is: the address realm of seeking address in judgement current request source, if address realm is in being configured to the address section of high address interleaved scheme, the value of described route judgement address BJA, with the final stage Cache daughter of DDR controller connection corresponding mapping one by one; If address realm is in being configured to the address section of low order address interleaved scheme, the value of described route judgement address BJA, the final stage Cache daughter that is connected with DDR controller are numbered and are shone upon according to cyclic module T, shine upon formula as follows:
Wherein W is the total number of the daughter that comprises of final stage Cache, and P is the number of the final stage Cache daughter that each DDR controller is corresponding.
7. according to many DDR access control method of the support address interleaved scheme configuration described in any one in 1～4 described in right, it is characterized in that, also comprise the address interleaved scheme switching flow while carrying out next task, step is:
3.1) result data of a upper task in DDR space is moved to non-DDR space, proceeded to execution step 3.2);
3.2) by the Cache that comprises DDR space copy in Cache system capable be set to invalid, proceed to execution step 3.3);
3.3) address interleaved scheme corresponding to configuration next task, proceeds to execution step 3.4);
3.4) program of next task is moved to corresponding DDR space according to the address interleaved scheme of configuration, and the address of program in DDR space described in mark, proceed to execution step 3.5);
3.5) jump to the address of described program in DDR space, the data-moving of next task, to DDR space, is completed to handoff procedure and starts and execute the task.
8. support an access control apparatus between many DDR of address interleaved scheme configuration, it is characterized in that comprising:
Address interleaved scheme configuration module, is configured to high address interleaved scheme, low order address interleaved scheme or high address interleaved scheme and low order address interleaved scheme integrated mode for the address interleaved scheme that external memory address space is distributed between a plurality of DDR controllers;
Access routing selecting module, for when the request access DDR space, the memory access address of request source being accessed to DDR space according to the described address interleaved scheme configuring maps in the final stage Cache daughter that target DDR controller is corresponding.
9. many DDR access control apparatus of support according to claim 8 address interleaved scheme configuration, is characterized in that: described address interleaved scheme configuration module comprises that high-order the intersection enables setting unit, integrated mode setting unit and low level cross grain setting unit; Described high-order the intersection enables setting unit setting and whether needs to enable high address interleaved scheme, described integrated mode setting unit arranges pattern configurations value N in high address interleaved scheme and low order address interleaved scheme integrated mode, and described low level cross grain is for arranging the interval unit of low order address interleaved scheme external memory address space between two adjacent DDR controllers.
10. many DDR access control apparatus of support address interleaved scheme configuration according to claim 8 or claim 9, it is characterized in that: described access routing selecting module comprises route judgement scalar/vector and route map unit, described route judgement scalar/vector generates route judgement address BJA according to the address interleaved scheme of the memory access address of request source and the configuration of described address interleaved scheme configuration module; Route map unit judges that by route address BJA maps in the final stage Cache daughter that corresponding target DDR controller is corresponding according to the address realm of seeking address of request source and mapping function.
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