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CN104102586B - A kind of method, apparatus of address of cache processing - Google Patents

A kind of method, apparatus of address of cache processing Download PDF

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CN104102586B
CN104102586B CN201310130486.6A CN201310130486A CN104102586B CN 104102586 B CN104102586 B CN 104102586B CN 201310130486 A CN201310130486 A CN 201310130486A CN 104102586 B CN104102586 B CN 104102586B
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address
physical
segment
intra
logical address
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CN104102586A (en
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黄苏
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Sanechips Technology Co Ltd
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ZTE Corp
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation

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  • Theoretical Computer Science (AREA)
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  • General Physics & Mathematics (AREA)
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Abstract

The invention discloses a kind of method and devices of address of cache processing, this method comprises: according to Double Data Rate synchronous random access memory (DDR) quantity of current-configuration to logical address subregion;The processing of the mapping between logical address and physical address is carried out respectively according to the logical address of segment each after subregion.The map processing unit of the device is used to carry out the processing of the mapping between logical address and physical address respectively according to the logical address of segment each after subregion.Using the present invention, RAM resource had not only been saved, but also has been able to achieve the efficient management to physical address.

Description

Address mapping processing method and device
Technical Field
The present invention relates to an address mapping technology in the field of data communication, and in particular, to a method and an apparatus for address mapping processing.
Background
A DDR SDRAM, which is a new generation of memory technology standard issued by Joint Electron Device Engineering Council (JEDEC) and 2004, is widely used in the field of data communication with high storage requirements due to its advantages of low price, high bandwidth data throughput, and low power consumption. However, in the field of data communication chips, the key performance index of a chip is the number of Packets Per Second (PPS), which determines that DDR SDRAM for packet buffering must achieve the lowest read/write efficiency to meet the processing capability of the chip. Meanwhile, because of cost factor, the data throughput rate of the whole chip cannot be improved by simply increasing the number of physical chips of the ddr sdram.
The DDR SDRAM is widely applied to the field of data communication chips, and is used for caching packet data in a message processing process, and is currently a third generation product of DDR, namely DDR3SDRAM, which is hereinafter referred to as DDR 3. The general processing modes of the data communication chip are as follows: after the data packet is processed by the MAC layer, the data packet is firstly buffered in an off-chip DDR3 chip, and simultaneously, a DDR3 physical address of the buffered data packet is generated and used as a part of the characteristic information of the data packet to continue other processing such as protocol and QoS functions. For the ethernet data packet, the minimum length of the packet is 64B, and meanwhile, the bit width of the burst address of the current mainstream DDR3 is 16B, it can be seen that at least 4 burst addresses are required for one data packet, and if the DDR3 physical address of the data packet is directly used as the characteristic information, at least 4 physical addresses need to be carried, which results in resource increase.
In order to reduce the overhead, the prior art generally adopts a logical address as the characteristic information of a packet cache address, one logical address represents a plurality of DDR3 physical addresses, and this scheme requires a one-to-one mapping relationship between the logical address and the physical address of the DDR3, but the prior art has the following problems: the processing scheme of address mapping wastes RAM resources and cannot realize efficient management of physical addresses
Disclosure of Invention
In view of the above, the main objective of the present invention is to provide an address mapping processing method and apparatus, which not only saves RAM resources, but also can implement efficient management on physical addresses.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
a method of address mapping processing, the method comprising:
partitioning the logic address according to the number of the currently configured double data rate synchronous random access memories DDR;
and mapping processing between the logical address and the physical address is respectively carried out according to the logical address of each partitioned segment.
Wherein the partitioning the logical address according to the currently configured DDR number specifically includes:
obtaining a total physical bank number according to the number of the DDR and the number of the physical memory bank banks contained in each DDR;
dividing the total logical address into a plurality of logical address segments equally, wherein the segment number is 2 in all common divisor of the total physical bank numbernN refers to the number of linked lists in the segment.
The mapping processing between the logical address and the physical address according to the logical address of each partitioned segment specifically includes:
number 2nUnder the condition of (1), each logical address segment corresponds to one physical bank, and is one-to-one mapping between the logical address and the physical address;
a value of not 2nIn the case of (3), each logical address segment corresponds to a plurality of physical banks, and is a one-to-many mapping between a logical address and a physical address.
Wherein, the method also comprises: and when the one-to-many mapping is carried out, configuring offset base addresses in the segments for each physical bank, wherein the number of the offset base addresses in the segments is n-1.
Wherein, the method also comprises: and obtaining the intra-segment offset physical bank address corresponding to the intra-segment offset address according to the intra-segment offset base address and the intra-segment offset address.
Wherein, the method also comprises: and obtaining a corresponding physical row address and a physical column address according to the intra-segment offset physical bank address.
An apparatus of address mapping processing, the apparatus comprising: a partition processing unit and a mapping processing unit; wherein,
the partition processing unit is used for partitioning the logic address according to the number of the currently configured DDR;
and the mapping processing unit is used for respectively mapping the logical address and the physical address according to the logical address of each partitioned segment.
The partition processing unit is further configured to obtain a total physical bank number according to the number of the DDRs and the number of the physical bank banks included in each DDR, equally divide a total logical address into a plurality of logical address segments, and the segment number is 2 of all common divisor of the total physical bank numbernN refers to the number of linked lists in the segment.
Wherein the mapping processing unit is further configured to obtain a value of 2nUnder the condition of (1), each logic address segment corresponds to one physical bank, and the mapping is one-to-one mapping between the logic address and the physical address; a value of not 2nIn the case of (3), each logical address segment is associated with a plurality of physical banks, and thus, one-to-many mapping between logical addresses and physical addresses is performed.
The mapping processing unit is further configured to configure an intra-segment offset base address for each physical bank when mapping is performed one-to-many, where the number of the intra-segment offset base addresses is n-1; obtaining an intra-segment offset physical bank address corresponding to the intra-segment offset address according to the intra-segment offset base address and the intra-segment offset address; and obtaining a corresponding physical row address and a physical column address according to the intra-segment offset physical bank address.
The scheme of the invention partitions the logic address according to the number of the DDR configured currently; and mapping processing between the logical address and the physical address is respectively carried out according to the logical address of each partitioned segment. The invention does not directly map the total logic address from the logic address to the physical address, but maps the total logic address after partitioning, thereby reducing the occupation of the logic address, saving RAM resources, facilitating the realization of address addressing by fewer logic addresses and realizing the high-efficiency management of the physical address.
Drawings
FIG. 1 is a flow chart of a method of the present invention;
FIG. 2 is a block diagram of logic addresses with different DDR3 numbers according to the first embodiment of the present invention;
FIG. 3 is a schematic diagram of a mapping apparatus according to a second embodiment of the present invention;
FIG. 4 is a block diagram of a decoding apparatus for implementing a decoding process based on mapping according to a third embodiment of the present invention.
Detailed Description
The scheme of the invention is a one-to-many mapping processing scheme between the logic address and the physical address of DDR3, the system design requirement is met by using the least logic address resources, the logic address is divided into the blocks according to the number of DDR3 configured by the current system, and then the mapping between the logic address and the physical address is carried out according to the blocks.
For simplicity of description, when the linked list array form is expressed, the logical address is referred to as PMAU description for short, and the full-text memory bank (bank) refers to physical bank instead of logical physical bank. N herein refers to the number of linked lists within a segment.
The following describes the embodiments in further detail with reference to the accompanying drawings.
Fig. 1 is a schematic flow chart of the method of the present invention, which includes the following steps:
and step 101, partitioning the logic address according to the number of the currently configured DDR.
And 102, respectively carrying out one-to-many mapping processing between the logical address and the physical address according to the logical address of each partitioned segment.
Application example one: the present embodiment specifically describes the mapping process of the present invention with the total number of logical addresses being 128k and the variable number of groups of off-chip DDR3 being 1-5.
Step 201: and partitioning the total logic address, and adopting an equal division mode.
Here, the specific process of step 201 is: dividing the total logic address idle node interval into n segments (each segment is represented by a segment number of a logic address) according to the group number of DDR3 configured in the current system, wherein the median of all common divisor of the total number of the segments is 2nSuch that PMAU [16:15-n ]]I.e. representing a segmented address.
For example, when the DDR3 number is 5 and each DDR3 contains 8 physical banks, the total physical bank number is 40, and the common divisor of 40 is 2nThe maximum value of (3) is 8, that is, when the number of the DDRs 3 is 5, 40 physical banks are equally divided into 8 segments.
The rules adopted by the segmentation are to enable the intra-segment offset address of each segment of the logical address to be quickly characterized by PMAU [16:15-n ], each segment contains the minimum number of physical banks, the residual PMAU [14-n:0] is the offset address of the logical address in each segment, and the subsequent decoding is simpler. The segmentation of logical addresses for different DDR3 quantity configurations is shown in the table contents of fig. 2.
Step 202: for each segment, according to the intra-segment offset address and the intra-segment offset base address configured by the system, obtaining an intra-segment offset physical bank address of the logical address corresponding to the segment, namely an intra-segment offset physical bank number corresponding to the logical address.
Is divided into 2nCases of (1) and not 2nCase 2nIn the case of (2) a one-to-one mapping of logical and physical addresses, handled as in the prior art; is different from 2nIn the case of a one-to-many mapping of logical and physical addresses.
For example, as can be seen from the table in FIG. 2, the system configuration is such that if the DDR3 sets are 1, 2, 4, etc. 2nIn this case, each segment includes only 1 physical bank, and the segment number in the table of fig. 2 represents the physical bank number to which the logical address belongs.
Number of sets other than 2 for DDR3nIn the case of DDR3, for example, the number of groups is 3 and 5, the segment partition of each logical address includes a plurality of physical banks, and in the present example, when the number of DD3 is 5, each segment includes the largest number of physical banks, and each segment includes 5 physical banks.
In order to distinguish the intra-segment offset physical bank addresses corresponding to the logical addresses in the segment, the invention respectively sets an offset base address for each physical bank, and the number of the offset base addresses of the required physical banks is n-1 on the assumption that the number of intra-segment chain tables is n. Therefore, in the present example, when the number of the DDR3 is 5, the required intra-segment offset base addresses are the largest, and the number is 4, and when the number of the DDR3 is 3, under the above segmentation rule, each segment only contains 3 physical banks, so that only 2 offset base addresses are required. Taking DDR3 equal to 3 as an example, assuming that the 2 offset addresses are a0 and a1, respectively, and the PMAU [13:0] is an offset address of the PMAU within a segment, because each segment contains 3 physical banks, when the PMAU [13:0] < a0, the offset physical bank address of the PMAU within the segment is 0, when a0< ═ PMAU [13:0] < a1, the offset physical bank address of the PMAU within the segment is 1, and when the PMAU [13:0 > < a1, the offset physical bank address of the PMAU within the segment is 2. That is, the purpose of partitioning is to obtain partitions partitioned by an offset base address in a system configuration, such as partitions (0-1) and (1-2) identified by offset base addresses 0, 1, 2, with offset addresses having a relationship to the offset base address: the division is continued in any one of the partitions (0-1) and (1-2) and is identified by an offset base address, such as the partition (0-1) which is further refined by 0.1, 0.2, 0.3 … … 0.9.9. It should be noted here that "0.1" and the like are for convenience of explanation, and are described in a number form, and in practical application, the form of address representation is adopted, and is similar to the description of PMAU [13:0], and the description thereof is omitted here.
In summary, when the number of the DDR3 is 3, if a0< ═ PMAU [13:0] < a1 and the segment address to which the PMAU belongs is 3, the physical bank number of the PMAU among 24 physical banks is: 9+1 ═ 10.
In the equation of 9+1 ═ 10, the first 9 on the left represents the physical bank base addresses of all physical banks with segment address 3 (each segment contains 3 physical banks), and 1 represents the offset physical bank address within the segment. Therefore, the intra-segment offset physical bank address corresponding to the logical address under various configurations can be obtained, and the intra-segment offset physical bank address can also be called as the physical bank number of the logical address.
Step 203: and acquiring the base addresses of the specific rows and columns of the offset physical bank address in the segment according to the offset physical bank address in the segment.
The expression form of the physical bank address is equivalent to a two-dimensional matrix, the offset physical bank address in the segment is found, and specific row and column base addresses of the physical bank address are also required to be found. After the belonging physical bank number of the logical address is calculated, the offset address of the logical address in the belonging physical bank can be easily obtained according to the comparison result of the offset base address in the segment and the PMAU [14-n:0 ]. Still taking the above DDR3 number equal to 3 as an example, assuming that the segment address of the logical address is 3, i.e. PMAU [16:14] ═ 3, and a0< ═ PMAU [13:0] < a1, then (PMAU [13:0] -a0) is the offset address in the physical bank to which the logical address belongs. Finally, the row and column addresses are obtained according to the current logical address and the length of each row of DDR3, for example, if the length of each row of DDR3 is 2KB, because each row has only one logical address, then PMAU [13:0] is the row address and the base address of the column is all 0. The calculation method of the row-column base address under other various configurations is similar.
It should be noted that, the present invention only uses the third generation DDR, namely DDR3 as an example to describe the mapping from the logical address to the physical address in the data chip field, so as to implement the management of the external cache, but as long as the DDR in the data chip field can use the mapping scheme of the present invention to manage the external cache, so as to implement the decoding quickly and efficiently.
Compared with the prior art and the present invention, taking DDR3 as an example, the one-to-one mapping between the logical address and the physical address in the prior art has the following problems:
in order to ensure certain caching performance, a fixed logical address number is generally required during implementation, and in the prior art, a simple mapping relation between a logical address bit domain and a DDR3 physical address bit domain is generally adopted during implementation. For example, for a 2G, 16 bit-wide DDR3, the bit widths of the corresponding physical bank address, row address and burst column address are 3 bits, 14 bits and 7 bits, respectively, if each logical address is fixed to 2KB and the number of logical addresses is fixed to 128K, because each row of DDR3 is 2KB, the logical address is the base address of each row, the decoding method from the logical address to the physical base address is also simple, and the decoding can be completed by using a method in which the highest 3 bits corresponds to the physical bank address, the middle 14 bits corresponds to the row address, and the lowest bit is complemented by 0 to be the column base address. However, the number of DDRs 3 required for practical use is often not an integer power of 2, such as 3 sets. If such a simple decoding method is still required, for a 128K logical address number, a 19bit characterization is required. Meanwhile, the requirement of the system scheme of sharing the cache generally requires that a logical address is managed in a chain table mode, and the logical address is required to be used as an addressing pointer of the RAM, so that the waste of the required RAM resources is 4 times. According to different application scenarios of the chip, the number of plug-in DDR3 may be required to be variable, and the same number of available logical addresses may be required.
If the total logical address is directly used for one-to-one mapping with the physical address as in the prior art, excessive logical addresses are wasted, and by adopting the method and the device, the total logical address is segmented firstly, and then the logical address and the physical address are mapped in the segment according to the logical address segment, so that the system design requirements can be met by using the least logical address resources, such as the number of 128K logical addresses, and the 17-bit representation is fixedly used, so that by adopting the method and the device, the system RAM resources are saved to the maximum extent, the high-efficiency management of the physical address can be realized, and the address addressing function is realized mainly through address mapping.
Application example two: based on a mapping device implementing the mapping scheme of the invention.
As shown in fig. 3, the mapping apparatus is located at the cache side, and includes: a partition processing unit and a mapping processing unit; the partition processing unit is used for partitioning the logic address according to the number of the currently configured DDR; and the mapping processing unit is used for respectively mapping the logical address and the physical address according to the logical address of each partitioned segment.
Here, the partition processing unit is further configured to obtain a total physical bank number according to the number of the DDRs and the number of physical bank banks included in each DDR, equally divide the total logical address into a plurality of logical address segments, and the number of the segments is 2 in all common divisor of the total physical bank numbernN refers to the number of linked lists in the segment.
Here, the mapping processing unit is further configured to have a value of 2nUnder the condition of (1), each logic address segment corresponds to one physical bank, and the mapping is one-to-one mapping between the logic address and the physical address; a value of not 2nIn the case of (3), each logical address segment is associated with a plurality of physical banks, and thus, one-to-many mapping between logical addresses and physical addresses is performed.
Here, a preferred embodiment of the mapping processing unit in the one-to-many mapping is: the mapping processing unit is used for configuring offset base addresses in the segments for each physical bank, and the number of the offset base addresses in the segments is n-1; obtaining an intra-segment offset physical bank address corresponding to the intra-segment offset address according to the intra-segment offset base address and the intra-segment offset address; and obtaining a corresponding physical row address and a physical column address according to the intra-segment offset physical bank address.
Application example three: the decoding process realized based on the mapping scheme of the invention.
As shown in fig. 4, the decoding apparatus used to implement the decoding process is shown, and the chinese-english comparison of the nouns in fig. 4 is as follows:
app _ pmau _ vld: a logical address valid indication to be decoded;
app _ pmau: a logical address to be decoded;
DFF: a D flip-flop;
match: a comparator;
pmau _ fld: resolving the segment number of the logic address to be decoded according to the DDR group number;
pmau _ fld _ offset: an intra-segment offset address of a logical address to be decoded;
pmau _ fld _ dly 1: after being segmented, the decoded data is stored;
pmau _ fld _ physical bank: according to the intra-segment offset address and the intra-segment base address, comparing the intra-segment offset physical bank number;
ddr _ physical bank _ addr: resolving the physical bank address;
ddr _ row _ addr: resolving the physical row address;
ddr _ col _ addr: resolving the physical column address;
pmau _ physical bank _ offset: the physical bank internal offset address of the ddr logical address to be resolved;
cfg _ physical bank _ addr [ i ]: the total number of the base addresses in the segments, which are configured by the user and used for comparison, is i;
cfg _ pmau _ width: configured PMAU length
cfg _ ddrc _ num: number of configured DDR groups.
Here, it should be noted that the trapezoidal components in fig. 4 all represent arithmetic units.
The decoding process (decoding from logical address to physical address) realized by the decoding device comprises the following steps:
1. first, the segment number (pmau _ fld) of the inputted logical address to be decoded and the offset address (pmau _ fld _ offset) in the segment where the logical address is located are determined according to the number of DDR groups (cfg _ ddrc _ num) configured by the user.
2. Comparing the offset address in the segment with the user-configured base address in the segment (cfg _ physical bank _ addr [ i ]) yields the offset address in the segment specifically belonging to the several physical banks within the segment, i.e., the intra-segment offset physical bank number (pmau _ fld _ physical bank [2:0]) and the offset physical address (pmau _ physical bank _ offset) within the corresponding physical bank.
3. And calculating the physical bank number of the logical address according to the segment number of the logical address and the offset physical bank number in the segment.
4. And decoding according to the offset physical address in the physical bank to obtain the row number and the column number of the physical address (thereby obtaining the specific row address and the specific column address of the physical address).
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims (2)

1. A method of address mapping processing, the method comprising:
partitioning the logic address according to the number of the currently configured double data rate synchronous random access memories DDR;
mapping processing between the logical address and the physical address is respectively carried out according to the logical address of each partitioned segment;
the partitioning of logical addresses according to the number of currently configured double data rate synchronous random access memories DDR comprises: according to the number of the DDR and the number of the physical memory bank contained in each DDRMeasuring to obtain the total physical bank number; dividing the total logical address into a plurality of logical address segments equally, wherein the segment number is 2 in all common divisor of the total physical bank numbernN refers to the number of linked lists in the segment;
the mapping processing between the logical address and the physical address according to the logical address of each partitioned segment comprises: the DDR number is 2nUnder the condition of (1), each logical address segment corresponds to one physical bank, and is one-to-one mapping between the logical address and the physical address; the DDR number is not 2nUnder the condition that each logical address segment corresponds to a plurality of physical banks, the logical address and the physical address are mapped in a one-to-many mode;
during the one-to-many mapping, configuring an intra-segment offset base address for each physical bank, wherein the number of the intra-segment offset base addresses is n-1;
obtaining an intra-segment offset physical bank address corresponding to the intra-segment offset address according to the intra-segment offset base address and the intra-segment offset address;
and obtaining a corresponding physical row address and a physical column address according to the intra-segment offset physical bank address.
2. An apparatus for address mapping processing, the apparatus comprising: a partition processing unit and a mapping processing unit; wherein,
the partition processing unit is used for partitioning the logic address according to the number of the currently configured DDR;
the mapping processing unit is used for respectively mapping the logical address and the physical address according to the logical address of each partitioned segment;
the partition processing unit is further configured to obtain a total physical bank number according to the number of the DDRs and the number of the physical bank banks included in each DDR, equally divide a total logical address into a plurality of logical address segments, and the number of the segments is 2 in all common divisor of the total physical bank numbernN refers to the number of linked lists in the segment;
the mapping processing unit is further used for the DDR with the number of 2nIn the case ofEach logical address segment corresponds to one physical bank, and the logical address and the physical address are mapped in a one-to-one mode; the DDR number is not 2nUnder the condition of (1), each logic address segment corresponds to a plurality of physical banks, and the mapping is one-to-many mapping between the logic address and the physical address;
the mapping processing unit is further configured to configure an intra-segment offset base address for each physical bank during one-to-many mapping, where the number of the intra-segment offset base addresses is n-1; obtaining an intra-segment offset physical bank address corresponding to the intra-segment offset address according to the intra-segment offset base address and the intra-segment offset address; and obtaining a corresponding physical row address and a physical column address according to the intra-segment offset physical bank address.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106547702B (en) * 2016-09-27 2019-09-10 中国电子科技集团公司第三十八研究所 A kind of 8 memory access address calculation method of bimodulus
CN107870870B (en) * 2016-09-28 2021-12-14 北京忆芯科技有限公司 Accessing memory space beyond address bus width
CN107870867B (en) * 2016-09-28 2021-12-14 北京忆芯科技有限公司 Method and device for 32-bit CPU to access memory space larger than 4GB
CN108550102B (en) * 2018-04-25 2022-05-17 珠海全志科技股份有限公司 Hardware accelerator
CN110851372B (en) * 2018-08-20 2023-10-31 慧荣科技股份有限公司 Storage device and cache area addressing method
CN111367461B (en) * 2018-12-25 2024-02-20 兆易创新科技集团股份有限公司 Storage space management method and device
CN110781101A (en) * 2019-10-25 2020-02-11 苏州浪潮智能科技有限公司 One-to-many mapping relation storage method and device, electronic equipment and medium
CN114328286B (en) * 2022-03-14 2022-07-15 南京芯驰半导体科技有限公司 Method for improving system access performance
CN114707478B (en) * 2022-06-06 2022-09-02 飞腾信息技术有限公司 Mapping table generation method, device, equipment and storage medium

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7932912B1 (en) * 2006-10-04 2011-04-26 Nvidia Corporation Frame buffer tag addressing for partitioned graphics memory supporting non-power of two number of memory elements
CN102156619A (en) * 2010-02-12 2011-08-17 群联电子股份有限公司 Flash memory, flash memory controller and data writing method
CN102622189A (en) * 2011-12-31 2012-08-01 成都市华为赛门铁克科技有限公司 Storage virtualization device, data storage method and system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7932912B1 (en) * 2006-10-04 2011-04-26 Nvidia Corporation Frame buffer tag addressing for partitioned graphics memory supporting non-power of two number of memory elements
CN102156619A (en) * 2010-02-12 2011-08-17 群联电子股份有限公司 Flash memory, flash memory controller and data writing method
CN102622189A (en) * 2011-12-31 2012-08-01 成都市华为赛门铁克科技有限公司 Storage virtualization device, data storage method and system

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