CN104078372B - The manufacture method of semiconductor device - Google Patents
The manufacture method of semiconductor device Download PDFInfo
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- CN104078372B CN104078372B CN201310360706.4A CN201310360706A CN104078372B CN 104078372 B CN104078372 B CN 104078372B CN 201310360706 A CN201310360706 A CN 201310360706A CN 104078372 B CN104078372 B CN 104078372B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73257—Bump and wire connectors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
- H01L2224/8113—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed on the semiconductor or solid-state body
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
The present invention provides the manufacture method of the semiconductor device of the position skew between will can suppress semiconductor chip when being connected and be laminated with projected electrode between semiconductor chip.In the manufacture method of the semiconductor device of implementation method, obtain in the first semiconductor chip（2A）Second semiconductor chip of upper stacking（2B）The 3rd alignment mark（5C）With move to the second semiconductor chip（4B）On the 3rd semiconductor chip（2C）The 4th alignment mark（5D）Positional information.Based in the first semiconductor chip（2A）The the first alignment mark for setting（5A）Positional information and the 3rd and the 4th alignment mark（5C）、（4D）Positional information by the second semiconductor chip（2B）With the 3rd semiconductor chip（2C）Align and be laminated.
Description
The application is with Japanese patent application 2013-61230（The applying date：On March 25th, 2013）
Based on and enjoy its priority.The application is by referring to the earlier application including entire contents.
Technical field
The present invention relates to the manufacture method of semiconductor device.
Background technology
In order to realize miniaturization and the high performance of semiconductor device, stacking multiple half in an encapsulation
Conductor chip and the laminated semiconductor device that is sealed are just practical.In stacked semiconductor dress
Put, it is necessary to send the electric signal received between semiconductor chip at high speed.In this case, partly leading
Microprotrusion is used during the electrical connection of body chip chamber（マイクロバンプ）.Microprotrusion has for example
5~50 μm or so of diameter, and with 10~100 μm or so of spacing on the surface of semiconductor chip shape
Into.In the case of semiconductor chip of the stacking with microprotrusion, recognized in semiconductor with video camera etc.
The alignment mark formed on the surface of chip, and based on the recognition result come by upper and lower semiconductor chip
Contraposition（Positioning）After be thermally compressed with connection bump each other.
As the alignment method of the semiconductor chip using alignment mark, it is known to undermost half
Partly led what is be laminated thereon on the basis of the recognition result of the alignment mark that the surface of conductor chip is formed
The method of body chip contraposition.In this case, the semiconductor chip of the second layer is not limited to, after third layer
Semiconductor chip can also be aligned relative to undermost semiconductor chip.For example, third layer is partly led
Body chip is with the alignment mark of nonrecognition second layer semiconductor chip in undermost semiconductor chip pair
The state of position is laminated on second layer semiconductor chip.4th layer of later semiconductor chip is similarly.
Therefore, though any semiconductor chip in raised mutual connection etc. after the second layer produce it is super
The position skew of allowed band is crossed, can not detect that the position offsets formation is laminated to the semiconductor of the superiors
Chip.This usage quantity increase for turning into semiconductor chip and the fabrication yield of multilayer laminated chip
The main cause of decline.
The content of the invention
The problem to be solved in the present invention is to provide will connected and is being laminated with projected electrode between semiconductor chip
When can suppress between semiconductor chip position skew semiconductor device manufacture method.
The manufacture method of the semiconductor device of implementation method, it is characterised in that possess：Prepare the first half
The operation of conductor chip, first semiconductor chip possesses the first projected electrode set in first surface
With the first alignment mark；Prepare the operation of the second semiconductor chip, second semiconductor chip possesses：
The second projected electrode set in second surface and the second alignment mark；Opposite with the second surface
The 3rd projected electrode and the 3rd alignment mark that 3rd surface of side is set；It is raised electric with by described second
Pole and the penetrating electrode of the 3rd projected electrode electrical connection；Prepare the operation of the 3rd semiconductor chip,
3rd semiconductor chip possesses the 4th projected electrode and the 4th alignment mark set on the 4th surface；
Make second semiconductor chip move on first semiconductor chip and make the first surface and
The relative operation of the second surface；Obtain an xy coordinates and be used as first semiconductor chip
The positional information and the 2nd xy coordinates of acquirement of the first alignment mark are used as moving to described first
The work of the positional information of the second alignment mark of second semiconductor chip on semiconductor chip
Sequence；Based on first and second xy described in the positional information as first and second alignment mark
The operation that first semiconductor chip and second semiconductor chip are aligned and be laminated by coordinate；
First projected electrode and second projected electrode is set to contact and heat, and it is raised by described first
Electrode and the operation of second projected electrode connection；Move to the 3rd semiconductor chip described
On second semiconductor chip and make the relative operation in the 3rd surface and the 4th surface；Obtain the
Three xy coordinates be used as second semiconductor chip it is described 3rd alignment mark positional information and
Obtain the 3rd semiconductor that the 4th xy coordinates are used as moving on second semiconductor chip
The operation of the positional information of the 4th alignment mark of chip；Obtain in second semiconductor chip
Stacking when obtain described in first alignment mark positional information an xy coordinates and conduct
The average coordinates of the 3rd xy coordinates of the positional information of the 3rd alignment mark, by by the described 4th
Alignment mark is compareed second semiconductor chip and described the relative to the average coordinates
The operation that three semiconductor chips are aligned and are laminated；With make the 3rd projected electrode and described 4th raised
Electrode contact is simultaneously heated, and the operation that the 3rd projected electrode and the 4th projected electrode are connected.
The manufacture method of the semiconductor device of implementation method, it is characterised in that possess：Prepare the first half
The operation of conductor chip, first semiconductor chip possesses the first projected electrode set in first surface
With the first alignment mark；Prepare the operation of the second semiconductor chip, second semiconductor chip possesses：
The second projected electrode set in second surface and the second alignment mark；Opposite with the second surface
The 3rd projected electrode and the 3rd alignment mark that 3rd surface of side is set；It is raised electric with by described second
Pole and the penetrating electrode of the 3rd projected electrode electrical connection；Prepare the operation of the 3rd semiconductor chip,
3rd semiconductor chip possesses the 4th projected electrode and the 4th alignment mark set on the 4th surface；
Make second semiconductor chip move on first semiconductor chip and make the first surface and
The relative operation of the second surface；Obtain the first alignment mark of first semiconductor chip
With second pair of fiducial mark of second semiconductor chip moved on first semiconductor chip
The operation of the positional information of knowledge；Positional information based on first and second alignment mark is come will be described
The operation that first semiconductor chip and second semiconductor chip are aligned and be laminated；Make the described 3rd half
Conductor chip is moved on second semiconductor chip and makes the 3rd surface and the 4th surface
Relative operation；Obtain the 3rd alignment mark of second semiconductor chip and move to described
The positional information of the 4th alignment mark of the 3rd semiconductor chip on the second semiconductor chip
Operation；With the positional information based on the described first alignment mark and the 3rd and the 4th alignment mark
Positional information second semiconductor chip and the 3rd semiconductor chip aligned and be laminated
Operation.
Brief description of the drawings
Fig. 1 is the sectional view for representing the semiconductor device manufactured with the manufacture method of implementation method.
Fig. 2 is the second semiconductor chip in the manufacture method of the semiconductor device for representing implementation method
The sectional view of contraposition operation and lamination process.
Fig. 3 is the 3rd semiconductor chip in the manufacture method of the semiconductor device for representing implementation method
The sectional view of contraposition operation and lamination process.
Fig. 4 is the 4th semiconductor chip in the manufacture method of the semiconductor device for representing implementation method
The sectional view of contraposition operation and lamination process.
Fig. 5 is the sectional view for representing the first semiconductor packages using the semiconductor device shown in Fig. 1.
Fig. 6 is the sectional view for representing the second semiconductor packages using the semiconductor device shown in Fig. 1.
Specific embodiment
The manufacture method of the semiconductor device of implementation method is illustrated below according to accompanying drawing.First, reference
Fig. 1 come describe using implementation method manufacture method manufacture semiconductor device.Semiconductor shown in Fig. 1
Device 1 possess the first semiconductor chip 2A, the second semiconductor chip 2B, the 3rd semiconductor chip 2C and
4th semiconductor chip 2D.Second to the 4th semiconductor chip 2B~2D is stacked gradually in the first semiconductor
On chip 2A.Here, it is illustrated that four semiconductor devices of semiconductor chip 21 of stacking, but, half
The stacking number of conductor chip 2 is not limited to this.Constitute the quantity of the semiconductor chip 2 of semiconductor device 1
（Stacking number）For more than three can, or three or more than five.
In the upper surface of the first semiconductor chip 2A（First surface）, it is formed with the first projected electrode 3A.
In the lower surface of the second semiconductor chip 2B（Second surface）, it is formed with the second projected electrode 4A.
The formation face of the first projected electrode 3A of the first semiconductor chip 2A（First surface）, it is provided with first pair
Fiducial mark knows 5A.In the formation face of the second projected electrode 4A of the second semiconductor chip 2B（Second surface）,
It is provided with the second alignment mark 5B.Second semiconductor chip 2B is raised electric by the second projected electrode 4A and first
Pole 3A is connected and is laminated on the first semiconductor chip 2A.I.e., the first semiconductor chip 2A and second
Semiconductor chip 2B is through the connector 6A of the first projected electrode 3A and the second projected electrode 4A with electricity
And be mechanically connected.
In the upper surface of the second semiconductor chip 2B（3rd surface）, it is formed with the 3rd projected electrode 3B
With the 3rd alignment mark 5C.Second projected electrode 4A and the 3rd projected electrode 3B is passed through in the second semiconductor
The penetrating electrode set in chip 2B（Silicon perforation：TSV）7A and electrically connect.In the 3rd semiconductor core
The lower surface of piece 2C（4th surface）, it is formed with the alignment marks of the 4th projected electrode 4B and the 4th 5D.
With the 3rd projected electrode 3B be connected 4th projected electrode 4B and is laminated in by the 3rd semiconductor chip 2C
On two semiconductor chip 2B.I.e., the second semiconductor chip 2B and the 3rd semiconductor chip 2C are convex through the 3rd
Play the connector 6B of electrode 3B and the 4th projected electrode 4B and connected in electrically and mechanically mode.
In the upper surface of the 3rd semiconductor chip 2C（5th surface）, it is formed with the 5th projected electrode 3C
With the 5th alignment mark 5E.4th projected electrode 4B and the 5th projected electrode 3C is passed through in the 3rd semiconductor core
The penetrating electrode set in piece 2C（Silicon perforation：TSV）7B and electrically connect.In the 4th semiconductor chip
The lower surface of 2D（6th surface）, it is formed with the alignment marks of the 6th projected electrode 4C and the 6th 5F.The
With the 5th projected electrode 3C be connected 6th projected electrode 4C and the 3rd is laminated in by four semiconductor chip 2D
On semiconductor chip 2C.I.e., the 3rd semiconductor chip 2C and the 4th semiconductor chip 2D are convex through the 5th
Play the connector 6C of electrode 3C and the 6th projected electrode 4C and connected in electrically and mechanically mode.6th
Projected electrode 4C is with the electrode 8 set in the upper surface of the 4th semiconductor chip 2D through penetrating electrode
（TSV）7C is electrically connected.
As projected electrode 3（3A、3B、3C）With projected electrode 4（4A、4B、4C）Combination,
The combination such as solder/solder, Au/ solders, solder/Au, Au/Au can be enumerated.As formation projected electrode
3rd, 4 solder, illustrates being welded without Pb using the Sn alloys of addition Cu, Ag, Bi, In etc. in Sn
Material（The fields of Pb フ リ ー half）.As the concrete example of Pb-free solder, can enumerate Sn-Cu, Sn-Ag,
Sn-Ag-Cu etc..As formed projected electrode 3,4 metal, it is possible to use Cu, Ni, Sn, Pd,
Ag or the alloy containing these elements etc. replace Au.These metal materials are not limited to monofilm, also may be used
Use the stacked film of multiple metal materials.As the shape of projected electrode 3,4, can enumerate it is hemispherical and
The shape for lugs such as column, however, it can be even shape as pad.As projected electrode 3,
4 combination, can enumerate combination of protruding body combination with one another, protruding body and flat body etc..
In the semiconductor chip 2 of lower layer side（2A、2B、2C）Upper surface set projected electrode 3
With the semiconductor chip 2 in upper layer side（2B、2C、2D）Lower surface set projected electrode 4 lead to
Cross and for example crimp to connect when heat or ultrasonic is applied.Projected electrode 3 and projected electrode 4 can be one by one
Ground connection, or can also be connected after by semiconductor chip 2A, 2B, 2C, 2D all stacking.
In the case of being connected between projected electrode 3,4 after the whole semiconductor chips 2 of stacking, in semiconductor chip
To temporarily be fixed between projected electrode 3,4 during 2 stacking, by chip layer after the stacking of semiconductor chip 2
Stack is crimped or Reflow Soldering with temperature more than the connection temperature of projected electrode 3,4（リフロー）.
It is separately filled between the semiconductor chip 2 that the connector 6 through projected electrode 3 and projected electrode 4 is connected
Underfill（アンダーフィル）Resin 9.The filling bottom between semiconductor chip 2 is not limited to fill out
Fill the situation of resin 9, it is possible to use the dielectric adhesive film with underfill function（NCF）
Starched with bonding agent（NCP）Carry out laminated semiconductor chip 2.
The semiconductor device 1 of above-mentioned implementation method is manufactured as example below.Reference picture 2, Fig. 3 and figure
4 illustrate the manufacturing process of semiconductor device 1（Lamination process）.Such as Fig. 2（a）It is shown, prepare tool
Have the first projected electrode 3A the first semiconductor chip 2A and with second and third projected electrode 4A,
The second semiconductor chip 2B of 3B.In the formation of the first projected electrode 3A of the first semiconductor chip 2A
Face, is provided with the first alignment mark 5A.In the shape of the second projected electrode 4A of the second semiconductor chip 2B
Into face, the second alignment mark 5B is provided with.Due to being laminated the 3rd semiconductor on the second semiconductor chip 2B
Chip 2C, thus the 3rd projected electrode 3B in the second semiconductor chip 2B formation face, be provided with the 3rd
Alignment mark 5C.
Shape and allocation position of alignment mark 5 etc. are not particularly limited.Alignment mark 5 is by for example half
The wiring material that the most surface of conductor chip 2 is formed（Formation material of Al wirings etc.）With projected electrode 3
（4）Formation material formed.In the case where alignment mark 5 is formed with wiring material, by rectangle shape
Hollow mark of the mark or rectangular shape of shape etc. is used as alignment mark 5.With projected electrode 3（4）'s
In the case of material is formed to form alignment mark 5, to configure projection from unique patterns different around
Electrode is for use as alignment mark 5.Alignment mark 5 preferably such as rectangular shape semiconductor chip 2 four
At least one of angle position is formed, two on the diagonal more preferably in corner position or with
Two positions that the two ends on individual profile side are suitable are formed.
Further, in Fig. 1 to Fig. 4, easily illustrating the two of profile side in semiconductor chip 2
End forms the state of alignment mark 5, but, two places on the diagonal form alignment mark 5
Situation is similarly.Below, alignment mark is formed based on the two ends on a profile side of semiconductor chip 2
5 accompanying drawing illustrates the contraposition operation and lamination process of semiconductor chip 2, however, in semiconductor chip 2
Diagonal on two positions formed alignment mark 5 in the case of similarly implement semiconductor chip 2
Contraposition operation and lamination process.Therefore, contraposition operation described below and lamination process are applicable to
In the alignment mark 5 that any position is formed.
Such as Fig. 2（a）It is shown, move to the second semiconductor chip 2B that holding is adsorbed by connector 12
It is positioned on workbench 11 and is adsorbed the top of the first semiconductor chip 2A of holding.Second semiconductor
Chip 2B makes formation face and first semiconductor chip of the alignment marks of the second projected electrode 4A and second 5B
The formation face of the alignment marks of the first projected electrode 3A of 2A and first 5A is relative.With the grade figure of video camera 13
The alignment mark 5A of the first semiconductor chip 2A is recognized as identifying device and the first semiconductor is moved to
The second alignment mark 5B of the second semiconductor chip 2B on chip 2A, and obtain coordinate and be used as first
And second alignment mark 5A, 5B positional information.
Based on the coordinate of the position for representing first and second alignment mark 5A, 5B, by the second semiconductor
Chip 2B is aligned relative to the first semiconductor chip 2A.Specifically, obtain at the first alignment mark 5A
The first mark coordinate（x11, y11）And second mark coordinate（x12, y12）With the second alignment
The coordinate of the first mark at mark 5B（x21, y21）And second mark coordinate（x22, y22）,
And by the position of the second semiconductor chip 2B in xy coordinate directions and direction of rotation（θ directions）Upper adjustment
So that the coordinate of the first mark difference each other（（x11, y11）With（x21, y21）Difference）With second
The coordinate of mark difference each other（（x12, y12）With（x22, y22）Difference）Respectively become minimum.
Here, the maximum that corresponding mark difference each other is meant as minimum is minimum（Such as the first mark
Coordinate difference each other and the second mark coordinate difference each other in any one larger minimum）Or
The aggregate values of the corresponding mark of person difference each other are minimum.And, such as Fig. 2（b）It is shown, while making second
Projected electrode 4A and the first projected electrode 3A contact edges make the second semiconductor chip 2B for having aligned
It is laminated on semiconductor chip 2A.
Secondly, in the temperature being heated to more than the connection temperature of first and second projected electrode 3A, 4A
Meanwhile, or while ultrasonic wave is applied to first and second projected electrode 3A, 4A, by the second half
Conductor chip 2B is crimped on the first semiconductor chip 2A.In the crimping process, by the first raised electricity
Pole 3A and the second projected electrode 4A is connected.The connection temperature of projected electrode 3A, 4A is to use solder shape
The temperature more than fusing point of the solder used in the case of into projected electrode 3A, 4A at least one.This
In, by the first raised electricity during for stacking in the first semiconductor chip 2A and the second semiconductor chip 2B
Pole 3A and the second projected electrode 4A connection situation be described, however, it is possible to as explained later that
Sample will be interim fixed between projected electrode 3A, 4A and by whole half in the stacking of semiconductor chip 2
Conductor chip 2 will formally be connected after being laminated between projected electrode 3,4（Real connection）.
Here, when the first semiconductor chip 2A and the second semiconductor chip 2B is aligned, based on alignment
The formation precision of mark 5（The formation precision of the exposure mask for for example being used in the formation of alignment mark 5
And exposure accuracy）Accuracy of identification formed with video camera 13 etc., and sometimes in the first semiconductor chip
Position skew is produced between 2A and the second semiconductor chip 2B.If between the semiconductor chip 2A, 2B
Position skew for semiconductor chip 2 installation accuracy in the range of, then have no problem, will not also make convex
Connection precision between electrode 3A, 4A etc. is played to decline.
Secondly, such as Fig. 3（a）It is shown, prepare the with the 4th and the 5th projected electrode 4B, 3C the 3rd
Semiconductor chip 2C.In the 3rd semiconductor chip 2C, set in the formation face of the 4th projected electrode 4B
There is the 4th alignment mark 5D, and the 5th alignment mark is provided with the formation face of the 5th projected electrode 3C
5E.The 3rd semiconductor chip 2C for adsorbing holding by connector 12 is set to move in the first semiconductor chip
The top of the second semiconductor chip 2B being laminated on 2A.3rd semiconductor chip 2C makes the 4th raised electricity
The 3rd projected electrode 3B for forming face and the second semiconductor chip 2B of the alignment marks of pole 4B and the 4th 5D
And the 3rd alignment mark 5C formation face it is relative.
The 3rd alignment mark 5C of the second semiconductor chip 2B is recognized with video camera 13 and the is moved to
The 4th alignment mark 5D of the 3rd semiconductor chip 2C on two semiconductor chip 2B, and obtain coordinate
It is used as the positional information of the 3rd and the 4th alignment mark 5C, 5D.Now, it is being based only upon expression the 3rd
And the 4th the coordinate of position of alignment mark 5C, 5D make the 3rd semiconductor chip 2C relative to second
When semiconductor chip 2B is aligned, during stacking with the first semiconductor chip 2A and the second semiconductor chip 2B
Equally, accuracy of identification that formation precision and video camera 13 based on alignment mark 5 are formed etc., and sometimes
Position skew is produced between the second semiconductor chip 2B and the 3rd semiconductor chip 2C.
In the case where the contraposition of the second semiconductor chip 2B and the 3rd semiconductor chip 2C is only considered, with
It is same during the stacking of the first semiconductor chip 2A and the second semiconductor chip 2B, if semiconductor chip
Position skew between 2B, 2C is in the range of the installation accuracy of semiconductor chip 2, then to have no problem,
Connection precision between projected electrode 3B and the 4th projected electrode 4B etc. will not also declined.Even if however,
3rd semiconductor chip 2C position skew relative to the second semiconductor chip 2B be allowed band in,
The 3rd semiconductor chip 2C can be also configured in semiconductor chip when being observed from the first semiconductor chip 2A
At the position of the position skew added up in the position skew between 2B, 2C between semiconductor chip 2A, 2B.
Formed position is accumulated in position skew between the stacking quantity of semiconductor chip 2 more at most semiconductor chip 2
Put side-play amount（Accumulation position offset）It is bigger.
For example, in the case where the installation accuracy of semiconductor chip 2 is for 2 μm, it is allowed to semiconductor chip 2
Between position offset within the value.In the case where eight semiconductor chips 2 are laminated, adjacent partly leads
Position offset between body chip 2 is 2 μm to the maximum, relatively, in the undermost of eight stacked dies
The position skew for being 14 μm to the maximum will be produced between the semiconductor chip 2 of semiconductor chip 2 and the superiors.
Position offset between the semiconductor chip 2 of undermost semiconductor chip 2 and the superiors is natural
Ground increases as the stacking quantity of semiconductor chip 2 increases, for example, being laminated 16 semiconductor cores
It is 30 μm in the case of piece 2 to the maximum.It is possible to the position skew of therefore based semiconductor chip 2 and makes for example
The appearance and size of multilayer laminated chip exceedes allowed band or makes resin to filling out between semiconductor chip 2
Filling property declines.
Then, in the manufacture method of implementation method, during based on stacking in the second semiconductor chip 2B
The coordinate of the first alignment mark 5A for obtaining is with new the 3rd and the 4th alignment mark 5C, 5D's for obtaining
Coordinate is aligned relative to the second semiconductor chip 2B making the 3rd semiconductor chip 2C.For example, obtaining
The average coordinates of the coordinate of the coordinate of the first alignment mark 5A and the 3rd alignment mark 5C, make the 4th alignment
Mark 5D is aligned relative to the average coordinates.So, the position between adjacent semiconductor chip 2 is inclined
Shifting amount be allowed band in maximum in the case of, can also suppress the 3rd semiconductor chip 2C relative to
The increase of the position offset of the first semiconductor chip 2A.
On specific contraposition, the coordinate of the first mark at the first alignment mark 5A is obtained（x11, y11）
With the coordinate of the first mark at the 3rd alignment mark 5C（x31, y31）Average coordinates（xA11, yA11）
And first alignment mark 5A at the second mark coordinate（x12, y12）With the 3rd alignment mark 5C
The coordinate of second mark at place（x32, y32）Average coordinates（xA12, yA12）, the 3rd half is led
The position of body chip 2C is adjusted on xy coordinate directions and direction of rotation so that these average coordinates and
The difference of the coordinate of first and second mark at four alignment mark 5D（（xA11, yA11）With（x41,
y41）Difference and（xA12, yA12）With（x42, y42）Difference）It is minimum.And, such as Fig. 3（b）
It is shown, while making the 4th projected electrode 4B make the aligned the 3rd half to lead with the 3rd projected electrode 3B contact edges
Body chip 2C is laminated on the second semiconductor chip 2B.
Secondly, in the temperature being heated to more than the connection temperature of the 3rd and the 4th projected electrode 3B, 4B
Meanwhile, or while ultrasonic wave is applied to the 3rd and the 4th projected electrode 3B, 4B, by the 3rd half
Conductor chip 2C is crimped on the second semiconductor chip 2B, so as to the 3rd projected electrode 3B and the 4th is convex
Play electrode 4B connections.Connection and first and second raised electricity between the 3rd and the 4th projected electrode 3B, 4B
Connection between pole 3A, 4A is similarly implemented.Therefore, it is not limited in the second semiconductor chip 2B and
The 3rd projected electrode 3B and the 4th projected electrode 4B is connected during the stacking of three semiconductor chip 2C, also may be used
With will be interim fixed and by whole half between projected electrode 3B, 4B in the stacking of semiconductor chip 2
Conductor chip 2（2A~2D）To formally be connected between whole projected electrodes 3,4 after stacking（Real connection）.
When the 3rd semiconductor chip 2C is laminated on the second semiconductor chip 2B, if not obtaining
4th alignment is just identified coordinates of the 5D relative to the first alignment mark 5A by the coordinate of three alignment mark 5C
Contraposition, although can then maintain contraposition essences of the 3rd semiconductor chip 2C relative to the first semiconductor chip 2A
Degree, but, even if producing the position more than allowed band during connection for example between projected electrode 3A, 4A
Skew is put, can not detect that the position offsets.This usage quantity for turning into semiconductor chip 2 increases and many
The main cause that the fabrication yield of layer stackup chip declines.In contrast, in the manufacture of implementation method
In method, due to achieving the coordinate of the 3rd alignment mark 5C, therefore can detect in the second semiconductor core
Burst position skew that piece 2B is produced etc..
3rd semiconductor chip 2C is not limited to the 4th pair relative to the contraposition of the second semiconductor chip 2B
Fiducial mark knows the average of the coordinate of coordinates of the 5D relative to the first alignment mark 5A and the 3rd alignment mark 5C
Coordinate is compareed.In terms of the position skew accumulation for suppressing semiconductor chip 2, can also make the 4th alignment
Mark 5D is pointed to the medial area of the coordinate of the first alignment mark 5A and the coordinate of the 3rd alignment mark 5C
Domain.In this case, on the basis of the centre coordinate of each coordinate, the 4th alignment mark 5D is set to be pointed to the
The inside region of the one and the 3rd alignment mark 5A, 5C.Specifically, in the seat of the first alignment mark 5A
The coordinate of mark and the 3rd alignment mark 5C is the inner side of the quadrilateral area on diagonal summit（Sat with center
Be designated as benchmark and by the region except the line segment on each summit of quadrilateral area and each summit of connection）, will
4th alignment mark 5D contrapositions.In order to effectively suppress the accumulation position offset of semiconductor chip 2
Increase, preferably identifies 5D and aligns in than above-mentioned quadrilateral area region in the inner part by the 4th alignment.
Secondly, such as Fig. 4（a）It is shown, prepare the 4th semiconductor chip with the 6th projected electrode 4C
2D.The 6th alignment mark is provided with the formation face of the 6th projected electrode 4C of the 4th semiconductor chip 2D
5F.The 4th semiconductor chip 2D for adsorbing holding by connector 12 is set to move in the second semiconductor chip
The top of the 3rd semiconductor chip 2C being laminated on 2B.4th semiconductor chip 2D makes the 6th raised electricity
The 5th projected electrode 3C for forming face and the 3rd semiconductor chip 2C of the alignment marks of pole 4C and the 6th 5F
And the 5th alignment mark 5E formation face it is relative.
The 5th alignment mark 5E of the 3rd semiconductor chip 2C is recognized with video camera 13 and the is moved to
The 6th alignment mark 5F of the 4th semiconductor chip 2D on three semiconductor chip 2C, and obtain coordinate
The positional information of 5E, 5F is identified as the 5th and the 6th alignment.With the stacking of the 3rd semiconductor chip 2C
The coordinate of the first alignment mark 5A obtained when similarly, based on the stacking in the second semiconductor chip 2B
The the 5th and the 6th alignment with new acquirement identifies the coordinate of 5E, 5F, by the 4th semiconductor chip 2D
Aligned relative to the 3rd semiconductor chip 2C.The contraposition of the 4th semiconductor chip 2D at least based on first,
The coordinate of the 5th and the 6th alignment mark 5A, 5E, 5F is implemented.
For example, obtaining the average seat of the coordinate of the first alignment mark 5A and the coordinate of the 5th alignment mark 5E
Mark, makes the 6th alignment mark 5D be aligned relative to the average coordinates.Except the first, the 5th and the 6th pair
Fiducial mark is known outside the coordinate of 5A, 5E, 5F, it is also contemplated that the coordinate of the 3rd alignment mark 5C.For example,
Obtain the first average coordinates obtained in the stacking of the second semiconductor chip 2B（First alignment mark 5A
Coordinate and the 3rd alignment mark 5C coordinate average coordinates）With the coordinate of the 5th alignment mark 5E
Second average coordinates, make the 6th alignment mark 5D be aligned relative to second average coordinates.Or, ask
The coordinate of the coordinate and the 3rd alignment mark 5C that go out the first alignment mark 5A is directed at mark 5E's with the 5th
The average coordinates of coordinate, make the 6th alignment mark 5D be aligned relative to the average coordinates.So, even if
In the case that position offset between adjacent semiconductor chip 2 is the maximum in allowed band,
The increase of position offsets of the 4th semiconductor chip 2D relative to the first semiconductor chip 2A can be suppressed.
Secondly, in the temperature being heated to more than the connection temperature of the 5th and the 6th projected electrode 3C, 4C
Meanwhile, or while ultrasonic wave is applied to the 5th and the 6th projected electrode 3C, 4C, by the 4th half
Conductor chip 2D is crimped on the 3rd semiconductor chip 2C, so as to by the 5th projected electrode 3C and the 6th
Projected electrode 4C is connected.Connection between the 5th and the 6th projected electrode 3C, 4C and first and second is convex
The connection risen between electrode 3A, 4A is similarly implemented.Therefore, it is not limited in the 3rd semiconductor chip 2C
The 5th projected electrode 3C and the 6th projected electrode 4C is connected during stacking with the 4th semiconductor chip 2D
Connect, it is also possible to interim between projected electrode 3C, 4C will be fixed and inciting somebody to action in the stacking of semiconductor chip 2
Whole semiconductor chips 2（2A~2D）To formally be connected between whole projected electrodes 3,4 after stacking（Very
Positive connection）.
4th semiconductor chip 2D is not limited to the 6th pair relative to the contraposition of the 3rd semiconductor chip 2C
Fiducial mark is known 5F and is compareed relative to average coordinates as described above.Suppressing the position of semiconductor chip 2
Put skew accumulation aspect, can also make the 6th alignment mark 5F be pointed to the first alignment mark 5A coordinate and
The inside region of the coordinate of the 5th alignment mark 5E（Centre coordinate benchmark）.Specifically, at first pair
The coordinate of coordinate and the 5th alignment mark 5E that fiducial mark knows 5A is the quadrilateral area on diagonal summit
Inner side（By the region except the line segment on each summit of quadrilateral area and each summit of connection）, by the 6th
Alignment mark 5F contrapositions.In the case where the semiconductor chip of more than five is laminated, layer 5 is later
Semiconductor chip 2 can be aligned in the same manner as the 4th layer of semiconductor chip 2D.
According to the manufacture method of implementation method, when the 3rd and the 4th semiconductor chip 2C, 2D is laminated,
It is not only the coordinate or the 5th and the 6th alignment mark 5E, 5F of the 3rd and the 4th alignment mark 5C, 5D
Coordinate, can also add the first alignment mark 5A obtained in the stacking of the second semiconductor chip 2B
Coordinate, by the 3rd and the 4th semiconductor chip 2C, 2D relative to its just under semiconductor chip 2B,
2C is aligned, therefore can suppress the position skew caused by the accumulation that the position between semiconductor chip 2 offsets
The increase of amount.Additionally, when the 3rd and the 4th semiconductor chip 2C, 2D is laminated, under also obtaining it just
Semiconductor chip 2B, 2C alignment mark 5C, 5E coordinate, even if therefore in semiconductor chip
2B, 2C unexpectedly produce abnormal position to offset, and can also detect such position skew.Therefore, according to
The manufacture method of implementation method, can be inclined in the accumulation position of the semiconductor chip 2 for suppressing multilayer laminated chip
Increase and the system of multilayer laminated chip of the usage amount of semiconductor chip 2 are prevented while the increase of shifting amount
Make the decline of yield rate.
In the whole semiconductor chip 2 of stacking（2A~2D）That implements afterwards between projected electrode 3,4 formal connecting
In the case of connecing, will temporarily be fixed between projected electrode 3,4 in the stacking of each semiconductor chip 2.Will be convex
Interim fixed die-stacks are with temperature more than the connection temperature of projected electrode 3,4 between playing electrode 3,4
Degree crimping or Reflow Soldering.So, will formally be connected between whole projected electrodes 3,4.In semiconductor core
In the case of the connection between projected electrode 3,4 is carried out during the stacking of piece 2, it is also possible to projected electrode 3,4
Connection temperature more than temperature come auxiliarily implement crimping or Reflow Soldering.
By the contraposition operation and lamination process of above-mentioned implementation method, will connected between projected electrode 3,4
While laminated semiconductor chip 2A~2D after, respectively to the first semiconductor chip 2A and the second semiconductor
The gap of chip 2B, the gap and the 3rd half of the second semiconductor chip 2B and the 3rd semiconductor chip 2C
The gap filling underfill resin 9 of conductor chip 2C and the 4th semiconductor chip 2D simultaneously makes resin hard
Change.So manufacture the semiconductor device 1 that implementation method is related to.Due to inhibiting semiconductor chip 2
Position skew accumulation caused by position offset increase, even if therefore in multilayer formation folded half
In the case of conductor chip 2, underfill resin 9 also can be well maintained between semiconductor chip 2
The fillibility in each gap, moreover it is possible to suppress bad generation of appearance and size etc..I.e., semiconductor dress can be improved
Put 1 fabrication yield.
The semiconductor device 1 that will be manufactured as the manufacture method of above-mentioned implementation method is used as shown in such as Fig. 5
Semiconductor packages 20.In the semiconductor packages 20 shown in Fig. 5, the semiconductor device 1 of implementation method is taken
It is loaded on the circuit board 23 with external connection terminals 21 and internal connection terminal 22.Circuit board 23
Inside connection terminal 22 through semiconductor device 1 the superiors semiconductor chip 2D upper surface shape
Into wiring layer again 24 and connecting line 25 and electrically connected with semiconductor device 1.On circuit board 23, shape
Into the sealing layer of resin 26 for together sealing semiconductor device 1 and the grade of connecting line 25.
The electrical connection of semiconductor device 1 and circuit board 23 can be implemented by upside-down mounting connection.Fig. 6 is represented
The state that semiconductor device 1 and the upside-down mounting of circuit board 22 are connected.In order to the upside-down mounting of semiconductor device 1 is connected
Connect, and the 7th projected electrode 27 is provided with the upper surface of the 4th semiconductor chip 2D.Semiconductor device 1
It is installed on circuit board 23 with the state opposite with lamination order so that the superiors in lamination order
Semiconductor chip 2D is located at the side of circuit board 22.The semiconductor chip 2D of circuit board 23 and the 4th is passed through in cloth
The 8th projected electrode 28 and the 7th projected electrode 27 set on the inside connection terminal 22 of line substrate 2
Connector and connected in electrically and mechanically mode.
Stored as being NAND-type flash memory in the semiconductor chip 2A~2D of composition semiconductor device 1
In the case of device chip, exist on semiconductor device 1 piggyback controller chip and/or interface chip that
The situation of the semiconductor chip for entering row data communication between external devices of sample.Such semiconductor core
Piece is laminated on such as semiconductor chip 2D, and with semiconductor device 1 through solder joint（Half field バ Application プ）
Deng electrical connection.In situation about being equipped on controller chip and/or interface chip etc. on semiconductor device 1
Under, solder joint etc. can be set through such semiconductor chip and connecting line or on semiconductor chip 2D will
Semiconductor device 1 and circuit board 33 are electrically connected.
Further, although the description of several embodiments of the invention, but, these implementation methods are only
Illustrate, be not intended to limit the scope of the present invention.These novel implementation methods can be with other various sides
Formula is implemented, and within a range not departing from the gist of the invention, can carry out various omissions, replacement, change.
These implementation methods and its deformation are contained in the scope and spirit of the present invention, and are contained in and are being asked
Inventing in equal scope described in the scope of protection.
Claims (5)
1. a kind of manufacture method of semiconductor device, it is characterised in that possess：
Prepare the operation of the first semiconductor chip, first semiconductor chip possesses in first surface setting
The first projected electrode and first alignment mark；
Prepare the operation of the second semiconductor chip, second semiconductor chip possesses：Set in second surface
The second projected electrode put and the second alignment mark；On the 3rd surface with the second surface opposition side
The 3rd projected electrode for setting and the 3rd alignment mark；With by second projected electrode and the described 3rd
The penetrating electrode of projected electrode electrical connection；
Prepare the operation of the 3rd semiconductor chip, the 3rd semiconductor chip possesses in the setting of the 4th surface
The 4th projected electrode and the 4th alignment mark；
Second semiconductor chip is moved on first semiconductor chip and make first table
Face and the relative operation of the second surface；
Obtain an xy coordinates be used as first semiconductor chip it is described first alignment mark
Positional information and obtain the 2nd xy coordinates be used as moving to it is described on first semiconductor chip
The operation of the positional information of the second alignment mark of the second semiconductor chip；
Based on first and second xy described in the positional information as first and second alignment mark
The operation that first semiconductor chip and second semiconductor chip are aligned and be laminated by coordinate；
First projected electrode and second projected electrode is set to contact and heat, and by described first
Projected electrode and the operation of second projected electrode connection；
The 3rd semiconductor chip is moved on second semiconductor chip and make the 3rd table
The relative operation in face and the 4th surface；
Obtain the 3rd xy coordinates be used as second semiconductor chip it is described 3rd alignment mark
Positional information and obtain the 4th xy coordinates be used as moving to it is described on second semiconductor chip
The operation of the positional information of the 4th alignment mark of the 3rd semiconductor chip；
Obtain what the first alignment described in obtained in the stacking of second semiconductor chip was identified
The 3rd xy seats of the first xy coordinates of positional information and the positional information as the described 3rd alignment mark
Target average coordinates, by by the described 4th alignment mark relative to the average coordinates compareed come
The operation that second semiconductor chip and the 3rd semiconductor chip are aligned and be laminated；With
The 3rd projected electrode and the 4th projected electrode is set to contact and heat, and by the described 3rd
Projected electrode and the operation of the 4th projected electrode connection.
2. a kind of manufacture method of semiconductor device, it is characterised in that possess：
Prepare the operation of the first semiconductor chip, first semiconductor chip possesses in first surface setting
The first projected electrode and first alignment mark；
Prepare the operation of the second semiconductor chip, second semiconductor chip possesses：Set in second surface
The second projected electrode put and the second alignment mark；On the 3rd surface with the second surface opposition side
The 3rd projected electrode for setting and the 3rd alignment mark；With by second projected electrode and the described 3rd
The penetrating electrode of projected electrode electrical connection；
Prepare the operation of the 3rd semiconductor chip, the 3rd semiconductor chip possesses in the setting of the 4th surface
The 4th projected electrode and the 4th alignment mark；
Second semiconductor chip is moved on first semiconductor chip and make first table
Face and the relative operation of the second surface；
Obtain the first alignment mark of first semiconductor chip and move to described the first half and lead
The operation of the positional information of the second alignment mark of second semiconductor chip on body chip；
Positional information based on first and second alignment mark come by first semiconductor chip and
The operation that second semiconductor chip is aligned and is laminated；
The 3rd semiconductor chip is moved on second semiconductor chip and make the 3rd table
The relative operation in face and the 4th surface；
Obtain the 3rd alignment mark of second semiconductor chip and move to described the second half and lead
The operation of the positional information of the 4th alignment mark of the 3rd semiconductor chip on body chip；
With
The position of positional information and the 3rd and the 4th alignment mark based on the described first alignment mark
The operation that second semiconductor chip and the 3rd semiconductor chip are aligned and be laminated by information.
3. the manufacture method of semiconductor device according to claim 2, it is characterised in that
3rd semiconductor chip possesses：With the 5th surface of the 4th surface opposition side on set
The 5th projected electrode put and the 5th alignment mark；With by the 4th projected electrode and described 5th convex
The penetrating electrode of electrode electrical connection is played,
The manufacture method of the semiconductor device is also equipped with：
Prepare the operation of the 4th semiconductor chip, the 4th semiconductor chip possesses and set on the 6th surface
The 6th projected electrode put and the 6th alignment mark；
The 4th semiconductor chip is set to move on the 3rd semiconductor chip and make the 5th table
The relative operation in face and the 6th surface；
Obtain the 5th alignment mark of the 3rd semiconductor chip and move to the described 3rd half and lead
The operation of the positional information of the 6th alignment mark of the 4th semiconductor chip on body chip；
With
What positional information and the 5th and the 6th alignment at least based on the described first alignment mark were identified
The work that 3rd semiconductor chip and the 4th semiconductor chip are aligned and be laminated by positional information
Sequence.
4. the manufacture method of semiconductor device according to claim 2, it is characterised in that
The contraposition of second semiconductor chip and the 3rd semiconductor chip is by described the second half
The xy coordinates and work of the positional information of the first alignment mark described in obtained during the stacking of conductor chip
For the xy coordinates of the positional information of the described 3rd alignment mark turn into the quadrilateral area on diagonal summit
Described 4th alignment mark is compareed to carry out by inner side.
5. the manufacture method of semiconductor device according to claim 2, it is characterised in that
The contraposition of second semiconductor chip and the 3rd semiconductor chip is by relative to described
The xy coordinates of the positional information of the first alignment mark described in obtained during the stacking of two semiconductor chips
With as the described 3rd alignment mark positional information xy coordinates average coordinates and by described 4th pair
Fiducial mark knowledge is compareed to carry out.
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| Publication number | Publication date |
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| TW201438122A (en) | 2014-10-01 |
| TWI512862B (en) | 2015-12-11 |
| CN104078372A (en) | 2014-10-01 |
| JP2014187220A (en) | 2014-10-02 |
| JP5763116B2 (en) | 2015-08-12 |
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