CN104051499B - Semiconductor device with low on-resistance and manufacturing method thereof - Google Patents

Abstract

The present invention discloses a semiconductor device with low on-resistance, which has a double dielectric layer structure defined by a thin dielectric layer adjacent to a thick dielectric layer; in particular, a high voltage metal oxide semiconductor transistor having a double gate oxide layer structure including a thin gate oxide layer adjacent to a thin oxide/thick oxide layer is provided; such a structure can be used for an extended drain metal oxide semiconductor field effect transistor, a laterally diffused metal oxide field effect transistor or any high voltage metal oxide semiconductor transistor. The present invention also discloses a method for manufacturing an extended drain metal oxide semiconductor field effect transistor device.

Description

Semiconductor device with low on-resistance and manufacturing method thereof

technical field

This application claims the benefit of US Provisional Application 61/776,835, filed March 12, 2013, the contents of which are hereby incorporated by reference in their entirety.

The present invention relates to a semiconductor device with increased characteristic on-resistance and its manufacturing method. In particular, the present invention relates to high voltage metal-oxide-semiconductor transistors having such device properties. The present invention can be extended to floating gate semiconductor devices.

Background technique

FIG. 1 is a cross-sectional view of a known extended-drain metal-oxide-semiconductor field-effect transistor (EDMOSFET). MOS generally includes a gate region 80 , a source region 90 and a drain region 95 . The metal-oxide-semiconductor transistor 1 of this exemplary figure is disposed on a substrate 10 having a deep N-type well 25 disposed along the substrate 10 . The substrate 10 may be a P-type substrate, a P-type back gate for an N-channel MOS transistor, an N-type substrate, or an N-type back gate for a P-channel MOS transistor.

P-type well 30 is arranged in deep N-type well 25 of source region 90 . The P-doped source region 35 and the N-doped source region 40 are disposed in the P-type well 30 and define a contact region of the source region 90 . N-doped drain region 45 defines a contact region for drain region 95 . The dielectric layer 60 may be a field oxide layer defining a boundary between a contact area of the drain region 95 and a contact area of the source region 90 . The conductive layer 70 may be a polysilicon layer disposed across a portion of the dielectric layer 60 and the field oxide layer 50 .

MOS transistors have three modes of operation depending on the terminal voltage. For example, a metal oxide semiconductor transistor has terminal voltages V _g (gate terminal voltage), V _s (source terminal voltage), and V _d (drain terminal voltage). When the bias voltage V _gs between the gate and the source is lower than the threshold voltage V _th of the MOS transistor, the N-channel MOS transistor operates in a cutoff mode. In cut-off mode, the channel does not increase and the current I _ds in the channel region is zero.

When the bias voltage V _gs exceeds the threshold voltage V _th , as long as the channel voltage V _ds does not exceed the saturation voltage V _ds,sat , the N-channel MOS operates in a linear mode. The saturation voltage is generally defined as the bias voltage V _gs minus the threshold voltage V _th . When N-channel MOS is in linear mode, the current I _ds increases with the channel voltage V _ds . Finally, when the channel voltage V _ds exceeds the saturation voltage V _ds,sat , the channel is pinched off and the current is saturated. When an N-channel MOS transistor is in this saturation mode, I _ds is independent of V _ds .

Extended-drain metal-oxide-semiconductor field-effect transistors (EDMOSFETs) are characterized by a relatively high characteristic on-resistance (RON) compared to laterally diffused metal-oxide-semiconductor field-effect transistors (LDMOSFETs). However, EDMOSFETs are characterized by a smaller number of shielding layers compared to LDMOSFETs. Generally, the breakdown voltage of EDMOSFET and LDMOSFET can be improved by reducing the doping concentration of the drift region or increasing the length of the drift region. This increases the specific on-resistance. This method will increase the specific on-resistance (Ron, sp) of the semiconductor structure, so that BVdss and Ron, sp cannot be improved simultaneously.

Contents of the invention

Embodiments of the present device provide a semiconductor device with increased breakdown voltage without changing the specific on-resistance of the device. Embodiments of the present device provide semiconductor devices with reduced specific on-resistance without affecting the breakdown voltage of the device.

An aspect of the present invention provides a semiconductor device comprising a double dielectric layer having a thin dielectric layer adjacent to a thick dielectric layer, an insulating layer disposed on the thick dielectric layer, and a thin dielectric layer having a layered portion along the The first conductive layer in which the layers are arranged, and at least a part of the layer portion is arranged along the insulating layer.

In an embodiment of the present invention, a semiconductor device may include a second conductive layer. For example, according to some embodiments of the present invention, a second conductive layer may be disposed over a portion of the first conductive layer and the insulating layer, and an intermediate conductive oxide layer may be disposed between the second conductive layer and the first conductive layer. and between a part of the insulating layer.

In some embodiments of the present invention, the thin dielectric layer may be a thin gate oxide layer and the thick dielectric layer may be a thick gate oxide layer. Still in accordance with this embodiment, the thickness of the thick gate oxide, insulating layer, and intermediate conductive oxide on the edge of the second polysilicon layer can vary from to In the range.

According to some embodiments of the present invention, the first conductive layer and/or the second conductive layer may include polysilicon. In certain embodiments of the present invention, the intermediate conductive oxide layer is an oxide layer deposited using a high temperature oxygen oxide deposition method.

An aspect of the present invention provides a high voltage metal oxide semiconductor (HVMOS) transistor including a substrate, a double gate oxide structure and a double conductive layer structure disposed along the substrate. According to an embodiment of the present invention, a dual gate oxide structure has a thin gate oxide layer adjacent to a thick gate oxide layer and an insulating layer disposed on the thick gate oxide layer.

In some embodiments of the present invention, the two-layer conductive layer structure includes a first conductive layer disposed along a thin gate oxide layer having a layer portion disposed at least partially along the insulating layer, disposed on the first A second conductive layer on a portion of the conductive layer and the insulating layer and an intermediate conductive oxide layer disposed between the second conductive layer and the portion of the first conductive layer and the insulating layer. In some embodiments of the present invention, the intermediate conductive oxide layer of the HVMOS transistor includes a high temperature oxide.

In an embodiment of the present invention, the HVMOS transistor further includes an N ^{-well disposed in the substrate below the two-layer conductive layer structure and a P-type implant disposed in the N- well} . According to an embodiment of the present invention, the P-type ions for the P-type implantation are selected from, for example, P-type ions that are easy to diffuse outward. Still in accordance with this embodiment of the invention, the doping concentration in the P-type implant is in the range from 5×10 ¹² /cm ² to 1×10 ¹⁴ /cm ² .

According to an embodiment of the present invention, HVMOS transistors have a reduction in effective channel length in the range from 0.2 μm to 1 μm in contrast to HVMOS transistors without double gate oxide structure, P-type implant and N ^- well.

In other embodiments of the present invention, the HVMOS transistor further includes an N-type doped drain (NDD) region disposed in the substrate extending from the drain region to below the two-layer conductive layer structure. Still according to this embodiment, the HVMOS transistor of the present invention has a reduction in effective channel length in the range from 0.2 μm to 1 μm, which is compared to the HVMOS transistor without the double gate oxide structure and the NDD region

In an embodiment of the invention, the HVMOS transistor has no quasi-saturation. In certain embodiments of the invention, the slope of the drain-source current versus the drain-source voltage is at least 6 x ^10-5 amperes/micron- volt.

In still other embodiments of the present invention, the HVMOS transistor further includes an N ^- implant configured to extend from the substrate extending across the upper portion of the N-well and the N-doped drain region to terminate below the thick gate oxide. Bottom. In some embodiments of the present invention, the N ^- implantation terminates at the edge of the second conductive layer below the two-layer conductive layer structure at the mid-level conductive oxide layer and the isolation layer.

In still other embodiments of the present invention, the substrate includes a P-body region, a P-doped source region and an N-doped source region each disposed in the P-body region and defining a contact region of the source region.

Still in other embodiments of the present invention, the HVMOS transistor may further include a P-doped source region with a contact region defining the source region and a P-type well with an N-doped source region, and a P-type well adjacent to the P-type well. An N-type well having an N-doped drain region defining a contact region of the drain region.

In some embodiments of the present invention, the first conductive layer is a first polysilicon layer and the second conductive layer is a second polysilicon layer. In an embodiment of the invention, a two-layer conductive layer structure is configured to define a polysilicon-insulator-polysilicon (PIP) capacitance.

An aspect of the present invention is to provide a method of fabricating a semiconductor, such as, for example, an extended-drain MOSFET device according to an embodiment of the present invention.

According to an embodiment of the present invention, a method of manufacturing a semiconductor may include, for example, providing a semiconductor device having a substrate, a deep N-type well, and an oxide layer; implanting an N-type well and a P-type well; The N-type well and the P-type well; depositing a silicon nitride layer; forming a field oxide layer; removing the silicon nitride layer and the oxide layer; forming a thick gate oxide; forming a thin gate oxide , a portion of the thin gate oxide is disposed along the thick gate oxide; a first conductive layer is formed, the first conductive layer is disposed along at least a portion of the thin gate oxide, including along The thick gate oxide is disposed at least a portion of the portion of the thin gate oxide; depositing a high temperature oxide layer; and forming a second conductive layer, the high temperature oxide layer extending the second conductive layer from along The thin oxide layer disposed along the second conductive layer is separated.

The method for manufacturing a semiconductor may further include implanting an N ^- doped region; depositing an ethyl silicate (TEOS) layer on the first conductive layer, etching the TEOS layer to form a gap layer; implanting an N ⁺ doped drain region; implanting N ⁺ doped source region; and implanting P ⁺ doped source region.

In a non-limiting exemplary embodiment of the present invention, the step of forming a thick gate oxide layer includes depositing a thick gate oxide layer; coating a thick gate oxide photoresist layer; etching the thick gate oxide layer; and removing the thick gate oxide photoresist layer.

These and other aspects of the invention, as well as embodiments of the invention, will become apparent when the following description is examined in conjunction with the accompanying drawings, although the invention is pointed out with particularity through the scope of the appended claims.

Description of drawings

Having thus described the invention in general terms, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and in which:

FIG. 1 is a cross-sectional view of a known metal oxide semiconductor;

2 is a cross-sectional view of an extended-drain metal-oxide-semiconductor transistor according to an embodiment of the present invention;

3A is a cross-sectional view of an extended-drain metal oxide semiconductor transistor according to another embodiment of the present invention;

3B is a detailed cross-sectional view of a portion of the extended-drain metal oxide semiconductor transistor of FIG. 3A;

4A is a cross-sectional view of an extended-drain metal oxide semiconductor transistor according to another embodiment of the present invention;

4B is a detailed cross-sectional view of a portion of the extended-drain metal oxide semiconductor transistor of FIG. 4A;

FIG. 5A is a TCAD simulation of the electronic properties of the extended-drain metal oxide semiconductor of FIG. 4A;

Figure 5B is a detailed overview of the TCAD simulation of Figure 5A;

6A is a graph of drain-source voltage versus drain-source current in a known extended-drain MOS;

6B is a graph of drain-source voltage versus drain-source current in an extended-drain MOS in accordance with an embodiment of the present invention;

7 is a cross-sectional view of an extended-drain metal oxide semiconductor transistor according to another embodiment of the present invention;

8 is a cross-sectional view of an N-type laterally doped metal oxide semiconductor transistor according to an embodiment of the present invention;

Figure 9 is a three-dimensional view of a RESURF device according to an embodiment of the present invention;

Figure 10 is a top view of the RESURF device;

Fig. 11 A is a sectional view along the line AA' of the RESURF device of Fig. 10;

Fig. 11 B is a sectional view along the BB' line of the RESURF device of Fig. 10;

12 is a cross-sectional view of an extended-drain metal-oxide-semiconductor transistor according to another embodiment of the present invention;

13 is a cross-sectional view of an extended-drain metal-oxide-semiconductor transistor with polysilicon-insulator-polysilicon (PIP) capacitance in accordance with an embodiment of the present invention;

14A is a top view of an extended-drain N-channel MOS in accordance with an embodiment of the present invention;

14B is a top view of an extended-drain N-channel MOS according to another embodiment of the present invention;

14C is a top view of an extended-drain N-channel MOS according to another embodiment of the present invention;

14D is a top view of an extended-drain N-channel MOS according to another embodiment of the present invention;

14E is a top view of an extended-drain N-channel MOS according to another embodiment of the present invention;

15A-15H are cross-sectional views of a semiconductor device after completion of various steps in fabricating the device, according to an embodiment of the present invention; and

FIG. 16 is a flowchart of different steps in fabricating a semiconductor device according to an embodiment of the present invention.

【Symbol Description】

1: metal oxide semiconductor transistor 10: substrate

25: Deep N-type well 30: P-type well

35: P-doped source region 40: N-doped source region

45: N-doped drain region 50: Dielectric layer

60: field oxide layer 70: conductive layer

80: gate area 90: source area

95: Drain region 100: Extended drain metal oxide semiconductor

102: Extended Drain Metal Oxide Semiconductor Transistor 104: NLDMOS

106: EDMOS 108: EDMOS

110: base

120: Deep N-type well 130: P-type well

135: P body region 140: N-type well

150: P-doped source region 155: P-doped source region

160: N-doped source region 165: N-doped source region

170: N-doped drain region 180: Dielectric layer

190: thin oxide layer 195: isolation layer

200: thick oxide layer 210: first polysilicon layer

220: high temperature oxide layer 230: second polysilicon layer

240: gate area 250: source area

260: Drain region 270: N ^- implantation

280: PIP capacitor

300: Extended Drain Metal Oxide Semiconductor 310: Substrate

320: Deep N-type well 330: P-type well

350: P-doped source region 360: N-doped source region

370: N-doped drain region 380: Dielectric layer

390: thin oxide layer 400: thick oxide layer

410: first polysilicon layer 340: N-type well

440: gate area 420: high temperature oxide layer

470: N ^- well 450: Source region

460: drain region 395: insulator

490: Channel 480: P Field Injection

495: effective length reduction

500: Extended Drain Metal Oxide Semiconductor 510: Substrate

520: Deep N-type well 540: N-type doped drain region

530: P-type well 550: P-doped source region

560: N-doped source region 570: N-doped drain region

580: Dielectric layer 590: Thin oxide layer

600: thick oxide layer 610: first polysilicon layer

630: second polysilicon layer 620: high temperature oxide layer

595: Insulator 640: Gate region

650: source region 660: drain region

615: Step part 680: Effective length

690: Channel 695: Effective length reduction

525: the first PN junction 535: the second PN junction

692: Area 694: Clearly Defined Currents

700: Extended Drain Metal Oxide Semiconductor 710: Substrate

720: Deep N-type well 730: P-type well

740: N-type well 750: P-doped source region

760: N-doped source region 770: N-doped drain region

810: first polysilicon layer 830: second polysilicon layer

880: P drift injection

950: source region 1050: source region

1150: source region 1250: source region

1350: source region 910: N-doped source region

1050: N-doped source region 1110: N-doped source region

1210: N-doped source region 1310: N-doped source region

920: P-doped source region 1020: P-doped source region

1120: P-doped source region 1220: P-doped source region

1320: P-doped source region 960: N-doped drain region

1060: N-doped drain region 1160: N-doped drain region

1260: N-doped drain region 1360: N-doped drain region

970: drain region 1070: drain region

1170: drain region 1270: drain region

1370: drain region 930: first polysilicon layer

1040: first polysilicon layer 1140: first polysilicon layer

1240: first polysilicon layer 1340: first polysilicon layer

940: second polysilicon layer 1040: second polysilicon layer

1140: second polysilicon layer 1240: second polysilicon layer

1340: second polysilicon layer 1500: semiconductor device

1700: EDMOS transistor 1710: Sacrificial oxide layer

1520: Deep N-type well 1720: Sacrificial oxide layer

1510: Substrate 1525: Sacrificial Oxide

1730: P-type well 1720: N-type well

1740: implant 1750: silicon nitride layer

1760: Field oxide layer 1585: Silicon nitride layer

1580: field oxide layer 1770: silicon nitride layer

1780: Sacrificial Oxide 1790: Thick Gate Oxide

1575: Silicon nitride layer 1600: Thick gate oxide

1590: Thin Gate Oxide 1800: Thin Gate Oxide

1605: thick gate and thin gate layer 1810: first conductive layer

1820: high temperature oxide layer 1830: second conductive layer

1620: high temperature oxide layer 1630: second conductive layer

1840: N ^- doped region 1850: P ^- implanted region

1860: Orthosilicate layer 1870: N ⁺ doped drain region

1880: N ⁺ doped source region 1890: P ⁺ doped drain region

1545: N ^- doped region 1550: P ⁺ doped source region

1560: N ⁺ doped source region 1570: N ⁺ doped drain region

detailed description

Certain embodiments of the invention will now be fully described below with reference to the accompanying drawings, but not all embodiments of the invention will be shown, various embodiments of the invention may be embodied in many different forms, and should not be construed as Rather, these examples are provided so that this invention will satisfy applicable legal regulations.

Unless the context clearly indicates otherwise, the singular forms "a" and "the" used in this specification and the appended claims shall cover multiple references, for example, the reference to "semiconductor device" includes multiple such semiconductor device.

Certain specific terms used in the present invention are used in general and descriptive terms only and not for the purpose of limitation. All terms, including technical and scientific terms, unless the context clearly defines otherwise, have the same meaning as in the present invention. The same meaning as generally understood by those of ordinary skill in the art; moreover, as defined in commonly used dictionaries, it should be interpreted as having the meaning generally understood by those of ordinary skill in the art to which the present invention belongs, And, as defined in commonly used dictionaries, should be interpreted as having meanings consistent with their meanings in the relevant fields and in the context of the present invention, and these commonly used terms will not be construed as being overly idealistic or stereotyped concepts unless the context clearly defines otherwise.

The inventors conceived of dual gate oxides to provide metal oxide semiconductor controlled power semiconductor devices. FIG. 2 is an exemplary illustration of a cross-section of a metal oxide semiconductor according to an embodiment of the present invention. FIG. 2 is an exemplary extended-drain metal-oxide-semiconductor (EDMOS) transistor showing one type of semiconductor device of the present invention. The extended drain metal oxide semiconductor 100 in FIG. 2 takes a P-type substrate as an example and has a substrate 110 on which a deep N-type well 120 is disposed. Disposed in the deep N-type well 120 are the P-type well 130 located in the source region 250 and the N-type well 140 located in the drain region 260 . The P-doped source region 150 and the N-doped source region 160 are disposed in the P-type well and define a contact region of the source region 250 . The N-doped drain region 170 disposed in the N-type well 140 defines a contact region of the drain region 260 .

The dielectric layer 180 defines the outer boundary of the contact region of the P-doped source region 150 to the source region 250 and the outer boundary of the N-type well 140 located in the drain region 260 . The dielectric layer ends from the contact region of the source region 250 to the N-doped source region 160 and continues approximately from the inner boundary of the N-type well 140 of the drain region 260 . According to the illustrated embodiment of FIG. 2 , the dielectric layer includes a thin oxide layer 190 and a thick oxide layer 200 . In an embodiment of the invention, the thin oxide layer 190 and the thick oxide layer 200 may be gate oxide layers. The dielectric layer 180 defines the outer boundary of the contact region of the P-doped source region 150 to the source region 250 and the outer boundary of the N-type well 140 located in the drain region 260 . The dielectric layer ends from the contact region of the source region 250 to the N-doped source region 160 and continues approximately from the inner boundary of the N-type well 140 of the drain region 260 . According to the illustrated embodiment of FIG. 2 , the dielectric layer includes a thin oxide layer 190 and a thick/thin oxide layer 200 . In an embodiment of the present invention, the thin oxide layer 190 and the thick oxide/thin oxide layer 200 may be gate oxide layers.

The two-layer conductive layer structure defining the gate region 240 is disposed on a dielectric layer including the double gate oxide layer of the present invention. For example, as shown in the illustrative embodiment of FIG. 2, a two-layer conductive layer structure includes a first polysilicon layer 210 and a second polysilicon layer 230 separated by a middle conductive oxide layer, which is a high temperature oxide layer (HTO) 220 . In the illustrated embodiment of FIG. 2 , first polysilicon layer 210 is disposed across thin oxide layer 190 and a portion of first polysilicon layer 210 . In an embodiment of the invention, thin oxide layer 190 may, at least partially, be disposed along thin oxide/thick oxide layer 200 . More precisely, the first polysilicon layer 210 extends along the thin oxide layer 190 with a fixed thickness, and then the first polysilicon layer 210 is stacked in a stepwise manner, extending along the thin oxide layer 190 to become thicker. At this time, when the thin oxide layer 190 is disposed across the thin oxide/thick oxide layer 200 , the thickness of the first polysilicon layer 210 changes to conform to the thin oxide/thick oxide layer 200 . The first polysilicon layer 210 continues to extend into the region where the thin oxide layer 190 is disposed along the thin oxide/thick oxide layer 200 . The thin oxide layer 190 is disposed along the thin oxide/thick oxide layer 200 and the remaining portion not covered by the first polysilicon layer is in contact with the high temperature oxide layer.

The second polysilicon layer 230, which is separated by the high temperature oxide layer 220, is configured in some parts inward from the first polysilicon layer 210 and the high temperature oxide layer 220, and the second polysilicon layer 230 extends along the first polysilicon layer 230. The outer surface of a polysilicon layer 210 extends conformally to the boundary of the two-layer conductive layer structure. In fact, the first polysilicon layer 210 and the high temperature oxide layer 220 are configured to form a field effect electric plate in the drift region, so as to protect the drift region from being affected by the charge effect to cause breakdown and increase the breakdown voltage.

As shown in the illustrative embodiment of FIG. 2 , the boundary of the two-layer conductive layer structure may be where the N-doped source region 160 begins. Therefore, portions of the thin oxide/thick oxide layer 200 may continue to extend to the N-doped source region 160 located at the drain region 260 .

While the embodiment of FIG. 2 is described in the form of a two-layer conductive layer structure having a polysilicon layer, in some embodiments, one or both of the conductive layers may comprise any material or known in the art as a conductive material. Material. Rather, the conductive material of the first conductive layer may be the same as or different from the conductive material of the second conductive layer. In some embodiments of the present invention, the first conductive layer and the second conductive layer may have different geometries as shown in the illustrated embodiments of the present invention and described above.

According to some embodiments of the present invention, the gate material of the two-layer conductive layer structure may be polysilicon, metal or silicide polysilicon. The interlayer insulating layer may be oxide, oxynitride oxide (ONO), or a high dielectric insulator. In some embodiments of the present invention, the first conductive layer and the second conductive layer may be configured to have the same bias voltage. In other embodiments of the present invention, the first conductive layer and the second conductive layer may be configured to have different bias voltages.

Without being bound by theory, the double gate oxide structure composite of the present invention increases the distance between the gate region 240 and the drain region 260 compared to a conventional extended drain metal oxide semiconductor field effect transistor (EDMOSFET). breakdown voltage, while the current flow path in the drift region is effectively reduced to lower the RON of the device.

In an embodiment of the present invention, the boundary conductive oxide layer (in some embodiments, a high temperature oxide layer), the insulating layer, and the second conductive layer (in some embodiments, a second polysilicon layer) edge The total thickness of the rear dielectric layer (thick gate oxide in some embodiments) is this thickness to increase the breakdown voltage. In an embodiment of the present invention, the total thickness of the aforementioned layers may vary from about to appointment between the ranges. In an embodiment of the invention, the thickness of the thin oxide layer may be about to appointment The thickness of the thick gate oxide can be approximately arrive The thickness of the high temperature oxide layer can be about to appointment In an embodiment of the invention, the thin oxide layer, which may be a gate oxide layer, may have a thickness of about to appointment In an embodiment of the invention, the thick oxide layer, which may be a gate oxide layer, may have a thickness of about to appointment Still in an embodiment of the invention, the intermediate conductive oxide layer, which may be an oxide deposited by high temperature oxidation, separating the first conductive layer from the second conductive layer, may be about to appointment

In an embodiment of the invention, the structure of the total oxide in the second polysilicon layer provides a contribution of about 10.8 MV/cm to the breakdown voltage. According to some embodiments of the present invention, the breakdown voltage between the edge of the second polysilicon layer and the drain region is in the range of about 39V to about 200V.

In some embodiments of the present invention, the drift region generally includes a P-type well and an N-type well, but there may be different configurations in the subsequent description. In an embodiment of the invention, the N-well may be an N-well. According to some embodiments, without being bound by theory, the N-well can help reduce the effective channel length and the resistance of the drift region.

According to some embodiments of the present invention, an N-type double drain (NDD) layer may be implanted in the drift region. In certain embodiments of the present invention, without being bound by theory, the NDD layer can reduce the RON of the device.

In some embodiments of the present invention, the material of the P-type well readily out-diffuses into the oxide layer. Without being bound by theory, the P-type material can be used to reduce the effective channel length and channel resistance.

The double oxide layer of the present invention can be formed by any technique known in the art for forming oxide layers. According to an embodiment of the present invention, the gate oxide layer may be applied to a process of area oxidation of silicon (LOCOS).

In an embodiment, the present invention may be applied to a semiconductor device fabricated in a shallow trench isolation (STI) method. In some embodiments, the present invention is applied to semiconductor devices fabricated by deep trench isolation (DTI) methods. In other embodiments of the present invention, the double gate oxide structure and the multi RESURF structure of the present invention can be applied to a semiconductor device with a silicon-on-insulator (SOI) structure. Still in other embodiments of the present invention, the double gate oxide structure and the RESURF structure of the present invention can be applied to N-type epitaxial methods, P-type epitaxial methods, non-epitaxial methods or a combination thereof. semiconductor.

In some embodiments of the present invention, the dual gate oxide structure and the RESURF power semiconductor of the present invention can be applied in N-channel extended-drain MOS. In other embodiments of the present invention, the double gate oxide structure and the RESURF power semiconductor of the present invention can be applied in the P-channel extended drain MOS. Still in other embodiments of the present invention, the dual gate oxide structure and the RESURF power semiconductor of the present invention can be applied to N-channel laterally diffused MOSFETs. Still in other embodiments of the present invention, the dual gate oxide structure and the RESURF power semiconductor of the present invention can be applied to a P-channel laterally diffused MOSFET.

3A is a cross-sectional view of an extended-drain MOSFET according to another embodiment of the present invention. The extended drain MOS 300 of FIG. 3A includes a substrate 310 on which a deep N-type well 320 is disposed. The N-well 470 is disposed between the P-type well 330 located in the source region 450 and the N-type well 340 located in the drain region 460 . The P-doped source region 350 and the N-doped source region 360 are arranged in the P-type well 330 and define the contact region of the source region 450 , while the N-doped drain region 370 arranged in the N-type well 340 A contact region of the drain region 460 is defined.

The dielectric layer 380 defines the outer boundary of the contact area of the P-doped source region 350 to the source region 450 and the outer boundary of the N-type well 340 located in the drain region 460 . The two-layer conductive layer structure defining the gate region 440 separates the source region 450 from the drain region 460 . The two-layer conductive layer structure includes the double oxide gate oxide layer of the present invention having a thin oxide layer 390 and a thin oxide/thick oxide layer 400 . The two-layer conductive layer structure includes a first polysilicon layer 410 which may be a first conductive layer and a second polysilicon layer 430 which may be a second conductive layer, wherein the first conductive layer and the second conductive layer are considered as high temperature The oxide layer 420 is separated by a dielectric layer.

An implant region or P field implant 480 is configured in the N-well 470 . In an embodiment of the present invention, the P-type ions may be, for example, boron. In some embodiments of the present invention, the P-type ions of the P-field implant 480 are selected for ease of outdiffusion after the implant drive-in procedure. In some embodiments of the invention, the doping concentration of P field implant 480 is in the range of about 5×10 ¹² /cm ² to about 1×10 ¹⁴ /cm ² .

3B is a detailed cross-sectional view of a portion of the extended-drain MOS transistor 300 of FIG. 3A showing channel 490 . 3B shows that the effective length of channel 490 is reduced by including P-field implant 480 disposed in N ^- well 470 , where channel 490 is adjacent to P-well 330 and N-well 340 . According to an embodiment of the present invention, the effective length reduction 495 of the channel may be in the range of about 0.2 μm to about 1 μm.

4A is a cross-sectional view of an extended-drain MOSFET according to another embodiment of the present invention. The extended drain MOS 500 of FIG. 4A includes a substrate 510 on which a deep N-type well 520 is disposed. The N-type doped drain region 540 forms a part of the P-type well 530 . The P-doped source region 550 and the N-doped source region 560 are configured in the P-type well 530 and define the contact area of the source region 650, while the N-doped drain region 570 is configured in the N-type doped A contact area of the drain region 660 is defined in the drain region 540 .

The dielectric layer 580 defines the outer boundary of the contact area of the P-doped source region 550 to the source region 650 and the outer boundary of the N-type doped drain region 540 located in the drain region 560 . The two-layer conductive layer structure defining the gate region 640 separates the source region 650 from the drain region 660 . The two-layer conductive layer structure includes the inventive double oxide gate oxide layer with thin oxide layer 590 and thin oxide/thick oxide layer 600 . The two-layer conductive layer structure includes a first polysilicon layer 610 which may be a first conductive layer and a second polysilicon layer 630 which may be a second conductive layer, wherein the first conductive layer and the second conductive layer are considered as high temperature The oxide layer 620 is separated by a dielectric layer.

According to the illustrated embodiment of FIG. 4A , N-type doped drain region 540 may be implanted to extend from drain region 660 into, at least partially, a portion of P-type well 530 below the two-layer conductive layer structure of gate region 640 terminated. 4B is a detailed cross-sectional view of a portion of the extended-drain MOS transistor 500 of FIG. 4A showing channel 690 . 4B shows that the effective length of the channel 690 is reduced by extending the N-type doped drain region 540 disposed in the P-type well 530 to under the two-layer conductive layer structure of the gate region 640 . According to an embodiment of the present invention, the N-type doped drain region 540 may terminate below the first polysilicon layer 610 . According to some embodiments of the present invention, the N-type doped drain region 540 terminates below the first polysilicon layer 610 before the stepped portion 615 of the first polysilicon layer 610 is laminated and thickened. According to an embodiment of the present invention, the effective length reduction 695 of the channel may be in the range of about 0.2 μm to about 1 μm.

FIG. 5A is a TCAD simulation of the electrical characteristics of the extended-drain MOS 500 of FIG. 4A . Figure 5B is a detailed overview of the channel 690 of the TCAD simulation of Figure 5A. A first PN junction 525 is shown between deep N-type well 520 and P-type well 530 . A second PN junction 535 is shown between the P-type well 530 and the N-type doped drain region 540 . The left side of the second PN junction 535 shows the effective length 680 and the effect of reducing the effective length 680 by the interface of the N-type doped drain region 540 with the P-type well 530 .

6A is a graph of drain-source voltage V _ds versus drain-source current I _ds in a known extended-drain MOS. FIG. 6A shows the saturation-like effect of a known extended-drain MOS transistor. A quasi-saturation effect is illustrated in region 692 and defines the current I _ds reaction between the drain and the source of a high voltage MOS device with an increased voltage Vds across the drain and source regions. As shown in Figure 6A, where the saturation voltage region is not indicated, I _ds approaches a well-defined current at saturation. In the saturation-like effect region, the electric field peak in the drift region and the channel current are not saturated, and the nonlinear resistance in the drift region is realized.

6B is a graph of drain-source voltage versus drain-source current in an extended-drain MOS in accordance with an embodiment of the present invention. FIG. 6B shows how the EDMOS of the present invention with NDD implanted regions overcomes the saturation-like effect of known EDMOS. The graph of FIG. 6B shows that I _ds in the EDMOS of an embodiment of the present invention results in a well-defined current 694 for the saturation state. In an embodiment of the invention, once saturation is reached, the response of I _ds is linear with respect to changes in V _ds as the response of I _ds approaches saturation at a fixed Ids, i.e., I _ds remains fixed or after saturation is reached , with only a slight change in relation to changes in V _ds . A transition zone is established between the curve and the straight line going to the saturation zone. It can be calculated from the curve that, in certain embodiments of the invention, the slope of the drain-source current versus the drain-source voltage is at least about 6× between the established transition region and the slope of the line for the saturation region 10 ^-5 amps/micron-volts.

FIG. 7 is a cross-sectional view of an extended-drain MOSFET according to another embodiment of the present invention. The extended drain MOS 102 of FIG. 7 includes a substrate 110 on which a deep N-type well 120 is disposed. The extended-drain MOSFET 102 further includes a P-type well 130 located in the source region 250 and an N-type well 140 located in the drain region 260 . The P-doped source region 150 and the N-doped source region 160 are arranged in the P-type well 130 and define the contact region of the source region 250 , while the N-doped drain region 170 arranged in the N-type well 140 A contact region of the drain region 260 is defined.

The dielectric layer 180 defines the outer boundary of the contact region of the P-doped source region 150 to the source region 250 and the outer boundary of the N-type well 140 located in the drain region 260 . The dielectric layer starts from the contact region of the source region 250 and ends at the N-doped source region 160 and continues approximately from the inner boundary of the N-type well 140 of the drain region 260 . According to the illustrated embodiment of FIGS. 6A and 6B , the dielectric layer includes a thin oxide layer 190 and a thick oxide layer 200 . In an embodiment of the invention, the thin oxide layer 190 and the thick oxide layer 200 may be gate oxide layers.

The two-layer conductive layer structure defining the gate region 240 is disposed on a dielectric layer including the double gate oxide layer of the present invention. The two-layer conductive layer structure can be configured according to the description of the two-layer conductive layer structure defined by taking FIG. 2 as an example.

The extended drain MOS transistor of FIG. 7 further includes an N ⁻ implant 270 disposed in the drain region 260 . According to the illustrated embodiment of FIG. 7 , N ^- implant 270 may span the upper portion of extended N-type well 140 and N-doped drain region 170 . Additionally, N ^- implant 270 may extend into N-type well 140 . According to an embodiment of the present invention, N ^- implant 270 may be terminated below thin oxide/thick oxide layer 200 . In some embodiments of the present invention, N ^- implant 270 is in the lower level portion of second polysilicon layer 230 disposed over high temperature oxide layer 220, thin oxide layer 190, and thin oxide/thick oxide layer 200. terminates below. In some embodiments of the present invention, N ^- implant 270 may terminate below the two-layer conductive layer structure where the edge of second polysilicon layer 230 is aligned with high temperature oxide layer 220 . In some embodiments of the present invention, N ^- implant 270 may terminate below the two-layer conductive layer structure where the edge of second polysilicon layer 230 is aligned with high temperature oxide layer 220 and thin oxide layer 190 . In some embodiments of the invention, the doping concentration of N ^- implant 270 is in the range from about 5×10 ¹² /cm ² to about 1×10 ¹⁴ /cm ² .

8 is a cross-sectional view of an N-type laterally doped metal oxide semiconductor (NLDMOS) transistor according to an embodiment of the present invention. The NLDMOS 104 of FIG. 8 includes a substrate 110 on which a deep N-type well 120 is disposed. The extended-drain MOSFET 102 further includes a P-body region 135 located in the source region 250 and an N-type well 140 located in the drain region 260 . The P-doped source region 155 and the N-doped source region 165 are arranged in the P body region 135 and define the contact region of the source region 250 , while the N-doped drain region 170 arranged in the N-type well 140 A contact region of the drain region 260 is defined.

The dielectric layer 180 defines the outer boundary of the contact area of the P-doped source region 155 to the source region 250 and the outer boundary of the N-type well 140 located in the drain region 260 . The dielectric layer starts from the contact region of the source region 250 and ends at the N-doped source region 160 and continues approximately from the inner boundary of the N-type well 140 of the drain region 260 . According to the illustrated embodiment of FIG. 8 , the dielectric layer includes a thin oxide layer 190 and a thick oxide layer 200 . In an embodiment of the present invention, the thin oxide layer 190 and the thick oxide layer 200 may be gate oxide layers, ie, a thin gate oxide layer and a thick gate oxide layer, respectively.

The two-layer conductive layer structure defining the gate region 240 is disposed on a dielectric layer including the double gate oxide layer of the present invention. Although the two-layer conductive layer structure may have known structures according to some embodiments of the present invention, the two-layer conductive layer structure may be configured according to the description of the two-layer conductive layer structure defined by taking FIG. 2 as an example.

Figure 9 is a three-dimensional view of a RESURF device according to an embodiment of the present invention. FIG. 9 shows an extended-drain MOS 700 with multiple lateral resurf. The extended drain MOS 700 includes a substrate 710 on which a deep N-type well 720 is disposed. The extended drain MOS transistor 700 also includes a P-type well 730 and an N-type well 740 . The P-doped source region 750 and the N-doped source region 760 are configured in the P-type well 730 , and the N-doped drain region 770 is configured in the N-type well 740 . Extended drain metal oxide semiconductor 700 includes a two-layer conductive structure having a first conductive layer or first polysilicon layer 810 according to this illustrative embodiment and a second conductive layer or second polysilicon layer 810 according to this illustrative embodiment. Silicon layer 830 . The extended-drain MOS 700 of FIG. 9 includes a plurality of P-drift implants 880 disposed in the N-type well 740 .

FIG. 10 is a top view of the extended drain MOS 700 of FIG. 9 . Figure 10 shows a plurality of separately configured and rectangular P-drift implants 880 in accordance with this illustrative embodiment. 11A is a cross-sectional view along line AA' of the RESURF device of FIG. 11B is a cross-sectional view along line BB' of the RESURF device of FIG.

The purpose of the semiconductor device in FIG. 9 is the multiple lateral resurf structure of the present invention in high voltage devices. The double oxide gate structure and the multiple lateral resurf structure of the present invention can be applied to semiconductor devices including high voltage devices.

In embodiments of the present invention, the deep N-well may be replaced with an N-well to form a low-side N-channel metal-oxide-semiconductor (NMOS) device. 11A and 11B are cross-sectional views of an EDMOS transistor according to another embodiment of the present invention. EDMOS 106 of FIG. 12 includes substrate 110 , eg, a P-type substrate or even an epitaxial substrate aligned with N-type well 145 and P-type well 135 . Other elements of this exemplary device, including the double oxide structure of the present invention, are described above.

The first conductive layer or first polysilicon layer according to some embodiments of the present invention and the second conductive layer or second polysilicon layer according to some embodiments of the present invention may be configured to have different bias voltages. In some embodiments of the present invention, the bias voltage of the first conductive layer and the second conductive layer may range from about 0 volts to about 28 volts.

For example, in embodiments of the present invention, a polysilicon-insulator-polysilicon (PIP) capacitor structure may be used to provide different bias voltages for the first polysilicon layer than the second polysilicon layer. FIG. 13 is a cross-sectional view of an EDMOS 108 transistor with a PIP capacitor 280 according to an embodiment of the present invention. According to some embodiments of the present invention, the high temperature oxide layer 220 of the PIP capacitor 280 may be used to achieve a desired specific capacitance.

In embodiments of the present invention, the total thickness of the thin oxide/thick oxide layer 200 and the high temperature oxide layer 220 can provide a higher drain breakdown voltage, but according to some embodiments of the present invention, the thin oxide/thick oxide layer The total thickness of the high temperature oxide layer 200 and the high temperature oxide layer 220 is configured to be thinner than the field oxide layer or the oxide of the shallow trench isolation structure.

The semiconductor device of the present invention can be manufactured from many different types of layers, including but not limited to N-type epitaxial layer, P-type epitaxial layer, N-type non-epitaxial layer, P-type non-epitaxial layer, N-type silicon-on-insulator layer and /or the P-type insulating layer is covered with a silicon layer. The structure of the present invention can be incorporated into various types of semiconductor devices including, but not limited to, for example, N-channel EDMOS, P-channel EDMOS, N-channel LDMOS, and P-channel LDMOS.

The semiconductor devices of the present invention may have any type of geometry. Certain exemplary embodiments of the geometry of the present invention are included, for example, in FIGS. 14A-14E . A typical structure consists of a source region (950, 1050, 1150, 1150, 1250, 1350) and drain regions (970, 1070, 1170, 1270, 1370) having N-doped drain regions (960, 1060, 1160, 1260, 1360). The two-layer conductive layer structure of this exemplary embodiment includes a first polysilicon layer (930, 1040, 1140, 1240, 1340) and a second polysilicon layer (940, 1040, 1140, 1240, 1340).

14A is a top view of an extended-drain N-channel MOS with a rectangular structure according to an embodiment of the present invention. 14B is a top view of an extended-drain N-channel MOS according to another embodiment of the present invention. 14C is a top view of an extended-drain N-channel MOS according to another embodiment of the present invention.

14D is a top view of an extended-drain N-channel MOS according to another embodiment of the present invention, wherein the second polysilicon layer 1240 has a tooth structure. 14E is a top view of an extended-drain N-channel MOS according to another embodiment of the present invention, wherein the second polysilicon layer 1240 has a circular tooth structure.

An aspect of the present invention is to provide a method of fabricating a semiconductor device such as an extended-drain metal-oxide-semiconductor transistor. According to an embodiment of the present invention, as shown in FIG. 16 , a method of fabricating an EDMOS transistor 1700 includes providing a semiconductor device having a substrate, a deep N-type well, and an oxide layer, or, in particular, a sacrificial oxide layer 1710 . According to an embodiment of the present invention as an example, FIG. 15A illustrates that a semiconductor device 1500 has a substrate 1510, a deep N-type well 1520 is implanted in the substrate 1510, and a sacrificial oxide layer 1525 is formed above the deep N-type well 1520.

The method of manufacturing the EDMOS transistor may further include the steps of implanting the P-type well 1730 and implanting the N-type well 1720, and vice versa. The steps of implanting N-type well 1720 and implanting P-type well 1730 may include various sub-steps known to those skilled in the art. In some embodiments of the present invention, these implantation steps may be performed photolithographically, possibly including the step of applying one or more layers of photoresist after removal of any photoresist masking layer, which is necessary for the P-type well and the N-well. Type well implantation helps. The steps of implanting the N-type well 1720 and implanting the P-type well 1730 may further include the step of driving the implant 1740 . Not intended to be limiting, the drive-in method facilitates penetration of implanted ions into deeper layers. FIG. 15B shows an exemplary embodiment of a semiconductor device 1500 completing the steps with a P-type well 1530 and an N-type well 1540 .

The method of fabricating an EDMOS transistor may further include depositing a silicon nitride layer 1750 . According to some embodiments of the present invention, the step of depositing the silicon nitride layer 1750 may also include applying diffusion, photoresist patterning, etching, and deposition across the semiconductor device one or more times. The method of fabricating an EDMOS transistor may further include forming a field oxide layer 1760 . Forming the field oxide layer 1760 may include a number of sub-steps including, for example, but not intended to be limiting, etching, applying a pad layer, depositing one or more photoresist layers, forming a spacer layer, etching, and the like. FIG. 15C shows an exemplary embodiment of a semiconductor device 1500 completing the steps with a silicon nitride layer 1585 and a field oxide layer 1580 .

The method of fabricating an EDMOS transistor may further include removing the silicon nitride layer 1770 , removing the sacrificial oxide layer 1780 and forming a thick gate oxide 1790 . In an embodiment of the present invention, the step of forming the thick gate oxide 1790 may include the step of oxidizing the thick gate oxide, applying a thick gate oxide photoresist layer, etching the thick gate oxide layer, and removing the thick gate oxide layer. gate photoresist layer, resulting in the formation of a thick gate oxide. 15D shows an exemplary embodiment of semiconductor device 1500 after the steps of removing sacrificial oxide layer 1525 and silicon nitride layer 1575 and forming thick gate oxide 1600 are completed.

The method of fabricating an EDMOS transistor may further include forming a thin gate oxide 1800 . FIG. 15E shows an exemplary embodiment of semiconductor device 1500 completed with the steps of forming thin gate oxide 1800 such that thin gate oxide 1590 is formed. In addition, a thin gate oxide layer, for example, acts as an insulating layer, combined with thick gate oxide 1600 to form a thick gate and thin gate layer 1605 .

The method of manufacturing an EDMOS transistor may further include forming a first conductive layer 1810 . In some embodiments of the present invention, the first conductive layer may include a first polysilicon layer. According to an embodiment of the present invention, the step of forming the first conductive layer may include the steps of depositing the first conductive layer, coating the first conductive photoresist layer, etching the first conductive layer, and removing the first conductive photoresist layer . FIG. 15F shows an exemplary embodiment of the semiconductor device 1500 after completing the steps of forming the first conductive layer 1800 such that the first conductive layer 1610 is formed.

The method of manufacturing an EDMOS transistor may further include depositing a high temperature oxide layer 1820 and forming a second conductive layer 1830 . In some embodiments of the present invention, the second conductive layer may include a polysilicon layer. According to an embodiment of the present invention, the step of forming the second conductive layer may include the steps of depositing the second conductive layer, coating the second conductive photoresist layer, etching the second conductive layer, and removing the second conductive photoresist layer . FIG. 15G shows an exemplary embodiment of a semiconductor device 1500 in which the above steps are performed to provide a high temperature oxide layer 1620 and a second conductive layer 1630 .

A method of fabricating an EDMOS transistor may include, optionally implanting N-doped regions 1840, optionally, implanting P-doped regions 1850, depositing a dielectric layer, such as a layer of tetraethyl silicate (TESO) 1860; according to the present invention In some embodiments of the invention, the dielectric layer or TESO layer is etched to form the gap layer 1870 . In some embodiments of the invention, the dielectric layer or TESO layer may be etched to form a spacer layer 1870 disposed at least partially along the edge of the first conductive layer. The method of manufacturing an EDMOS transistor may further include implanting an N ⁺ doped drain/source region 1880 and implanting a P ⁺ doped drain region 1900 . According to an embodiment of the present invention, the order of the above steps is not important. According to some embodiments of the present invention, the ion implantation step includes applying a photoresist layer to mask desired areas where ions are to be implanted, implanting individual ions, and removing the photoresist layer. These steps can be repeated until every region has been implanted. FIG. 15H shows a semiconductor having the above steps completed to provide N ^- doped regions 1545, P ⁺ -doped source regions 1550, N ⁺ -doped source regions 1560, N ⁺ -doped drain regions 1570, and a spacer (SPR) layer 1595. An exemplary embodiment of apparatus 1500 . SPR layer 1595 width from approx. to

One aspect of the present invention provides a method of manufacturing the semiconductor device of the present invention. Any fabrication method known to those of ordinary skill in the art having benefit of the present invention may be used to fabricate the semiconductor device of the present invention. In some embodiments, MOS devices can be formed using any of the methods described herein. In further embodiments, LDMOS devices may be formed using any of the methods described herein.

The multiple variations and other embodiments of the present invention proposed here will prompt those skilled in the art to think of the benefits presented by the foregoing description and its associated drawings. Therefore, the present invention is not limited Among the specific embodiments and modifications disclosed, other embodiments are also intended to be included within the protection scope of the appended claims. Furthermore, although the foregoing description and related drawings have certain exemplary elements and/or functions Embodiments are described in the context of combinations, but different combinations of elements and/or functions may be provided in alternative embodiments without departing from the scope of the appended claims, and in this regard, other than the foregoing expressly described Different combinations of elements and/or functions are also contemplated as possible in some of the appended claims; certain specific terms used in the present invention are used in general and descriptive terms only and not for the purpose of limitation Purpose.

Claims (21)

1. A semiconductor device comprising: a double dielectric layer having a thin dielectric layer adjacent to a thick dielectric layer, wherein the thin dielectric layer is a thin gate dielectric layer and the thick dielectric layer is a thick gate dielectric layer; an insulating layer disposed on the thick dielectric layer; a first conductive layer disposed along the thin dielectric layer, the first conductive layer having a stepped portion at least partially disposed along the insulating layer; a second conductive layer disposed over the first conductive layer and a portion of the insulating layer; and a conductive interlayer oxide layer disposed between the second conductive layer and the first conductive layer and the part of the insulating layer, the conductive interlayer oxide layer is a high temperature oxide layer; Wherein, there is an N-well under the double dielectric layer, and the N-well is configured in the junction region of the P-type well with the source region and the N-type well with the drain region; The second conductive layer comprises: (a) a first portion located on a portion of the first conductive layer that does not include a stepped portion; (b) a second portion disposed on the first conductive layer at the step (c) the third portion is not located above the first conductive layer, wherein the second portion is further positioned at a vertical distance measured from the substrate, and the vertical distance from the second portion to the substrate is greater than The vertical distance from the first part and the third part to the substrate is large. 2. The semiconductor device according to claim 1, wherein a thickness of the thick gate dielectric layer, the insulating layer, and the conductive interlayer oxide layer on the edge of the second conductive layer ranges from arrive between the ranges. 3. The semiconductor device according to claim 1, wherein the first conductive layer is a first polysilicon layer. 4. A high voltage metal oxide semiconductor (HVMOS) transistor comprising: a substrate; and A double gate oxide structure is disposed on the substrate and has a thick gate oxide layer; a thin gate oxide adjacent to the thick gate oxide; an insulating layer disposed on the thick gate oxide layer; and A two-layer conductive layer structure having: a first conductive layer disposed along the thin gate oxide layer, the first conductive layer having a stepped portion at least partially disposed along the insulating layer; a second conductive layer disposed over a portion of the first conductive layer and the insulating layer; and a conductive interlayer oxide layer disposed between the second conductive layer and the first conductive layer and the part of the insulating layer, the conductive interlayer oxide layer is a high temperature oxide layer; Wherein, there is also an N-well under the double gate oxide structure, and the N-well is configured in the junction region of the P-type well with the source region and the N-type well with the drain region; The second conductive layer comprises: (a) a first portion located on a portion of the first conductive layer that does not include a stepped portion; (b) a second portion disposed on the first conductive layer at the step (c) the third portion is not located above the first conductive layer, wherein the second portion is further positioned at a vertical distance measured from the substrate, and the vertical distance from the second portion to the substrate is greater than The vertical distance from the first part and the third part to the substrate is large. 5. The HVMOS transistor according to claim 4, wherein a P-type implantation region is disposed in the N-well. 6. The HVMOS transistor according to claim 5, wherein a P-type ion of the P-type implanted region is boron. 7. The HVMOS transistor of claim 5, wherein a doping concentration in the P-type implant region is in the range from 5×10 ¹² /cm ² to 1×10 ¹⁴ /cm ² . 8. The HVMOS transistor of claim 5, wherein a reduction in an effective channel length of the HVMOS transistor is in the range from 0.2 μm to 1 μm compared to without the A high voltage metal-oxide-semiconductor transistor with double gate oxide structure, the P-type implant, and the N-well. 9. The high voltage metal oxide semiconductor transistor according to claim 4, further comprising an N-type doped drain (NDD) region configured to extend from a drain region to below the two-layer conductive layer structure in this substrate. 10. The HVMOS transistor of claim 9, wherein a reduction in an effective channel length of the HVMOS transistor is in the range from 0.2 μm to 1 μm compared to without the A high voltage MOS transistor with double gate oxide structure and the N-type doped drain (NDD) region. 11. The HVMOS transistor of claim 9, wherein the HVMOS transistor does not have a type of saturation region. 12. The high voltage metal oxide semiconductor transistor according to claim 11, wherein when the high voltage metal oxide semiconductor transistor is close to a saturation, a slope of the drain-source current with respect to the drain-source voltage is a slope of the transition region between the linear region and the saturation region, the slope being at least 6 x 10 ^-5 amperes/micron-volts. 13. The HVMOS transistor of claim 4, further comprising an N-implant configured to extend across an upper portion of an N-type well and an N-doped drain region to the The substrate terminates at the bottom of the thick gate oxide. 14. The HVMOS transistor according to claim 13, wherein the N-implantation at the edge of the second conductive layer is aligned with the two-layer conductive layer structure at the conductive interlayer oxide layer and the insulating layer Terminate below. 15. The high voltage metal oxide semiconductor transistor according to claim 4, wherein the substrate comprises: a P body region; and A P-doped source region and an N-doped source region are respectively disposed in the P body region and define a contact region of a source region. 16. The high voltage metal oxide semiconductor transistor according to claim 4, further comprising: a P-type well having a P-doped source region and an N-doped source region defining a contact region of a source region; and An N-type well is adjacent to the P-type well, the N-type well having an N-doped drain region defining a contact region of a drain region. 17. The HVMOS transistor of claim 4, wherein the first conductive layer is a first polysilicon layer and the second conductive layer is a second polysilicon layer. 18. The HVMOS transistor of claim 17, wherein the two-layer conductive layer structure is configured to define a polysilicon-insulator-polysilicon (PIP) capacitor. 19. A method of manufacturing a semiconductor device, comprising: A semiconductor device is provided, which has a substrate, a deep N-type well, and an oxide layer; Implanting an N-type well and a P-type well; driving into the N-type well and the P-type well to form an N-well in the junction region of the N-type well and the P-type well; depositing a silicon nitride layer; form an oxide layer; removing the silicon nitride layer and the oxide layer; forming a thick gate oxide layer; forming a thin gate oxide layer, a portion of the thin gate oxide layer is disposed along the thick gate oxide layer; forming a first conductive layer disposed along at least a portion of the thin gate oxide layer including at least a portion of the portion of the thin gate oxide layer disposed along the thick gate oxide layer a part; depositing a high temperature oxide layer; and forming a second conductive layer, the high temperature oxide layer separating the second conductive layer from the first conductive layer and the second conductive layer from the thin gate oxide layer; Wherein, the step of forming the second conductive layer may include depositing the second conductive layer, coating the second conductive photoresist layer, etching the second conductive layer, and removing the second conductive photoresist layer. 20. The method of claim 19, further comprising: Implanting an N-doped region; Depositing a Tetraethyl Silicate (TESO) layer on the first conductive layer; etching the TEOS layer to form a gap layer; implant N ⁺ doped drain region; Implanting N ⁺ doped source regions; and Implanted P ⁺ doped drain region. 21. The method of claim 19, wherein the step of forming a thick gate oxide layer comprises: Oxidize a thick gate oxide layer; apply a thick layer of gate oxide photoresist; etching the thick gate oxide layer; and The thick gate oxide photoresist layer is removed.