CN104051431A - 具有射频屏蔽的系统、半导体器件及其制造方法 - Google Patents
具有射频屏蔽的系统、半导体器件及其制造方法 Download PDFInfo
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Abstract
根据本发明的一种实施方式,提供一种半导体器件,所述半导体器件具有前侧表面、后侧表面和垂直表面。半导体器件包括有源器件管芯,在前侧表面上具有电触点。覆盖金属屏蔽位于有源器件管芯的后侧表面和垂直表面。导电连接将覆盖金属屏蔽连接到前侧表面上选定的电触点。
Description
技术领域
本发明涉及半导体器件封装。特别地,涉及对裸芯片/圆片级封装进行的改进,以增强有源器件管芯设置到系统中时的射频屏蔽。
背景技术
电子工业持续依赖于半导体工艺的进步以实现在更紧凑的面积上的更强功能的器件。对于许多应用而言,实现更强功能的器件要求将许多电子器件集成进单一硅片中。由于在硅片的每一给定面积上的电子器件的数目上升,制造过程变得更加困难。
IC器件的封装在其最终性能中所起的作用越来越重要。在便携式电子设备中,如PDA、智能手机、平板电脑等,.随着微处理器电路、射频发送器/接收器电路的运行速度越来越快,处理需求的规模上升到千兆赫兹级别。因此,相应的电子设备受到更多的电磁干扰(EMI)的辐射或射频干扰(RFI)及其附随的影响。对于电子电路而言,由于从外源发射的电磁感应或电磁辐射,将会对其产生干扰影响。这种干扰可能中断、阻碍、或降低、限制所述电路的实际性能。例如,这种影响可以从数据的简单退化到数据的完全消失。
可以在高性能器件管芯中应用射频屏蔽。然而,这种屏蔽不能充分利用便携式设备的系统装配中的精确空间。
射频屏蔽存在着这样的需求,可以为有源器件管芯提供保护,且不该有源器件管芯的规格。
发明内容
本发明可应用于半导体器件的封装中,半导体器件进一步可运用于便携式电子设备。在裸芯片上覆盖射频屏蔽。所覆盖的射频屏蔽并不显著地增加器件管芯的整体尺寸。在器件管芯锡焊到系统印刷电路板上后,所植的射频屏蔽形成包围六面的连续射频屏蔽。
根据本发明的一种实施方式,提供一种从晶圆衬底制造硅器件的方法,所述晶圆衬底具有前侧表面和后侧表面。该方法包括:将晶圆衬底的后侧表面附着到划片膜上,所述晶圆衬底的前侧表面上具有数个有源器件;对晶圆衬底进行划片,并拉伸划片膜,将数个有源器件分离为分开的器件,每个分开的器件具有前侧表面;将粘性膜施加到分开的器件上,粘性膜保护每个分开的器件的前侧表面并保持其他表面暴露;去除划片膜,暴露每个分开器件的后侧表面;将分开的器件保持于镀覆溶液直至分开的器件的暴露表面上被沉积预定厚度的金属。
根据本发明另一实施方式,提供一种半导体器件,所述半导体器件具有前侧表面、后侧表面和垂直表面,其特征在于,半导体器件包括:有源器件管芯,在前侧表面上具有电触点;覆盖金属屏蔽,位于有源器件管芯的后侧表面和垂直表面;以及导电连接,将覆盖金属屏蔽连接到前侧表面上选定的电触点。
根据本发明的另一实施方式,提供一种具有射频屏蔽的系统,该系统包括射频屏蔽的半导体器件,其包括:有源器件管芯,在前侧表面上具有凸点触点;覆盖金属屏蔽,位于有源器件管芯的后侧表面和垂直表面;以及导电连接,将覆盖金属屏蔽连接到前侧表面上选定的凸点触点,其中选定的凸点触点为接地连接。该系统进一步包括印刷电路板(PCB)基底,包括在绝缘基底上的接地连接。其中射频屏蔽的半导体器件的接地连接耦合到PCB的接地连接,所述连接形成为包围整个射频屏蔽半导体器件的射频屏蔽。
根据本发明的一种实施方式,提供一种从晶圆衬底制造硅器件的方法,所述晶圆衬底具有前侧表面和后侧表面。该方法包括:将晶圆衬底的后侧表面附着到划片膜上,所述晶圆衬底的前侧表面上具有数个有源器件;对晶圆衬底进行划片,并拉伸划片膜,将数个有源器件分离为分开的器件,每个分开的器件具有前侧表面;将粘性膜施加到分开的器件上,粘性膜保护每个分开的器件的前侧表面并保持其他表面暴露;去除划片膜,暴露每个分开器件的后侧表面;以及向分开的器件的暴露表面上溅射金属直至金属沉积至预定厚度。
以上的发明内容并不代表本发明的下述的各实施方式或其方面。本发明的其他方面和示例的实施方式如以下附图及其说明所述。
附图说明
以下将结合附图对于本发明的实施方式进行进一步详细地描述,其中:
图1A-1C是一种金属屏蔽系统的示例;
图2是一种晶圆级封装器件的金属屏蔽系统的示例;
图3A-3I为本发明一种实施方式的射频屏蔽有源器件管芯的流程;
图4A-4C示出了将有源器件管芯的Vss(地)延伸连接到划片槽的示例,从而在形成的有源器件管芯上,可以通过边缘接触将Vss与射频屏蔽相连;
图5A-5B为本发明一种实施方式的有源器件,其中延伸的Vss连接与印刷电路板的接地平面相连;以及
图6是本发明一种实施方式的金属屏蔽流程的流程图。
以下将通过附图中示例的说明详细阐述本发明的细节,本发明亦可适用各种变通与修饰。应当理解的是,本发明不局限于所描述的特定实施方式。对于所属领域的技术人员而言,在不背离本发明的权利要求的范畴内可以作出多种具体变化,均应包含在本发明的范围内。
具体实施方式
本发明的实施例有利于增强裸芯片/芯片级封装器件在被设置到印刷电路板上时的射频屏蔽。在裸芯片上覆有射频屏蔽。所覆的射频屏蔽并不实际性地增加器件管芯的整体尺寸。在器件管芯锡焊到系统印刷电路板上后,所覆的射频屏蔽形成包围六面的连续射频屏蔽。这种工艺可以集成到既有的后道封装中。
在形成便携式电子系统时,提供充足的射频屏蔽一直是挑战,射频屏蔽不能占用太多的空间。图1A到1C所示的是在一种射频屏蔽封装110中的示例性的器件管芯130的包装。通过在角部的连接125和选定的球焊,器件管芯130的接电连接与接地连接可以被接到相应的系统板上的接电与接地。在其他例子中,图2示出了一种器件管芯230及其球焊220。这种器件可以被贴装到系统板上。具有球焊210的射频屏蔽205可以装配到器件管芯230上。射频屏蔽205被贴装到系统板上的接地连接上。然而,在上述两种示例中,射频屏蔽将会增加系统板上为相应的器件管芯130、230所需要的空间大小。
根据一种示例的实施方式,半导体晶圆被贴合到由制造工具托置的弹性膜上。晶圆被切割为单独的器件管芯,而弹性膜可以被制造工具拉伸,从而在器件管芯之间形成更大的分离空间。器件管芯的有源侧(前侧表面)上被应用热塑带层叠;利用紫外照射处理该层叠以保证器件管芯的附着。器件管芯被贴装到热塑带上,而从弹性膜上拆下。器件管芯被浸入水成化学镀覆溶液中,从而暴露于其中的器件管芯的侧面上被覆镀上金属。在一种示例性的流程中,在所述化学镀覆之前,器件管芯被通过适当的刻蚀溶液进行预清洁,并利用去离子水进行漂洗以去除任何可能对于镀覆的附着力产生负面影响的污染。从而可以获得并不实际性地增加器件管芯的整体尺寸的射频屏蔽。对于所述射频屏蔽了的管芯的后续工艺将其装载到卷带中,以供终端用户使用。
关于化学镀覆的背景可以在IBM研发部的Eugene J.O′Sullivan的名为“Electroless Deposition”,IBM T.J,Watson Research Center,YorktownHeights,NY,2011年2月的文章中参考。
在另一示例性的实施方式的工艺中,器件管芯的暴露侧面可以被浸入一种凝胶剂或胶质剂中。利用这种凝胶剂或胶质剂,可以以化学镀覆工艺镀覆适当的金属。这种金胶剂工艺在Lynne M.Svedberg等人的美国授权专利6194032B2(2001年2月27日授权)、名为“Selective SubstrateMetallization”中呈现,其作为引用结合在本文中。
请参考图3A到3D。根据一种示例的实施方式,提供一种工具装置310,弹性固化带300贴着在工具装置310上。在弹性固化带上置有半导体晶圆320,其包括接触区360。接触区360可以是铜座、锡块或球焊等。晶圆320被分割为器件管芯。为在器件管芯325之间形成更大的分离空间,工具装置310可以拉伸弹性固化带330。在器件管芯325的上表面上(如具有电接触有源器件区的区域),层叠有弹性热塑带。器件管芯325被从固化带330上拆下。请参考图3E到3G,贴着到热塑带335上的器件管芯325被浸入银340的水成溶液中。也可以使用其他合适的水成金属溶液。例如,可以使用其他如金、铜、铝、锌、锡、镍等金属,
然而本申请并不以此为限。
在一种利用化学镀覆镍的工艺中,镀层的百度同样影响包覆的电阻:具有2微米到10微米范围内厚度的镀层可以用作抵挡侵蚀的钝化层,在5微米到10微米范围内的可以提供对于轻微机械损伤的阻挡。可以利用厚度在10微米到25微米之间的镀层来提供更高级别的保护,厚度值在25微米到50微米之间及超过50微米的则可以分别提供最高级别的保护。表1所示的是镀覆到器件管芯以获得射频屏蔽的部分元素。越厚的镀覆(如.镍)越能够提供在装配操作时的划伤保护特性。
在可选的其他实施方式中,如果使用了凝胶剂/胶质剂工艺,厚度范围的低值是由掺杂了特定的金属屏蔽的填充材料的量决定的。当然,较厚的凝胶剂/胶质剂能够增加器件管芯的机械保护。
具有镀覆层345的器件管芯325被拆下,其所贴着的热塑带335经过处理并发生热释放。镀覆好的器件管芯325被贴着到装载于另一工具装置350的载带355上。利用真空工具20,具有镀覆好的射频屏蔽345的器件管芯325被卷入卷带中提供给终端用户。请参考图3I,成品的管芯325由镀覆好的射频屏蔽345将其下侧面和竖面包围。当利用球焊360进行贴装时,该屏蔽可以耦合到系统板的接电或接地平面上。
请参考图4A-4D。根据本发明的一个实施方式,形成阵列400的器件管芯在其下侧包括延伸到划片槽的连接点420和425。单个器件管芯410的放大图(器件边界以虚线标识)示出了连接点420和425的更近的视图。请参考图4C,连接点420、425设置于划片槽区域。划片槽连接区域420显示于由射频屏蔽440屏蔽了的器件管芯430上。选定的球焊435耦合到划片槽连接区域420、425,划片槽连接区域420、425耦合到射频屏蔽440。晶圆划片之后,如图4C所示,划片槽连接区域420、425暴露于侧墙上。金属屏蔽440连接到该等区域420、425。通过再分布层(Redistribution Layer,RDL)422,所述区域420、425被连接到引脚(或锡球、球焊、焊垫等),其被定义为地。RDL为芯片或衬底上的额外的金属层,其使得集成电路的I/O、电源和地等垫处引到其他位置423等。在本例中,与连接区域420、425一起,所述其他位置423位于有源器件的边缘位置(见虚线所示)。例如,RDL422的四个区域由图4B中的箭头所指出。连接区域420、425在预定的位置与RDL422之间有电性连接。
请参考图5A,根据一种示例的实施方式,器件500被贴装到系统板510上。器件管芯530由所镀覆的射频屏蔽540所包围。选定的球焊550、550′耦合到屏蔽连接545、545′。器件500通过球焊550、550′被焊接到PCB的焊垫555、555′上。图5B为器件管芯530被接地屏蔽560所包围的代表图像。
请参考图6,根据本发明一种实施方式的流程,步骤100,有源器件的晶圆片被贴着到弹性固化带。步骤102,贴着后的晶圆被划开形成单独的管芯,弹性固化带被拉伸。步骤120,将热塑带叠装到有源器件一侧,这将保护器件免受后续处理的损伤。步骤122,分离后的器件管芯被移转到热塑带时被从弹性固化带上拆下。步骤140,器件的暴露表面被利用室温镀覆工艺进行镀覆。可以使用银进行镀覆,但也可以使用其他金属。步骤150,贴着有器件管芯的热塑带被处理;步骤160,实施附着释放。步骤170,热塑带上的已镀覆的器件管芯被置于另外的载带上。步骤180,已镀覆的器件管芯被真空装置一个一个地转移并卷绕到卷带上。步骤190,将装有已镀覆的器件管芯的卷带送至终端用户。
除了将器件管芯的暴露一侧浸入到水成镀溶液中之外,还可以利用溅射沉积工艺将金属施加到器件管芯的暴露表面上。溅射沉积是一种利用溅射来沉积薄膜的方法,其涉及将靶材上的材料蚀转到器件管芯上。在某些实施方式的应用中,溅射过程可能涉及将合适的材料进行沉积以进行射频和电磁干扰屏蔽、以及其后的保护性塑料薄层沉积。对于裸芯片/芯片级封装器件而言,如果塑料薄层的厚度足够的话,其可以起到保护作用,以减小在后续处理和装配到电子产品的PCB子系统时剥落的风险。在一种示例的实施方式中,为射频屏蔽的效果,0.1微米到大约1微米的范围厚度就足够。为机械保护的效果,大于3微米的厚度为合适。
对于所属领域的技术人员而言,在不背离本发明的权利要求的范畴内可以作出多种具体变化。
Claims (20)
1.一种从晶圆衬底制造硅器件的方法,所述晶圆衬底具有前侧表面和后侧表面,所述硅器件具有射频屏蔽,其特征在于:所述方法包括:
将晶圆衬底的后侧表面附着到划片膜上,所述晶圆衬底的前侧表面上具有数个有源器件;
对晶圆衬底进行划片,并拉伸划片膜,以将数个有源器件分离为数个分开的器件,每个分开的器件具有前侧表面;
将粘性膜施加到分开的器件上,粘性膜保护每个分开的器件的前侧表面并保持其他表面暴露;
去除划片膜,暴露每个分开的器件的后侧表面;
将分开的器件浸入镀覆溶液;以及
将分开的器件保持于镀覆溶液中直至每个分开的器件的暴露表面上被沉积具有厚度的金属。
2.如权利要求1所述的方法,其特征在于:浸入分开的器件进一步包括:
预清洁每个分开的器件的暴露表面。
3.如权利要求1所述的方法,其特征在于:在浸入之前,分开的器件的暴露表面覆有具有厚度的凝胶剂/胶质剂材料,凝胶剂/胶质剂材料亲镀覆溶液,从而在凝胶剂/胶质剂材料上沉积金属。
4.如权利要求1所述的方法,其特征在于:所沉积的金属是从以下组中选择的:银(Ag)、金(Au)、铜(Cu)、铝(A1)、锌(Zn)、锡(Sn)及镍(Ni)。
5.如权利要求4所述的方法,其特征在于:沉积金属的厚度不小于0.05微米。
6.如权利要求5所述的方法,其特征在于:沉积金属的厚度在0.05微米至125微米的范围内。
7.如权利要求5所述的方法,其特征在于:沉积金属的厚度在0.05微米至10微米的范围内。
8.如权利要求2所述的方法,其特征在于,进一步包括:
在粘性膜上附着附加的带;以及
将分开的器件转移到卷带上。
9.一种半导体器件,所述半导体器件具有前侧表面、后侧表面和垂直表面,其特征在于,所述半导体器件包括:
有源器件管芯,在前侧表面上具有电触点;
镀覆金属屏蔽,位于有源器件管芯的后侧表面和垂直表面上;以及
导电连接,将镀覆金属屏蔽连接到前侧表面上选定的电触点。
10.如权利要求9所述的半导体器件,其特征在于,导电连接包括:
再分布层,将前侧表面上的电触点连接到有源器件的预先定义的边缘位置的触点;以及
选定的边缘位置的触点,耦合到划片连接区域。
11.如权利要求9所述的半导体器件,其特征在于:选定的电触点为接地连接。
12.如权利要求10所述的半导体器件,其特征在于:划片连接区域耦合到地。
13.一种具有射频屏蔽的系统,其特征在于,该系统包括:
射频屏蔽的半导体器件,包括:
有源器件管芯,在前侧表面上具有凸点触点;
镀覆金属屏蔽,位于有源器件管芯的后侧表面和垂直表面上;以及
导电连接,将镀覆金属屏蔽连接到前侧表面上选定的凸点触点,其中选定的凸点触点为接地连接;
印刷电路板(PCB)基板,包括在绝缘基板上的接地连接;
其中射频屏蔽的半导体器件的接地连接耦合到印刷电路板的接地连接,所述射频屏蔽的半导体器件的接地连接形成为包围整个射频屏蔽半导体器件的射频屏蔽。
14.如权利要求13所述的系统,其特征在于:所述导电连接由施加到有源器件管芯的前侧表面的再分布层提供。
15.一种从晶圆衬底制造硅器件的方法,所述晶圆衬底具有前侧表面和后侧表面,所述硅器件具有射频屏蔽,其特征在于:所述方法包括:
将晶圆衬底的后侧表面附着到划片膜上,所述晶圆衬底的前侧表面上具有数个有源器件;
对晶圆衬底进行划片,并拉伸划片膜,以将数个有源器件分离为数个分开的器件,每个分开的器件具有前侧表面;
将粘性膜施加到分开的器件上,粘性膜保护每个分开的器件的前侧表面并保持其他表面暴露;
去除划片膜,暴露每个分开的器件的后侧表面;以及
向分开的器件的暴露表面上溅射金属直至金属沉积至预定厚度。
16.如权利要求15所述的方法,其特征在于,进一步包括:向溅射的金属上溅射塑料。
17.如权利要求15所述的方法,其特征在于:所溅射的金属是从以下组中选择的:银(Ag)、金(Au)、铜(Cu)、铝(A1)、锌(Zn)、锡(Sn)及镍(Ni)。
18.如权利要求17所述的方法,其特征在于:溅射金属的厚度不小于0.05微米。
19.如权利要求18所述的方法,其特征在于:溅射金属的厚度在0.05微米至50微米的范围内。
20.如权利要求16所述的方法,其特征在于:溅射塑料的厚度不小于3微米。
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