CN104037090B - 氧化物薄膜晶体管结构制作方法及氧化物薄膜晶体管结构 - Google Patents
氧化物薄膜晶体管结构制作方法及氧化物薄膜晶体管结构 Download PDFInfo
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- 238000000034 method Methods 0.000 claims abstract description 60
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 10
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 5
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Abstract
本发明提供一种氧化物薄膜晶体管结构的制作方法及氧化物薄膜晶体管结构。该氧化物薄膜晶体管结构的制作方法包括如下步骤:步骤1、提供载体;步骤2、形成氧化物半导体层(4);步骤3、形成蚀刻阻挡层(5);步骤4、在蚀刻阻挡层(5)上形成两个通孔(51、53),露出部分氧化物半导体层(4);步骤5、移除露置于两个通孔(51、53)内的氧化物半导体层(4)的表层,形成两个分别与该两个通孔(51、53)连通的凹槽(41、43);步骤6、于蚀刻阻挡层(5)上形成源极(61)与漏极(63),且该源极(61)填充一个通孔(51)及与其连通的凹槽(41),该漏极(63)填充另一个通孔(53)及与其连通的凹槽(43);步骤7,进行后制程。
Description
技术领域
本发明涉及显示技术领域,尤其涉及一种氧化物薄膜晶体管结构的制作方法及氧化物薄膜晶体管结构。
背景技术
薄膜晶体管(TFT)在电子装置中被广泛的作为开关装置和驱动装置使用。具体地,因为薄膜晶体管可形成在玻璃基板或塑料基板上,所以它们通常用在诸如液晶显示装置(LCD)、有机发光显示装置(OLED)等平板显
示装置领域。
氧化物半导体由于具有较高的电子迁移率(氧化物半导体的电子迁移率>10cm2/Vs,非晶硅(a-Si)的电子迁移率仅0.5~0.8cm2/Vs),而且相比低温多晶硅(LTPS),氧化物半导体制程简单,与非晶硅制程相容性较高,可以应用于液晶显示装置、有机发光显示装置、柔性显示(Flexible)等领域,且与高世代生产线兼容,可应用于大中小尺寸显示,具有良好的应用发展前景,为当前业界研究热门。
氧化物半导体在具有较高的电子迁移率、制程简单等优点的同时,目前也存在着稳定性差,受温、湿度变化影响大,氧化物薄膜晶体管电性随时间漂移,而且对制程条件,如成膜速率、制程气氛、制程温度、湿度控制等要求较高的缺点。此外,氧化物薄膜晶体管除了对氧化物半导体层本身,对绝缘层、氧化物半导体层与绝缘层的接触界面、氧化物半导体层与金属层接触界面都有较高的要求。
请参阅图1,为一种现有的底栅阻挡型氧化物薄膜晶体管结构的剖面示意图。该氧化物薄膜晶体管结构的制作方法主要包括:步骤1、提供一基板(100);步骤2、于基板(100)上形成栅极(200);步骤3、于基板(100)与栅极(200)上形成栅极绝缘层(300),使所述栅极绝缘层(300)覆盖所 述栅极(200);步骤4、于栅极绝缘层(300)上形成氧化物半导体层(400);步骤5、于氧化物半导体层(400)上形成蚀刻阻挡层(500);步骤6、在蚀刻阻挡层(500)上通过蚀刻分别形成两个通孔(510、530),露出氧化物半导体层(400);步骤7、于蚀刻阻挡层(500)上形成源极(610)与漏极(630),所述源极(610)填充一个通孔(510),从而与氧化物半导体层(400)连接,所述漏极(630)填充另一个通孔(530),从而与氧化物半导体层(400)连接;步骤8、于源极(610)与漏极(630)上形成保护层(700),以覆盖源极(610)与漏极(630)。
在上述氧化物薄膜晶体管结构的制作方法中,步骤5中蚀刻阻挡层(500)一般采用由TEOS+O2或者SiH4+N2O化学气相沉积SiOx膜层形成,但是在蚀刻阻挡层(500)成膜过程中等离子体会影响氧化物半导体层(400)的表面特性,例如SiH4+N2O中含氢,与氧化物半导体层(400)的氧结合,使得氧缺陷增加,导致阈值电压Vth偏负,而TEOS+O2中的氧会导致氧化物半导体层(400)中的氧缺陷减少,使沟道的导电性降低。因此,在源极(610)与漏极(630)成膜后,源极(610)与漏极(630)与受到破坏的氧化物半导体层(400)表面接触,最终影响该氧化物薄膜晶体管的电性。请参阅图2,为该氧化物薄膜晶体管结构的制作方法制得的现有氧化物薄膜晶体管结构的电性曲线图,由图可知,当漏极电压Vd=10V时,阈值电压Vth=-5V,亚阈值摆幅S.S=0.45,该氧化物薄膜晶体管的电性较差。
发明内容
本发明的目的在于提供一种氧化物薄膜晶体管结构的制作方法,通过该方法能够使源极和漏极与未受到破坏、并保持初始特性的氧化物半导体层接触,使得通过该方法制得的氧化物薄膜晶体管具有更稳定、更优异的电性。
本发明的另一目的在于提供一种氧化物薄膜晶体管结构,其具有良好的电性,能够提升氧化物薄膜晶体管的品质。
为实现上述目的,本发明首先提供一种氧化物薄膜晶体管结构的制作方法,包括如下步骤:
步骤1、提供载体;
步骤2、于载体上形成氧化物半导体层;
步骤3、于氧化物半导体层上形成蚀刻阻挡层;
步骤4、在蚀刻阻挡层上形成两个通孔,露出部分氧化物半导体层;
步骤5、移除露置于两个通孔内的氧化物半导体层的表层,形成两个分别与该两个通孔连通的凹槽;
步骤6、于蚀刻阻挡层上形成源极与漏极,且该源极填充一个通孔及与其连通的凹槽,从而与氧化物半导体层连接,该漏极填充另一个通孔及与其连通的凹槽,从而与氧化物半导体层连接。
所述氧化物薄膜晶体管结构的制作方法,通过化学气相沉积于氧化物半导体层上形成蚀刻阻挡层;通过干蚀刻在蚀刻阻挡层上形成两个通孔;通过溅镀于蚀刻阻挡层上形成源极与漏极;通过干蚀刻或者湿蚀刻移除露置于两个通孔内的氧化物半导体层的表层。
所述蚀刻阻挡层采用由TEOS+O2或SiH4+N2O化学气相沉积SiOx膜层。
所述载体包括基板、形成于基板上的栅极及形成于基板与栅极上的栅极绝缘层。
所述氧化物薄膜晶体管结构的制作方法还包括步骤7,进行后制程,该后制程包括于源极与漏极上形成保护层,以覆盖源极与漏极。
所述载体为一基板。
所述氧化物薄膜晶体管结构的制作方法还包括步骤7,进行后制程,该后制程包括于源极与漏极上形成栅极绝缘层,并于该栅极绝缘层上溅镀栅极。
本发明还提供一种氧化物薄膜晶体管结构,包括:氧化物半导体层、位于氧化物半导体层上的蚀刻阻挡层、及位于蚀刻阻挡层上的源极与漏极,所述蚀刻阻挡层设有两个通孔,所述氧化物半导体层分别对应该两个通孔设置两个凹槽,且该两个凹槽分别与该两个通孔连通,该源极填充一个通孔及与其连通的凹槽,从而与氧化物半导体层连接,该漏极填充另一个通孔及与其连通的凹槽,从而与氧化物半导体层连接。
所述氧化物薄膜晶体管结构还包括基板、位于基板上的栅极、位于该基板与栅极上的栅极绝缘层及位于所述源极与漏极上的保护层;所述氧化物半导体层设置于所述栅极绝缘层上。
所述氧化物薄膜晶体管结构还包括一基板、位于源极与漏极上的栅极绝缘层及位于该栅极绝缘层上的栅极;所述氧化物半导体层设置于所述基板上。
本发明的有益效果:本发明提供的氧化物薄膜晶体管结构的制作方法,通过对露置于蚀刻阻挡层两个通孔内的氧化物半导体层的表层进行干蚀刻或者湿蚀刻,去除了因蚀刻阻挡层成膜时受等离子体中O及H的破坏而导致特性发生变化的氧化物半导体层的表层,使得源极和漏极与未受到破坏、并保持初始特性的氧化物半导体层接触,所以通过该方法制得的氧化物薄膜晶体管具有更稳定、更优异的电性,且该方法简便易操作。本发明提供的氧化物薄膜晶体管结构,通过在氧化物半导体层设置与蚀刻阻挡层两通孔对应的两个凹槽,且该两个凹槽分别与该两个通孔连通,使得源极和漏极与保持初始特性的氧化物半导体层接触,从而能够获取良好的电性并提升氧化物薄膜晶体管的品质。
附图说明
为了能更进一步了解本发明的特征以及技术内容,请参阅以下有关本发明的详细说明与附图,然而附图仅提供参考与说明用,并非用来对本发明加以限制。
附图中,
图1为一种现有的氧化物薄膜晶体管结构的剖面示意图;
图2为现有氧化物薄膜晶体管的电性曲线图;
图3为本发明氧化物薄膜晶体管结构的制作方法的第一实施例的流程图;
图4为本发明氧化物薄膜晶体管结构的制作方法的第一实施例的步骤4的示意图;
图5为本发明氧化物薄膜晶体管结构的制作方法的第一实施例的步骤5的示意图;
图6为本发明氧化物薄膜晶体管结构的制作方法的第一实施例的步骤6的示意图;
图7为本发明氧化物薄膜晶体管结构的制作方法的第一实施例的步骤7的示意图暨本发明氧化物薄膜晶体管结构的第一实施例的剖面示意图;
图8为本发明氧化物薄膜晶体管结构的电性曲线图;
图9为本发明氧化物薄膜晶体管结构的制作方法的第二实施例的流程图;
图10为本发明氧化物薄膜晶体管结构的制作方法的第二实施例的步骤3的示意图;
图11为本发明氧化物薄膜晶体管结构的制作方法的第二实施例的步骤4的示意图;
图12为本发明氧化物薄膜晶体管结构的制作方法的第二实施例的步骤5的示意图;
图13为本发明氧化物薄膜晶体管结构的制作方法的第二实施例的步骤6的示意图;
图14为本发明氧化物薄膜晶体管结构的制作方法的第二实施例的步骤7的示意图暨本发明氧化物薄膜晶体管结构的第二实施例的剖面示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果,以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图3至图7,为本发明氧化物薄膜晶体管结构的制作方法的第一实施例,该第一实施例适用于制作底栅阻挡型的薄膜晶体管结构,其包括如下步骤:
步骤1、提供载体。
在该第一实施例中,所述载体包括:基板1、形成于基板1上的栅极2及形成于基板1与栅极2上的栅极绝缘层3。所述基板1为透明基板,优选的,所述基板1为玻璃基板。
步骤2、于载体上形成氧化物半导体层4。
优选的,所述氧化物半导体层4的材料为铟镓锌氧化物(IGZO)。
步骤3、于氧化物半导体层4上形成蚀刻阻挡层5。
所述蚀刻阻挡层5通过化学气相沉积于氧化物半导体层4上,进一步的,所述蚀刻阻挡层5采用由TEOS+O2或SiH4+N2O化学气相沉积SiOx膜层形成于所述氧化物半导体层4上。
步骤4、在蚀刻阻挡层5上形成两个通孔51、53,露出部分氧化物半导体层4。
在该步骤4中,通过干蚀刻的方式在蚀刻阻挡层5上形成两个通孔51、53。
步骤5、移除露置于两个通孔51、53内的氧化物半导体层4的表层,形成两个分别与该两个通孔51、53连通的凹槽41、43。
在该步骤5中,通过干蚀刻或者湿蚀刻的方式移除露置于两个通孔51、53内的氧化物半导体层4的表层。
由于所述氧化物半导体层4的表层在蚀刻阻挡层5形成的过程中,受等离子体中O及H的破坏,导致氧化物半导体层4的表层的特性发生了变化,而经该步骤5移除了露置于两个通孔51、53内的已受到破坏且特性发生变化的氧化物半导体层4的的表层。所述两个分别与该两个通孔51、53连通的凹槽41、43内新形成的氧化物半导体层4的的表层则未受破坏并保持氧化物半导体层4的初始特性。
步骤6、于蚀刻阻挡层5上形成源极61与漏极63,且该源极61填充一个通孔51及与其连通的凹槽41,从而与氧化物半导体层4连接,该漏极63填充另一个通孔53及与其连通的凹槽43,从而与氧化物半导体层4连接。
具体的,所述源极61与漏极63通过溅镀的方式形成于蚀刻阻挡层5上。
由于所述凹槽41、43内的氧化物半导体层4的表层未受破坏并保持氧化物半导体层4的初始特性,所述源极61与漏极63分别与保持初始特性的氧化物半导体层4连接。
步骤7、进行后制程,于源极61与漏极63上形成保护层7,以覆盖源极61与漏极63。
请参阅图8,为通过上述氧化物薄膜晶体管结构的制作方法制得的薄膜晶体管结构的电性曲线图。由图可知,当漏极电压Vd=10V时,阈值电压Vth=0.2V,亚阈值摆幅S.S=0.13,阈值电压Vth在0V附近,亚阈值摆幅S.S 变小,通过本发明氧化物薄膜晶体管结构的制作方法制得的薄膜晶体管结构的电性得到明显改善。
请参阅图9至图14,为本发明氧化物薄膜晶体管结构的制作方法的第二实施例,该第二实施例适用于制作顶栅阻挡型的薄膜晶体管结构。该第二实施例与上述第一实施例的区别在于:
步骤1:提供载体。
在该第二实施例中,所述载体为1基板1’。所述基板1’为透明基板,优选的,所述基板1’为玻璃基板。
步骤7:进行后制程,于源极61与漏极63上形成栅极绝缘层3’,并于该栅极绝缘层3’上溅镀栅极2’。
其它步骤2-6与上述第一实施例相同,此处不再赘述。
在该氧化物薄膜晶体管结构的制作方法的基础上,本发明还提供一种氧化物薄膜晶体管结构,可用于LCD显示装置与OLED显示装置。
请参阅图7,为本发明氧化物薄膜晶体管结构第一实施例的剖面示意图,在该第一实施例中,所述氧化物薄膜晶体管结构为底栅阻挡型,包括:氧化物半导体层4、位于氧化物半导体层4上的蚀刻阻挡层5、及位于蚀刻阻挡层5上的源极61与漏极63,所述蚀刻阻挡层5设有两个通孔51、53,所述氧化物半导体层4分别对应该两个通孔51、53设置两个凹槽41、43,且该两个凹槽41、43分别与该两个通孔51、53连通,该源极61填充一个通孔51及与其连通的凹槽41,从而与氧化物半导体层4连接,该漏极63填充另一个通孔53及与其连通的凹槽43,从而与氧化物半导体层4连接;还包括基板1、位于基板1上的栅极2、位于该基板1与栅极2上的栅极绝缘层3及位于所述源极61与漏极63上的保护层7;所述氧化物半导体层4设置于所述栅极绝缘层3上。值得一提的是,所述两个凹槽41、43使得源极61和漏极63与保持初始特性的氧化物半导体层4接触,能够获取良好的电性。
请参阅图14,为本发明氧化物薄膜晶体管结构第二实施例的剖面示意图,在该第二实施例中,所述氧化物薄膜晶体管结构为顶栅阻挡型,其与上述第一实施例的区别在于,还包括一基板1’、位于源极61与漏极63上的栅极绝缘层3’及位于该栅极绝缘层3’上的栅极2’;所述氧化物半导体层4设置于所述基板1’上。其它结构与上述第一实施例相同,此处不再赘述。
综上所述,本发明的氧化物薄膜晶体管结构的制作方法,通过对露置于蚀刻阻挡层两个通孔内的氧化物半导体层的表层进行干蚀刻或者湿蚀刻,去除了因蚀刻阻挡层成膜时受等离子体中O及H的破坏而导致特性发生变化的氧化物半导体层的表层,使得源极和漏极与未受到破坏、并保持初始特性的氧化物半导体层接触,所以通过该方法制得的氧化物薄膜晶体管具有更稳定、更优异的电性,且该方法简便易操作。本发明提供的氧化物薄膜晶体管结构,通过在氧化物半导体层设置与蚀刻阻挡层两通孔对应的两个凹槽,且该两个凹槽分别与该两个通孔连通,使得源极和漏极与保持初始特性的氧化物半导体层接触,从而能够获取良好的电性并提升氧化物薄膜晶体管的品质。
以上所述,对于本领域的普通技术人员来说,可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形,而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。
Claims (10)
1.一种氧化物薄膜晶体管结构的制作方法,其特征在于,包括如下步骤:
步骤1、提供载体;
步骤2、于载体上形成氧化物半导体层(4);
步骤3、于氧化物半导体层(4)上形成蚀刻阻挡层(5);
步骤4、在蚀刻阻挡层(5)上形成两个通孔(51、53),露出部分氧化物半导体层(4);
步骤5、移除露置于两个通孔(51、53)内的氧化物半导体层(4)的表层,形成两个分别与该两个通孔(51、53)连通的凹槽(41、43);
步骤6、于蚀刻阻挡层(5)上形成源极(61)与漏极(63),且该源极(61)填充一个通孔(51)及与其连通的凹槽(41),从而与氧化物半导体层(4)连接,该漏极(63)填充另一个通孔(53)及与其连通的凹槽(43),从而与氧化物半导体层(4)连接。
2.如权利要求1所述的氧化物薄膜晶体管结构的制作方法,其特征在于,通过化学气相沉积于氧化物半导体层(4)上形成蚀刻阻挡层(5);通过干蚀刻在蚀刻阻挡层(5)上形成两个通孔(51、53);通过干蚀刻或者湿蚀刻移除露置于两个通孔(51、53)内的氧化物半导体层(4)的表层;通过溅镀于蚀刻阻挡层(5)上形成源极(61)与漏极(63)。
3.如权利要求2所述的氧化物薄膜晶体管结构的制作方法,其特征在于,所述蚀刻阻挡层(5)采用由TEOS+O2或SiH4+N2O化学气相沉积SiOx膜层。
4.如权利要求1所述的氧化物薄膜晶体管结构的制作方法,其特征在于,所述载体包括基板(1)、形成于基板(1)上的栅极(2)及形成于基板(1)与栅极(2)上的栅极绝缘层(3)。
5.如权利要求4所述的氧化物薄膜晶体管结构的制作方法,其特征在于,还包括步骤7,进行后制程,该后制程包括于源极(61)与漏极(63)上形成保护层(7),以覆盖源极(61)与漏极(63)。
6.如权利要求1所述的氧化物薄膜晶体管结构的制作方法,其特征在于,所述载体为一基板(1’)。
7.如权利要求6所述的氧化物薄膜晶体管结构的制作方法,其特征在于,还包括步骤7,进行后制程,该后制程包括于源极(61)与漏极(63)上形成栅极绝缘层(3’),并于该栅极绝缘层(3’)上溅镀栅极(2’)。
8.一种氧化物薄膜晶体管结构,包括:氧化物半导体层(4)、位于氧化物半导体层(4)上的蚀刻阻挡层(5)、及位于蚀刻阻挡层(5)上的源极(61)与漏极(63),所述蚀刻阻挡层(5)设有两个通孔(51、53),其特征在于,所述氧化物半导体层(4)分别对应该两个通孔(51、53)设置两个凹槽(41、43),且该两个凹槽(41、43)分别与该两个通孔(51、53)连通,该源极(61)填充一个通孔(51)及与其连通的凹槽(41),从而与氧化物半导体层(4)连接,该漏极(63)填充另一个通孔(53)及与其连通的凹槽(43),从而与氧化物半导体层(4)连接。
9.如权利要求8所述的氧化物薄膜晶体管结构,其特征在于,还包括基板(1)、位于基板(1)上的栅极(2)、位于该基板(1)与栅极(2)上的栅极绝缘层(3)及位于所述源极(61)与漏极(63)上的保护层(7);所述氧化物半导体层(4)设置于所述栅极绝缘层(3)上。
10.如权利要求8所述的氧化物薄膜晶体管结构,其特征在于,还包括一基板(1’)、位于源极(61)与漏极(63)上的栅极绝缘层(3’)及位于该栅极绝缘层(3’)上的栅极(2’);所述氧化物半导体层(4)设置于所述基板(1’)上。
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JPWO2007032128A1 (ja) * | 2005-09-16 | 2009-03-19 | シャープ株式会社 | 薄膜トランジスタ |
KR100873081B1 (ko) * | 2007-05-29 | 2008-12-09 | 삼성모바일디스플레이주식회사 | 박막 트랜지스터, 그의 제조 방법 및 박막 트랜지스터를구비하는 평판 표시 장치 |
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KR100993416B1 (ko) * | 2009-01-20 | 2010-11-09 | 삼성모바일디스플레이주식회사 | 박막 트랜지스터, 그의 제조 방법 및 박막 트랜지스터를 구비하는 평판 표시 장치 |
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KR20130040706A (ko) * | 2011-10-14 | 2013-04-24 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 및 반도체 장치의 제작 방법 |
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CN101901839A (zh) * | 2009-05-29 | 2010-12-01 | 株式会社半导体能源研究所 | 半导体装置及其制造方法 |
CN102403313A (zh) * | 2011-08-26 | 2012-04-04 | 友达光电股份有限公司 | 半导体元件及其制作方法 |
TW201324740A (zh) * | 2011-12-02 | 2013-06-16 | Ind Tech Res Inst | 半導體元件及其製造方法 |
US8895379B2 (en) * | 2012-01-06 | 2014-11-25 | International Business Machines Corporation | Integrated circuit having raised source drains devices with reduced silicide contact resistance and methods to fabricate same |
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US20160240687A1 (en) | 2016-08-18 |
US10991827B2 (en) | 2021-04-27 |
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US20200212225A1 (en) | 2020-07-02 |
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US10629745B2 (en) | 2020-04-21 |
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