CN104035897A

CN104035897A - Storage controller

Info

Publication number: CN104035897A
Application number: CN201410261435.1A
Authority: CN
Inventors: 景蔚亮; 陈邦明
Original assignee: Shanghai Xinchu Integrated Circuit Co Ltd
Current assignee: Shanghai Xinchu Integrated Circuit Co Ltd
Priority date: 2014-06-12
Filing date: 2014-06-12
Publication date: 2014-09-10
Anticipated expiration: 2034-06-12
Also published as: CN104035897B

Abstract

The invention provides a storage controller. A single-layer cell storage array is integrated into the storage controller and replaces part or all of data buffers, so that the integrated single-layer cell NAND storage array has the advantages of being small in storage unit size, low in cost, low in power consumption, nonvolatile and the like, and the novel NAND storage controller of the structure is suitable for the application field with high requirements on power consumption, cost or capacity. In addition, if a certain application environment has quite high requirements on speed, the single-layer cell NAND array can be taken as a second-stage data buffer to be together with a first-stage SRAM or DRAM buffer to form a mixed data buffer, so that the objective of high-speed reading and writing is achieved, and the advantages of small cell size, low cost, low power consumption, nonvolatility and the like are realized.

Description

A kind of memory controller

Technical field

The present invention relates to semiconductor applications, be specifically related to a kind of memory controller, utilize this memory controller can realize data cache.

Background technology

NAND type solid state hard disc has become the non-volatile memory technology of current main flow, is widely used in the every field such as data center, PC, mobile phone, intelligent terminal, consumer electronics, and still presents the ever-increasing situation of demand.The manufacturing process of NAND type solid state hard disc has also developed into 16nm, from two-dimentional manufacturing process, to three-dimensional manufacturing process, transforms.Samsung has announced commercially producing of three dimensional NAND chip that 128Gb24 unit (bit) is stacking.Company of Micron Technology has announced the New Two Dimensional NAND chip of 16nm128Gb, uses novel two-dimentional cellular construction to break through the restriction that conventional two-dimensional physical dimension is dwindled.

Traditional NAND solid state hard disc storage chip and the manufacturing process of memory controller chip are generally different, and the large factories of NAND solid state hard disc such as Samsung, Micron Technology, Toshiba, Hynix all adopt special production line, incompatible with CMOS logic process.Each wafer foundry that the CMOS technique of take is master all cannot realize the production of NAND solid state hard disc.Although traditional two-dimentional NAND solid state hard disc technique and three dimensional NAND solid state hard disc technique are to the technique of tens nanometers, but this is only for NAND storage array, what its logic control circuit and artificial circuit part still adopted is the CMOS technique falling behind very much, for example, only have 180nm, 130nm.Be the consideration of chip cost on the one hand, advanced CMOS processing procedure can increase the manufacturing cost of chip; Be the voltage that writing of NAND solid state hard disc unit needs 20V left and right on the other hand, technology difficulty and the cost of in advanced CMOS technique, realizing high-voltage CMOS pipe are also larger.Although the New Two Dimensional NAND solid state hard disc technique of Micron Technology has adopted the Advanced CMOS Process of high-dielectric constant metal grid (HKMG) in memory cell areas, but what the logic control circuit of its chip and artificial circuit part still adopted is the CMOS technique falling behind very much, and the HKMG process using of its NAND solid state hard disc unit is the technology integrating method of Gate First, incompatible with the Advanced CMOS Process of current main flow.

General nand memory can be divided into single layer cell NAND (SLC, single-level cell) and multilevel-cell NAND (MLC, multi-level cell).SLC is exactly cell stores 1bit data, be characterized in that cost is high, capacity is little, speed is fast, erasable number of times (Endurance) is up to 100,000 times, higher 10 times than MLC solid state hard disc, and data holding ability (Retention) is 10 years.MLC is exactly that a storage unit can be stored a plurality of bit data, can realize at present every unit storage 2bit and 3bit data, and its maximum feature is exactly that the large cost of capacity is low, but speed is slow, and endurance life is also lower, and data holding ability also can decline.Because the data of depositing in each MLC storage unit are more, structure relative complex, the probability of makeing mistakes can increase, must carry out more error correction, thereby the poor multilevel-cell NAND of some data holding abilities even needs to carry out periodic refresh guarantees data reliability, and these actions all can cause its performance significantly to lag behind SLC solid state hard disc simple in structure.

The one-piece construction of General N AND solid state hard disc as shown in Figure 1.Memory controller is connected to system bus by front-end interface.Memory controller is connected with NAND chip by rear end bus.The status of the control core of memory controller in memory controller is most important, and is exactly interior data impact damper (buffer) to the performance impact of memory controller important indicator.Data buffer has been optimized the data transmission between system and NAND chip.System order of read data from solid state hard disc is generally: by rear end bus, from NAND chip, read page data; Page data is saved in data buffer; System is read I/O data from data buffer by Front Side Bus.System is write order from data to solid state hard disc is just contrary with read data.Visible, data buffer has played the effect of stepping-stone (stepping Stone), has alleviated system and the unmatched problem of NAND chip reading speed, is also of value to improve NAND chip resistance to simultaneously and writes the life-span.Along with solid state hard disc memory capacity more come also large, also increasing to the capacity requirement of buffer.The capacity that increases data buffer increases memory controller chip area, and cost constantly rises, and power consumption also constantly increases.And another solution is exactly to adopt the mode of external impact damper to reduce memory controller chip area and cost, structure as shown in Figure 2.External data buffer is generally SRAM structure or dram chip, although capacity increases, power consumption is still very large, especially DRAM, also need regularly to refresh to keep data integrity, in addition owing to adopting external mode but not integration mode can decrease reading speed.

Summary of the invention

A memory controller, is applicable to operating system External memory equipment is carried out to data processing, and wherein, described memory controller comprises core controller module and data buffering module;

Described operating system transmit operation instruction is to described core controller module, and described core controller module, according to the operational order receiving, is optimized the data interaction between described operating system and described External memory equipment by described data buffering module;

Wherein, described data buffering module comprises one or more storage unit that constitute in single layer cell NAND storage array, NOR FLASH array, PCM, ReRAM, FeRAM, SRAM, DRAM, for data cached.

Above-mentioned memory controller, wherein, described storage unit comprises first order storer and second level storer, the buffer memory capacity of described first order storer is less than the buffer memory capacity of described second level storer;

Wherein, described first order storer comprises SRAM or DRAM storer, and described second level storer is single layer cell NAND storage array.

Above-mentioned memory controller, wherein, the control gate of described single layer cell NAND storage array is prepared based on Gate Last high-K metal gate (gate last HKMG, high dielectric metal gate) technique.

Above-mentioned memory controller, wherein, described memory controller also comprises a front-end interface and a back end interface;

Described data buffering module is all connected with back end interface with described front-end interface; And

Described core controller module is all connected with back end interface with described front-end interface.

The present invention is integrated into single layer cell NAND storage array in memory controller, and Substitute For Partial or total data buffer module, read with erasable speed, endurance life and power consumption on all possess obvious advantage.If certain applied environment is also very high to rate request simultaneously, single layer cell NAND array can be used as second level data buffer so, form a hybrid data buffer with other storeies such as first order SRAM or DRAM buffer, reach the object of high-speed read-write, met again the advantages such as unit size is little, cost is low, low in energy consumption, non-volatile.

Accompanying drawing explanation

By reading the detailed description of non-limiting example being done with reference to the following drawings, it is more obvious that the present invention and feature thereof, profile and advantage will become.In whole accompanying drawings, identical mark is indicated identical part.Deliberately proportionally do not draw accompanying drawing, focus on illustrating purport of the present invention.

Accompanying drawing 1 is traditional NAND solid state hard disc one-piece construction schematic diagram;

Accompanying drawing 2 is the NAND solid state hard disc structural representation of conventional art external data impact damper;

Accompanying drawing 3 is a kind of novel NAND memory controller schematic diagram of the present invention;

Accompanying drawing 4 is a kind of specific embodiment schematic diagram of the present invention.

Embodiment

In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.Yet, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, for technical characterictics more well known in the art, be not described.

Should be understood that, the present invention can be with multi-form enforcement, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiment to expose thorough and complete, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, for clear, the size in Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.

The object of term is only to describe specific embodiment and not as restriction of the present invention as used herein.When this uses, " " of singulative, " one " and " described/to be somebody's turn to do " also intention comprise plural form, unless the other mode of pointing out known in context.It is also to be understood that term " composition " and/or " comprising ", when using in this instructions, determine the existence of described feature, integer, step, operation, element and/or parts, but do not get rid of one or more other existence or the interpolations of feature, integer, step, operation, element, parts and/or group.When this uses, term "and/or" comprises any and all combinations of relevant Listed Items.

In order thoroughly to understand the present invention, will detailed step and detailed structure be proposed in following description, to explain technical scheme of the present invention.Preferred embodiment of the present invention is described in detail as follows, yet except these are described in detail, the present invention can also have other embodiments.

Embodiment mono-

The invention discloses a kind of memory controller, be applicable to operating system and External memory equipment carried out to the processing of data.Shown in Fig. 3, it includes data buffering module (buffer), data are deposited module (register) and core controller module (MCU), and data buffering module is deposited module with data and is all connected with core controller module.Operating system transmit operation instruction is to controller core core module, core controller module according to its received instruction to described NAND chipset carry out data read-write, wipe and/or address mapping, and described External memory equipment is carried out to loss equalizing control and DMA control operation, further, controller core core module is according to received operational order, by the data interaction between data buffering module Optimum Operation system and described external memory storage.

This memory controller is also provided with front-end interface and back end interface, data buffering module is all connected with back end interface with front-end interface with core controller module, and between data buffering module and back end interface, be provided with an error correction module (Error Correction Code, ECC), for carrying out real-time data correction.

Above-mentioned front-end interface is other interfaces such as PCI, IDE or SATA, and back end interface is other interfaces such as Toggle DDR or ONFI.ONFI (Open NAND Flash Interface) interface Shi Shiyou Intel, magnesium light, Hynix, Taiwan group joins electronics, SanDisk, Sony, flies to announce the unified connection nand flash memory of formulating and a kind of interface standard of control chip headed by rope semiconductor; Toggle ddr interface standard is by Samsung and jointly customization of Toshiba.Because memory controller provided by the present invention has adopted the interface standard of current main flow, so apply also more extensive.Meanwhile, this back end interface connects some NAND chipsets.In certain embodiments, this NAND chipset can be one or more combinations in single layer cell NAND chipset, multilevel-cell NAND chipset, the stacking NAND chipset of 3D, the NAND chipset that this NAND chipset can be single type, the stacking NAND chipset of single layer cell NAND chipset or multilevel-cell NAND chipset or 3D for example, also can be the NAND chipset mixing, for example both comprised single layer cell NAND chip, comprise again multilevel-cell NAND chip, can also comprise the stacking NAND chip of 3D etc., it will not go into details for related embodiment.

Further, data buffering module comprises one or more storage unit that constitute in single layer cell NAND storage array, NOR FLASH array, PCM, ReRAM, FeRAM, SRAM, DRAM, for data cached.Further preferred, this storage unit is single layer cell NAND storage array, and the included control gate of this single layer cell NAND storage array is prepared based on Gate Last high dielectric metal gate (high-k metal gate) technique, by metal gate process, realize the control gate of NAND unit, rather than traditional polysilicon is around control gate, can realize integrated with high-dielectric constant metal grid Advanced CMOS Process, Gate Last CMOS process compatible with current main flow, overcome current NAND solid state hard disc technique cannot with the problem of advanced standard logic process compatibility, thereby make logic control circuit and artificial circuit part speed faster, and then greatly improve the readwrite performance of NAND chip.Adopt Gate Last CMOS technique can realize the logic function that realizes various complexity at a high speed, can access again larger NAND storage space.Meanwhile, based on the prepared device of Gate Last technique, aspect high-performance & low-power consumption, also can there iing good performance.

In other embodiment of the present invention, single layer cell NAND storage array also can be NOR FLASH array, can realize reading speed faster, but erasable slower; Also can adopt novel storer to replace single layer cell NAND storage array simultaneously, the storeies such as example PCM described above, ReRAM, FeRAM, be characterized in that reading speed more accelerates, erasable speed improves greatly, and area can continue to dwindle, the most important thing is that leakage current is less, be introduced into data buffering and deposit the effect that all can play boost device performance in module.

Shown in Fig. 3 is in data cache module, is provided with single layer cell NAND storage array and SRAM or DRAM storer simultaneously.If certain applied environment is also very high to rate request, single layer cell NAND storage array can be used as second level data buffer so, form a hybrid data cache module with first order SRAM or DRAM buffer, both reach the object that improves read-write, met again the advantages such as unit size is little, cost is low, low in energy consumption, non-volatile.And for hybrid data buffer, the capacity of first order data buffer storage can be far smaller than the capacity of second level buffer memory, when the advantage of buffer is all brought into play greatly separately two-stage like this, also well desalinated shortcoming separately.At this, it should be noted that, if be provided with SRAM or DRAM buffer in data cache module, in data cache module, also must comprise so other any one or multiple storage unit.

This integrated single layer cell NAND storage array of the present invention and traditional SRAM or the contrast of DRAM data buffer are as shown in table 1:

Table 1

According to form, can learn, although compare with SRAM or DRAM storage unit and do not have an advantage with the resistance to single layer cell NAND storage array of writing aspect the life-span in erasable speed, but the integrated single layer cell NAND storage array of the present invention possesses the advantages such as memory cell size is little, cost is low, low in energy consumption, non-volatile, thereby this novel NAND memory controller structure of the present invention is applicable to the application higher to power consumption, cost or capacity requirement.

When computer system need to be carried out read operation to External memory equipment, the read operation instruction that the described computer system that controller core core module receives according to it is sent, by back end interface, transfer the corresponding data stored in External memory equipment to data buffering module, computer system reads the data that are stored in data buffering module by front-end interface;

When computer system need to be carried out write operation to External memory equipment, the write operation instruction that the computer system that controller core core module receives according to it is sent, the data that described computer system write by front-end interface are kept in to data buffering module, and by back end interface, adjust the data of storing in data buffering module to store to portion's memory device.

Embodiment bis-

Lifting a specific embodiment is below further elaborated.

Suppose for every unit 2bit multilevel-cell NAND solid state hard disc, thereby can substitute whole traditional data impact dampers by integrated single layer cell NAND storage array in its storage inside controller chip, the structure of whole solid state hard disc as shown in Figure 4.When system is from solid state hard disc during read data, order is: (1) memory controller takes orders and from every unit 2bit multilevel-cell NAND chip, reads page data by rear end bus; (2) page data is saved in single layer cell NAND data buffer; (3) system is read I/O data by Front Side Bus from single layer cell NAND data buffer.When system is when writing data in solid state hard disc, order is: (1) system is transmitted the data that need to write by Front Side Bus; (2) the I/O data that needs write are saved in single layer cell NAND data buffer; (3) memory controller takes orders and by rear end bus, I/O data Yi Yewei unit is write in the assigned address in every unit 2bit multilevel-cell NAND chip.Visible, this novel NAND memory controller structure of the present invention can realize traditional data buffer function with single layer cell NAND storage array, can play the effect of stepping-stone (stepping stone), and possess and leak that power consumption is little, cost is low and the characteristic such as non-volatile.

The present invention is based on Gate Last high-K metal gate technique and propose a kind of novel NAND controller architecture, single layer cell NAND storage array is integrated in memory controller, and Substitute For Partial or total data impact damper.Adopt single layer cell NAND storage array rather than multilevel-cell NAND array or the stacking NAND array of 3D to be because single layer cell NAND array read with erasable speed, endurance life and power consumption on all possess obvious advantage.Why single layer cell NAND storage array in this NAND of being integrated into memory controller of the present invention can replace traditional data impact damper, first be because it can approach the read or write speed that even reaches traditional data impact damper in read or write speed, this mainly has benefited from: (1) adopts Gate Last CMOS technique to make the logical circuit of memory controller and mimic channel can adopt more advanced CMOS technique, speed is faster, thereby the logic function that realizes various complexity that can faster speed, memory controller is greatly improved in performance; (2) because memory controller and single layer cell NAND storage array are integrated in same SoC chip, thereby between the two, can adopt the wider parallel port data transmission of the faster bandwidth of speed, thereby memory controller can access single layer cell NAND storage array more fast, thereby the read or write speed of NAND storage array is further improved; (3) because Gate Last CMOS metal gate process improves memory controller performance greatly, because of and further improved the readwrite performance to single layer cell NAND storage array.Above-mentioned reason makes the read or write speed of integrated single layer cell NAND storage array can approach the read or write speed that even reaches traditional data impact damper, compare with external data buffer chip, read or write speed even may be faster, thereby have the ability completely Substitute For Partial or whole traditional data impact dampers.

In sum, because the present invention has adopted as above technical scheme, by single layer cell storage array is integrated in memory controller, and Substitute For Partial or total data impact damper, therefore integrated single layer cell NAND storage array provided by the present invention has the advantages such as memory cell size is little, cost is low, low in energy consumption, non-volatile, thereby this novel NAND memory controller structure of the present invention is applicable to the application higher to power consumption, cost or capacity requirement.Simultaneously, if certain applied environment is also very high to rate request, single layer cell NAND array can be used as second level data buffer so, form a hybrid data buffer with first order SRAM or DRAM buffer, reach the object of high-speed read-write, met again the advantages such as unit size is little, cost is low, low in energy consumption, non-volatile.And for described hybrid data buffer, the capacity of first order data buffer storage can be far smaller than the capacity of second level buffer memory, when two-stage, the advantage of buffer is all brought into play greatly separately like this, also well desalinated shortcoming separately, and then in global level, improve device performance, and effectively control cost.

Above preferred embodiment of the present invention is described.It will be appreciated that, the present invention is not limited to above-mentioned specific implementations, and the equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or being revised as the equivalent embodiment of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.

Claims

1. a memory controller, is applicable to operating system External memory equipment is carried out to data processing, it is characterized in that, described memory controller comprises core controller module and data buffering module;

2. memory controller as claimed in claim 1, is characterized in that, described storage unit comprises first order storer and second level storer, and the buffer memory capacity of described first order storer is less than the buffer memory capacity of described second level storer;

3. memory controller as claimed in claim 1, is characterized in that, the control gate of described single layer cell NAND storage array is prepared based on rear grid high-K metal gate technique.

4. memory controller as claimed in claim 1, is characterized in that, described memory controller also comprises a front-end interface and a back end interface;