CN104009518B - Battery charger - Google Patents
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- CN104009518B CN104009518B CN201410084356.8A CN201410084356A CN104009518B CN 104009518 B CN104009518 B CN 104009518B CN 201410084356 A CN201410084356 A CN 201410084356A CN 104009518 B CN104009518 B CN 104009518B
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Abstract
Propose with integrated MOSFET and the semiconductor chip of equivalence enhancement mode JFET.MOSFET JFET chip includes the common semiconductor substrate district of Class1 conduction type.MOSFET element and equivalence enhancement mode JFET device are positioned at above common semiconductor substrate district.Equivalent diode enhancement mode JFET device has common semiconductor substrate district, drains as equivalent diode enhancement mode JFET.The equivalent diode enhancement mode JFET gate region of at least two type 2 conduction type is above equivalent diode enhancement mode JFET drains, and is separated from each other in the horizontal direction, with equivalent diode enhancement mode JFET gate pitch.The equivalent diode enhancement mode JFET source electrode of at least one Class1 conduction type is positioned at above common semiconductor substrate district, and between equivalent diode enhancement mode JFET grid.Top equivalent diode enhancement mode JFET electrode is positioned at above equivalent diode enhancement mode JFET gate regions and equivalent diode enhancement mode JFET source area, and contacts with them.If being arranged to suitable, equivalent diode enhancement mode JFET can have significantly less than the forward voltage Vf of PN junction diode simultaneously, and can be comparable with PN junction diode reverse leakage current.
Description
Technical field
The invention mainly relates to semiconductor device structure field.More precisely, the present invention is for battery about preparation
The device architecture of the integrated power semiconductor device of charging circuit and preparation method, specifically, relate to integrated
Semiconductor device chip of equivalent diode enhancement mode JFET of MOSFET and low forward voltage and preparation method thereof.
Background technology
Figure 1A represents the battery charger 1 of a kind of original technology, can be used for battery boxes for portable telephone charging as example.
The negative pole end of the battery charging source pole V electric charge 1b provided is connected to the negative pole end of battery 1a.Battery charging source pole V electric charge 1b's
Positive terminal is bridged to the positive terminal of battery 1a, and the Schottky diode D that connectsS1f and a power metal-oxidation
Thing-semiconductor field (MOSFET) 1c, during for P-passage MOSFET, connect an embedded body diode 1e with
And grid control signal V controls 1d.But, in some cases, embedded body diode 1e is very favorable, for specific
Application, such as battery charger part, body diode 1e will become a problem, be hereinafter described.Fill normally
Under power mode, reduce grid control signal V and control 1d, open power MOSFET1c, produced charging current IFORWARDPass
Schottky diode DS1f and power MOSFET1c, charges to battery 1a.1d(is controlled such as by improving grid control signal V
Grid control signal 1d is connected on MOSFET1c source voltage), until rupturing duty MSOFET1c, can interrupt filling
Electric process.But, without Schottky diode DS1f, and battery charging source pole V electric charge 1b accidental short circuit, then even if
When power MOSFET1c closes, battery 1a still can be by flowing through the reverse current I of embedded body diode 1eREVERSEAnd
Short circuit.Therefore, Schottky diode DS1f can also prevent battery 1a accidental short circuit as reverse hold-off diode.Although Xiao
The advantage of special based diode is have extremely short switch recovery time, but for battery charging application, this is not one
Individual very important performance parameter.For a person skilled in the art it may also use other kinds of diode in place Xiao Te
Based diode.But, owing to the low forward voltage drop of Schottky diode 1f makes battery 1a consume in normal charging process
Dissipated power is relatively low, and therefore it is highly beneficial for energy efficiency.
Schottky diode D in the circuit 1 of corresponding Figure 1ASThe series connection of 1e and MOSFET1c, Figure 1B represents a kind of original skill
The MOSFET-Schottky diode of art encapsulates 2 jointly.MOSFET-Schottky diode jointly encapsulates 2 and with pin group 2f and draws
Foot group 2e, for external connection.Common encapsulation 2 must be with chip mat one 2a, Yi Jiyong for installing MOSFET chip 2c
In chip mat two 2b installing Schottky diode chip 2d.Additionally, jointly encapsulation 2 must be with bonding wire group 2g and connect
Close lead-in wire group 2h, in order to be connected on pin group 2f by Schottky diode chip 2d and MOSFET chip 2c.Pin group 2e from
Chip mat one 2a and chip mat two 2b starts to extend.By two chip mats (2a and 2b) and two chips (2c and 2d),
MOSFET-Schottky diode encapsulates 2 jointly can cause the biggest overall package size, and bring relevant high assembly cost with
And high manufacturing cost.Therefore, it is necessary to by Schottky diode D in Figure 1ASThe series connection of 1f and power MOSFET1c is integrated in
On one semiconductor chip, thus utilize a single lead frame to reduce package dimension, reduce assembly cost and manufacturing cost.
Fig. 1 C is that United States Patent (USP) 6476442(is hereinafter referred to as the U.S. 6476442) in the copy of Figure 12 A.In the U.S.
In 6476442, Schottky diode is substituted by pseudo-Schottky diode.The prepared source electrode of N-passage MOSFET, body
Link together with grid, under forward voltage about its drain bias.Prepared two-terminal device (referred to as " pseudo-Schottky mould
Formula ") as a diode, but its cut-in voltage is less than traditional PN diode.Especially Fig. 1 C represents a lateral junction
The profile of one example structure of the pseudo-Schottky diode 1200 formed in structure.Utilize traditional technology, at P+ substrate
A P-epitaxial layer 1204 is grown on 1202.P+ body joint 1206 and N+ source electrode 1208 is by metal source/body joint
1218 short circuits.Grid 1216 is also connected on the source/body joint 1218 in the node being labeled as S/B/G (A), thus will
The anode of pseudo-Schottky diode 1200 made by source/body joint 1218.The metal-drain being connected in N+ drain electrode 1212 connects
1214 is the negative electrode of pseudo-Schottky diode 1200, and its contact node is labeled as D(K), thus drain connector 1214 is made
The negative electrode of pseudo-Schottky diode 1200.N-drift region 1210 is positioned near N+ drain electrode 1212.
Therefore, Fig. 1 D-1 and Fig. 1 D-2 is Fig. 4 A and the copy of Fig. 4 B in the U.S. 6476442 respectively, and the feature of MOSFET is
Its grid is shorted to drain electrode, by Schottky diode pseudo-in the computing of MOSFET and quadrant III (i.e. in the computing of quadrant I
There is the device of pseudo-Schottky performance) drain electrode to source current Id with drain electrode to compared with source voltage Vds.It is labeled as PS's
What curve represented is pseudo-Schottky diode, that be labeled as that the curve of M represents is MOSFET.In both cases, MOSFET
Grid be connected to the positive terminal of MOSFET.Fig. 4 A represents owing to the cut-in voltage of pseudo-Schottky diode reduces, therefore pseudo-Xiao
The I-V curve of special based diode offsets towards initial point.Fig. 4 B and Fig. 4 A is identical, but represent is the logarithm of Id, and this is to keep away
The comparison range exempting from electric current is wide, especially in drain electrode to the threshold value region below of source voltage Vds.In part A, only
Leakage current is through pseudo-Schottky diode and MOSFET, therefore electric current approximately equal.In part B in the drawings, pseudo-Schottky two
Pole pipe has already turned on；Therefore, the electric current of pseudo-Schottky diode is much larger than MOSFET electric current.In C portion, MOSFET opens,
Bulk effect disappears, and therefore electric current is again close to.It should be noted that when Vds is between 0.2-0.6V, pseudo-Schottky diode
In more much higher than the Id in MOSFET order of magnitude of Id.
It is hereinafter referred to as the U.S. 6734715 in United States Patent (USP) 6734715() in, two described end semiconductor circuits can substitute for
Traditional DC power supply circuit is used as the semiconductor diode of commutator.Propose many under the lowest direct current power source voltage
Work, can effectively provide the semiconductor circuit of DC current in discrete circuit and integrated circuit.All these circuit is all
There is a forward or current conducted state and a reverse or conducted state for non-present, be similar to traditional quasiconductor
Diode, but forward conduction voltage VT is relatively low, and also electric current control performance is more preferably.Especially Fig. 1 E-1 and Fig. 1 E-2 represents respectively
The copy of Fig. 4 and Fig. 5 in the U.S. 6734715.Fig. 1 E-1 represents that one based on the asymmetrical normally closed JFET of n-passage and is passed through
The two-terminal device 400 of 435 formation it is directly connected between grid 420 and source electrode 430.Source electrode 430 and two ends of drain electrode 410 composition
Device can represent with diode equivalent 450.The source lead 430 of the corresponding JFET of the anode tap 460 of diode, and diode
The drain lead 410 of the corresponding JFET of cathode leg 470.Fig. 1 E-2 represents asymmetrical often by transformator 505 and n-passage
Close connect and compose two terminal circuit 500 of JFET525.The two terminal circuit of source electrode 530 and drain electrode 550 composition can use two poles
Pipe equivalent 570 represents.The source lead 530 of the corresponding JFET of the anode tap 580 of diode, and the cathode leg 590 of diode
The drain lead 550 of corresponding JFET.Transformer 510 is connected between the source electrode of JFET and drain electrode.Two connected
One end of secondary coil 520 is connected between it and the grid 540 of JFET with current limiting device 560, and the other end of secondary coil connects
On the source electrode of JFET.Current limiting device can stop the electric current of excess between p-type grid structure and n-type epitaxial region.On transformator
Polarity dots 515 indication transformer primary coil and secondary coil electric potential difference between 180 degree of phase shifts.This transformator be one by
The transformator being gradually incremented by, the wherein big coefficient N of the voltage of the voltage ratio primary coil of secondary coil, the definition of N is secondary line
The number of turn of primary coil in the turn ratio of circle.
In view of these original technology, still it is necessary: replace tradition with the Novel diode with more preferably performance parameter
Schottky diode；And in semiconductor device chip level, by integrated with power MOSFET for Novel diode, to reduce encapsulation
Size also reduces cost.
Summary of the invention
Propose and a kind of strengthen with integrated metal oxide semiconductor field effect tube (MOSFET) and equivalent diode
The semiconductor device chip of type field effect transistor (JFET).This semiconductor device chip can be containing two conduction node (or terminal)
Terminal-S, terminal-D and control node (or terminal) terminal-grid.MOSFET-JFET semiconductor device chip includes:
The relatively low common semiconductor substrate district (CSSR) of type-1 conduction type (or referred to as first conduction type).
It is positioned at the MOSFET element district at top, common semiconductor substrate district.This MOSFET element district has:
Common semiconductor substrate district is as its MOSFET drain region.
The MOSFET body zone of at least one type-2 conduction type (or referred to as second conduction type), type-1 are conducted electricity
The MOSFET gate regions of type and MOSFET source district are positioned at top, MOSFET drain region.
One equivalent diode enhancement mode JFET(DCE-JFET) device region is positioned at top, common semiconductor substrate district.Such
Effect diode enhancement mode JFET device district has:
Common semiconductor substrate district is as its equivalent diode enhancement mode JFET drain region.
The equivalent diode enhancement mode JFET gate region of at least two type-2 conduction type strengthens in equivalent diode
Top, type JFET drain region, and be laterally separated from each other along common semiconductor substrate district principal plane, with equivalent diode enhancement mode
JFET gate pitch.
At least equivalent diode enhancement mode JFET source area of type-1 conduction type is positioned at top, common semiconductor substrate district
Between portion and equivalent diode enhancement mode JFET gate regions, wherein equivalent diode enhancement mode JFET source area is shorted to equivalence
Diode enhancement mode JFET gate regions.
Therefore, MOSFET element drain region is connected in series to equivalent diode enhancement mode JFET device by common semiconductor substrate district
Drain region.
In a more typical embodiment, MOSFET also includes:
One top source electrode being connected to MOSFET source district, as terminal-S.
Equivalent diode enhancement mode JFET can also have:
One top equivalent diode enhancement mode JFET electrode, is positioned at equivalent diode enhancement mode JFET gate regions and equivalence
Contact above diode enhancement mode JFET source area and with them, as terminal-D.
In a more typical embodiment, MOSFET also includes:
One top grid electrode being connected to MOSFET gate regions, as terminal-grid.
In a more typical embodiment, the conductivity level of equivalent diode enhancement mode JFET gate regions, equivalent two poles
Equivalent diode enhancement mode between tube enhancement type JFET gate regions and below equivalent diode enhancement mode JFET source area
Conductivity level and the equivalent diode enhancement mode JFET gate pitch of JFET channel region are all joined on each of which preset level
Put, so that equivalent diode enhancement mode JFET device is as enhancement mode JFET, there is at a fairly low forward voltage simultaneously
Vf and at a fairly low reverse leakage current.Especially Vf can be more much lower than the Vf of PN junction diode, and reverse leakage current is permissible
Comparable with the reverse leakage current of PN junction diode.
In a more typical embodiment, in order to simplify the preparation technology of MOSFET-JFET semiconductor device chip:
Choose the dopant material of MOSFET body zone, concentration and the degree of depth, make they and equivalent diode enhancement mode JFET grid
The dopant material of polar region, concentration are identical with the degree of depth.
Choose the dopant material in MOSFET source district, concentration and the degree of depth, make they and equivalent diode enhancement mode JFET source
The dopant material of polar region, concentration are identical with the degree of depth.
In order to simplify the preparation of MOSFET-JFET chip further, choose MOSFET top source electrode and top grid
The material of electrode and thickness, make them identical with top equivalent diode enhancement mode JFET electrode.
In a more typical embodiment, MOSFET gate regions is configured to trench-gate, extends downwardly into MOSFET
In body zone and common semiconductor substrate district.In another more typical embodiment, MOSFET gate regions is configured to plane
Grid, is positioned at above MOSFET body zone, MOSFET source district is bridged to common semiconductor substrate district.
In a more typical embodiment, common semiconductor substrate district includes type-1 conduction of a relatively low conductivity
The upper strata of type, is positioned at above the lower substrate layer of type-1 conduction type of high electrical conductivity.
As a more typical example, type-1 conduction type is P-type, and type-2 conduction type is N-type, will
MOSFET-JFET semiconductor device chip makes a P-passage device.As an optional example, type-1 conduction type is
N-type, type-2 conduction type is P-type, and MOSFET-JFET semiconductor device chip is made a N-passage device.
Proposing a kind of battery charger, it includes:
One battery, has first battery-end and second battery-end.
One battery charging source pole, has first charging end and second charging end, and the first charging end is connected to
In first battery-end.
Series connection MOSFET and enhancement mode JFET, in order to the second charging end is bridged to the second battery-end.Configuration enhancement mode
JFET, makes its JFET source shorted JFET grid to it, thus as a reverse hold-off diode, has the lowest just
To voltage drop.
Propose a kind of for preparing with integrated MOSFET and equivalent diode enhancement mode field effect transistor (DCE-
The method of semiconductor device chip JFET).This semiconductor device chip has two conduction node (or terminal) terminal-S, ends
Son-D and control node (or terminal) terminal-grid.This semiconductor device chip also has type-1 conduction type
Relatively low common semiconductor substrate district (CSSR) and:
MOSFET is positioned at top, common semiconductor substrate district, and has:
Common semiconductor substrate district is as its MOSFET drain region.
The MOSFET body zone of at least one type-2 conduction type, the MOSFET gate regions of type-1 conduction type and
MOSFET source district is positioned at top, drain region.
MOSFET can also contain a top source electrode being connected to MOSFET source district, as terminal-S, and
One top grid electrode being connected to MOSFET gate regions, as terminal-grid.
It is positioned at equivalent diode enhancement mode JFET at top, common semiconductor substrate district, and has:
Common semiconductor substrate district is as its equivalent diode enhancement mode JFET drain region.
The equivalent diode enhancement mode JFET gate regions storehouse of at least two type-2 conduction type increases at equivalent diode
Top, strong type JFET drain region, and be laterally separated from each other along Your Majesty's semiconductor substrate region plane altogether, strengthen with equivalent diode
Type JFET gate pitch.
The equivalent diode enhancement mode JFET source area storehouse of at least one type-1 conduction type serves as a contrast in common semiconductor
Between top, base area and equivalent diode enhancement mode JFET gate regions.
Equivalent diode enhancement mode JFET can also contain a top equivalent diode enhancement mode JFET electrode, is positioned at
Contact, as end above effect diode enhancement mode JFET gate regions and equivalent diode enhancement mode JFET source area and with them
Son-D.
The method includes:
Preparation common semiconductor substrate district, is divided into a MOSFET region by its principal plane and an equivalent diode strengthens
Type JFET district, then prepares a MOSFET gate regions in MOSFET region.Wherein, preparation common semiconductor substrate district includes:
The lower substrate layer of type-1 conduction type of preparation high electrical conductivity.
Above lower substrate layer, the upper strata of type-1 conduction type of one relatively low conductivity of preparation.
In MOSFET region, prepare MOSFET body zone, and in equivalent diode enhancement mode JFET district, preparation equivalence
Diode enhancement mode JFET gate regions.
In MOSFET region, prepare MOSFET source district, and in equivalent diode enhancement mode JFET district, preparation equivalence
Diode enhancement mode JFET source area.
Equivalent diode enhancement mode JFET source area is shorted to equivalent diode enhancement mode JFET gate regions.
In a relatively particular embodiment, the method can also comprise the following steps:
Above MOSFET region, prepare the top, passivation layer with contact openings and form pattern；And/or
Preparation metal layer at top also forms pattern.This includes:
The top source electrode of MOSFET and top grid electrode；And
Top equivalent diode enhancement mode JFET electrode, wherein top equivalent diode enhancement mode JFET electrode is by equivalence two
Pole tube enhancement type JFET source area is shorted to equivalent diode enhancement mode JFET gate regions.
In a relatively particular embodiment, the method also include configure following items:
Between the conductivity level of equivalent diode enhancement mode JFET gate regions, equivalent diode enhancement mode JFET gate regions with
And the conductivity level of the equivalent diode enhancement mode JFET channel region below equivalent diode enhancement mode JFET source area and etc.
Effect diode enhancement mode JFET gate pitch all configures on each of which preset level, so that made equivalent diode
Enhancement mode JFET device, as equivalent diode enhancement mode JFET, has the lowest forward voltage Vf, much smaller than PN junction two
The forward voltage Vf of pole pipe, and there is the lowest reverse leakage current, close to the reverse leakage current of PN junction diode.
In a more typical embodiment, MOSFET gate regions is configured as trench-gate, extends downwardly into
In MOSFET body zone and common semiconductor substrate district.In contrast, MOSFET region is prepared MOSFET gate regions to include:
A trench mask is prepared at top, common semiconductor substrate district, the MOSFET gate regions in corresponding MOSFET region,
But trench mask covers the common semiconductor substrate district in equivalent diode enhancement mode JFET district.
By trench mask, anisotropically etching common semiconductor substrate district, form MOSFET gate trench, then remove
Go trench mask.
Gate dielectric layer is prepared in gate trench.
Gate dielectric layer deposits a conductive gate layer.
In a more typical embodiment, preparation MOSFET gate regions include anisotropically returning conductive gate layer at quarter and
Gate dielectric layer, until being divided into original MOSFET gate regions, and till completely removing planar gate polar region by conductive gate layer.
In a more typical embodiment, above MOSFET body zone, MOSFET gate regions is configured to planar gate
Pole.In contrast, preparation MOSFET gate regions is included in common semiconductor substrate district top face, successively prepares a grid electricity
Dielectric layer and a conductive gate layer.This also includes:
At conductive gate layer top, prepare a gate mask, the MOSFET gate regions in corresponding MOSFET region, but naked
Expose the conductive gate layer in equivalent diode enhancement mode JFET district.
By gate mask, anisotropically return conductive gate layer at quarter and gate dielectric layer, until by conductive grid material
Till material is divided into MOSFET gate regions original in MOSFET region, then remove gate mask.
In an embodiment in greater detail, preparation MOSFET body zone and equivalent diode enhancement mode JFET gate regions bag
Include:
Implant mask, the MOSFET implantation region being simultaneously implanted in MOSFET region by one first, and waiting
The first equivalent diode enhancement mode JFET implantation region in effect diode enhancement mode JFET district.
Spread simultaneously and activate a MOSFET implantation region and the first equivalent diode enhancement mode JFET implantation region, respectively shape
Become MOSFET body zone and equivalent diode enhancement mode JFET gate regions.
In an embodiment in greater detail, preparation MOSFET source district and equivalent diode enhancement mode JFET source area bag
Include:
Implant mask, the 2nd MOSFET implantation region being simultaneously implanted in MOSFET region by one second, and waiting
The second equivalent diode enhancement mode JFET implantation region in effect diode enhancement mode JFET district.
Spread simultaneously and activate the 2nd MOSFET implantation region and the second equivalent diode enhancement mode JFET implantation region, respectively shape
Become MOSFET source district and equivalent diode enhancement mode JFET source area.
In an embodiment in greater detail, preparation metal layer at top also forms pattern and includes:
Above MOSFET region and equivalent diode enhancement mode JFET district, deposit a metal layer at top.
By a top metal mask, the pattern of the metal layer at top prepared by formation so that:
Top source electrode needed for patterned top metal layer segment, correspondence and top grid electricity in MOSFET region
Pole.
In equivalent diode enhancement mode JFET district needed for patterned top metal layer segment, correspondence top equivalence two poles
Tube enhancement type JFET electrode.
For those skilled in the art, after reading the herein below of this explanation, the aspects of the invention and multiple
Embodiment will be apparent to.
The present invention can be used for integrated circuit (IC) chip and discrete power chip.Electrode can be any type of gold
Belong to and connecting.Terminal refers to the node in circuit, it is not limited to the metal electrode of discrete power device.Terminal can also be IC
The junction point of the equivalent diode enhancement mode JFET circuit in chip.
Accompanying drawing explanation
In order to be described more fully various embodiments of the present invention, can refer to accompanying drawing.But, these accompanying drawings are used only as solving
Release explanation, be not intended as the limitation of the scope of the invention.
Figure 1A represents the battery charger of a kind of original technology；
Figure 1B represents what the Schottky diode of a kind of original technology being similar to Figure 1A and MOSFET encapsulated jointly
MOSFET-Schottky diode；
Fig. 1 C is the copy of Figure 12 A in the United States Patent (USP) 6476442 of original technology；
Fig. 1 D-1 is the copy of Fig. 4 A in the United States Patent (USP) 6476442 of original technology；
Fig. 1 D-2 is the copy of Fig. 4 B in the United States Patent (USP) 6476442 of original technology；
Fig. 1 E-1 is the copy of the Fig. 4 in the United States Patent (USP) 6476442 of original technology；
Fig. 1 E-2 is the copy of the Fig. 5 in the United States Patent (USP) 6476442 of original technology；
Fig. 2 A to Fig. 2 C represents the section half of equivalent diode enhancement mode technotron (JFET) of the present invention
Conductor chip structure, and equivalent circuit and the symbolic notation as component；
Fig. 3 A and Fig. 3 B represents the section quasiconductor of equivalent diode JFET of the present invention and MOSFET element respectively
Chip structure；
Fig. 4 A is denoted as example, and equivalent diode JFET of the present invention becomes battery with MOSFET element arranged in series
The circuit diagram of a part for charging circuit；
Fig. 4 B represents the circuit diagram of corresponding diagram 4A, integrated trench-gate MOSFET element and of the present invention etc.
The section semiconductor chip structure of effect diode JFET；
Fig. 5 represents configuration circuit diagram shown in Fig. 4 A in battery charger；
Fig. 6 A to Fig. 6 C represents equivalence two pole in integrated trench-gate MOSFET element and Fig. 4 B of the present invention
Pipe JFET, the circuit diagram structure under various bias states；
Fig. 7 A represents that equivalent diode JFET of the present invention becomes battery charger with MOSFET element arranged in series
The circuit diagram of a part；
Fig. 7 B represents the circuit diagram of corresponding diagram 7A, integrated trench-gate MOSFET element and of the present invention etc.
The section semiconductor chip structure of effect diode JFET；
Fig. 8 A represents that equivalent diode N-passage JFET and N-passage MOSFET element arranged in series of the present invention becomes
The circuit diagram of a part for battery charger；
Fig. 8 B represents the circuit diagram of corresponding diagram 8A, integrated trench-gate N-passage MOSFET element and institute of the present invention
The section semiconductor chip structure of the equivalent diode N-passage JFET stated；
Fig. 9 A to Fig. 9 V represent in integrated trench-gate N-passage MOSFET element and Fig. 4 B of the present invention etc.
The semiconductor chip preparation technology of effect diode N-passage JFET；And
Figure 10 represents the equivalent diode JFET in integrated trench-gate MOSFET element and Fig. 4 B of the present invention
Simplification after top view.
Detailed description of the invention
Address following description on contained by Ben Wen and accompanying drawing be merely to illustrate the present invention one or more existing preferably
Embodiment, and some typical selectable unit and/or alternative embodiments.Illustrate and accompanying drawing is used for illustrating, with regard to itself
Speech, does not limit to the present invention.Therefore, those skilled in the art will easily grasp various change, variations and modifications.These change
Dynamic, variations and modifications also are regarded as belonging to the scope of the present invention.
Fig. 2 A to Fig. 2 C represents equivalent diode P-passage enhancement mode technotron (Diode-of the present invention
Connected p-channel enhancement mode junction field effect transistor, is called for short
DCE-JFET) the section semiconductor chip structure of 10, and simplify after equivalent circuit 36 and as circuit representation 38.Equivalence
Diode enhancement mode JFET device district 8 is positioned at the relatively low common semiconductor substrate district (Common of P-type conduction type
Semiconductor substrate region, is called for short CSSR) above 11.In the present embodiment, common semiconductor substrate district
11 containing p-epitaxial region, the top 11b of a relatively low conductivity, are positioned at bottom P+ substrate zone 11a upper of higher conductivity
Side.Equivalent diode enhancement mode JFET device district 8 has:
Common semiconductor substrate district 11 is as its equivalent diode enhancement mode JFET drain region；
Multiple N-type equivalent diode enhancement mode JFET14 are positioned at top, common semiconductor substrate district 11.In the horizontal direction
On, adjacent equivalent diode enhancement mode JFET gate regions 14 is separated from each other along Your Majesty's semiconductor substrate region 11 plane altogether, with
Equivalent diode enhancement mode JFET gate pitch (Gate spacing is called for short GTSP) 15；
Multiple P-type (being P+ in this example) equivalent diode enhancement mode JFET source area 12, is positioned at common semiconductor substrate
Between top, district 11, and N-type equivalent diode enhancement mode JFET gate regions 14；And
One top equivalent diode enhancement mode JFET electrode 20, is positioned at equivalent diode enhancement mode JFET gate regions 14 He
The top of equivalent diode enhancement mode JFET source area 12, and contact, as terminal-D.
Therefore, the P-N junction diode element 27 of multiple equivalences is formed at N-type equivalent diode enhancement mode JFET gate regions
Between 14 and p-epitaxial region 11b.The edge of the p-epitaxial region 11b on the surface of p-epitaxial region 11b increases with N-type equivalent diode
The intersection of strong type JFET gate regions 14, the P-N junction diode element 27 of equivalence has a built-in common semiconductor substrate
District's depletion region 25, with depletion region border, common semiconductor substrate district 26.Additionally, multiple JFET pass element district (Channel
Element zones) 28 it is also formed in the P-epitaxial layer between neighbouring N-type equivalent diode enhancement mode JFET gate regions 14
In 11b, JFET pass element district 28, mainly as resistance current path, makes the P-N junction diode element 27 of equivalence shunt.JFET
The conduction type in pass element district 28 depends on the covering of they neighbouring common semiconductor substrate district depletion regions 25.At Fig. 2 A
In shown state, common semiconductor substrate district depletion region 25 completely depleted JFET pass element district 28, thus close JFET and lead to
Road.But, if the covering of common semiconductor substrate district depletion region 25 can become fairly small, then JFET pass element district 28
To open and conduct, this will be described in detail later.
As hereafter will introducing, JFET pass element district 28 on p+ substrate zone 11a and terminal-D20 etc.
Effect JFET aisle resistance is controlled by bias voltage VBIAS.Especially, higher VBIAS can produce less common semiconductor lining
Base area depletion region 25 and relatively low equivalent JFET aisle resistance.Therefore, the equivalent diode enhancement mode JFET letter shown in Fig. 2 B
The equivalent circuit 36 changed is the parallel connection of the variable JFET aisle resistance 28 of equivalence P-N junction diode 27 and equivalence.State on by
Bright, equivalent diode enhancement mode technotron (DCE-JFET) 10 can use the P-passage equivalence two shown in Fig. 2 C easily
Pole tube enhancement type JFET circuit representation 38 represents, P-passage equivalent diode enhancement mode JFET circuit representation 38 has one
12, N-grid 14 of P-source electrode and P-drain 11b, and P-source electrode 12 and N-grid 14 links together.
Fig. 3 A and Fig. 3 B is section semiconductor chip structure, represents equivalent diode enhancement mode of the present invention respectively
JFET10 and basic, existing Metal-oxide-semicondutor field effect transistor (MOSFET) device 50 with trench-gate.
Similar with equivalent diode enhancement mode JFET10, the MOSFET element of Metal-oxide-semicondutor field effect transistor (MOSFET) 50
District 48 also is located at above common semiconductor substrate district 11, as MOSFET drain region.Additionally, it is also well known that MOSFET element district
48 have:
Multiple MOSFET N-type body zone 52, multiple MOSFET trench gate polar region 54 and multiple MOSFET P-type source electrode
District 56, is positioned at above common semiconductor substrate district 11, and trench gate polar region 54 downwardly extends, and through N-type body zone 52, arrives
In common semiconductor substrate district 11.
One top source electrode 58, is connected on multiple MOSFET P-type source area 56 and multiple MOSFET N-type
In body zone 52, as terminal-S, and a top grid electrode (invisible in this profile), it is connected to multiple
On MOSFET trench gate polar region 54, see Figure 10 as terminal-grid 45().For a person skilled in the art, due to
Terminal-grid 45 is connected on MOSFET trench gate polar region 54 be perpendicular in the region of paper plane, and therefore it is in this profile
It is sightless.
Multiple top, passivation layer 57, are positioned at above MOSFET trench gate polar region 54 and MOSFET source district 56, with top
The contact openings of source electrode 58.
Fig. 3 A and Fig. 3 B is done contrast directly perceived, it can be seen that equivalent diode enhancement mode JFET10 and MOSFET50 are partly leading
There is in body chip-scale a lot of structural similarities, therefore effectively both devices can be integrated in one and individually partly lead
On body device chip.
As shown in Figure 4 A, the circuit that equivalent diode enhancement mode JFET of the present invention is connected is represented with MOSFET element
Figure, equivalent diode enhancement mode JFET provides reverse locking function for MOSFET, such as, it can be made as battery charger
A part.MOSFET-JFET device circuitry representation 68 has a P-passage equivalent diode enhancement mode JFET circuit table
Show method 38, at common node 39, be connected in series in P-passage MOSFET circuit representation 40.MOSFET circuit representation 40 contains
One built-in body diode 41, body diode 41 is formed at N-type MOSFET body zone 52 and following P-type epitaxial layer 11b
Between.In addition to common node 39, other the outside available terminal-S58 that terminal is source terminal, terminal-D20 of drain electrode end
And the terminal-grid 45 of gate terminal.
Fig. 4 B represents the section semiconductor device of a kind of integrated P-channel groove gate MOS FET-JFET device chip 66
Structure, the circuit diagram shown in corresponding diagram 4A.Therefore, MOSFET-JFET device chip 66 have two conduction terminals terminal-S58,
A terminal-D20 and terminal-grid 45(controlling end is invisible in this section).Equivalent diode enhancement mode JFET10
Source electrode 20 also serve as the terminal-D of drain electrode end of whole circuit 68.It should be noted that MOSFET-JFET device chip 66
Containing the available end in extra the 4th outside, i.e. P+ substrate zone 11a.In the horizontal direction, MOSFET-JFET device chip
66 have equivalent diode enhancement mode JFET device district 8 and MOSFET element district 48.Common semiconductor substrate district CSSR11 under
MOSFET element drain region is connected in series to equivalent diode enhancement mode JFET device drain region by face.As it has been described above, MOSFET-JFET
The simple inner vertical structure layer of device chip 66, arises directly from equivalent diode enhancement mode JFET10 and MOSFET50(figure
3A, Fig. 3 B) between corresponding similarity.
Other important contents of MOSFET-JFET device chip 66 include:
Choose the dopant material of MOSFET body zone 52, concentration and the degree of depth, make they and equivalent diode enhancement mode JFET
Gate regions 14 is identical.
Choose the dopant material in MOSFET source district 56, concentration and the degree of depth, make they and equivalent diode enhancement mode JFET
Source area 12 is identical.
Choose material and the thickness of MOSFET top source electrode 58, make they and top equivalent diode enhancement mode JFET
Electrode 20 is identical.
For a person skilled in the art, these aspects will simplify the corresponding crystalline substance of MOSFET-JFET device chip 66
Circle preparation technology.That is, it is not necessary to any extra preparation process or masking process, JFET part just can be integrated in one
On MOSFET.
Fig. 5 represents the MOSFET-JFET device circuitry representation 68 shown in Fig. 4 A is arranged in a battery charger
In 70.MOSFET-JFET device circuitry representation 68 herein is by battery charging source pole (i.e. battery charging source, Battery
Charging source) 74 the second charging end 74b be bridged in the second battery-end 72b of battery 72.More precisely, end
Son-S58 is connected to the positive terminal 74b of battery charging source pole 74, and terminal-D20 is connected to the positive terminal 72b of battery 72, and electricity
The negative pole end 72a in pond is connected to the negative pole end 74a of battery charging source pole 74.
Fig. 6 A to Fig. 6 C represents the fortune under various bias states of the integrated MOSFET-JFET device chip 66 shown in Fig. 4 B
Row principle.In fig. 6, bias for no-voltage between terminal-S58 and terminal-D20.N-type equivalent diode enhancement mode herein
The conductivity level of JFET gate regions 14, between equivalent diode enhancement mode JFET gate regions 14 and equivalent diode strengthens
The conductivity level in the p-type JFET pass element district 28 below type JFET source area 12, and equivalent diode enhancement mode JFET grid
The all configurations on each of which preset level of die opening GTSP15 (namely they can set in advance according to actual demand value
Fixed) so that: the current carrier in JFET pass element district 28 is by its two adjacent common semiconductor substrate district depletion regions 25
Exhaust (owing to being enhancement mode JFET, therefore JFET pass element district 28 under zero-bias by pinch off).Therefore, by JFET passage
The electric current conduction of element region 28 is by its two adjacent and overlapping depletion region pinch ofves.
Owing to equivalent variable JFET aisle resistance 28 is the highest and inclined close to zero between terminal-S58 and terminal-D20
Pressure, therefore the netted ability of MOSFET-JFET device chip 66 has the lowest electric current conduction under zero-bias.
In fig. 6b, between terminal-S and terminal-D, (electromotive force of terminal-S is higher than terminal-D) has forward voltage bias.?
In this case, MOSFET can open, and makes the battery 72 shown in Fig. 5 charge, and forward voltage bias makes P-type epitaxial layer
It is formed on equivalence P-N junction diode element 27 corresponding between 11b and N-type equivalent diode enhancement mode JFET gate regions 14
Forward bias, thus the common semiconductor substrate district depletion region shown in Fig. 6 A is narrowed down to the common semiconductor substrate shown in Fig. 6 B
In district's depletion region 25 '.The conductivity level of equivalent diode enhancement mode JFET gate regions 14 herein, it is positioned at equivalent diode and strengthens
JFET pass element district 28 ' between type JFET gate regions 14 and below equivalent diode enhancement mode JFET source area 12 leads
Electricity level, and all configurations on each of which preset level of equivalent diode enhancement mode JFET gate pitch GTSP15 so that:
Owing to the common semiconductor substrate district depletion region 25 ' after reducing now is separated from each other, the therefore JFET shown in Fig. 6 A
Pass element district 28 opens in JFET pass element district 28 ', and JFET pass element district 28 ' is with the electric current current-carrying for conduction
Son.
When voltage is relatively low, JFET pass element district 28 may still close or only open a part, along with the liter of voltage
Height, JFET pass element district 28 ' more fully opens so that more electric current passes through.In view of JFET pass element district 28 '
Shunt current performance, the netted ability of MOSFET-JFET device chip 66, under forward configures, sees the equivalence two shown in Fig. 2 B
Pole tube enhancement type JFET equivalent circuit 36, owing to equivalent variable JFET aisle resistance 28 can be made very in low forward bias pressure
Low, therefore the forward cut-in voltage Vf of equivalent diode enhancement mode JFET10 is lower very than the forward cut-in voltage of PN junction diode
Many.When P-N diode 27 the most only conducts a part of, (such as more than 0.7V), P-N at higher voltages
Junction diode 27 conducts more, improves the current capability of device.As example, of the present invention equivalent two can be prepared
The Vf of pole tube enhancement type JFET10 is in the range of 0.3V-0.5V, more much lower than the 0.7V-1V of traditional PN junction diode.
JFET gate regions 14, JFET pass element district 28 and the doping content of equivalent diode enhancement mode JFET gate pitch GTSP15
Determine the forward voltage Vf of device.
In figure 6 c, the electromotive force of terminal-S58 and terminal-D20(terminal-S be less than terminal-D) between there is reverse biased.
As example, if still connecting battery 72, battery charging source pole 74 short circuit, then the battery charger shown in Fig. 5 will
There is this phenomenon.It should be noted that in this state, even if MOSFET40 disconnects, body diode 41 built-in for MOSFET
(being formed between n-type body zone 52 and p-type epitaxial layer 11b) also can configure by forward so that conducts on MOSFET40, because of
This must use the reverse blocking element that equivalent diode enhancement mode JFET38 provides.Reverse biased causes equivalence P-N junction two pole
Produce corresponding reverse biased on tube elements 27, thus the common semiconductor substrate district depletion region 25 shown in Fig. 6 A is extended to figure
Common semiconductor substrate district depletion region 25 shown in 6C " in, further pinch off JFET pass element district 28 " in JFET passage
Element region, and make any electric current flowed through the lowest.Therefore, the equivalent diode enhancement mode JFET equivalence shown in Fig. 2 B is seen
Circuit 36, due to higher than Fig. 6 A of equivalent variable JFET aisle resistance 28, MOSFET-JFET device chip 66 is in reverse biased
Under netted leakage current characteristic, with equivalence P-N junction diode 27 similar.As example, can prepare of the present invention etc.
The reverse leakage current of effect diode enhancement mode JFET10, can reverse with PN junction diode in the range of 0.1nA 100nA
Leakage current comparable (the two can almost identical or be more or less the same).
Summing up the described above of Fig. 6 A to Fig. 6 C, the equivalent JFET aisle resistance in each JFET pass element district 28, all by P
Bias voltage control on epitaxial region 11a and terminal-D.More precisely, higher bias can make equivalence JFET aisle resistance relatively low.
Fig. 7 A represents equivalent diode enhancement mode JFET of the present invention and the circuit diagram of MOSFET element series connection, as
Example, this cascaded structure can be as a part for battery charger.MOSFET-JFET device circuitry representation 68 has one
Individual P-passage equivalent diode enhancement mode JFET circuit representation 38, at common node 39, is connected in series to P-passage MOSFET electricity
In road representation 40.The outside of circuit 68 can use end can contain terminal-S58, terminal-D20 and terminal-grid 45, also may be used
Select containing common node 39.Fig. 7 B represents the section half of integrated P-channel plane gate MOS FET-JFET device chip 69
Conductor chip structure, the circuit representation 68 of corresponding diagram 7A.Various MOSFET planar gate polar regions 84 are positioned at N-type MOSFET body
Above district 52, and P-type MOSFET source district 56 is bridged to p-epitaxial region 11b.Fig. 7 B and Fig. 4 B is made comparisons, can see
Go out in addition to replacing MOSFET trench gate polar region 54 with MOSFET planar gate polar region 84, MOSFET-JFET device chip 69 with
MOSFET-JFET device chip 66 is the most closely similar.
Although shown in above-mentioned example is P-passage MOSFET and P-passage JFET, but by changing each semiconductor region
The conduction type in territory, these examples just can be used for contrary conduction type, such as N-passage MOSFET and N-passage JFET.Fig. 8 A
Represent equivalent diode enhancement mode JFET of the present invention and the circuit diagram of MOSFET element series connection, as example, this series connection
Structure can be as a part for battery charger.MOSFET-JFET device circuitry representation 78 has a N-passage etc.
Effect diode enhancement mode JFET circuit representation 88, at common node 39, is connected in series to N-passage MOSFET circuit representation 90
On.The outside of circuit 78 can use end can contain terminal-S58, terminal-D20 and terminal-grid 45, also optional containing public affairs
Conode 39.Fig. 8 B represents the section semiconductor chip junction of integrated P-channel plane gate MOS FET-JFET device chip 86
Structure, the circuit diagram of corresponding diagram 8A.The difference of Fig. 4 B and Fig. 8 B is, in addition to semiconductor conductivity types is exchanged,
The structural topology of MOSFET element chip 86 is identical with MOSFET-JFET device chip 66.
Fig. 9 A to Fig. 9 V represents the preparation technology of the MOSFET-JFET device chip 66 shown in Fig. 4 B.Such as Fig. 9 A and Fig. 9 B
Shown in, the principal plane in common semiconductor substrate district 11 is divided into MOSFET element district 48 and equivalent diode enhancement mode JFET device
District 8.In this case, the common semiconductor substrate district 11 upper epitaxial district 11b containing a relatively low conductivity, it is positioned at higher
The top of the bottom p+ substrate zone 11a of conductivity type.It should be noted that p-epitaxial region 11b can be formed at above p+ substrate zone 11a.
Then, common semiconductor substrate district 11 forms multiple MOSFET gate trench 100, such as:
Common semiconductor substrate district 11 is formed a trench mask (the most not representing), corresponding MOSFET element
MOSFET gate regions in district 48, but trench mask covers in equivalent diode enhancement mode JFET device district 8 public half
Conductor substrate zone 11.
By trench mask, anisotropically etching common semiconductor substrate district 11, to prepare MOSFET gate trench
100, then remove trench mask.
Fig. 9 C to Fig. 9 F represents in the MOSFET element district 48 shown in Fig. 3 B, prepares MOSFET trench gate polar region 108.?
In Fig. 9 C and Fig. 9 D, gate dielectric layer 102(such as gate oxide) it is formed at the gate trench 100 in MOSFET element district 48
In, it is also formed on other exposed surfaces in MOSFET element district 48 and equivalent diode enhancement mode JFET device district 8.At figure
In 9E and Fig. 9 F, by above gate dielectric layer 102, deposit conductive gate layer 109, form MOSFET trench gate polar region
108.Conductive gate layer 109 can be the polysilicon of suitable doping.
Fig. 9 G to Fig. 9 H represents conductive gate layer 109 is divided into basic MOSFET gate regions 54 simultaneously, and from public
Conductive gate layer 109 is removed on the end face of semiconductor substrate region 11.This can be by anisotropically returning conductive gate layer 109 at quarter
Realize, until MOSFET gate regions 108 is divided into basic MOSFET gate regions 54.Then can select to use screen oxide
110 cover MOSFET element district 48 and equivalent diode enhancement mode JFET device district 8, such as, pass through oxidation technology.
Fig. 9 I to Fig. 9 L represents and prepares simultaneously:
MOSFET body zone 52 below the optional screen oxide 110 in MOSFET element district 48.
Equivalent diode below the optional screen oxide 110 in equivalent diode enhancement mode JFET device district 8 strengthens
Type JFET gate regions 14.
In Fig. 9 I and Fig. 9 J, implant mask (not representing in figure) by first, below screen oxide 110,
Prepare first (N-type) MOSFET implantation region 120 in MOSFET element district 48, and equivalent diode enhancement mode JFET simultaneously
First (N-type) equivalent diode enhancement mode JFET implantation region 126 in device region 8.In Fig. 9 K and Fig. 9 L, such as by height
Temperature diffusion cycles, in N-type MOSFET body zone 52 and N-type equivalent diode enhancement mode JFET gate regions 14, distinguishes simultaneously
Spread and activate all of MOSFET implantation region 120 and a first equivalent diode enhancement mode JFET implantation region 126.
Fig. 9 M to Fig. 9 P represents and prepares simultaneously:
MOSFET source district 56 below the optional screen oxide 110 in MOSFET element district 48.
Equivalent diode below the optional screen oxide 110 in equivalent diode enhancement mode JFET device district 8 strengthens
Type JFET source area 12.
In Fig. 9 M and Fig. 9 N, implant mask (not representing in figure) by second, below screen oxide 110,
Prepare second (N-type) MOSFET implantation region 130 in MOSFET element district 48, and equivalent diode enhancement mode JFET simultaneously
Second (N-type) equivalent diode enhancement mode JFET implantation region 136 in device region 8.In Fig. 9 O and Fig. 9 P, such as by height
Temperature diffusion cycles, in MOSFET source district 56 and N-type equivalent diode enhancement mode JFET source area 12, spreads the most respectively
And activate all of 2nd MOSFET implantation region 130 and the second equivalent diode enhancement mode JFET implantation region 136.But, preparation
MOSFET source district 56 and equivalent diode enhancement mode JFET source area 12 need not be carried out simultaneously, the preparation process needed for minimizing and
Mask may be risky；Also it is such for preparation MOSFET body zone 52 and equivalent diode enhancement mode JFET gate regions 14.
Fig. 9 Q to Fig. 9 T represents in MOSFET element district 48, prepares the top, passivation layer with top contact opening 142
57 and form pattern.In Fig. 9 Q and Fig. 9 R, in MOSFET element district 48 and equivalent diode enhancement mode JFET device district 8,
Form silica glass (LTO/BPSG) double passivation layer 140 thickening of low temperature oxide/containing boric acid.In Fig. 9 S and Fig. 9 T, logical
Cross top passivation mask (not representing in figure), the pattern of the double passivation layers 140 prepared by formation so that:
Remove the double passivation layer 140 of the part formed in equivalent diode enhancement mode JFET device district 8.
With in the top, passivation layer 57 needed for top contact opening 142, the double passivation layer of the part prepared by formation
The pattern of 140, matches with top, the top in MOSFET source district 56 of MOSFET body zone 52, covers MOSFET grid simultaneously
The top of polar region 54.
Fig. 9 U and Fig. 9 V represents and prepares top source electrode 58 in MOSFET element district 48 and form pattern, in equivalence two
Tube enhancement type JFET device district, pole 8 prepares top equivalent diode enhancement mode JFET electrode 20.This includes: in MOSFET element
District 48 and equivalent diode enhancement mode JFET device district 8, deposit a metal layer at top.By a top metal mask (figure
In do not represent), the pattern of the metal layer at top prepared by formation so that: the part band figure in MOSFET element district 48
The metal layer at top of case, the top source electrode 58 needed for correspondence and top grid electrode (invisible in this section).
The patterned metal layer at top of part in equivalent diode enhancement mode JFET device district 8, the top needed for correspondence
Portion's equivalent diode enhancement mode JFET electrode 20.
According to the above-mentioned preparation technology to trench-gate MOSFET-JFET device chip 66 (Fig. 9 A to Fig. 9 V), and ditch
The detailed description of the fine structure difference (opposite side Fig. 4 B and Fig. 7 B) between groove gate MOS FET and plane gate MOS FET, plane
The preparation technology of gate MOS FET-JFET device chip 69 is closely similar with trench-gate MOSFET-JFET device chip 66, flat
Face gate MOS FET-JFET device chip 69 is it is noted that herein below:
Equivalent diode on above gate dielectric layer in MOSFET region and common semiconductor substrate district end face
In enhancement mode JFET district, prepare conductive gate layer.
In basic MOSFET gate regions, concurrently separating conductive gate layer, this includes:
Above conductive gate layer, prepare a gate mask, the MOSFET gate regions in corresponding MOSFET region, but it
Expose the conductive gate layer in equivalent diode enhancement mode JFET district.
By gate mask, return and carve conductive gate layer and gate dielectric layer, until conductive gate layer being divided into basic
Till MOSFET gate regions, after completely removing conductive gate layer in equivalent diode enhancement mode JFET district, remove gate mask.
Preparing MOSFET planar gate is a ripe technology, is well known to those skilled in the art.Additionally, to the greatest extent
How manage that above-mentioned technique tells about is by integrated for P-passage MOSFET and P-passage JFET, but by changing above-mentioned semiconductor region
The conduction type in territory, this technique can also be used for integrated for N-passage MOSFET and N-passage JFET.
Finally, for the locus of the MOSFET-JFET device chip 66 top grid electrode shown in clear and definite Fig. 4 B, figure
Top view after 10 simplification representing MOSFET-JFET device chip 66a, MOSFET-JFET device chip 66a has and is similar to
Of the present invention integrated MOSFET element shown in Fig. 4 B and equivalence JFET.MOSFET element district 48 represents a top source
Pole electrode 58 and a top grid electrode 45, and equivalent diode enhancement mode JFET device district 8 represents a top equivalence two
Pole tube enhancement type JFET electrode 20.
Although described above contains multiple detail parameters, but these parameters are only used as preferable reality existing to the present invention
Execute the explanation of example, the scope of the present invention can not be limited to accordingly.Such as, the present invention can be used for integrated circuit (IC) chip with
And discrete power chip." terminal " refers to the node in circuit." electrode " can be that any type of metal connects.By saying
Bright and accompanying drawing, gives the various exemplary embodiments about typical structure.For those skilled in the art it should be apparent that this
Invention may be used for other specific form various, and above-mentioned various embodiments are through easily amendment, it is possible to be suitable for other concrete
Application.This patent document is intended to explanation, and the scope of the present invention should not be limited to the exemplary embodiments in described above, and should by with
Under claims define.Any and all come from claims in the perhaps correction in equivalents, all incite somebody to action
Within being considered to belong to protection scope of the present invention.
Claims (10)
1. a battery charger, it is characterised in that including:
One battery, has first battery-end and second battery-end；
One battery charging source pole, has first charging end and second charging end, and the first charging end is connected to first
In battery-end；
One series connection MOSFET and enhancement mode JFET, bridge to the second charging end the second battery-end, wherein configure enhancement mode
JFET, makes its JFET source shorted JFET grid to it, thus as a reverse hold-off diode, has than PN junction two
The forward drop that pole pipe is lower；
Wherein, described MOSFET is metal oxide semiconductor field effect tube MOSFET, and described enhancement mode JFET is equivalent two poles
Tube enhancement type field effect transistor JFET, and one with integrated described metal oxide semiconductor field effect tube MOSFET and described etc.
The semiconductor device chip of effect diode enhancement mode field effect transistor JFET includes:
The common semiconductor substrate district (CSSR) of the first conduction type；
One MOSFET element district being positioned at top, common semiconductor substrate district, has:
Common semiconductor substrate district is as its MOSFET drain region；
The MOSFET body zone of at least one the second conduction type, a MOSFET gate regions and first conduction type
MOSFET source district is positioned at top, MOSFET drain region；And
One equivalent diode enhancement mode JFET (DCE-JFET) device region is positioned at top, common semiconductor substrate district, has:
Common semiconductor substrate district is as its equivalent diode enhancement mode JFET drain region；
The equivalent diode enhancement mode JFET gate region of at least two the second conduction type is in equivalent diode enhancement mode JFET
Top, drain region, and laterally it is separated from each other an equivalent diode enhancement mode along the principal plane in common semiconductor substrate district
The gate pitch of JFET；
The equivalent diode enhancement mode JFET source area of at least one the first conduction type is positioned at top, common semiconductor substrate district
And between equivalent diode enhancement mode JFET gate regions, wherein equivalent diode enhancement mode JFET source area is shorted to equivalence two
Tube enhancement type JFET gate regions, pole；And
MOSFET element drain region is connected in series to the drain region of equivalent diode enhancement mode JFET device by common semiconductor substrate district.
2. the battery charger described in claim 1, it is characterised in that described semiconductor device chip also includes:
Two conduction node terminal-S and terminal-D；Wherein:
One is connected to MOSFET source district, as terminal-S；And
One contacts with described equivalent diode enhancement mode JFET gate regions and equivalent diode enhancement mode JFET source area,
As terminal-D.
3. the battery charger described in claim 1, it is characterised in that the conduction of equivalent diode enhancement mode JFET gate regions
Equivalence two between level, equivalent diode enhancement mode JFET gate regions and below equivalent diode enhancement mode JFET source area
Conductivity level and the equivalent diode enhancement mode JFET gate pitch of pole tube enhancement type JFET channel region are all pre-in each of which
If configuring in level, so that equivalent diode enhancement mode JFET device is as equivalent diode enhancement mode JFET, have
At a fairly low forward voltage Vf and at a fairly low reverse leakage current, wherein equivalent diode enhancement mode JFET device is described
Vf is in the range of 0.3V-0.5V, more much lower than the 0.7V-1V of the Vf of PN junction diode, and described reverse leakage current is permissible
Comparable with the reverse leakage current of PN junction diode.
4. the battery charger described in claim 1, it is characterised in that choose the dopant material of MOSFET body zone, concentration
And the degree of depth, make them identical with equivalent diode enhancement mode JFET gate regions；And
Choose the dopant material in MOSFET source district, concentration and the degree of depth, make they and equivalent diode enhancement mode JFET source area
Identical.
5. the battery charger described in claim 2, it is characterised in that choose MOSFET top source electrode and top grid
The material of electrode and thickness, make them identical with top equivalent diode enhancement mode JFET electrode.
6. the battery charger described in claim 1, it is characterised in that described MOSFET gate regions is configured to trench gate
Pole, extends downwardly in MOSFET body zone and common semiconductor substrate district.
7. the battery charger described in claim 1, it is characterised in that described MOSFET gate regions is configured to planar gate
Pole, is positioned at above MOSFET body zone, MOSFET source district is bridged to common semiconductor substrate district.
8. the battery charger described in claim 1, it is characterised in that common semiconductor substrate district includes one first conduction
The upper strata of type, is positioned at above the lower substrate layer of first conduction type, the conduction on the upper strata in common semiconductor substrate district
Rate is lower than the conductivity of lower substrate layer.
9. the battery charger described in claim 1, it is characterised in that the first described conduction type is P-type, described
Second conduction type is N-type, and described semiconductor device chip makes a P-passage device.
10. the battery charger described in claim 1, the first wherein said conduction type is N-type, and described second is led
Electricity type is P-type, and described semiconductor device chip makes a N-passage device.
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| CN201410084356.8A CN104009518B (en) | 2011-09-26 | 2011-09-26 | Battery charger |
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| CN201410084356.8A CN104009518B (en) | 2011-09-26 | 2011-09-26 | Battery charger |
| CN201110306022.7A CN102437187B (en) | 2010-09-29 | 2011-09-26 | Semiconductor device die with integrated MOSFET and low forward voltage diode-connected enhancement mode JFET and method |
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Effective date of registration: 20200429 Address after: Ontario, Canada Patentee after: World semiconductor International Limited Partnership Address before: 475 oakmead Avenue, Sunnyvale, California 94085, USA Patentee before: Alpha and Omega Semiconductor Inc. |