CN104007571A - Array base plate and manufacture method thereof - Google Patents
Array base plate and manufacture method thereof Download PDFInfo
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- CN104007571A CN104007571A CN201410244058.0A CN201410244058A CN104007571A CN 104007571 A CN104007571 A CN 104007571A CN 201410244058 A CN201410244058 A CN 201410244058A CN 104007571 A CN104007571 A CN 104007571A
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- layer
- hole
- terminal
- data line
- quarter
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- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 46
- 239000002184 metal Substances 0.000 claims abstract description 46
- 238000009413 insulation Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 230000004888 barrier function Effects 0.000 claims description 44
- 230000000452 restraining effect Effects 0.000 claims description 44
- 239000012212 insulator Substances 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 16
- 230000008021 deposition Effects 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 7
- 238000003384 imaging method Methods 0.000 abstract description 4
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 abstract 1
- 239000004973 liquid crystal related substance Substances 0.000 description 15
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 238000010586 diagram Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 230000010287 polarization Effects 0.000 description 2
- 230000001737 promoting effect Effects 0.000 description 2
- 239000003086 colorant Substances 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses an array base plate. The array base plate comprises a substrate base plate (1), a first metal layer (2), a JAS layer (3) and an ITO (Indium Tin Oxide) electrode layer (4), wherein the JAS layer (3) and the ITO electrode layer (4) are positioned on a source drain insulation layer; a first metal layer (2) forms data line terminals and scanning line terminals in an array manufacture procedure. The array base plate is characterized in that hole etching baffling layers (5) positioned between a grid electrode insulation layer (7) and the source drain electrode insulation layer are formed above hole etching parts at the data line terminals and the scanning line terminals; the residual ITO electrodes that are produced by the ITO electrode layer (4) at the side edge of the JAS layer (3) during imaging the ITO electrode layer (4) can be remained on the hole etching baffling layers (5) through the hole etching baffling layers (5). According to the array base plate, the hole etching baffling layers arranged enable the ITO electrodes that are residual at the side edge of the JAS layer during imaging the ITO electrode layer to be remained only on the hole etching baffling layers, and thus short circuit generated between the data line terminals or the scanning line terminals can be avoided.
Description
Technical field
The present invention relates to liquid crystal display manufacturing technology field, specifically a kind of terminal by the first metal layer is carved above position, hole and is added and carve array base palte and the manufacture method thereof that restraining barrier, hole prevents the short-circuit of terminals.
Background technology
Traditional CRT monitor relies on the fluorescent powder that cathode-ray tube (CRT) electron emission clashes on screen to show image, but the principle of liquid crystal display is completely different.Conventionally, liquid crystal display (LCD) device has upper substrate and infrabasal plate, have each other certain intervals and mutually over against.Be formed on a plurality of electrodes on two substrates mutually over against.Liquid crystal is clipped between upper substrate and infrabasal plate.Voltage is applied on liquid crystal by the electrode on substrate, thereby the arrangement that then changes liquid crystal molecule according to acted on voltage shows image, because liquid crystal indicator utilizing emitted light not as mentioned above, and it needs light source to show image.Therefore, liquid crystal indicator has and is positioned at liquid crystal panel backlight below.Thereby control from the light quantity of backlight incident and show image according to the arrangement of liquid crystal molecule.Between two polaroids of this liquid crystal display, accompany glass substrate, colored filter, electrode, liquid crystal layer and transistor film, liquid crystal molecule is the material with refractive index and dielectric constant anisotropy.The light that backlight sends, through lower polaroid, becomes the polarized light with certain polarization direction.Institute's making alive between transistor controls electrode, and this voltage acts on the polarization direction that liquid crystal is controlled polarized light, polarized light forms monochromatic polarized light after seeing through corresponding color film chromatograph, if polarized light can penetrate upper strata polaroid, demonstrates corresponding color; Electric field intensity is different, and the deflection angle of liquid crystal molecule is also different, and the light intensity seeing through is different, and the brightness of demonstration is also different.The combination of the different light intensity by three kinds of colors of RGB shows motley image.
Terminal on array base palte is for connecting the interface of sweep trace, data line and external drive IC.Generally on array base palte, sweep trace terminal and data line terminal can be set, because data line can be generally several times of sweep trace, so data line terminal quantity can be more than sweep trace terminal, and interval is less, data line terminal spacing is 12.5um, sweep trace terminal pitch is 27.5um, and because data line terminal interval is little, the probability being short-circuited is also relatively large.Portion of terminal essential structure covers ITO above being generally strip sweep trace, and rear extended meeting connects with corresponding COF by crimping engineering.
In high opening design, can on SD insulation course, make organic insulator (hereinafter referred to as JAS layer), can effectively improve aperture opening ratio.JAS layer is organic material layer more than 2um.In JAS machine portion of terminal, can JAS layer and insulation course be removed by carving hole engineering, expose data line terminal and sweep trace terminal, then make ITO electrode.But now to cause photoresist that exposure occurs insufficient residual due to the Gao Duan missionary society at JAS layer edge, cause between terminal ITO electrode layer (transparent electrode layer) residual and cause the short-circuit of terminals.As shown in Figure 1, while using JAS material, the bad phenomenon that terminal place is short-circuited, main manifestations is that the ITO electrode between terminal occurs residual.As shown in Figure 2, the array base palte that is patterned into of ITO electrode layer 4 forms last step, in this step, forms pixel electrode, contact hole electrode and terminal electrode; First be on array base palte, to form ITO electrode layer 4 figures of whole, be then coated with photoresist 6.As shown in Figure 3, photoresist 6 is carried out to exposure imaging, due to JAS material thicker (general 2-3um) thus thicker with respect to other places at the photoresist 6 of JAS layer 3 bottom margin, cannot expose fully, cause occurring that photoresist 6 is residual when developing.As shown in Figure 4, while carrying out ITO electrode layer 4 graphical, due to the protection of photoresist 6, the ITO electrode material at JAS layer 3 edge cannot be etched away, and left behind, and this has caused the ITO electrode between terminal to connect short circuit.As shown in Figure 5, be the signal of interface, B-B place, between terminal, the residual short-circuit of terminals that causes of ITO electrode occurs.
Summary of the invention
The object of the invention is the problem existing for prior art, provide a kind of and carve above position, hole and add and carve array base palte and the manufacture method thereof that restraining barrier, hole prevents the short-circuit of terminals by the terminal at the first metal layer.
The object of the invention is to solve by the following technical programs:
A kind of array base palte, comprise underlay substrate, the first metal layer, be positioned at JAS layer and ITO electrode layer on source-drain electrode insulation course, in array processing procedure, by the first metal layer, form data line terminal and sweep trace terminal, it is characterized in that: above the position, hole at quarter of data line terminal and sweep trace terminal, be provided with the restraining barrier, hole at quarter between gate insulator and source-drain electrode insulation course, so that ITO electrode layer is positioned at residual being present in that the ITO electrode layer at JAS layer edge produces when graphical, carve on restraining barrier, hole.
Between described restraining barrier, hole at quarter and the first metal layer, there is gate insulator.
Described restraining barrier, hole at quarter is the second metal level or semiconductor active layer.
Described restraining barrier, hole at quarter covers the top at the position, hole at quarter of data line terminal and sweep trace terminal.
Described restraining barrier, hole at quarter is continuous type pattern or discontinuous form pattern.
The width on the restraining barrier, hole at quarter of continuous type pattern is not less than the width of data line terminal and sweep trace terminal.
The width on the restraining barrier, hole at quarter of discontinuous form pattern is not less than the width of any data line terminal and sweep trace terminal.
The bore edges at the position, hole at quarter of described restraining barrier, hole at quarter and data line terminal and sweep trace terminal intersects.
A manufacture method for array base palte, is characterized in that: this manufacture method comprises that step is as follows:
(a), on underlay substrate, form the first metal layer, by the first metal layer, form sweep trace, grid and data line terminal, sweep trace terminal;
(b), on the first metal layer, deposit gate insulator;
(c), deposited semiconductor active layer on gate insulator;
(d), on semiconductor active layer, form the second metal level, by the second metal level, form data line, source-drain electrode, and semiconductor active layer or the second metal level top that covers the position, hole at quarter of data line terminal and sweep trace terminal forms and carves restraining barrier, hole;
(e) on the second metal level, form source-drain electrode insulation course;
(f) on source-drain electrode insulation course, form JAS layer;
(g) data line terminal and sweep trace terminal, source-drain electrode are carved respectively to hole;
(h) on JAS layer, deposit ITO electrode layer and carry out the graphical technique of ITO electrode layer, forming pixel electrode, contact hole electrode and terminal electrode, completing the manufacture process of array base palte.
The present invention has the following advantages compared to existing technology:
The present invention adds restraining barrier, hole at quarter above carving position, hole by the terminal at the first metal layer, make in the patterned process of ITO electrode layer, when JAS layer edge generation ITO electrode is residual, residual ITO electrode only can be present in to be carved on restraining barrier, hole, and carve between restraining barrier, hole and the first metal layer, there is gate insulator, thus avoid between data line terminal or sweep trace terminal between produce short circuit; This restraining barrier, hole at quarter can be realized by the extension of the second metal level or semiconductor active layer, and technological process is clear and operation easier is little, suitable promoting the use of.
Accompanying drawing explanation
Structural representation when accompanying drawing 1 is data line terminal on the array base palte of JAS machine in prior art or the sweep trace short-circuit of terminals;
Structural representation when accompanying drawing 2 was coated with photoresist for A-A cross section in accompanying drawing 1 before ITO electrode layer is graphical;
Accompanying drawing 3 is the structural representation after the photoresist exposure imaging in accompanying drawing 2;
Accompanying drawing 4 is the structural representation after ITO electrode layer etching in accompanying drawing 3;
Accompanying drawing 5 is B-B cross section structure schematic diagram in accompanying drawing 1;
Accompanying drawing 6 is the array base-plate structure schematic diagram of the embodiment of the present invention one;
Accompanying drawing 7 is the A-A cross section structure schematic diagram of accompanying drawing 6;
Accompanying drawing 8 is the array base-plate structure schematic diagram of the embodiment of the present invention two.
Wherein: 1-underlay substrate; 2-the first metal layer; 3-JAS layer; 4-ITO electrode layer; 5-carve restraining barrier, hole; 6-photoresist; 7-gate insulator.
Embodiment
Below in conjunction with accompanying drawing and embodiment, the present invention is further illustrated.
As shown in Fig. 6-8: a kind of array base palte, array base palte making step is: the first step forms the first metal layer 2 on underlay substrate 1, second step forms gate insulator 7, the 3rd step forms semiconductor active layer, the 4th step forms the second metal level, and forms source-drain electrode, and the 5th step forms source-drain electrode insulation course, the 6th step forms JAS layer 3, the 7th step forms contact hole, and the 8th step forms ITO electrode layer 4.
In array processing procedure, by the first metal layer 2, form data line terminal and sweep trace terminal, in order to prevent that the ITO electrode between terminal from existing the residual short-circuit of terminals that causes, above the position, hole at quarter of data line terminal and sweep trace terminal, be provided with the restraining barrier, hole at quarter 5 between gate insulator 7 and source-drain electrode insulation course, so that being positioned at residual being present in that the ITO electrode layer 4 at JAS layer 3 edge produces when graphical, carves on restraining barrier, hole 5 ITO electrode layer 4, owing to carving between restraining barrier, hole 5 and the first metal layer 2, there is gate insulator 7, thereby avoid between data line terminal or sweep trace terminal between produce short circuit.Above-mentioned restraining barrier, hole at quarter 5 cover data line terminal and sweep trace terminal position, hole at quarter top and carve restraining barrier, hole 5 and intersect with the bore edges at the position, hole at quarter of data line terminal and sweep trace terminal, carve in addition restraining barrier, hole 5 and can be arranged to continuous type pattern or discontinuous form pattern, when quarter, restraining barrier, hole 5 was continuous type pattern, the width of carving restraining barrier, hole 5 is not less than the width of data line terminal and sweep trace terminal; When quarter, restraining barrier, hole 5 was discontinuous form pattern, the width of carving restraining barrier, hole 5 is not less than the width of any data line terminal and sweep trace terminal.This facilitates array processing procedure, and these restraining barrier, hole at quarter 5 extensions by the second metal level or semiconductor active layer can realize, and restraining barrier, hole 5 can be the second metal level or semiconductor active layer at once.
The step of the manufacture method of above-mentioned array base palte is as follows: (a), on underlay substrate 1, form the first metal layer 2, by the first metal layer 2, form sweep trace, grid and data line terminal, sweep trace terminal; (b), on the first metal layer 2, deposit gate insulator 7; (c), deposited semiconductor active layer on gate insulator 7; (d), on semiconductor active layer, form the second metal level, by the second metal level, form data line, source-drain electrode, and semiconductor active layer or the second metal level top that covers the position, hole at quarter of data line terminal and sweep trace terminal forms and carves restraining barrier, hole 5; (e) on the second metal level, form source-drain electrode insulation course; (f) on source-drain electrode insulation course, form JAS layer 3; (g) data line terminal and sweep trace terminal, source-drain electrode are carved respectively to hole; (h) on JAS layer 3, deposit ITO electrode layer 4 and carry out the graphical technique of ITO electrode layer, forming pixel electrode, contact hole electrode and terminal electrode, completing the manufacture process of array base palte.
The present invention adds restraining barrier, hole 5 at quarter above carving position, hole by the terminal at the first metal layer 2, make in the patterned process of ITO electrode layer 4, when JAS layer 3 edge ITO electrode occur when residual, residual ITO electrode only can be present in to be carved on restraining barrier, hole 5, and carve between restraining barrier, hole 5 and the first metal layer 2, there is gate insulator 7, thus avoid between data line terminal or sweep trace terminal between produce short circuit; These restraining barrier, hole at quarter 5 extensions by the second metal level or semiconductor active layer can realize, and technological process is clear and operation easier is little, suitable promoting the use of.
Above embodiment only, for explanation technological thought of the present invention, can not limit protection scope of the present invention with this, every technological thought proposing according to the present invention, and any change of doing on technical scheme basis, within all falling into protection domain of the present invention; The technology that the present invention does not relate to all can be realized by prior art.
Claims (9)
1. an array base palte, comprise the first metal layer (2), be positioned at JAS layer (3) and ITO electrode layer (4) on source-drain electrode insulation course, in array processing procedure, by the first metal layer (2), form data line terminal and sweep trace terminal, it is characterized in that: above the position, hole at quarter of data line terminal and sweep trace terminal, be provided with the restraining barrier, hole at quarter (5) being positioned between gate insulator (7) and source-drain electrode insulation course, so that being positioned at residual being present in that the ITO electrode layer (4) at JAS layer (3) edge produces when graphical, carves on restraining barrier, hole (5) ITO electrode layer (4).
2. array base palte according to claim 1, is characterized in that: between described restraining barrier, hole at quarter (5) and the first metal layer (2), have gate insulator (7).
3. array base palte according to claim 1 and 2, is characterized in that: described restraining barrier, hole at quarter (5) is the second metal level or semiconductor active layer.
4. array base palte according to claim 1 and 2, is characterized in that: described restraining barrier, hole at quarter (5) covers the top at the position, hole at quarter of data line terminal and sweep trace terminal.
5. array base palte according to claim 1 and 2, is characterized in that: described restraining barrier, hole at quarter (5) is continuous type pattern or discontinuous form pattern.
6. array base palte according to claim 5, is characterized in that: the width on the restraining barrier, hole at quarter (5) of continuous type pattern is not less than the width of data line terminal and sweep trace terminal.
7. array base palte according to claim 5, is characterized in that: the width on the restraining barrier, hole at quarter (5) of discontinuous form pattern is not less than the width of any data line terminal and sweep trace terminal.
8. array base palte according to claim 5, is characterized in that: intersect with the bore edges at the position, hole at quarter of data line terminal and sweep trace terminal on described restraining barrier, hole at quarter (5).
9. a manufacture method for array base palte, is characterized in that: this manufacture method comprises that step is as follows:
(a), at the upper the first metal layer (2) that forms of underlay substrate (1), by the first metal layer (2), form sweep trace, grid and data line terminal, sweep trace terminal;
(b), at the upper deposition of the first metal layer (2) gate insulator (7);
(c), at the upper deposited semiconductor active layer of gate insulator (7);
(d), on semiconductor active layer, form the second metal level, by the second metal level, form data line, source-drain electrode, and semiconductor active layer or the second metal level top that covers the position, hole at quarter of data line terminal and sweep trace terminal forms and carves restraining barrier, hole (5);
(e) on the second metal level, form source-drain electrode insulation course;
(f) on source-drain electrode insulation course, form JAS layer (3);
(g) data line terminal and sweep trace terminal, source-drain electrode are carved respectively to hole;
(h) at JAS layer (3), above deposit ITO electrode layer (4) and carry out the graphical technique of ITO electrode layer, forming pixel electrode, contact hole electrode and terminal electrode, completing the manufacture process of array base palte.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410244058.0A CN104007571B (en) | 2014-06-04 | 2014-06-04 | Array base plate and manufacture method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410244058.0A CN104007571B (en) | 2014-06-04 | 2014-06-04 | Array base plate and manufacture method thereof |
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| Publication Number | Publication Date |
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| CN104007571A true CN104007571A (en) | 2014-08-27 |
| CN104007571B CN104007571B (en) | 2017-01-18 |
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| CN201410244058.0A Expired - Fee Related CN104007571B (en) | 2014-06-04 | 2014-06-04 | Array base plate and manufacture method thereof |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106648250A (en) * | 2016-12-30 | 2017-05-10 | 南京中电熊猫液晶显示科技有限公司 | In-Cell touch control panel and manufacturing method thereof |
| CN107367771A (en) * | 2017-07-11 | 2017-11-21 | 中国科学院电子学研究所 | Electrochemistry geophone sensitive electrode and preparation method thereof |
| WO2018218987A1 (en) * | 2017-06-02 | 2018-12-06 | Boe Technology Group Co., Ltd. | Display substrate, display apparatus, and method of fabricating display substrate |
| CN110109573A (en) * | 2019-05-27 | 2019-08-09 | 昆山龙腾光电有限公司 | Touch control component and touch-control display panel |
| CN110221488A (en) * | 2018-03-02 | 2019-09-10 | 群创光电股份有限公司 | Display device |
| CN110488525A (en) * | 2019-08-30 | 2019-11-22 | 厦门天马微电子有限公司 | Display panel and display device |
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| CN110488525B (en) * | 2019-08-30 | 2021-12-17 | 厦门天马微电子有限公司 | Display panel and display device |
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| Publication number | Publication date |
|---|---|
| CN104007571B (en) | 2017-01-18 |
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