CA2477763A1 - Methods and apparatus for fabricating chip-on-board modules - Google Patents
Methods and apparatus for fabricating chip-on-board modules Download PDFInfo
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- CA2477763A1 CA2477763A1 CA002477763A CA2477763A CA2477763A1 CA 2477763 A1 CA2477763 A1 CA 2477763A1 CA 002477763 A CA002477763 A CA 002477763A CA 2477763 A CA2477763 A CA 2477763A CA 2477763 A1 CA2477763 A1 CA 2477763A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
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- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
- H05K1/029—Programmable, customizable or modifiable circuits having a programmable lay-out, i.e. adapted for choosing between a few possibilities
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10159—Memory
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- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/16—Inspection; Monitoring; Aligning
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- H05K3/22—Secondary treatment of printed circuits
- H05K3/225—Correcting or repairing of printed circuits
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Abstract
A method of assembling a Chip-on-Board memory module as shown in Fig. 1, the method may be divided into several area or steps, mounting (step 100), patching (step 110), testing (step 120), and covering (step 130). During mounting (step 100), preferably, at least one unpackaged chip is mounted on a printing circuit board. In some embodiments, a selectively settable material may used to mount unpackaged memory parts. When mounting die on PC (step 101 ), a ring of selectively settable material is preferably used to surround the d ie and hold the die in place. Once mounted the alignment of each unpackaged chi p may be adjusted (step 102), after which the ring selectively settable materi al disposed around the chip is cured or hardened (step 103). The hardened ring around each die keeps the die in place. In some embodiments, the ring is higher than the die it surround to facilitate the addition of bond wires.</S DOAB>
Description
TITLE METHODS AND APPARATUS FOR FABRICATING CHIP-ON-BOARD MODULES
TEC~CAL FIELD
Selected embodiments of the present invention relate to electronic logic modules that use unpackaged die. More specifically, embodiments of the present invention relate to fabrication processes for Chip-on-Board modules.
BACKGROUND
to Semiconductor manufacturing processes have become increasingly more complex.
From the beginning with the creation of discrete transistors and other semiconductor devices through subsequent medium and large scale integrated devices, the number of transistors or independent elements which can fit on to a semiconductor chip has grown exponentially each year. For example, the first integrated processors comprised on the order of 2300 transistors.
i5 A recently announced integrated circuit processor comprises more than 220 million transistors. Other circuits are projected to contain over 1 billion transistors in the foreseeable future.
This continued exponential growth of semiconductor manufacturing processes, while contributing to the greatly decreased costs of individual semiconductor devices and products a o has also exacerbated many production and testing problems associated with commercial semiconductor manufacturing processes. The substantial increase in the density of electronic circuits in the semiconductor integrated manufacturing processes has resulted in the production of many more less-than-perfect semiconductor die or chips. This increase in the production of less than perfect chips and die has spawned a new market for electronic z s component sellers who find ways to utilize less-than-perfect chips or die to assemble working components.
The many enhancements and advancements in semiconductor manufacturing and packaging processes have resulted in the creation of a number of price sensitive semiconductor product applications for electronic parts sellers. In particular, these electronic parts sellers develop low cost memory modules or other semiconductor devices through the utilization of cost effective processes, including less-than-perfect semiconductor parts.
One method of building memory modules using partially-defective memory parts may use unpackaged semiconductor memories, or die, for all or part of the memory parts used to s build a memory module. Using die instead of packaged parts increases the complexity of the fabrication process, but provides substantial savings by eliminating the cost of packaging parts. The use of unpackaged parts to build memory modules, or other electronics, is called Chip-on-Board, or COB. In recent years, improvements in semiconductor memory technology and manufacturing have led to the creation of new memory products and patching io techniques implemented using a Chip-on-Board process.
While the process used to assemble Chip-on-Board modules, refernng to the process disclosed in U.S. Patent 6,119,049, is effective, modern adhesives provide new methods of mounting unpackaged parts. In particular, an improvement in the yield of Chip-on-Board memory modules can be attained by using one or more selectively settable liquids. A
i5 standard burn-in process used to test electronic memory modules (including Chip-on-Board modules) under high heat and high voltage stress may frequently cause a number of failed and broken chips, due mostly to a difference in the thermal expansion coefficients of the chips and the circuit board base. By using one or more selectively settable liquids to provide a thermal and physical buffer (pad) between an unpackaged part and a printed circuit board, z o heat expansion stress can be reduced.
In summary, there is an ongoing need in the art for means and methods of producing low cost semiconductor devices, particularly memory modules. Related to this is an ongoing need to make use of semiconductor devices that are partially-defective so that such device are not completely wasted. The use of unpackaged parts, including new mounting techniques, is z 5 desirable to provide important cost saving practices.
SUMMARY OF SELECTED EMBODIMENTS
Among many possible embodiments, the present invention provides a number of Chip-on-Board memory modules fabricated using a variety of patching methods and a new and novel mounting process. Each Chip-on-Board memory module preferably uses partially-defective memory parts or a combination of partially-defective and flawless memory parts.
Another embodiment of the present invention includes mounting unpackaged electronic parts, not limited to memory parts, using one or more selectively settable liquids.
s By tacking an unpackaged electronic part to a circuit board base, hereafter described as a PC
board, using one or more selectively settable liquids, part adjustments such as repositioning, removal, and bonding wire installation are greatly expedited and facilitated.
Another embodiment of the present invention encompasses a variety of memory modules, including, Dynamic Random Access Memory (DRAM), Synchronous Dynamic io Random Access Memory (SDRAM), Double Data Rate (DDR), etc., created using the presently described Chip-on-Board fabrication method. These modules may use a number of patching methods, e.g., the methods described in US Patent 6,119,049.
Additionally, new patching methods are described in the above referenced patent application, "Methods and Apparatus for Patching Memory Modules," which is co-pending and of common ownership i5 with the present application by US Patent No. 6,119,049 inventor, Charles I. Peddle, and may be used to fabricate the Chip-on-Board memory modules.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings illustrate various embodiments of the present invention a o and are a part of the specification. Together with the following description, the drawings demonstrate and explain the principles of the present invention. The illustrated embodiments are examples of the present invention and do not limit the scope of the invention.
Fig. 1 is a flowchart illustrating a method of manufacturing Chip-on-Board memory modules according to one embodiment of the present invention.
2 5 Fig. 2 is a schematic diagram illustrating a memory part that may be used to fabricate a memory module according to one embodiment of the present invention.
Fig. 3 is an illustration of a top-view of an unpackaged semiconductor chip with inline central pads connected to a PC board base according to one embodiment of the present invention.
TEC~CAL FIELD
Selected embodiments of the present invention relate to electronic logic modules that use unpackaged die. More specifically, embodiments of the present invention relate to fabrication processes for Chip-on-Board modules.
BACKGROUND
to Semiconductor manufacturing processes have become increasingly more complex.
From the beginning with the creation of discrete transistors and other semiconductor devices through subsequent medium and large scale integrated devices, the number of transistors or independent elements which can fit on to a semiconductor chip has grown exponentially each year. For example, the first integrated processors comprised on the order of 2300 transistors.
i5 A recently announced integrated circuit processor comprises more than 220 million transistors. Other circuits are projected to contain over 1 billion transistors in the foreseeable future.
This continued exponential growth of semiconductor manufacturing processes, while contributing to the greatly decreased costs of individual semiconductor devices and products a o has also exacerbated many production and testing problems associated with commercial semiconductor manufacturing processes. The substantial increase in the density of electronic circuits in the semiconductor integrated manufacturing processes has resulted in the production of many more less-than-perfect semiconductor die or chips. This increase in the production of less than perfect chips and die has spawned a new market for electronic z s component sellers who find ways to utilize less-than-perfect chips or die to assemble working components.
The many enhancements and advancements in semiconductor manufacturing and packaging processes have resulted in the creation of a number of price sensitive semiconductor product applications for electronic parts sellers. In particular, these electronic parts sellers develop low cost memory modules or other semiconductor devices through the utilization of cost effective processes, including less-than-perfect semiconductor parts.
One method of building memory modules using partially-defective memory parts may use unpackaged semiconductor memories, or die, for all or part of the memory parts used to s build a memory module. Using die instead of packaged parts increases the complexity of the fabrication process, but provides substantial savings by eliminating the cost of packaging parts. The use of unpackaged parts to build memory modules, or other electronics, is called Chip-on-Board, or COB. In recent years, improvements in semiconductor memory technology and manufacturing have led to the creation of new memory products and patching io techniques implemented using a Chip-on-Board process.
While the process used to assemble Chip-on-Board modules, refernng to the process disclosed in U.S. Patent 6,119,049, is effective, modern adhesives provide new methods of mounting unpackaged parts. In particular, an improvement in the yield of Chip-on-Board memory modules can be attained by using one or more selectively settable liquids. A
i5 standard burn-in process used to test electronic memory modules (including Chip-on-Board modules) under high heat and high voltage stress may frequently cause a number of failed and broken chips, due mostly to a difference in the thermal expansion coefficients of the chips and the circuit board base. By using one or more selectively settable liquids to provide a thermal and physical buffer (pad) between an unpackaged part and a printed circuit board, z o heat expansion stress can be reduced.
In summary, there is an ongoing need in the art for means and methods of producing low cost semiconductor devices, particularly memory modules. Related to this is an ongoing need to make use of semiconductor devices that are partially-defective so that such device are not completely wasted. The use of unpackaged parts, including new mounting techniques, is z 5 desirable to provide important cost saving practices.
SUMMARY OF SELECTED EMBODIMENTS
Among many possible embodiments, the present invention provides a number of Chip-on-Board memory modules fabricated using a variety of patching methods and a new and novel mounting process. Each Chip-on-Board memory module preferably uses partially-defective memory parts or a combination of partially-defective and flawless memory parts.
Another embodiment of the present invention includes mounting unpackaged electronic parts, not limited to memory parts, using one or more selectively settable liquids.
s By tacking an unpackaged electronic part to a circuit board base, hereafter described as a PC
board, using one or more selectively settable liquids, part adjustments such as repositioning, removal, and bonding wire installation are greatly expedited and facilitated.
Another embodiment of the present invention encompasses a variety of memory modules, including, Dynamic Random Access Memory (DRAM), Synchronous Dynamic io Random Access Memory (SDRAM), Double Data Rate (DDR), etc., created using the presently described Chip-on-Board fabrication method. These modules may use a number of patching methods, e.g., the methods described in US Patent 6,119,049.
Additionally, new patching methods are described in the above referenced patent application, "Methods and Apparatus for Patching Memory Modules," which is co-pending and of common ownership i5 with the present application by US Patent No. 6,119,049 inventor, Charles I. Peddle, and may be used to fabricate the Chip-on-Board memory modules.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings illustrate various embodiments of the present invention a o and are a part of the specification. Together with the following description, the drawings demonstrate and explain the principles of the present invention. The illustrated embodiments are examples of the present invention and do not limit the scope of the invention.
Fig. 1 is a flowchart illustrating a method of manufacturing Chip-on-Board memory modules according to one embodiment of the present invention.
2 5 Fig. 2 is a schematic diagram illustrating a memory part that may be used to fabricate a memory module according to one embodiment of the present invention.
Fig. 3 is an illustration of a top-view of an unpackaged semiconductor chip with inline central pads connected to a PC board base according to one embodiment of the present invention.
Fig. 4a is a perspective side view of a Chip-on-Board memory module according to one embodiment of the present invention.
Fig. 4b is a close-up cross-sectional view of an unpackaged part mounted to a PC
board according to one embodiment of the present invention.
s Fig. 5 is a block diagram illustrating a layout of major components of a Chip-on-Board memory module fabricated using patching networks according to one embodiment of the present invention.
Fig. 6 is an illustrative cross-sectional view of a shielded Chip-on-Board memory module according to one embodiment of the present invention.
1 o Fig. 7 is an illustrative top-view of a Chip-on-Board memory module according to one embodiment of the present invention.
Fig. 8 is an illustration of a top-view of an unpackaged semiconductor chip with pads connected to a PC board base, according to another embodiment of the present invention.
Fig. 9 is a flowchart illustrating a method of mounting unpackaged semiconductor i5 chips according to another embodiment of the present invention.
Throughout the drawings, identical reference numbers designate similar, but not necessarily identical, elements.
DETAILED DESCRIPTION OF SELECTED EMBODIMENTS
a o ~ Chip-on-Board memory modules fabricated using partially-defective memory parts or a combination of partially-defective and flawless memory parts are disclosed herein. A
combination of memory parts, which in one embodiment includes at least one unpackaged chip, are mounted on a printed circuit board and tested. By using one or more selectively settable liquids to mount unpackaged memory chips, a number of fabrication benefits are 25 facilitated, e.g., unpackaged chips are easily oriented, bonding wires are secured, memory chips may be removed if necessary, etc. A number of different circuit boards, memory parts, and patching techniques result in a variety of functional modules.
Additionally, a cover may be used as part of the module for aesthetic value and protection of fragile parts, leads, wires, etc.
Fig. 4b is a close-up cross-sectional view of an unpackaged part mounted to a PC
board according to one embodiment of the present invention.
s Fig. 5 is a block diagram illustrating a layout of major components of a Chip-on-Board memory module fabricated using patching networks according to one embodiment of the present invention.
Fig. 6 is an illustrative cross-sectional view of a shielded Chip-on-Board memory module according to one embodiment of the present invention.
1 o Fig. 7 is an illustrative top-view of a Chip-on-Board memory module according to one embodiment of the present invention.
Fig. 8 is an illustration of a top-view of an unpackaged semiconductor chip with pads connected to a PC board base, according to another embodiment of the present invention.
Fig. 9 is a flowchart illustrating a method of mounting unpackaged semiconductor i5 chips according to another embodiment of the present invention.
Throughout the drawings, identical reference numbers designate similar, but not necessarily identical, elements.
DETAILED DESCRIPTION OF SELECTED EMBODIMENTS
a o ~ Chip-on-Board memory modules fabricated using partially-defective memory parts or a combination of partially-defective and flawless memory parts are disclosed herein. A
combination of memory parts, which in one embodiment includes at least one unpackaged chip, are mounted on a printed circuit board and tested. By using one or more selectively settable liquids to mount unpackaged memory chips, a number of fabrication benefits are 25 facilitated, e.g., unpackaged chips are easily oriented, bonding wires are secured, memory chips may be removed if necessary, etc. A number of different circuit boards, memory parts, and patching techniques result in a variety of functional modules.
Additionally, a cover may be used as part of the module for aesthetic value and protection of fragile parts, leads, wires, etc.
The embodiments described involve an effective utilization of semiconductor chips or die which both benefit the semiconductor manufacturers by reducing their production losses and various electronic system manufacturers which are often able to utilize lower cost memory and subcomponents manufactured using less-than-flawless semiconductor memories.
s Fig. 1 is a flowchart illustrating a method of assembling a Chip-on-Board memory module. As shown in Fig. 1, the method may be divided into several areas or steps: mounting (step 100), patching (step 110), testing (step 120), and covering (step 130).
During mounting (step 100), preferably, at least one unpackaged chip is mounted on a printed circuit board. In some embodiments, a selectively settable material may be used to i o mount unpackaged memory parts. More specifically, selectively settable liquids, such as adhesives made by Dymax Corporation, are used, in some examples, to tack die to a PC
board.
While many types of adhesives may be used to tack unpackaged die to a PC
board, IJV material, i.e., material hardened by exposure to certain wavelengths of light, is used in i5 selected embodiments. When using UV material, different wavelengths of light may cause different levels of hardness. For example, light with 700 nm (nanometers) wavelength may cause a certain liquid UV material to thicken, while light at 1000 nm causes the UV material to permanently harden. Accordingly, tools that dispense UV material and emit light may be used in the process. Such tools include the PC-3D made by Dymax.
a o When mounting die on a PC board (step 101), a ring of selectively settable material is preferably used to surround the die and hold the die in place. Once mounted, the alignment of each unpackaged chip may be adjusted (step 102), after which the ring of selectively settable material disposed around the chip is cured or hardened (step 103). The hardened ring around each die keeps the die in place. In some embodiments, the ring is higher than the die it a s surrounds to facilitate the addition of bond wires.
A layer of selectively settable material is placed between each die and the PC
board.
In one embodiment, the same settable material that is used between each die and the PC board may also be used around each die or two different selectively settable materials may be used.
More specifically, the selectively settable material used between the die and the PC
3 o board should have a higher curing temperature than the material used around the die. This configuration allows the material around the die to be hardened, while the material between the die and the PC board remains liquid. For example, when using UV material, light at a specified wavelength will harden the ring around the die, while the material between the die and the PC board remains liquid. In other words, using two different materials allows a s memory part to be firmly tacked to the PC board, while being buffered, or padded, physically and thermally from the surface of the PC board to which it is mounted.
Alternatively, if the same selectively settable material is used underneath and around the die, care may be taken to harden only the outer ring of the selectively settable material.
A second ring (or layer) of selectively settable material may also be added (step 104) io on top of the first ring of selectively settable material. This second ring is used to capture the wires, known as bonding wires, which electrically connect the die to the conductive pads of the PC board. The wires may be captured by carefully placing the wires within the second ring while the selectively settable material is still manageable and then hardening the ring.
The use of the second ring prevents the wires from touching the die or other wires. After the i5 bonding wires are captured, the memory unit can be loaded into a bonding machine that locates each die and, using an automated program, bonds the wires to the contact pads on the die and the PC board (step 105).
After the wires are bonded, connecting the die to the module, a visual inspection of the wires is made (step 106). If there are any missing or broken wires (determination 107), a a o manual adjustment of the bonds (step 108) is used to correct the problem.
The unit is visually inspected again (step 107), and if there are no missing or broken wires (determination 107), a small amount of selectively settable material is placed over the wires and hardened (step 109).
Any packaged parts used on a Chip-on-Board memory module may be mounted by soldering the leads of the package to pads on the circuit board. Specific pads on the PC board a s are usually designed purposely for use with packaged or unpackaged parts.
As used herein, a "Chip-on-Board" PC board may contain any combination of pads utilizable for connecting memory devices to the PC board. Preferably, at least one set of pads is designed for use with an unpackaged part or device.
After the memory parts have been mounted (step 100), the patching process (step 110) 3 o begins. Preferably, the module is first tested (step 111 ) using a series of read/write functionality tests, and defective I/O lines are identified. If the defective parts can be patched (determination 112), the patching technique corresponding to the particular memory product and PC board layout is used to patch the defective parts (step 114). As herein above mentioned, the patching processes of US patent 6,119,049 and co-pending patent application, s "Method and Apparatus for Patching Memory Modules," may be used.
All patching techniques require the disconnection of failed I/O lines and the connection of other unused, functional I/O lines. The disconnection and connection may be accomplished by adding or removing solder, called solder-dots. Another alternative is to add or remove a jumper wires.
io If there are not enough bits to patch the defective parts (determination 111), one or more low value parts, i.e., parts with few operable I/O lines, must be replaced with higher value parts (step 113) to provide sufficient bits for a fully-functional module. As used herein, the "value" of a memory part refers to the proportion of functioning, as opposed to non-functioning, input/output lines. A higher value part, used to replace a low value part, must 15 pass through the mounting process (step 100) before the module can continue on to the patching process (step 110).
After a suitable combination of memory parts and patches provides a functional module, the module goes through a testing process (step 120). Preferably, the module is first placed under a high heat and high voltage test called burn-in (step 114). The burn-in test a o (step 114) accelerates the aging process of the electronics and may cause "early-life" failures to occur in the oven. If a fail occurs during burn-in (determination 122), the patching process (step 110), and if needed the mounting process (step 100), is repeated until a module passes the burn-in test (determination 122).
As indicated above, the uncured adhesive liquid that remains under a select memory 2 5 die serves as a thermal and physical buffer between the die and the PC
board. This buffer may be valuable during the burn-in test to prevent damage to the unit caused by unequal thermal expansion coefficients of the die and the PC board.
There are a number of commercial-ly available testers, which may be used to test memory in the form of die, chips (packaged parts), and modules. Such testers are commonly known in the art. Additionally, commercially available machines used for burn-in tests, bonding wire installation, etc., are commonly known in the art.
Once a module passes the burn-in test (determination 122), an industry standard parameter test, called a "four-corner" test, is performed (step 123), testing the combinations:
s high voltage/high signal level, high voltage/low signal level, low voltage/high signal level, and low voltage/low signal level. This test assures memory modules that pass a number of subsequent pattern tests (step 123) will run the same on any motherboard.
If the module fails either the parameter test or the pattern test (determination 124), the patching process (step 110) and testing process (step 120) are repeated until a module passes 1 o the parameter and pattern tests (determination 124).
If desired, a cover can then be added (step 131 ) to protect the memory parts and all exposed circuitry on the surface of the PC board. In some embodiments, the cover provides ESD (Electrostatic Discharge) protection to the module, but does not act as a heat sink, i.e., the cover does not touch the memory parts.
i5 The process of Fig. 1 may be carned out using automated machinery for fabrication, patching, and testing purposes. In one embodiment, automated machines are programmed to dispense one or more selectively settable liquids, mount memory parts to a PC
board, connect I/O bit lines to I/O output lines, perform functionality tests, attach the protective cover, etc.
In another embodiment, the dispensing of selectively settable liquids, mounting of memory z o parts to a PC board, connecting I/O bit lines to I/O output lines, performing functionality tests as described above, mounting a protective cover, etc., may be performed manually. Another embodiment of the Chip-on-Board fabrication process, shown in Fig. 1, uses a combination of automated and manual labor.
Fig. 2 is a schematic diagram of a memory part that may be used to build a memory z s module as described herein. As shown in Fig. 2, the memory part (200) may be represented by a block (201) and a number of labeled pins (202). The memory part itself (200) may be any size or shape, and the pins (202) may be located at any location on the surface of the semiconductor material from which the memory part (200) is made. There are many types of memory units and technologies, e.g., DRAM, SDRAM, Single Inline Memory Module 3 0 (SIMM), Dual Inline Memory Module (DIMM), BGA (Ball Grid Array), etc. In general, these memory units and technologies perform the same functions, and are described by Table 1.
Table 1 Symbol Type Description A[n:0] Input-Synchronous Pin definitions; a function of array size CLK Input-Clock Master Clock input CKE Input-Clock Enable Activates CLK when high, deactivates ~ when low RAS# Input-Synchronous Row address strobe CS# Input-Synchronous Selects chip when active CAS# Input-Synchronous Column address strobe WE# Input-Synchronous Write enable strobe DQM# Read mode - controls the data output DQML/H# Input-Synchronous buffers Write mode - masks data from being written DQ(x:0) Input/output-SynchronousData I/O pins Vcc, Vss Power pins Supply pins for the core VccQ, VssQ Power pins Supply pins for the output buffers As shown in Table 1, a variety of signals function together to read data and write data using a memory part (200). In particular, these signals allow a host device to activate a memory part (200), access a particular memory segment defined by row and column, write information to the memory cells, read information from the memory cells, etc.
io Fig. 3 is an illustration of a top-view of an unpackaged memory chip with in-line central pads connected to a printed circuit board base. As shown in Fig. 3, the input and output signals, e.g., the signals of Table 1, may be connected to a host device by bonding wires (303) between pads (304) of the unpackaged memory part (301) to pads (302) on a circuit board (305). The pads (302) of the circuit board (305) may be pre-wired to allow a i5 host device to effectively utilize the memory part (301). Specifically, the memory part (301) of Fig. 3 is an illustration of a physical embodiment of the memory part (200) schematic of Fig. 2 attached to a PC board. As illustrated, the pin numbers (202) of Fig.
2, representing particular signals, are also illustrated in Fig. 3.
Fig. 4a is a perspective side view of a Chip-on-Board memory module. As shown in Fig. 4a, an unpackaged memory part (402) is attached to a PC board (401), and wires (403) s connect the signals of the memory part (402) to the circuit board (401). In order to protect the wires (403) and unpackaged die (402), a selectively settable liquid (404) is dispensed around the die (402), wires (403), pads, etc., and hardened.
Fig. 4b is a close-up cross-sectional view of an unpackaged part mounted to a PC
board. As shown in Fig. 4b, an unpackaged part (402) is mounted to a PC board (401) using i o several sections of selectively settable material. A first section of selectively settable material (414) is placed between the die (402) and the PC board (401). In some embodiments, this first section of selectively settable material (414) remains liquid and provides a physical and thermal pad between the die (402) and PC board (401).
In order to tack the unpackaged part (402) to the PC board (401 ) a ring (or layer) of 15 selectively settable material (413) is placed around the perimeter of the unpackaged part (402). After the unpackaged part (402) is correctly oriented, the ring of selectively settable material (413) is hardened, thereby tacking the die (402) to the PC board (401). Additionally, the height of this first layer (413) may be higher than the die (402), thus allowing bonding wires to rest on the first layer (413) without touching the die (402).
a o After being hardened, the first ring of selectively settable material (413) may be covered with a second ring (or layer) of selectively settable material (416).
By placing part of the bonding wires (414) within the second layer of selectively settable material (416) and hardening the second layer (416), the wires (414) may be captured. By trapping the wires (414), the process of connecting bonding wires between a die (402) and a PC
board (401 ) is 25 greatly facilitated. During this process, care should be taken to separate each bonding wire (414) within the second ring of selectively settable material (416) to avoid shorting wires (414) together.
Fig. S is a block diagram illustrating a layout of major components of a Chip-on-Board memory module fabricated using patching networks. As shown in Fig. 5, the memory 3 o module (S00) comprises a printed circuit board (SO1), unpackaged memory parts (502), patching networks (503), resistor elements (504), capacitor elements (505), and interface connections (506). In another embodiment of the invention, a memory module (S00) may include packaged memory parts (507). Additionally, other electrical components, e.g., voltage regulators, inductors, phase locked loop units, differential clock drivers, etc., may be s mounted to the circuit board (501).
The printed circuit board (501) uses several different layers to create a complex network of electrical paths and connection points purposefully designed to allow the fabrication of a functional memory product using the patching networks (503) and partially-defective memory parts (502, 507).
s o There are a variety of memory products that may be assembled using the module (500) illustrated in Fig. S, e.g., Single Inline Memory Module (SIMM), Dual Inline Memory Module (D1MM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), etc. In general, memory parts, e.g., the memory part of Fig. 2, enable a host device to store and access one or more bits, i.e., an electronic, or logic, 1 i5 or 0. A single bit or group of bits, i.e., byte, word, etc., stored and accessible in memory, provide information significant to the host device and software applications running on the host device.
The I/O signals, e.g., DQ(x:0) in Table l, of the memory parts (502, 507; Fig.
s Fig. 1 is a flowchart illustrating a method of assembling a Chip-on-Board memory module. As shown in Fig. 1, the method may be divided into several areas or steps: mounting (step 100), patching (step 110), testing (step 120), and covering (step 130).
During mounting (step 100), preferably, at least one unpackaged chip is mounted on a printed circuit board. In some embodiments, a selectively settable material may be used to i o mount unpackaged memory parts. More specifically, selectively settable liquids, such as adhesives made by Dymax Corporation, are used, in some examples, to tack die to a PC
board.
While many types of adhesives may be used to tack unpackaged die to a PC
board, IJV material, i.e., material hardened by exposure to certain wavelengths of light, is used in i5 selected embodiments. When using UV material, different wavelengths of light may cause different levels of hardness. For example, light with 700 nm (nanometers) wavelength may cause a certain liquid UV material to thicken, while light at 1000 nm causes the UV material to permanently harden. Accordingly, tools that dispense UV material and emit light may be used in the process. Such tools include the PC-3D made by Dymax.
a o When mounting die on a PC board (step 101), a ring of selectively settable material is preferably used to surround the die and hold the die in place. Once mounted, the alignment of each unpackaged chip may be adjusted (step 102), after which the ring of selectively settable material disposed around the chip is cured or hardened (step 103). The hardened ring around each die keeps the die in place. In some embodiments, the ring is higher than the die it a s surrounds to facilitate the addition of bond wires.
A layer of selectively settable material is placed between each die and the PC
board.
In one embodiment, the same settable material that is used between each die and the PC board may also be used around each die or two different selectively settable materials may be used.
More specifically, the selectively settable material used between the die and the PC
3 o board should have a higher curing temperature than the material used around the die. This configuration allows the material around the die to be hardened, while the material between the die and the PC board remains liquid. For example, when using UV material, light at a specified wavelength will harden the ring around the die, while the material between the die and the PC board remains liquid. In other words, using two different materials allows a s memory part to be firmly tacked to the PC board, while being buffered, or padded, physically and thermally from the surface of the PC board to which it is mounted.
Alternatively, if the same selectively settable material is used underneath and around the die, care may be taken to harden only the outer ring of the selectively settable material.
A second ring (or layer) of selectively settable material may also be added (step 104) io on top of the first ring of selectively settable material. This second ring is used to capture the wires, known as bonding wires, which electrically connect the die to the conductive pads of the PC board. The wires may be captured by carefully placing the wires within the second ring while the selectively settable material is still manageable and then hardening the ring.
The use of the second ring prevents the wires from touching the die or other wires. After the i5 bonding wires are captured, the memory unit can be loaded into a bonding machine that locates each die and, using an automated program, bonds the wires to the contact pads on the die and the PC board (step 105).
After the wires are bonded, connecting the die to the module, a visual inspection of the wires is made (step 106). If there are any missing or broken wires (determination 107), a a o manual adjustment of the bonds (step 108) is used to correct the problem.
The unit is visually inspected again (step 107), and if there are no missing or broken wires (determination 107), a small amount of selectively settable material is placed over the wires and hardened (step 109).
Any packaged parts used on a Chip-on-Board memory module may be mounted by soldering the leads of the package to pads on the circuit board. Specific pads on the PC board a s are usually designed purposely for use with packaged or unpackaged parts.
As used herein, a "Chip-on-Board" PC board may contain any combination of pads utilizable for connecting memory devices to the PC board. Preferably, at least one set of pads is designed for use with an unpackaged part or device.
After the memory parts have been mounted (step 100), the patching process (step 110) 3 o begins. Preferably, the module is first tested (step 111 ) using a series of read/write functionality tests, and defective I/O lines are identified. If the defective parts can be patched (determination 112), the patching technique corresponding to the particular memory product and PC board layout is used to patch the defective parts (step 114). As herein above mentioned, the patching processes of US patent 6,119,049 and co-pending patent application, s "Method and Apparatus for Patching Memory Modules," may be used.
All patching techniques require the disconnection of failed I/O lines and the connection of other unused, functional I/O lines. The disconnection and connection may be accomplished by adding or removing solder, called solder-dots. Another alternative is to add or remove a jumper wires.
io If there are not enough bits to patch the defective parts (determination 111), one or more low value parts, i.e., parts with few operable I/O lines, must be replaced with higher value parts (step 113) to provide sufficient bits for a fully-functional module. As used herein, the "value" of a memory part refers to the proportion of functioning, as opposed to non-functioning, input/output lines. A higher value part, used to replace a low value part, must 15 pass through the mounting process (step 100) before the module can continue on to the patching process (step 110).
After a suitable combination of memory parts and patches provides a functional module, the module goes through a testing process (step 120). Preferably, the module is first placed under a high heat and high voltage test called burn-in (step 114). The burn-in test a o (step 114) accelerates the aging process of the electronics and may cause "early-life" failures to occur in the oven. If a fail occurs during burn-in (determination 122), the patching process (step 110), and if needed the mounting process (step 100), is repeated until a module passes the burn-in test (determination 122).
As indicated above, the uncured adhesive liquid that remains under a select memory 2 5 die serves as a thermal and physical buffer between the die and the PC
board. This buffer may be valuable during the burn-in test to prevent damage to the unit caused by unequal thermal expansion coefficients of the die and the PC board.
There are a number of commercial-ly available testers, which may be used to test memory in the form of die, chips (packaged parts), and modules. Such testers are commonly known in the art. Additionally, commercially available machines used for burn-in tests, bonding wire installation, etc., are commonly known in the art.
Once a module passes the burn-in test (determination 122), an industry standard parameter test, called a "four-corner" test, is performed (step 123), testing the combinations:
s high voltage/high signal level, high voltage/low signal level, low voltage/high signal level, and low voltage/low signal level. This test assures memory modules that pass a number of subsequent pattern tests (step 123) will run the same on any motherboard.
If the module fails either the parameter test or the pattern test (determination 124), the patching process (step 110) and testing process (step 120) are repeated until a module passes 1 o the parameter and pattern tests (determination 124).
If desired, a cover can then be added (step 131 ) to protect the memory parts and all exposed circuitry on the surface of the PC board. In some embodiments, the cover provides ESD (Electrostatic Discharge) protection to the module, but does not act as a heat sink, i.e., the cover does not touch the memory parts.
i5 The process of Fig. 1 may be carned out using automated machinery for fabrication, patching, and testing purposes. In one embodiment, automated machines are programmed to dispense one or more selectively settable liquids, mount memory parts to a PC
board, connect I/O bit lines to I/O output lines, perform functionality tests, attach the protective cover, etc.
In another embodiment, the dispensing of selectively settable liquids, mounting of memory z o parts to a PC board, connecting I/O bit lines to I/O output lines, performing functionality tests as described above, mounting a protective cover, etc., may be performed manually. Another embodiment of the Chip-on-Board fabrication process, shown in Fig. 1, uses a combination of automated and manual labor.
Fig. 2 is a schematic diagram of a memory part that may be used to build a memory z s module as described herein. As shown in Fig. 2, the memory part (200) may be represented by a block (201) and a number of labeled pins (202). The memory part itself (200) may be any size or shape, and the pins (202) may be located at any location on the surface of the semiconductor material from which the memory part (200) is made. There are many types of memory units and technologies, e.g., DRAM, SDRAM, Single Inline Memory Module 3 0 (SIMM), Dual Inline Memory Module (DIMM), BGA (Ball Grid Array), etc. In general, these memory units and technologies perform the same functions, and are described by Table 1.
Table 1 Symbol Type Description A[n:0] Input-Synchronous Pin definitions; a function of array size CLK Input-Clock Master Clock input CKE Input-Clock Enable Activates CLK when high, deactivates ~ when low RAS# Input-Synchronous Row address strobe CS# Input-Synchronous Selects chip when active CAS# Input-Synchronous Column address strobe WE# Input-Synchronous Write enable strobe DQM# Read mode - controls the data output DQML/H# Input-Synchronous buffers Write mode - masks data from being written DQ(x:0) Input/output-SynchronousData I/O pins Vcc, Vss Power pins Supply pins for the core VccQ, VssQ Power pins Supply pins for the output buffers As shown in Table 1, a variety of signals function together to read data and write data using a memory part (200). In particular, these signals allow a host device to activate a memory part (200), access a particular memory segment defined by row and column, write information to the memory cells, read information from the memory cells, etc.
io Fig. 3 is an illustration of a top-view of an unpackaged memory chip with in-line central pads connected to a printed circuit board base. As shown in Fig. 3, the input and output signals, e.g., the signals of Table 1, may be connected to a host device by bonding wires (303) between pads (304) of the unpackaged memory part (301) to pads (302) on a circuit board (305). The pads (302) of the circuit board (305) may be pre-wired to allow a i5 host device to effectively utilize the memory part (301). Specifically, the memory part (301) of Fig. 3 is an illustration of a physical embodiment of the memory part (200) schematic of Fig. 2 attached to a PC board. As illustrated, the pin numbers (202) of Fig.
2, representing particular signals, are also illustrated in Fig. 3.
Fig. 4a is a perspective side view of a Chip-on-Board memory module. As shown in Fig. 4a, an unpackaged memory part (402) is attached to a PC board (401), and wires (403) s connect the signals of the memory part (402) to the circuit board (401). In order to protect the wires (403) and unpackaged die (402), a selectively settable liquid (404) is dispensed around the die (402), wires (403), pads, etc., and hardened.
Fig. 4b is a close-up cross-sectional view of an unpackaged part mounted to a PC
board. As shown in Fig. 4b, an unpackaged part (402) is mounted to a PC board (401) using i o several sections of selectively settable material. A first section of selectively settable material (414) is placed between the die (402) and the PC board (401). In some embodiments, this first section of selectively settable material (414) remains liquid and provides a physical and thermal pad between the die (402) and PC board (401).
In order to tack the unpackaged part (402) to the PC board (401 ) a ring (or layer) of 15 selectively settable material (413) is placed around the perimeter of the unpackaged part (402). After the unpackaged part (402) is correctly oriented, the ring of selectively settable material (413) is hardened, thereby tacking the die (402) to the PC board (401). Additionally, the height of this first layer (413) may be higher than the die (402), thus allowing bonding wires to rest on the first layer (413) without touching the die (402).
a o After being hardened, the first ring of selectively settable material (413) may be covered with a second ring (or layer) of selectively settable material (416).
By placing part of the bonding wires (414) within the second layer of selectively settable material (416) and hardening the second layer (416), the wires (414) may be captured. By trapping the wires (414), the process of connecting bonding wires between a die (402) and a PC
board (401 ) is 25 greatly facilitated. During this process, care should be taken to separate each bonding wire (414) within the second ring of selectively settable material (416) to avoid shorting wires (414) together.
Fig. S is a block diagram illustrating a layout of major components of a Chip-on-Board memory module fabricated using patching networks. As shown in Fig. 5, the memory 3 o module (S00) comprises a printed circuit board (SO1), unpackaged memory parts (502), patching networks (503), resistor elements (504), capacitor elements (505), and interface connections (506). In another embodiment of the invention, a memory module (S00) may include packaged memory parts (507). Additionally, other electrical components, e.g., voltage regulators, inductors, phase locked loop units, differential clock drivers, etc., may be s mounted to the circuit board (501).
The printed circuit board (501) uses several different layers to create a complex network of electrical paths and connection points purposefully designed to allow the fabrication of a functional memory product using the patching networks (503) and partially-defective memory parts (502, 507).
s o There are a variety of memory products that may be assembled using the module (500) illustrated in Fig. S, e.g., Single Inline Memory Module (SIMM), Dual Inline Memory Module (D1MM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), etc. In general, memory parts, e.g., the memory part of Fig. 2, enable a host device to store and access one or more bits, i.e., an electronic, or logic, 1 i5 or 0. A single bit or group of bits, i.e., byte, word, etc., stored and accessible in memory, provide information significant to the host device and software applications running on the host device.
The I/O signals, e.g., DQ(x:0) in Table l, of the memory parts (502, 507; Fig.
5) are connected to one or more patching networks (503). The patching networks (503) comprise a a o collection of traces, etc., that allow one I/O signal line to be substituted with another I/O
signal line by manually or automatically changing the connection at one or more designated locations. Preferably, the patching solution uses more controllable memory parts (502, 507) than past patching solutions, e.g., the solutions presented in US Patent No.
signal line by manually or automatically changing the connection at one or more designated locations. Preferably, the patching solution uses more controllable memory parts (502, 507) than past patching solutions, e.g., the solutions presented in US Patent No.
6,119,049, to accomplish another process for patching memory parts. Some examples of patching z5 networks that may be used include 2-to-l, 4-to-1, and 8-to-1 patching networks as described in the co-pending patent application entitled, "New Methods and Apparatus for Patching Memory Modules."
Specifically, the memory parts (502, 507) shown in Fig. 5 allow the host device to provide a number of additional read/write control signals, e.g., DQM# in Table l, that 3 o eliminate the need to steer CAS (Column Address Select) and RAS (Row Address Select) signals to the memory parts (502, 507) used for patching. Instead, memory parts (502, 507) that are used to substitute failed memory outputs share the same read/write control signals as the memory part (502, 507) whose output they are replacing. Typical memory parts include 8Mx8, 16Mx8, and 32Mx8 memory parts commonly used in the art to build memory modules.
In operation of the memory module (500) fabricated using the patching networks (503), all I/O signals are sent through resistance networks (504) that provide a buffer between the memory part (502, 507) and the host device accessing the memory. Another component of the memory module (500) is a group of capacitors (505), which serve to stabilize the power io supply signal for each memory part (502, 507) by removing most high frequency electrical noise that may occur.
The interface connections (506) enable the memory module (500) to be conveniently plugged into an appropriate connection device of a host device. Through the connection, the host device is able to interact with the memory module (500) as herein above described, etc.
15 For more detailed information regarding patching networks (503) and processes, a reference may be made to US Patent No. 6,119,049 and the co-pending patent application, entitled, "Improved Patching Methods and Apparatus for Fabricating Memory Modules."
Fig. 6 is an illustrative cross-sectional view of a shielded Chip-on-Board memory module. As shown is Fig. 6, the module (600) uses a PC board (601) as a base.
Attached to 2o the PC board (601) are packaged parts (602) and unpackaged parts (603). In particular, any combination of packaged parts (602) and unpackaged parts (603) may be used. In some embodiments, at least one unpackaged part is used (603).
Covering the memory parts (and any other electronics, leads, wires, etc.) is a cover (804), which may be mounted to the PC board (601 ). In at least one embodiment, there is no z5 electrical or physical contact between the cover (604) and the memory parts (602, 603) such that the cover (604) does not act as a heat sink for the memory parts (602, 603). The cover (604) advantageously increases the security and aesthetic appearance of the module (600).
Fig. 7 is an illustrative top-view of a Chip-on-Board memory module. As shown in Fig. 7, a cover (704) is attached on one or both sides of the module (700) using rivets (707), 30 or other fasteners, that attach the cover (704) to the PC board (901). As an added protection, a ground plane of the PC board (701) may be made to connect to one or more rivets (707) touching the cover (704), thus providing a means of discharging any electrostatic charges, i.e., ESD (Electrostatic Discharge), that could potentially damage the module (700).
The cover (704) also provides physical protection to any electronics, wires, etc., used to create the s memory module (700). Using the interface connections (706), the module may be connected to any device, e.g., the motherboard of a host device, equipped to read and write information to the particular memory module (700).
Fig. 8 is an illustration of a top-view of an unpackaged semiconductor chip with perimeter pads connected to a PC board base. As shown in Fig. 8, an unpackaged to semiconductor chip (801) may be attached to a PC board (805) in similar fashion as shown in Fig. 3, wherein bonding wires (803) may be attached between pads (804) of the unpackaged chip (801) and pads (802) of the PC board (805).
The illustration of Fig. 8 shows another configuration of pads (804) on an unpackaged part (801), wherein the pads (804) are distributed around the perimeter of the unpackaged part 15 (801 ). More specifically, an outer layer of pads (806) and an inner layer of pads (807) are shown in Fig. 8. The arrangement of perimeter pads (804) shown in Fig. 8 is in contrast to other pad configurations, e.g., the inline central pads shown for the die of Fig. 3.
In general, the use of selectively settable material may greatly facilitate the process of attaching bonding wires to unpackaged chips for any variety of pad configurations. By using a o selectively settable materials, as described herein, bonding wires can be positioned, physically separated from other wires, readjusted, protected, etc.
Fig. 9 is a flowchart illustrating a method of mounting an unpackaged semiconductor chip with perimeter pads. As shown, the method of Fig. 9 is similar to the mounting method (step 100, Fig. 1) shown in Fig. 1. In particular, the method of Fig. 9 illustrates a method of as mounting unpackaged semiconductor parts, e.g., the unpackaged part (801, Fig. 8) shown in Fig. 8, which have one or more layers of pads around the perimeter of the unpackaged part.
As shown in Fig. 9, the method comprises mounting a die on a PC board (step 901).
This may be accomplished as described for Fig. 1, wherein the alignment of each unpackaged chip is adjusted (step 902), after which a ring of selectively settable material disposed around the chip is cured or hardened (step 903). The hardened ring around each die keeps the die in place.
In some embodiments, a layer of selectively settable material is placed between each die and the PC board. The same settable material that is used between each die and the PC
s board may also be used around each die or two different selectively settable materials are used as described above.
A bonder may then attach wires between the outer pads of the unpackaged part and pads on a PC board (step 904), as illustrated in Fig. 8. A layer of selectively settable material may be used to cover the bonding wires attached to the outer pads of the unpackaged part i o (step 905). After which a bonding machine may attach wires between the inner pads of an unpackaged part and pads of a PC board (step 906). By using selectively settable material (as described for Fig. 4b), the possibility of damaging wires, unpackaged parts, etc., is significantly reduced.
After attaching bonding wires between the inner pads of the unpackaged part and pads i5 of a PC board (step 906), another layer of selectively settable material may be added to cover the inner layer of wires and pads (step 907). After the wires are bonded (steps 904, 906), and selectively settable material separates and covers these wires (steps 905, 907), a visual inspection of the wires is made (step 908). If there are any problems (determination 909), e.g., wires that are broken, shorted, out of place, etc., a manual adjustment of the wires and z o bonds may be used to correct the problem (step 910). The unit may then be visually inspected again (step 908), and if there are no problems (determination 909), the selectively settable material, which covers the wires and pads, is completely hardened (step 911 ).
The process of Fig. 9 may be carried out using automated machinery for fabrication, etc. In one embodiment, automated machines are programmed to dispense one or more a s selectively settable liquids, mount unpackaged parts to a PC board, bond wires between unpackaged parts and a PC board, perform functionality tests, etc. In another embodiment, the dispensing of selectively settable liquids, mounting of unpackaged parts to a PC board, and performing functionality tests as described above, may be performed manually. Another embodiment of the Chip-on-Board fabrication process, shown in Fig. 9, uses a combination of 3 o automated and manual labor.
As is apparent, there exists a variety of Chip-on-Board mounting methods, which may use selectively settable material in a number of ways. In particular, selectively settable material may advantageously be used as a thermal and physical buffer between an unpackaged part and a PC board. Additionally, one or more layers of selectively settable s material may effectively be used to capture bonding wires attached to unpackaged semiconductor parts, which use a variety of pad configurations. As illustrated above, pads on an unpackaged semiconductor part may be placed in the center of a die (as shown in Fig. 3), around the perimeter of a die (as shown in Fig. 8), or any other configuration.
The preceding description has been presented only to illustrate and describe 1 o embodiments of invention. It is not intended to be exhaustive or to limit the invention to any precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be defined by the following claims.
Specifically, the memory parts (502, 507) shown in Fig. 5 allow the host device to provide a number of additional read/write control signals, e.g., DQM# in Table l, that 3 o eliminate the need to steer CAS (Column Address Select) and RAS (Row Address Select) signals to the memory parts (502, 507) used for patching. Instead, memory parts (502, 507) that are used to substitute failed memory outputs share the same read/write control signals as the memory part (502, 507) whose output they are replacing. Typical memory parts include 8Mx8, 16Mx8, and 32Mx8 memory parts commonly used in the art to build memory modules.
In operation of the memory module (500) fabricated using the patching networks (503), all I/O signals are sent through resistance networks (504) that provide a buffer between the memory part (502, 507) and the host device accessing the memory. Another component of the memory module (500) is a group of capacitors (505), which serve to stabilize the power io supply signal for each memory part (502, 507) by removing most high frequency electrical noise that may occur.
The interface connections (506) enable the memory module (500) to be conveniently plugged into an appropriate connection device of a host device. Through the connection, the host device is able to interact with the memory module (500) as herein above described, etc.
15 For more detailed information regarding patching networks (503) and processes, a reference may be made to US Patent No. 6,119,049 and the co-pending patent application, entitled, "Improved Patching Methods and Apparatus for Fabricating Memory Modules."
Fig. 6 is an illustrative cross-sectional view of a shielded Chip-on-Board memory module. As shown is Fig. 6, the module (600) uses a PC board (601) as a base.
Attached to 2o the PC board (601) are packaged parts (602) and unpackaged parts (603). In particular, any combination of packaged parts (602) and unpackaged parts (603) may be used. In some embodiments, at least one unpackaged part is used (603).
Covering the memory parts (and any other electronics, leads, wires, etc.) is a cover (804), which may be mounted to the PC board (601 ). In at least one embodiment, there is no z5 electrical or physical contact between the cover (604) and the memory parts (602, 603) such that the cover (604) does not act as a heat sink for the memory parts (602, 603). The cover (604) advantageously increases the security and aesthetic appearance of the module (600).
Fig. 7 is an illustrative top-view of a Chip-on-Board memory module. As shown in Fig. 7, a cover (704) is attached on one or both sides of the module (700) using rivets (707), 30 or other fasteners, that attach the cover (704) to the PC board (901). As an added protection, a ground plane of the PC board (701) may be made to connect to one or more rivets (707) touching the cover (704), thus providing a means of discharging any electrostatic charges, i.e., ESD (Electrostatic Discharge), that could potentially damage the module (700).
The cover (704) also provides physical protection to any electronics, wires, etc., used to create the s memory module (700). Using the interface connections (706), the module may be connected to any device, e.g., the motherboard of a host device, equipped to read and write information to the particular memory module (700).
Fig. 8 is an illustration of a top-view of an unpackaged semiconductor chip with perimeter pads connected to a PC board base. As shown in Fig. 8, an unpackaged to semiconductor chip (801) may be attached to a PC board (805) in similar fashion as shown in Fig. 3, wherein bonding wires (803) may be attached between pads (804) of the unpackaged chip (801) and pads (802) of the PC board (805).
The illustration of Fig. 8 shows another configuration of pads (804) on an unpackaged part (801), wherein the pads (804) are distributed around the perimeter of the unpackaged part 15 (801 ). More specifically, an outer layer of pads (806) and an inner layer of pads (807) are shown in Fig. 8. The arrangement of perimeter pads (804) shown in Fig. 8 is in contrast to other pad configurations, e.g., the inline central pads shown for the die of Fig. 3.
In general, the use of selectively settable material may greatly facilitate the process of attaching bonding wires to unpackaged chips for any variety of pad configurations. By using a o selectively settable materials, as described herein, bonding wires can be positioned, physically separated from other wires, readjusted, protected, etc.
Fig. 9 is a flowchart illustrating a method of mounting an unpackaged semiconductor chip with perimeter pads. As shown, the method of Fig. 9 is similar to the mounting method (step 100, Fig. 1) shown in Fig. 1. In particular, the method of Fig. 9 illustrates a method of as mounting unpackaged semiconductor parts, e.g., the unpackaged part (801, Fig. 8) shown in Fig. 8, which have one or more layers of pads around the perimeter of the unpackaged part.
As shown in Fig. 9, the method comprises mounting a die on a PC board (step 901).
This may be accomplished as described for Fig. 1, wherein the alignment of each unpackaged chip is adjusted (step 902), after which a ring of selectively settable material disposed around the chip is cured or hardened (step 903). The hardened ring around each die keeps the die in place.
In some embodiments, a layer of selectively settable material is placed between each die and the PC board. The same settable material that is used between each die and the PC
s board may also be used around each die or two different selectively settable materials are used as described above.
A bonder may then attach wires between the outer pads of the unpackaged part and pads on a PC board (step 904), as illustrated in Fig. 8. A layer of selectively settable material may be used to cover the bonding wires attached to the outer pads of the unpackaged part i o (step 905). After which a bonding machine may attach wires between the inner pads of an unpackaged part and pads of a PC board (step 906). By using selectively settable material (as described for Fig. 4b), the possibility of damaging wires, unpackaged parts, etc., is significantly reduced.
After attaching bonding wires between the inner pads of the unpackaged part and pads i5 of a PC board (step 906), another layer of selectively settable material may be added to cover the inner layer of wires and pads (step 907). After the wires are bonded (steps 904, 906), and selectively settable material separates and covers these wires (steps 905, 907), a visual inspection of the wires is made (step 908). If there are any problems (determination 909), e.g., wires that are broken, shorted, out of place, etc., a manual adjustment of the wires and z o bonds may be used to correct the problem (step 910). The unit may then be visually inspected again (step 908), and if there are no problems (determination 909), the selectively settable material, which covers the wires and pads, is completely hardened (step 911 ).
The process of Fig. 9 may be carried out using automated machinery for fabrication, etc. In one embodiment, automated machines are programmed to dispense one or more a s selectively settable liquids, mount unpackaged parts to a PC board, bond wires between unpackaged parts and a PC board, perform functionality tests, etc. In another embodiment, the dispensing of selectively settable liquids, mounting of unpackaged parts to a PC board, and performing functionality tests as described above, may be performed manually. Another embodiment of the Chip-on-Board fabrication process, shown in Fig. 9, uses a combination of 3 o automated and manual labor.
As is apparent, there exists a variety of Chip-on-Board mounting methods, which may use selectively settable material in a number of ways. In particular, selectively settable material may advantageously be used as a thermal and physical buffer between an unpackaged part and a PC board. Additionally, one or more layers of selectively settable s material may effectively be used to capture bonding wires attached to unpackaged semiconductor parts, which use a variety of pad configurations. As illustrated above, pads on an unpackaged semiconductor part may be placed in the center of a die (as shown in Fig. 3), around the perimeter of a die (as shown in Fig. 8), or any other configuration.
The preceding description has been presented only to illustrate and describe 1 o embodiments of invention. It is not intended to be exhaustive or to limit the invention to any precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be defined by the following claims.
Claims (27)
1. A method of fabricating Chip-on-Board logic modules using selectively settable materials, said method comprising:
mounting unpackaged die using a first layer of selectively-settable material;
hardening said first layer of selectively-settable material;
covering said first layer of selectively-settable material with a second layer of selectively-settable material; and capturing bonding wires connecting said unpackaged die to a printed circuit board in said second layer of selectively-settable material.
mounting unpackaged die using a first layer of selectively-settable material;
hardening said first layer of selectively-settable material;
covering said first layer of selectively-settable material with a second layer of selectively-settable material; and capturing bonding wires connecting said unpackaged die to a printed circuit board in said second layer of selectively-settable material.
2. The method of claim 1, wherein part of said first layer of selectively-settable material is physically above said unpackaged die.
3. The method of claim 1, wherein said capturing bonding wires comprises placing part of the bonding wires in said second layer of selectively-settable material, then hardening said second layer of selectively settable material.
4. The method of claim 1, further comprising placing selectively settable material between said unpackaged die and said printed circuit board to provide a physical and thermal buffer.
5. The method of claim 4, wherein said selectively settable material between said unpackaged die and said printed circuit board is less cured said first and second layers of selectively-settable material.
6. The method of claim 1, wherein said selectively settable materials comprise UV materials.
7. A Chip-on-Board logic module fabricated according to method 1.
8. A method of fabricating a Chip-on-Board logic module using selectively settable materials, said method comprising:
mounting one or more electronic logic parts on a printed circuit board using said selectively settable materials;
selectively hardening areas of a selectively settable material;
attaching bonding wires between pads of said logic parts and pads of said printed circuit board;
applying selectively settable material to cover said bonding wires;
inspecting bonding wire connections;
readjusting bonding wires; and hardening selectively settable material that covers said bonding wires.
mounting one or more electronic logic parts on a printed circuit board using said selectively settable materials;
selectively hardening areas of a selectively settable material;
attaching bonding wires between pads of said logic parts and pads of said printed circuit board;
applying selectively settable material to cover said bonding wires;
inspecting bonding wire connections;
readjusting bonding wires; and hardening selectively settable material that covers said bonding wires.
9. The method of claim 8, wherein said one or more selectively settable materials comprises UV materials.
10. The method of claim 8, wherein said mounting one or more memory parts further comprises aligning the memory parts on said printed circuit board.
11. The method of claim 8, wherein said mounting one or memory parts using said selectively settable materials comprises applying a quantity of a selectively settable material between unpackaged logic parts and said printed circuit board.
12. The method of claim 8, wherein said mounting one or memory parts using said selectively settable materials further comprises applying a quantity of a selectively settable material around unpackaged logic parts.
13. The method of claim 11, wherein said selectively settable material between unpackaged logic parts and said printed circuit board is not hardened.
14. The method of claim 8, wherein said selectively hardening areas of said selectively settable material comprises hardening a ring of selectively settable material around said unpackaged logic part.
15. The method of claim 8, wherein one selectively settable material is used.
16. The method of claim 8, wherein more than one selectively settable materials are used.
17. The method of claim 16, wherein a selectively settable material used between an unpackaged logic part and a printed circuit board does not harden when a selectively settable material used around said unpackaged logic part hardens.
18. A Chip-on-Board logic module fabricated according to the method of claim 7.
19. A multi-layer printed circuit board for fabricating Chip-on-Board memory modules using partially-defective memory parts comprising:
pads for connecting electrical components to said circuit board;
a patching network; and interface connections.
pads for connecting electrical components to said circuit board;
a patching network; and interface connections.
20. The circuit board of claim 19, wherein said electrical components comprise a variety of packaged or unpackaged memory parts.
21. The circuit board of claim 19, wherein said electrical components further comprise resistors, capacitors, voltage regulators, phase locked loop units, differential clock drivers, etc.
22. The circuit board of claim 19, wherein said patching network comprises a 2-to-1 patching network.
23. The circuit board of claim 19, wherein said patching network comprises a 4-to-1 patching network.
24. The circuit board of claim 19, wherein said patching network comprises an to-1 patching network.
25. The circuit board of claim 19, wherein said interface connections comprise a collection of pins, allowing said circuit board to plug into and interact with a host device.
26. A memory module comprising a multi-layer printed circuit board for fabricating Chip-on-Board memory modules using partially-defective memory parts comprising:
pads for connecting electrical components to said circuit board;
a patching network; and interface connections.
pads for connecting electrical components to said circuit board;
a patching network; and interface connections.
27. The memory module of claim 26, wherein said memory module is formed by a method of fabricating Chip-on-Board logic modules using selectively settable materials, said method comprising:
mounting unpackaged die using a first layer of selectively-settable material;
hardening said first layer of selectively-settable material;
covering said first layer of selectively-settable material with a second layer of selectively-settable material; and capturing bonding wires connecting said unpackaged die to a printed circuit board in said second layer of selectively-settable material.
mounting unpackaged die using a first layer of selectively-settable material;
hardening said first layer of selectively-settable material;
covering said first layer of selectively-settable material with a second layer of selectively-settable material; and capturing bonding wires connecting said unpackaged die to a printed circuit board in said second layer of selectively-settable material.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US36003602P | 2002-02-26 | 2002-02-26 | |
| US60/360,036 | 2002-02-26 | ||
| US10/371,800 | 2003-02-20 | ||
| PCT/US2003/005846 WO2003073357A1 (en) | 2002-02-26 | 2003-02-24 | Methods and apparatus for fabricating chip-on-board modules |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2477763A1 true CA2477763A1 (en) | 2003-09-04 |
Family
ID=27766178
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002477763A Abandoned CA2477763A1 (en) | 2002-02-26 | 2003-02-24 | Methods and apparatus for fabricating chip-on-board modules |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP1483723A1 (en) |
| KR (2) | KR20040096611A (en) |
| AU (1) | AU2003219909A1 (en) |
| CA (1) | CA2477763A1 (en) |
-
2003
- 2003-02-24 CA CA002477763A patent/CA2477763A1/en not_active Abandoned
- 2003-02-24 AU AU2003219909A patent/AU2003219909A1/en not_active Abandoned
- 2003-02-24 KR KR10-2004-7013210A patent/KR20040096611A/en not_active Application Discontinuation
- 2003-02-24 EP EP03716193A patent/EP1483723A1/en not_active Withdrawn
- 2003-02-24 KR KR10-2004-7013249A patent/KR20050004787A/en not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| KR20050004787A (en) | 2005-01-12 |
| KR20040096611A (en) | 2004-11-16 |
| EP1483723A1 (en) | 2004-12-08 |
| AU2003219909A1 (en) | 2003-09-09 |
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