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CA2336385A1 - Protocole ameliore de bus en serie entre dispositifs - Google Patents

Protocole ameliore de bus en serie entre dispositifs Download PDF

Info

Publication number
CA2336385A1
CA2336385A1 CA002336385A CA2336385A CA2336385A1 CA 2336385 A1 CA2336385 A1 CA 2336385A1 CA 002336385 A CA002336385 A CA 002336385A CA 2336385 A CA2336385 A CA 2336385A CA 2336385 A1 CA2336385 A1 CA 2336385A1
Authority
CA
Canada
Prior art keywords
data
wire
master
slave
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002336385A
Other languages
English (en)
Inventor
Sanjay K. Jha
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CA2336385A1 publication Critical patent/CA2336385A1/fr
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Small-Scale Networks (AREA)

Abstract

L'invention concerne un protocole de bus en série entre dispositifs qui facilite l'interconnexion et la communication entre plusieurs dispositifs via un bus en série. Le bus (48) comprend une connexion d'horloge, une connexion de données et une connexion marche/arrêt. Une interface de bus en série principale raccorde un dispositif principal au bus en série. Une interface de bus en série asservie raccorde un dispositif asservi au bus en série. L'interface (180) de bus en série principale peut comprendre un initiateur de transaction, un mécanisme d'écriture de données, un mécanisme de lecture de données et une commande d'horloge. L'initiateur de transaction initie une transaction en abaissant le niveau du signal de la connexion marche/arrêt. Le mécanisme d'écriture de données commande le niveau du signal dans la connexion de données en fonction des données à inscrire dans le dispositif asservi. Le mécanisme de lecture de données lit des données en contrôlant le niveau de signal dans la connexion de données. La commande d'horloge commande le niveau de signal dans la connexion d'horloge en fonction d'un signal d'horloge voulu.
CA002336385A 1998-07-01 1999-06-30 Protocole ameliore de bus en serie entre dispositifs Abandoned CA2336385A1 (fr)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US9138398P 1998-07-01 1998-07-01
US60/091,383 1998-07-01
US24893999A 1999-02-11 1999-02-11
US09/248,939 1999-02-11
PCT/US1999/014696 WO2000002134A2 (fr) 1998-07-01 1999-06-30 Protocole ameliore de bus en serie entre dispositifs

Publications (1)

Publication Number Publication Date
CA2336385A1 true CA2336385A1 (fr) 2000-01-13

Family

ID=26783906

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002336385A Abandoned CA2336385A1 (fr) 1998-07-01 1999-06-30 Protocole ameliore de bus en serie entre dispositifs

Country Status (9)

Country Link
EP (1) EP1145132A3 (fr)
JP (1) JP2003534580A (fr)
KR (1) KR20010053365A (fr)
AU (1) AU4843299A (fr)
BR (1) BR9911732A (fr)
CA (1) CA2336385A1 (fr)
IL (1) IL140568A0 (fr)
NO (1) NO20006698L (fr)
WO (1) WO2000002134A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102696021A (zh) * 2009-11-05 2012-09-26 拉姆伯斯公司 接口时钟管理

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7076225B2 (en) * 2001-02-16 2006-07-11 Qualcomm Incorporated Variable gain selection in direct conversion receiver
FR2828947B1 (fr) * 2001-08-27 2003-12-19 Pierre Trazic Fonctions out et in de connection sur un bus uce
JP4831899B2 (ja) * 2001-08-28 2011-12-07 富士通セミコンダクター株式会社 半導体集積回路及びクロック制御方法
EP1461713A1 (fr) * 2001-12-28 2004-09-29 Koninklijke Philips Electronics N.V. Systeme de communication
DE102005007333B4 (de) * 2004-05-07 2008-07-03 Avago Technologies General Ip (Singapore) Pte. Ltd. Mehrchip-Gehäuse mit seriellen Hochgeschwindigkeitskommunikationen zwischen Halbleiterformen
US7342310B2 (en) 2004-05-07 2008-03-11 Avago Technologies General Ip Pte Ltd Multi-chip package with high-speed serial communications between semiconductor die
US20050259609A1 (en) 2004-05-20 2005-11-24 Hansquine David W Single wire bus interface
US20060031618A1 (en) * 2004-05-20 2006-02-09 Hansquine David W Single wire and three wire bus interoperability
KR100698303B1 (ko) * 2005-03-21 2007-03-22 엘지전자 주식회사 직렬 버스 디렉션 컨트롤러
KR100910446B1 (ko) 2007-12-03 2009-08-04 주식회사 동부하이텍 디스플레이 장치용 ｉ２ｃ 타임 콘트롤러의 데이터 동기화구현 회로 및 방법
US9300129B2 (en) 2013-03-12 2016-03-29 Ascensia Diabetes Care Holding Ag Reverse battery protection for battery-powered devices
TWI636367B (zh) * 2014-02-07 2018-09-21 瑞士商安晟信醫療科技控股公司 用於多個主機匯流排協定的方法與裝置
US10417172B2 (en) 2014-04-28 2019-09-17 Qualcomm Incorporated Sensors global bus
US9734121B2 (en) 2014-04-28 2017-08-15 Qualcomm Incorporated Sensors global bus
IT201800002767A1 (it) * 2018-02-16 2019-08-16 St Microelectronics Srl Circuito per il pilotaggio di led, dispositivo e procedimento corrispondenti

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4910509A (en) * 1988-03-17 1990-03-20 Zenith Electronics Corporation Bus expander for digital TV receiver
EP0589499B1 (fr) * 1992-08-12 1999-04-07 Koninklijke Philips Electronics N.V. Système omnibus de communication à stations multiples ainsi que station maítre et station esclave destinées à être utilisées dans un tel système
GB2278259B (en) * 1993-05-21 1997-01-15 Northern Telecom Ltd Serial bus system

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102696021A (zh) * 2009-11-05 2012-09-26 拉姆伯斯公司 接口时钟管理
CN102696021B (zh) * 2009-11-05 2016-03-16 拉姆伯斯公司 接口时钟管理
US9824056B2 (en) 2009-11-05 2017-11-21 Rambus Inc. Handshake signaling for interface clock management
US11681648B2 (en) 2009-11-05 2023-06-20 Rambus Inc. Interface clock management
US12032508B2 (en) 2009-11-05 2024-07-09 Rambus Inc. Interface clock management

Also Published As

Publication number Publication date
WO2000002134A2 (fr) 2000-01-13
IL140568A0 (en) 2002-02-10
EP1145132A3 (fr) 2002-08-21
NO20006698D0 (no) 2000-12-29
BR9911732A (pt) 2002-01-29
WO2000002134A3 (fr) 2001-09-27
NO20006698L (no) 2001-02-20
EP1145132A2 (fr) 2001-10-17
AU4843299A (en) 2000-01-24
KR20010053365A (ko) 2001-06-25
JP2003534580A (ja) 2003-11-18

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Legal Events

Date Code Title Description
FZDE Discontinued