CA2164523A1 - Bicmos current mode driver and receiver - Google Patents

Abstract

An apparatus for reducing transmisson delay tones when transmitting differential signals in an integrated circuit along long interconnect lines (10, 11) includes a current mode line driver which converts the differential signal to be transmitted into a signal that has a relatively low peak-to-peak voltage and large differential current changes. A receiver responsive to differential current changes converts the signal back into an output differential signal having peak-to-peak voltages adaptable to subsequent logic stages. A feedback circuit (Q5, Q6) coupled to the interconnect lines (10, 11) and the receiver functions to clamp the interconnect lines (10, 11) to a predetermined voltage while allowing the output differential signal to have peak-to-peak voltages greater than the predetermined voltage.

Description

wo 95l05033 pcT~ss4lo46l3 -BiCMOS CURRENT MODE DRIVER AND RECEIVER

FIELD OF T~ INVENTION
The present invention relates to the field of circuit design, and s~ifi~lly to tr~ncmiccion of dirr~ .enLial signals within an 5 in~Pg~ P~ circuit.

BACKGROUND OF THE INVENTION
In digital logic circuits information in the form of digital signals is processed so as to cause the logic circuit to ~rvllll a spe~ific task or function. A digital signal generally has two states;
10 a high level state and a low level state. Each logic state CO~ yOntlC to some voltage pv~ l In other words the high logic state co~ ,onds to a first voltage potential and the low state coll~ n-lc to a second voltage potential. The voltage ~IPn~ c are ~el- ...;n~d by the design of the logic circuit.

A digital signal is also char~ctP~i7P~ by its peak-to-peak voltage. The peak-to-peak voltage of a given digital signal is equal to its .. ;.~i.. signal voltage (i.e., the voltage potential coll~l~ntling to the high logic state~ minus its ...;n;...u... signal voltage (i.e., the voltage ~,l~ial cvll~;s~vnding to the low logic 20 state).

Often times, certain applications within a logic circuit require a digital signal and the inverse of that digital signal - - -~ 0 ~ ;C~- 2 ~ 6 4 5 2 3 PCT~TSg4l046l.

(l~L.l~d to as a differential signal) to be utilized. Typically, to t~ncmit a dirrerc-,~ial signal from one part of an int~gr~ted circuit (IC) to another you need a tr~ncmitte~ to drive two interc~nn~t lines with the dirrc.c .Lial signal and a receiver to detect the signals 5 on these lines.

The traditional method for dirr~erlial signal tr~ncmiccisn utilizes high power buffers for driving the ir.lel~;onn~t lines. The buffers, (also lcrcLled to as line drivers), are differential ~mrlifiers comrricing two emitter-coupled transistors each having a resistive 10 load collplçd bel~n their c~ll~tor and a supply voltage. Their &...;11~ ~ are courl~ to a current source. For dirrel...~.al signal ~ncmiccion, a signal and its inverse is couplçd to each of the bases of the emitter~lpl~ tr~ncictors. The dirrcl~n~ial ~mrlifier cclllpares the two input base signals. Dep~nriing on whether one of - 15 the base signals is less than or greater than the other, the dirrcl~ ial arnplifier steers the current established by the current source through one of the emitter-coupled t~ncictors. This current flow causes a c~ s~nding voltage drop across only one of the load resistors. At the same time, because no current flows through 20 the other transistor, the collector of that t~nCictQr remains at a~lu~ ely ground ~ ial. The output of the dirL.. r.~ial ~mplifi.or is typically taken at the collector of each of the emitter--oourl~ tr~nCictors. Thus, one coll~tQr is always at a voltage potf-~ l col.~s~l.ding to a low logic level and the other collector 25 is at a voltage pot~r.tial collcs~onding to a high logic level. The dirrcl~nlial voltage signal outputted by the collectors is coupled to a wo 95J05033 2 1 6 4 5 2 3 PCT/US94/04613 -pair of in~r~r.nPct lines for tr~ncmiccinn to receivers in other parts of the IC.

Similar to the line drivers, the receivers compricp a pair of emitter coupled tranCictors each having a resistive load coupled S be h ~ their c~llpctor and a supply voltage. A current source is coupled to their common e~ . The ~lAn~ r~ dirr. .~.~ial signal is coupled between the bases of the emitter-coupled pair and the output of the receiver is taken at their collpctors~ The receiver, in ~ ce to voltage c h~ngPs on the in~.u)~ lines, outputs a 10 co~ Qn~ g ~liîr~e.,lial signal. Since this type of tr~ncmiccion system r~ C such that it detects changes in voltage in the t-~--C.t~ A signal, it is ,~fe.l~d to as a voltage mode tr~ncmiccion system.

- Of~en times signals need to be ~A~-~.. ;ur~ along leldLiv~ly 15 long lines within the IC. A f~nite delay occurs from the time the signal l~ ;ol~c at the output of the tr~nc...;ll~ to the time the input of the receiver detects the t. .nc;t;.)n. This delay is directly related to the resistive loading of the line and its ~Cc~-;~t~
c~ For very long lines, delays can beco.. r large.

The amount of delay of a llAn~.. illed signal due to line is also ri~ . ,n;.~ed by the signals peak-to-peak voltage.
For a given line having a spPrifir ~Csoci~te line c~ rce and resistive loading, longer delays occur for LIAnclll;tl~ signals having relatively high peak-to-pealc voltages than for lower voltages. For ~' O g; I ~SC~ ` ` ~ . 1 3S~ 41~i ~6 L _ inct~nr~e a longer tr~nciti~n delay occurs on a sperific inLc co line for a 700 mV peak-to-peak signal than a 20 mV peak-to-peak signal having the sarne current. The reason for this is because it takes a longer time for a signal to reach a 700 mV peak voltage as 5 opposcd to a 20 mV peak voltage. Thus, t~nc...;ll;,-g signals having low peak-to-peak voltages equates to l~duced delay times.

One type of tr~ncmiccion system that reduces delays by reducing peak-to-peak voltages ope,~tes in a manner in which dirL,~ "tial current changes on the i~ ;onneot lines are ~iet~trd 10 instead of dirr~ .~, Lial voltage ch~nges In a system in which dirr~"ial current çh~ng~os are det~cte~, the signals are ~cfe~l~d to as current mode signals; (as o~osed to a system that detects voltage changes in voltage mode signals). Thus, instead of driving int~nnr~l lines with dirr. ,c.~ial voltage mode signals having - 15 relatively large çh~ngcs in voltage, intcl~;c7nn~t lines are driven with current mode signals having relatively large difr~,.Lial changes in current and small peak-to-peak voltage changes. Since peak voltages are reduced, so are the ~c~;~led tr7ncmiccir)~l delays. FY~mples of circuits for driving common mode signals are 20 ~ ;hed in the article, "Current-Mode Techniques For High Speed VLSI Circuits With Appliration To Current Sense ~mplifi~r For CMOS SRAM's," by E. Seevinck et al., LTSSC Vol. 26, No. 4 April, 1991.

The current mode driver is basically the same as the voltage 25 mode line driver except that the load resistors coupled to the WO 95tO5033 2 1 6 4 5 2 3 PCT/US94/04613 cnll~ors of the emitter-coupled transistors are Pli""n~t~
Spec-ifi~lly, the coll~ctQrs of the emitter-coupl~ pair are coupled directly to the int~r~ol-n~l lines. Thus, instead of a dirrc~clllial voltage being developed across the inte.conn~t lines, a ref~ncc 5 currcnt is routed through either one or the other ~l~.~nn~:l line.
This causes a difr~.er.Lial current signal to be developed across the i~t~ nn~.;l lines. This dirr~.ellial current signal is det~ted by the current mode receiver.

One prior art current mode receiver, referred to as a 10 c~le clamp, converts current mode signals into dirre.~ ial voltage mode signals while cl~mping the intercol~n~oct lines to a voltage of ap~,u~ y 60 mV. The c~ e clamp cornpri~ps two h~n~i~tl rs each having their bases coupl~ to a rer~ ce voltage, VDD. A resistor is also coupled b~lw~n each of their - 15 cQ~ rs and VDD. F~t~h of the dirr~cnlial inlL.coi~nPct lines are coupled to one of the e~ of the c~c~e~d pair. When a dirr~lence in current is ~et~ted at the C.lliLLc~l~ of the c~c~e pair, a CCl~ nlling dirf~,~..Lial voltage is established across their e-~;lh a The m~vnih-~e of this dirr..~ ial voltage is an 20 c~ -f r.l;~l function of the ratio of the current dirr~ ce in the P- .-;11 ~ of the c~ pair. For bipolar tr~n~i~tors c~upl~ in this l-~mcr, a 10:1 ratio in the dirr~ r~...Lial current results in a 60 mV voltage dirr~.encc across the e-.-iu~.~ at 25 degrees Cplci~lc Thus, for a current mode tr~ncmiccion system lltili7inv a pair of 25 bipolar c~croded transistors, tr~ncmiccion delays are reduccd be~u~e the r~c~e circuit clamps the differential peak-to-pealc '~ C~ 2 ~ 6 4 5 2 3 P-~ r~7sg~/o~l voltages on the in~elconn~ct lines. However, these reduced peak-t~peak voltage swings are still large enough to cause sig..;~ delays for ver,v long dict~nce signal tr~ncmicsion The present invention is a circuit design for trancmitting 5 current mode signals. The current mode tr~ncmicci~n system of the precent invention utilizes a dir~e,lLial ~mplifier fe~db~cl~ circuit to chmp peak-to-peak voltages on intelconnect lines while providing output signals peak voltage swings co.,lpalible with ECL logic. As a result, t~ncmic~ n delays ~csoc;~lr~ with line c~p~it~n~ are 10 ci~nifi~ntly reduc~i.

Sl~fARY OF T~ INVENTION
The present invention is a current mode signal tr~ncmiccio~
- circuit. The trancmiccion circuit in~ ln~es a current mode driver and receiver. The receiver utilizes fee~b~rl~ to clamp peak-to-peak 15 voltages of signals on diffcl~ ial inte.~;omlecl lines while ou~ lg signals having peak-to-peak swings col,lpa~ble with ECL
circuit design.

The current mode driver of the present invention includes first pair of emitter-coupled tr~ncictors. The ellliuel~ of this first 20 pair of t~ncictors are coupled to a current source. In one i.". .n the current source is an n-type metal oxide silicon (NMOS) device having its gate coupled to a reference voltage. The input diLL~ellLial signal to be tr~ncmi~ted is coupled to the bases of wo 95/0~033 2 1 6 4 5 2 3 PCT/US94l04613 _ the emitter-coupled pair which causes a current mode dir~lenLial signal to be est~blicheA across the coll~tors of the emitter coupled pair. The cnllPctors are coupled to a pair of ir,L.".-o~ ~,t lines.

This current mode difrc~lLial signal is tr~nsmittç~ along the S intL~ lines to the current mode receiver of the present invention. The receiver converts the current mode signal to a voltage mode signal having a greater peak-to-pcak voltage swing than the current mode signal. The receiver in~ d~s a second pair Of tr~n~ict~rs. Each of the enliLLcla of the second pair of transistors 10 are coupled to one of the int.~onn~t lines. One embo~iim~nt of the present invention also incllldt~s MOS current sources coupled to each of the e.,lilL~a of the second pair of tr~ncict~rs to bias them in their low r~-cict~nc~ Op~ t;ilg range. The bases of the third and fourth ~nSist~rs are coupled to a feedb~ circuit.

The fe~ba~'lr circuit is a diff~c~Lial ~mplifi~r having a third pair of emitter-coupled ~nCictnrs~ a current source, and a pair of load resistors. The difr~,.c.,Lial ~mpiifi~r's function is to drive the bases of the second-pair of transistors in the oppoaiLe dircc~,oll from which their c.,~ onding ell~LL~a are moving. In this way, the 20 intc.~ l lines are cla,ll~d to a voltage swing that is much less than the swing the receiver is trying to achieve.

In one embodiment, a single current mode driver is coupled to a single current mode receiver. In this embo~im~nt, the output of the receiver is taken at the coll~tQrs of the second pair of C;/Q--~ ,~TS94/~

tr~n.ci.CtOrS.

In another embodiment m~lltiple drivers are coupled to a single receiver. In this case, the output of the receiver is at the cnllrctnrs of the third pair of emitter-coupled tr~ncictors S BRIEF DESCRIPIION OF THE~ DRAWINGS
The present invention is illusLId~d by way of eY~mple and not limit~tion in the figures of the accol,lp~lying drawings, in which like lcr~ences intlic~t~ similar elrmrnt~, and ~I,~

Figure 1 is a circuit S~hF~ I;c ~ii~r~m which ill~str~t~5 the 10 current mode driver and receiver of the pre~sent invcntioll.

- Figure 2 is another embo~im~nt of the present invention having mnltirle drivers co--pl~d to a single receiver.

DETAILED DESCRIPIION
In the following des~ .l;nn, a current mode driver and 15 receiver is ~esçrihe~ in which llu-l~c.u~ls specific details are set forth, such as specific con~uctivity types, circuit config~lratit)nc, etc., in order to provide a thorough underst~n-iing of the present invention. It will be obvious, however, to one skilled in the art that these specific details need not be employed to p~ tir~ the 20 present invention. In other in~t~nr~s~ well-known structures and wo 95l05033 2 1 6 4 5 2 3 PCT/US94/04613 circuits have not been shown in detail in order to avoid nn~c,..;ly obsculing the present invention.

Figure 1 shows a circuit sn~ ;c ~i~gl~m of one embo~im~nt of the present invention. ~trh~ NPN bipolar ~"~;c~Ol~ Q1 and Q2 and NMOS tr~n~i~tor M1 comprise the current mode line driver portion of the present invention. The e-- il~.~ of Q1 and Q2 are coupled to the drain of M1. The source of M1 is coupled to a first supply voltage referred to as VSS. In the p~ f~l~cd e~bori~ nt~ VSS is equal to -3 volts, however a 5 volt VSS is also ~ pt~hle. The gate of M1 is coupled to reference voltage VREF. VREF biases M1 to function as a current source such that M1 supplies a current equal to IREF. An input dirr~ .~ntial signal comprising IN and IN/ is coupled to the bases of Q1 and Q2. It should be noted that INt is - 15 the inverse signal of IN. Consequently, when IN is high, IN/ is low and when IN/ is high, IN is low. As a result, the input dirr~ ial signal causes either Ql or Q2 to be biased on and the other to be biased off. As is typical of difr. .~:nLial ~mplifi~rs, the current supplied by current source M1, is routed through either Q1 or Q2 to either in~.;onn~L line 10 or 11. Thus, in the steady state the current llllough one of the ir~rcunne~t lines is zero and the current through the other in~rConnpct line is IREF.

In~rc~n~ ;L lines 10 and 11 are coupled to the current mode receiver of the present invention. It should be noted that although i lt~rconl-A~ lines 10 and 11 are fe~lcsen~ed as relatively short lines WO U~lQiG-' ` P~r~JTS~4lo46~-they can be any length.

The current mode receiver compric~s a c~cc4de clamp portion and a f~b~ portion. The c~cc~le clamp portion of the receiver in~ es m~trh~d NPN tr~ncictors Q5 and Q6, their S resistive loads R3 and R4, and current source biased NMOS
devices M2 and M4. The fe~b~cl~ portion inClU~eS .~ ch~
t~.~ncictors Q3 and Q4, their resistive loads R1 and R2, and current source biased NMOS device M3. As can be seen, VREF provides the bias voltage to the gates of M2, M3 and M4. These tr~ncictnrs 10 are siæd so they each provide the desired current.

The diLf~ mrlifi~r portion of the receiver filntti~-nc such that when the base-to e..liu~r voltages of Q3 and Q4 are equal, the current ~ll~lied by M3, i.e., I3, is split equally between Q3 - and Q4.

Thus, the current through each of the branches of the dirr~lh~ mplifi~r when Vb~(Q3) = Vb~(Q4) is (13)/2. However, when the base-t~ emitter voltage for one of the transistors is greater than the other, more current will be flowing through the t~ncictor with the higher base-t~emitter voltage. Since more 20 current is flowing in one branch and less current is flowing through the other, the voltage at one of the collectors of the emitter-coupled tr~nCictors will begin to fall while the other rises. In other words, a diLre~ lLial voltage signal is developed across the coll~tors of Q3 and Q4. The cascode portion of the receiver function~ similar to wO ssl0so33 PCTIUS94/04613 2t 64523 prior art c~ccQde clamp ~e~ignC7 in that when the current through their e~ are unequal, their base-to e.l.iLLer voltages c~ n.i;ngly adjust. Spe~ifir~lly, Vb~ (Q5) - Vb, (Q6) = (VT) x In(I5/I6), i~noring the base re~i~n-e (Rb) of Q5 and Q6.

In the embo~im~nt shown in Figure 1, where the c~de pair are NPN t~nCi~tors~ when the ratio of the emitter CUllCnti of Q5 and Q6 is 10:1 the difference bc~w~n their base-to e~lliLLcr voltages is equal to about 60 mV (at a tel~ dlulc of 25 degrees Celsius).

In the case when the current mode receiver is in a state in which the driver is not supplying any current to intcr~n.~ lines 10 and 11, i.e. I(line 10) = I(line 11) = 0, then I5 = I2, I6 = I4 and I3 is split equally between the branches of the receiver's - difLd~ mrlifi~-. As a result voltage po~ .Lials are ~l~illul~d lhlou~l~uu~ the receiver, i.e., V(node 1 ) = V(node 3) and V(node 2) = V(node 4). Further, the dirÇe~- nlial voltage between the output lines OUT and OI~T/ is zero since V(OUT) = V(OUT/).

In the case where IN is high and IN/ is low, IREF is steered llllougll Ql. As a result the current through line 10 is equal to IREF and the current through line 11 is a~r~ t~oly zero. This causes I5 to start to in~;l~se and I6 to remain equal to I4.

Q5 and Q6 function as a c~code pair, when I5 begins to increase, the emitter of Q5 (node 2) begins to drop below ~ o~/~;c- Dcr~rJss4/~

the emitter of Q6 (node 4). In a~f ~fitiQn~ as I5 increases, the collector current of Q3 decreases. Q3 of x;l~lcs in the region in which its cofUector current is related to its base-to-emitter voltage (Vbe) such that Ic = IS(eVW~), (where IS is the szt~flr~tinn current 5 of Q3 and ignoring the base reCictf~n;~ of Q3). So, as I5 incrcase Ic(Q3) df~l~s, b~s-~ the Vb, of Q3 de~l~ses. This is due to the node 2 pot~nLial going negative with respect to node 4.

At this point, I3 no longer splits equally between the two br7n~-hPc of the differential ~mfrlifier. Tnct~ozfffi', more of I3 is routed 10 through Q4 and R2. Thus, the current through R1 decreaces while the current through R2 increases. This causes a coll~ ing increase in voltage f~o~.l~ial at node 1 and a dec,fase in voltage ~ote.,Lial at node 3.

- Node 1 increases and node 3 decreases, as node 2 declcases 15 until the delta(Vbc) of Q6 and Q5 is such that the above e~ tinn is .c~ticfi~'. AS m~ntion~a above, node 2 (the emitter of Q5) tries to approach a voltage potential equal to [(VT) x In(15/I6)] below node 4 (the emitter of Q6). However, due to the movement of nodes 1 and 3, node 2 never rcaches that po~cnlial. In other words, instead 20 of the voltage ~,olclltial at node 2 dropping below node 4 by [(VT) x In(I5/I6)] to adjust for the difference in ~;UllClll5 bc~n Q5 and Q6, the ~tf n~ on node l and 3 co"~ibule to part of the delta(vbe) bclwcen Q5 and Q6. Resistors Rl and R2 are chosen so that they supply the a~,ul.,iate potential to the bases Q5 and Q6 to 25 achieve the .-;ni-~-~..- stable dirrcl~:ntial voltage at nodes 2 and 4.

-Wo 95/05033 2 1 6 4 5 2 3 PCTIUS94/04613 -As can be seen, the peak-to-peak voltage of in~rconnect line lO is mped to a voltage potential less than (VT) x In(I5/I6), (i.e., less than 60 mV at 25 degrees Celsius for an NPN c~code pair clamp).
The m,qgni~le of the voltage swing on nodes 1 and 3 is much 5 higher than that of nodes 2 and 4. However, since nodes 1 and 3 are gPnP~IIy low c-q-~qcit-qn~ short intercolmect lines relative to n~oL lines 10 and 11, signal delays on these lines are minimql Thus, the present invention reduces delays by re~ucing the voltage swing of the differential signals sent along logic circuit 10 int~ nn~t lines lO nd 11.

The outputs of the receiver, OIJT and Ol)~/, are taken at the cnllP~tors of Q5 and Q6. For the e~mple in which IREF is flowing through in~.~ .nP~;l line 10, OUT/ is equal to VDD - (R3 x IREF) and OUT is VDD-(R4 x I4). Since IREF is much greater - 15 than I4, OI~T is high and O~T/ is low. Resistors R3 and R4 are chosen so that the receiver outputs the desired peak-to-peak voltage.
The output of the receiver needs to have a peak-to-peak swing that intPr~s with subs~uc:nt logic gates. Consequently, the sel~ted m~gnih-~e of the peak-to-peak voltages, (and R3 and R4) depend on 20 the type of logic design to be utili7~. For in~t~nce7 for emitter-coupled logic (ECL) the typical peak-to-peak voltage is 750 mV. In general, logical output peak-to-peak voltages range from 250 mV - 750 mV.

Current sources M2 and M4 in Figure 1 function to provide 25 a low level current to bias the c~co(le clamp t~n~i~tors in their wo o;lQ;~ ss4/(~

low recict~n~ region. This reduces the transient recovery time on lines 10 and 11. As can be seen in Figure 1, M2 biases Q5 and M4 biases Q6.

In the above ~es~ ;sn, all of IREF is routed Lhluugh 5 i,lL~ nP~t }ine 10 when IN is high and IN/ is low. When IN is low and IN/ is high all of IREF is routed through intc,~on~ t line 11. When this occurs, I6 starts to increase and I5 remains equal to I2. Similar to the previous desc~ ion, node 4 and the intern~l nodes of the .~i~e" nodes 3 and 1, adjust until the delta(Vb,) of 10 Q6 and Q5 is such that the equation, delta(Vb,) between Q6 and Q5 = [(VT) x In(16/I5)] is true. Node 4 (the emitter of Q6) tries to a~ h a voltage pot .,lial equal to [(VT) x In(16/I5)] below node 2 (the emitter of Q5). However, due to the movement of nodes 1 and 3, node 4 never reaches that potential. Thus, the peak-to-peak - 15 voitage of in~ConnF~l line 11 is cl~mFe~ to a voltage potential less than [(VT) x In(I6/I5)], (i.e., less than the 60 mV at 25 d~l~es Celsius for an NPN c~code pair clamp).

Since IREF is flowing through inL~u~lnect line 11, OIJT is equal to VDD - (R4 x IREF + I4) and Oll'r/ is equal to VDD -20 (R3 x I2). Since IREF is much greater than I2, OUT is low andOUI/ is high.

Figure 2 shows another embodiment of the present invention. In this em~o~im~nt m~ iple current mode drivers are coupled to a pair of i.,L~lConnect lines and a single current mode wo 95/O5û33 2 1 6 45 2 3 PCTIUS94/0~613 ~ ;vcr. Refe~ g to Figure 2, it should be noted that current mode drivers 1 and 2 are shown in close l~lUAi~ y, however they may be located ;~ywl.~ within the IC. In :~dfliti~n, more than two drivers may be couplP~ to in~wnn~l lines 10 and 11.

S Current mode driver 1 inrllldes NPN tr~ncictors Ql and Q2 and current mode driver 2 in~ des Q8 and Q9. NMOS device M1 is biased to function as a current source by VREF. M1 supplies IREF to either of the drivers depen~ing on control signals S1 and S2.

Select tr~ncictors Q7 and Q10 are contrûlled by signals S1 and S2. Control ignals S1 and S2 ~etf ...;n~ which current mode driver ! -, n.~ its co~ ùndi lg data to the current mode ~ . For e~mple when S1 is high and S2 is low, IREF flows - thl~u~ll Q7 and current mode driver 1. When this occurs, the data on the input of current mode driver 1, i.e., IN1 and IN1/, is tr~ncmitted to the current mode receiver in the fûrm of a current mode signal. Current mode driver 2 has no effect on lines 10 and 11 since Q10 is offand no current flows through Q8 ûr Q9.

~imil~rly, when S1 is low and S2 is high, IREF flows ~.lough Q10 and current mode driver 2. When this occurs, the data on the input of current mode driver 2, i.e. IN2 and IN2/, is l.,.n.~...;~l~l to the current mode receiver in the form of a current mode signal. Current mode driver 1 has no effect on lines 10 and 11 since Q7 is offand no current flows through Q1 or Q2.

~CI CS/û;G3^~ P~TI~ 941()~

The current mode receiver converts the current mode signal from the ~l~tP~ driver into a dirr~,~"~ial voltage mode signal.
The current mode receiver in Figure 2 includes cascode clamp tr~ncictors Q5 and Q6 and their col~ ,onding NMOS biasing S current sources M2 and M4. M2 and M4 are biased by VREF and are sized so as to provide a ~l~t~d biasing current. Devices M2 and M4 function to bias Q5 and Q6 in their low recict~nre regions to ensure quick recovery from tran~ ntc.

The cascode clamp portion of the receiver includes m~tched 10 load resistors R5 and R6. These resistors are the loads of the f~dh~rl~ ~mplifi~.r which help reduce the voltage excursion at nodes 2 and 3. Under certain circumct~nces during the switching ~.~n the drivers, the total current injection into the tr~ncmiccion lines is greater than IREF. This may result in saturating the - 15 c~cr4de ~mplifirr. The,e~ole, the output is not taken from the cnll~tors of the c~cQde ~mplifirr, but rather at the collectors of the f~db~cl~ ~mplifi~r Q3 and Q4. R7 and R8 are added to increase the gain to produce the l~uiled swing.

The current mode receiver in Figure 2 f~lnctionc in the same 20 manner as the previously desrrihed current mode receiver shown in Figure 1. Thus, similar to the embo~imPns shown in Figure 1, smaller voltage swings are seen on the intelconnect lines (nodes 2 and 4) while relatively larger voltage swing occur on intemal nodes 1 and 3 of s-he receiver. Consequently, tr~nsmi~sion delays are 25 reduced since the peak-to-peak voltage swing on the interconnect Wo 95/05033 211 ~ ré~3 PCT/US94/04613 lines is re~uc~. In addition, in contrast to prior art current mode receivers in which peak-to-peak swings are limited to 60 mV (or slightly higher dep~n-~ing on ~ e and current d~Pncities), the range of output swing of the present invention's receiver is more 5 versatile.
-Although the present invention has been ~esrrihe~ inconju~ ion with certain embo~ u~c, it is app.~ia~ed that the invention may be im~lPmPntPIl in a variety of other ways. By way of e~mr1P~ the conc_~L of the present invention is not strictly 10 limited to a BiCMOS circuit; it can be implemrntPIi with just - bipolar devices. Consequently, it is to be understood that the particular embo li...~ -ls shown and desrrihe~ by way of i~ ctr~tion are in no way intpnded to be concidPred limitin~ Rer~.~nce to the details of these Pmho~im~Pntc is not intPn~P~ to limit the scope of 15 the claims which themselves recite only those fe~lul~ s regarded as e.~ 1 to the invention.

Claims (26)

I Claim:

1. An apparatus for reducing transmission delays of a first differential signal comprising:
a transmitting means for converting said first differential signal into an intermediate differential signal having a peak-to-peak voltage less than the peak-to-peak voltage of said first differential signal, said transmitting means coupling said intermediate differential signal on first and second interconnect lines;
a receiving means for converting said intermediate differential signal into an output differential signal having a peak-to-peak voltage greater than said peak-to-peak voltage of said intermediate differential signal in response to said intermediate differential signal, said receiving means loading said first and second interconnect lines such that said peak-to-peak voltage of said intermediate differential signal is driven to a specific magnitude;
said receiving means also including a feedback means for clamping said peak-to-peak voltage of said intermediate differential signal to a magnitude less than said specific magnitude, said feedback means being coupled to said first and second interconnect lines.

2. The apparatus as described in claim 1 wherein said feedback means comprises a differential amplifier responsive to differential current in said intermediate differential signal.

3. The apparatus as described in claim 2 wherein said receiving means comprises a pair of transistors responsive to said differential current changes, each of the bases of said pair of transistors being coupled to said feedback means and each of the emitters of said pair of transistors being coupled to one of said first and second interconnect lines, said feedback means adjusting the base-to-emitter voltage potentials of each of said pair of transistors such that said peak-to-peak voltage of said intermediate differential signal is clamped to said magnitude less than said specific magnitude.

4. The apparatus as described in claim 3 wherein said peak-to-peak voltage of said output differential signal is greater than about 60 mV and said clamped magnitude of said peak-to-peak voltage of said intermediate differential signal is less than about 60 mV.

5. The apparatus as described in claim 3 wherein said clamped magnitude is approximately equal to 20 mV.

6. The apparatus as described in claim 3 wherein said peak-to-peak voltage of said output differential signal is compatible with emitter coupled logic (ECL) levels.

7. An apparatus for reducing transmission delays of a first voltage mode differential signal comprising:
a transmitting means for converting said first voltage mode differential signal into a current mode differential signal having a peak-to-peak voltage less than the peak-to-peak voltage of said first voltage mode differential signal, said transmitting means coupling said current mode differential signal onto first and second interconnect lines; a receiving means for converting said current mode differential signal into a second voltage mode differential signal in response to differential current changes in said current mode differential signal, said receiving means including a first pair of transistors having each of their emitters coupled to one of said first and second interconnect lines, said first pair of transistors loading said first and second interconnect lines such that said peak-to-peak voltage of said current mode differential signal is driven towards a specific magnitude; said receiving means including a differential amplifier being coupled to the bases of said first pair of transistors, said differential amplifier including a second pair of emitter-coupled transistors having each of their bases coupled to said one of said first and second interconnect lines and their emitters coupled to a first current source, said differential amplifier clamping said peak-to-peak voltage of said current mode differential signal to a magnitude less than said specific magnitude.

8. The apparatus as described in claim 7 wherein said each of said emitters of said first pair of transistors is coupled to one of a pair of current sources, said pair of current sources biasing said first pair of transistors in their low resistance region.

9. The apparatus as described in claim 8 wherein said first current source and said pair of current sources are n-type metal oxide silicon devices each having their gates coupled to a reference voltage, and their sources coupled to a first working potential.

10. The apparatus as described in claim 9 wherein said first and second pairs of transistors are NPN bipolar transistors.

11. The apparatus as described in claim 10 wherein said receiving means further includes a first pair of matched resistive loads each coupled between one of the collectors of said first pair of transistors and a second working potential, said differential output signal being output by said collectors of said first pair of transistors.

12. The apparatus as described in claim 11 wherein said differential amplifier further includes a second pair of matched resistive loads, each of said second pair of matched resistive loads being coupled between one of said collectors of said second pair of emitter-coupled transistors and said second working potential.

13. The apparatus as described in claim 12 wherein said transmitting means comprises a third pair of emitter-coupled transistors having their emitters coupled to a second current source and each of their collectors coupled to said one of said first and second interconnect lines, and their bases coupled to said first voltage mode differential signal.

14. The apparatus as described in claim 13 wherein said peak-to-peak voltage of said second voltage mode signal is greater than 60 mV and said peak-to-peak voltage of said current mode differential signal is less than 60 mV.

15. The apparatus as described in claim 13 wherein said peak-to peak voltage of said current mode differential signal is approximately equal to 20 mV.

16. The apparatus as described in Claim 13 wherein said peak-to-peak voltage of said second voltage mode differential signal is compatible with emitter coupled logic (ECL) levels.

17. An apparatus for reducing transmission delays of at least one differential signal comprising: means for transmitting said at least one differential signal within said integrated circuit, said at least one transmitting means converting said at least one differential signal into a corresponding intermediate differential signal having a peak-to-peak voltage less than the peak-to-peak voltage of said at least one differential signal, said transmitting means coupling said intermediate differential signal onto first and second interconnect lines; means for selecting said transmitting means responsive to a select signal; receiving means for converting said intermediate differential signal into an output differential signal having a peak-to-peak voltage greater than said peak-to-peak voltage of said intermediate differential signal, said receiving means loading said first and second interconnect lines such that said peak-to-peak voltage of said intermediate differential signal is driven to a specific magnitude; said receiving means also including a feedback means for clamping said peak-to-peak voltage of said intermediate differential signal to a magnitude less than said specific magnitude, said feedback means being coupled to said first and second interconnect lines.

18. The apparatus as described in claim 17 wherein said feedback means comprises a differential amplifier responsive to differential current changes in said intermediate differential signal, said differential amplifier including a first pair of emitter-coupled transistors having their emitters coupled to a first current source and each of their collectors coupled to one of a first pair of matched resistive loads, said output differential signal being taken across said collectors of said first pair of emitter-coupled transistors.

19. The apparatus as described in claim 18 wherein said receiving means comprises a second pair of transistors being responsive to said differential current changes, each of the bases of said second pair of transistors being coupled to said feedback means and each of the emitters of said second pair of transistors being coupled to one of said first and second interconnect lines, said feedback means adjusting the base-to-emitter voltage potentials of each of said second pair of transistors such that said peak-to-peak voltage of said intermediate differential signal is clamped to said magnitude less than said specific magnitude.

20. The apparatus as described in claim 19 wherein said each of the emitters of said second pair of transistors is coupled to one of a pair of current sources, said pair of current sources biasing said second pair of transistors in their low resistance region.

21. The apparatus as described in claim 20 wherein said receiving means further includes a second pair of matched resistive loads each being coupled between one of said bases of said second pair of transistors and a first working potential.

22. The apparatus as described in claim 21 wherein said transmitting means includes a third pair of emitter-coupled transistors having their emitters coupled to said selecting means, each of their collectors coupled to said one of said first and second interconnect lines, and their bases coupled to said at least one differential signal, said select means determining whether a second current source is coupled to said emitters of said third pair of emitter-coupled transistors in response to said select signal.

23. The apparatus as described in claim 22 wherein said first, said second, and said pair of current sources are n-type metal oxide silicon devices each having their gates coupled to a reference voltage, and their sources coupled to a second working potential.

24. The apparatus as described in Claim 23 wherein said peak-to-peak voltage of said output differential signal is greater than 60 mV and said peak-to-peak voltage of said intermediate.

differential signal is less than 60 mV.

25. The apparatus as described in Claim 23 wherein said peak-to-peak voltage of said intermediate differential signal is approximately equal to 20 mV.

26. The apparatus as described in Claim 23 wherein said peak-to-peak voltage of said output differential signal is compatible with emitter coupled logic (ECL) levels.