CA2019002C - Data transfer between high bit rate buses via unshielded low bit rate bus - Google Patents
Data transfer between high bit rate buses via unshielded low bit rate busInfo
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- CA2019002C CA2019002C CA002019002A CA2019002A CA2019002C CA 2019002 C CA2019002 C CA 2019002C CA 002019002 A CA002019002 A CA 002019002A CA 2019002 A CA2019002 A CA 2019002A CA 2019002 C CA2019002 C CA 2019002C
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- 230000005540 biological transmission Effects 0.000 claims abstract description 14
- 230000003750 conditioning effect Effects 0.000 claims abstract description 5
- 230000002093 peripheral effect Effects 0.000 claims description 30
- 230000001143 conditioned effect Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 11
- 230000002411 adverse Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
- H04Q11/0435—Details
- H04Q11/0471—Terminal access circuits
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/103—Memories
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/216—Code signals; Framing (not synchronizing)
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/297—Coupling circuits between different (rate) TDM systems
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/299—Bus
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- Computer Networks & Wireless Communication (AREA)
- Communication Control (AREA)
Abstract
A method and apparatus for transferring high data rate data between a pair of separated high data rate buses comprising storing a group of high data rate data from one of the buses, one of which is connected to a digital telephone set, reading the stored data at a low data rate, conditioning the low data rate data to remove high frequency components therefrom, applying the conditioned data to an unshielded cable for transmission to the separated other high data rate bus, receiving and storing the conditioned data from the unshielded cable and reading the stored conditioned data at a high data rate to said other bus.
Description
201~02 02 This invention relates to a data transfer 03 apparatus which is useful to transfer high bit rate 04 data to remote terminals or peripherals without 05 requiring the use of shielded cables.
06 The CCITT has standardized an integrated 07 services digital network (ISDN) protocol by defining a 08 so-called S-interface for transmitting data between 09 various elements of a telephone system. The standard utilizes as what is referred to as 2B+D transmission, 11 that is, transmission on a synchronous serial bus with 12 two 8 bit data channels, referred to as B channels and 13 an 8 bit control channel, that is a D channel. Each 14 data word therefore is comprised of 24 bits. The bit rate is standardized at a high speed 2,048 kilobits 16 per second.
17 The 2B+D protocol, while being used for 18 transmission between systems, is sometimes modified 19 within a system. For example, in some PABX'S produced by Mitel Corporation the stream of data is divided 21 into frames, each frame having a period of 125 22 microseconds. Each frame is divided into 32 8 bit 23 channels, the first four of which are, in sequence, 24 the D channel, an intermediate C channel, and the B
channels. The D and C channels, while 8 bits long, 26 utilize only the first 2 bits in each.
27 Whatever system is used, in order to 28 conform to the CCITT standard, conforming telephone 29 sets or other terminal devices have high data rate (e.g. 2,048 Kb/sec) links with the main control system 31 such as a key telephone system.
32 It is desirable to be able to add 33 peripheral functions to a basic telephone set to be 34 used in an ISDN form of system. For example, a basic telephone set without special features can initially 36 be provided, and as additional features are to be 37 added, modules can be added to the system to provide 38 the additional features and functions. The add-on j 2019~02 -02 modules, in order to meet the CCITT ISDN standard, 03 may each require a 2B+D interface. However the add-on 04 modules can be located a significant distance from the 05 basic telephone set. For example the peripheral 06 modules could be a voice announce module, an analog 07 terminal adapter, a data transmission module, a 08 specialized visual display module, etc. Those modules 09 could be located, if not plugged directly into the telephone set or located meters away, even as far as 11 one hundred meters or more from the basic telephone 12 set.
13 The requirement to locate a peripheral 14 module a significant distance from the telephone set 15 using a high data rate bus presents a significant 16 problem. The high data rate bus requires shielding in 17 order to minimize radio frequency emissions. This is 18 costly and presents installation problems involving a 19 thick cable. It has been found that with the 20 connection of the peripherals to the digital telephone 21 set when the peripherals are located a signicant 22 distance from the telephone set, and especially when 23 there are several peripherals connected to the 24 telephone set, even with shielded cable the amount of 25 radio frequency emissions increases to an intolerable 26 level, interfering with the operation of nearby 27 equipment and exceeding national standards.
28 The present invention is a data transfer 29 apparatus which connects to the high speed bus of the telephone set or other 2B+D data signal generating 31 apparatus or other ISDN high data rate signal 32 generating apparatus, which converts the signal to a 33 low data rate. Similar converting apparatus is 34 connected to the high speed data interface at each of the peripherals. The telephone set, or other 36 corresponding central terminal, and the peripherals 37 thereby communicate between themselves by means of a 38 low data rate serial bus. With conditioning of the 201~2 01 _ 3 _ 02 data pulse edges of signals transmitted on the low 03 data rate bus, an unshielded bus cable can be used 04 without generating adverse levels of radio frequency 05 emissions. Indeed, rather than using a shielded 06 cable, inexpensive standard four wire telephone cable 07 can be used. This results in considerable cost 08 reduction, minimization of interference with other 09 equipment, and the ability to add additional peripheral equipment in a modular manner at minimum 11 cost, while obtaining the benefits of ISDN and meeting 12 the CCITT 2B+D channel standard external to the low 13 data rate serial bus.
14 The above advantages are obtained in an embodiment of the invention which is a data transfer 16 apparatus comprising first and second shift registers 17 each having similar capacities, apparatus for writing 18 incoming data from a first high data rate bus into the 19 first shift register during a first predetermined time interval at a high bit rate, apparatus for reading the 21 data stored in the first shift register onto a low 22 data rate bus for outward transmission during a second 23 predetermined time interval at a low bit rate, 24 apparatus for writing incoming data from the low data rate bus into the second shift register during the 26 interval when data stored in the first shift register 27 is being read, apparatus for reading outgoing data 28 from the second shift register to the first high data 29 rate bus during the interval when data stored in the first shift register is being written, apparatus for 31 providing a high bit rate clock signal, apparatus for 32 providing a low bit rate clock signal, apparatus for 33 clocking both first and second shift registers using 34 the high bit rate clock signal during the first predetermined time interval, and apparatus for 36 clocking both first and second shift registers using 37 the low bit rate clock signal during the second 38 predetermined time interval, the clocking intervals of 20190~2 02 the low and high bit rate clock signals alternating 03 with each other.
04 Another embodiment of the invention is a 05 data transfer apparatus between a terminal such as a 06 telephone set having a first high bit rate serial data 07 bus and plural peripherals, comprising a first 08 converter connected to the data bus for converting 09 high bit rate incoming data signals carried by the data bus to low bit rate signals and low bit rate 11 incoming data signals to high bit rate outing data 12 signals, plural second converters each at a peripheral 13 for converting low bit rate incoming data signals to 14 high bit rate outgoing data signals and high bit rate incoming data signals to low bit rate outgoing data 16 signals, each of the converters comprising first and 17 second shift registers each having the capacity of a 18 data frame, apparatus for writing incoming data 19 signals from a high data rate bus connected thereto into the first shift register during a data frame time 21 interval at a high bit rate, apparatus for reading the 22 data stored in the first shift register onto a low 23 speed data rate bus for outward transmission during a 24 data frame time interval at a low bit rate, apparatus for writing incoming data from the low data rate bus 26 into the second shift register during the interval 27 when data stored in the first shift register is being 28 read, apparatus for reading data from the second shift 29 register to the high data rate bus connected thereto during the interval when data stored in the first 31 shift register is being written, apparatus for 32 providing a separate high bit rate clock signal for 33 each converter, apparatus for providing a separate low 34 bit rate clock signal for each converter, apparatus for clocking both first and second shift registers of 36 each converter using the respective high bit rate 37 clock signal during the high data rate data frame time 38 interval, and apparatus for clocking both first and 20lsao2 02 second shift registers of each converter using the 03 low bit rate clock signal during the low data rate 04 data frame time interval, the clocking intervals of 05 the low and high bit rate clock signals in each 06 converter alternating with each other, apparatus for 07 outwardly transmitting low data rate data between the 08 peripherals on the low data rate bus and for receiving 09 low data rate data from the low data rate data bus.
Preferably the clock at the peripheral 11 units is generated by synchronization to frames of 12 data received from the telephone set or terminal, 13 rather than on a clock pulse by clock pulse basis.
14 This ensures that no data will be lost due to a cycle slip caused by differences in clock frequencieS
16 between the telephone set and the peripheral units.
17 Rather than the shift registers having the 18 capacities of a frame of data, they could 19 alternatively have the capacities of data words, superframes, or some other convenient quantity.
21 However for the 2B+D standard, a frame containing the 22 2B+D channels is the preferred capacity.
23 A better understanding of the invention 24 will be obtained by reference to the detailed description below, and to the following figures, in 26 which:
27 Figure 1 is a basic block diagram 28 illustrating a system in which the invention is to be 29 used, Figure 2 is a basic block diagram of the 31 invention, 32 Figure 3 is a block diagram of the 33 converter at the telephone set or main terminal.
34 Figure 4 is a block diagram of the converter found in each of the remote terminals, and 36 Figure 5 is a timing diagram of data used 37 to illustrate the operation of the invention.
38 While the term telephone set will be used 02 below in the description, it is intended that the term 03 should be construed to mean any controlling terminal 04 which is to communicate with peripheral terminals 05 which have 2B+D interfaces or the equivalent for 06 implementing the invention.
07 Turning now to Figure 1, a key telephone 08 system control unit KSU 1 has trunks 2 connected to it 09 for communicating in a well known manner. In addition line circuits 3 which communicate also in an ISDN or 11 other digital based format are provided, to which 12 plural telephone sets such as telephone set 4 are 13 connected. Terminals or peripherals which provide 14 various functions, such as those described above, are connected to telephone set 4. The terminals 5 can be 16 located a significant distance from telephone set 4.
17 It is to the link between the telephone set 4 and 18 terminals 5 to which the present invention is 19 directed.
Figure 2 illustrates a block diagram of 21 such a link. Telephone set 4 contains a digital 22 network interface unit (DNIC) 6 which communicates 23 using a standard digital format via high data rate 24 link 7 to the KSU. ThuS each link 7 corresponds to a line circuit 3, what in analog terms would be called 26 the subscriber loop. The digital network interface 27 unit DNIC 6 is a known device, and is sold by Mitel 28 Corporation under the code type MT8972. The output of 29 the DNIC is a high data rate bus referred by Mitel Corporation in literature describing the MT8972 device 31 as an ST bus 8. Bus 8 is a high data rate bus which 32 is a variant of the CCITT standard 2s+D.
33 Each terminal 5 also has a corresponding 34 high speed bus interface 9, which corresponds to the bus 8 in data rate and standard data transmission 36 protocol.
37 Data signals in, for example, the ST bus 38 standard thus normally appear on bus 8, are - 2019~02 02 transmitted to terminals 5. Thus terminals 5 can 03 communicate with other peripherals, other devices, 04 etc. at the same data rate as if they were connected 05 directly to DNIC 6.
06 AS noted earlier, the distance of 07 terminals 5 from telephone set 4, and the number of 08 terminals 5 used has been found to cause objectionable 09 radio frequency emissions even when they are connected by means of shielded cables. The present invention 11 provides means for eliminating this problem.
12 In accordance with the present invention 13 the telephone set 4 contains a first converter 10.
14 Converter 10 is connected to high data rate serial bus 8 and converts the data thereon to low data rate 16 signals, which are applied to low data rate bus 11.
17 Converter 10 also receives low data rate 18 signals from bus 11 and converts them to high data 19 rate signals in the format carried by bus 8 for application to bus 8.
21 Each of the terminals 5 contains a 22 corresponding second converter 12 which receives low 23 data rate signals from bus 11 and converts them to 24 high data rate signals of the same format as the signals carried by bus 8, and applies them to 26 corresponding bus 9. Preferably the low bit rate 27 clock is obtained from the telephone set 4.
28 Figure 3 illustrates a preferred 29 embodiment of converter 10 in a more detailed block diagram. Refer also to the timing diagram of Figure 31 5. The DNIC 6 high data rate bus variant of the 2B+D
32 CCITT bus, referred to as an ST bus, has an STo 33 (output) line and STi (input) line, as well as a low 34 bit rate clock and frame pulse output line 14 (C4, F0).
36 Two 24 bit shift registers 15 and 16 each 37 having capacity of a 2B+D + 2 unused bits + C + 2 38 unused bits are used. High speed (data rate) data 02 signal on the STo line is applied to shift register 03 15. The clock on one of the leads of line 14 and the 04 frame pulse FO on the second lead of line 14 are 05 applied to clock control and synchronization circuit 06 17. When the frame pulse appears, the clock control 07 and synchronization circuit 17 applies a clock signal 08 at the high data rate (2,048 kb/sec) to shift register 09 15. A frame of the high data rate signal is as a result serially written into the shift register 15.
11 The STo bus carries four data channels in 12 a frame referred to as D, C, B, and B, the D and two B
13 channels corresponding to the D and two B channels of 14 the CCITT standard. As may be seen from the signal timing diagram in Figure 5, at the left hand side of 16 the top diagram, the shift register loads first the D, 17 2 unused bits, then the C plus 3 unused bits, then the 18 two B channels, in sequence. At the above-noted high 19 speed data rate, this takes 15.6 microseconds, as shown on the diagram.
21 The low bit rate (e.g. 256 Kb/sec) clock 22 from line 14 at the output of circuit 17 is counted in 23 counter and control circuit 18, which, after counting 24 the clock counts corresponding to the number of bits of each 2B+C+D data word, applies a clock control 26 signal (level change) to the clock control and 27 synchronization circuit 17. As a result, circuit 17 28 switches its clock to a low data rate, i.e.
29 256 Kb/sec. This clock is applied to shift register 15.
31 Because the format of the Mitel system 32 ST-BUS~ is 8 bits for the D and C channels, 4 bits in 33 each channel are ignored. The circuit switches after 34 32 bits. However other protocols may be used, within the scope of the invention.
36 Circuit 17 also applies a read control 37 signal to the shift register, which terminates its 38 writing mode and causes reading of the stored data - 20~9Q0~
01 _ 9 _ 02 therein at 256 kb/sec. This data is read out to edge 03 conditioner 19, which reduces the rate of change (the 04 rise and fall times) of the edges of the data pulses 05 read from shift register 15, and rolls the corners of 06 the data pulses, in order to remove high frequency 07 components therefrom, and thereby to reduce or 08 eliminate radio frequency harmonics. The output of 09 the edge conditioning circuit is applied to the low data rate bus lead llA.
11 While shift register 15 is controlled by 12 circuit 17 to read data that has been stored therein, 13 shift register 16 is controlled by circuit 17 to write 14 data received from the low data rate bus lead 11B.
15 Data appearing thereon at the same data rate as on 16 line llA, received from the peripherals, is written 17 into shift register 16, which is clocked at the same 18 rate as shift register 15. Therefore while shift 19 register 15 is outputting data at the low data rate to 20 low data rate bus lead llA, shift register 16 is 21 reading low data rate data into it from the low data 22 rate bus lead 4B, as may be seen in Figure 5. BUS
23 lead 11B is Schmitt triggered at its input to reduce 24 false signals due to noise on the line.
Following the high data rate writing 26 activity in shift register 15 of the D, C, B and B
27 channels described above, the low data rate channels 28 are transmitted over the following interval of 93.8 29 microseconds. An interval of 15.6 microseconds following the termination of the low data rate 31 transmission, labelled "not active" follows. The 32 inactive period is preferred to be left idle to allow 33 for frame synchronization due to clock frequency and 34 phase differences, etc. It therefore forms a variable buffered interval.
36 The counter and control circuit 18 counts 37 the clock pulses (e.g. 32) applied to shift register 38 15 by clock control and synchronization 17, and 201~)2 02 following that count applies a clock control signal to 03 clock control and synchronization circuit 17 to cause 04 it to switch it to clocking at the high data rate of 05 2,048 kb/sec after waiting for the start of the next 06 data frame as indicated by a pulse on the F0 lead.
07 Shift register 15, having been emptied of data, as a 08 result writes signals received from the STo lead, as 09 before, having received a write enable signal from circuit 17 generated at the clock rate change line.
11 The shift register 16 also receives a read enable 12 signal from circuit 17 generated at the same time, 13 which causes it to read its data out at the clock 14 speed of circuit 17 applied to both shift registers, i.e. at the high data rate of 2,048 kb/sec. The high 16 data rate signal is applied from shift register signal 17 16 through multiplexer 20, if used, to the input lead 18 STi of the ST bus. The signal is applied to DNIC 6, 19 to be transmitted to the key system unit 1.
The clock signal from circuit 17 during 21 the low data speed bus active intervals, is applied to 22 an edge conditioner 21, which controls the rise and 23 fall edges of the clock pulses in a manner similar to 24 that of edge conditioner 19, and applies the clock pulses to the clock lead llC of the low speed bus.
26 Following the count of 32 clock pulses 27 applied to shift registers 15 and 16, the counter and 28 control circuit 18 applies another control signal to 29 circuit 17 which again enables shift register 15 to read and again reduces the clock rate to the slow bit 31 rate, i.e. 256 kb/sec. The sequence then repeats, as 32 may be seen in the top row of Figure 5. The shift 33 register 15 first writes (Tx ST-BUS In) at the high 34 bit rate, then reads to the low speed bus at the low bit rate. When the data is being read to the low bit 36 rate bus from shift register 15, it is written (row RX
37 in Figure 5) from the low bit rate bus into register 38 16.
06 The CCITT has standardized an integrated 07 services digital network (ISDN) protocol by defining a 08 so-called S-interface for transmitting data between 09 various elements of a telephone system. The standard utilizes as what is referred to as 2B+D transmission, 11 that is, transmission on a synchronous serial bus with 12 two 8 bit data channels, referred to as B channels and 13 an 8 bit control channel, that is a D channel. Each 14 data word therefore is comprised of 24 bits. The bit rate is standardized at a high speed 2,048 kilobits 16 per second.
17 The 2B+D protocol, while being used for 18 transmission between systems, is sometimes modified 19 within a system. For example, in some PABX'S produced by Mitel Corporation the stream of data is divided 21 into frames, each frame having a period of 125 22 microseconds. Each frame is divided into 32 8 bit 23 channels, the first four of which are, in sequence, 24 the D channel, an intermediate C channel, and the B
channels. The D and C channels, while 8 bits long, 26 utilize only the first 2 bits in each.
27 Whatever system is used, in order to 28 conform to the CCITT standard, conforming telephone 29 sets or other terminal devices have high data rate (e.g. 2,048 Kb/sec) links with the main control system 31 such as a key telephone system.
32 It is desirable to be able to add 33 peripheral functions to a basic telephone set to be 34 used in an ISDN form of system. For example, a basic telephone set without special features can initially 36 be provided, and as additional features are to be 37 added, modules can be added to the system to provide 38 the additional features and functions. The add-on j 2019~02 -02 modules, in order to meet the CCITT ISDN standard, 03 may each require a 2B+D interface. However the add-on 04 modules can be located a significant distance from the 05 basic telephone set. For example the peripheral 06 modules could be a voice announce module, an analog 07 terminal adapter, a data transmission module, a 08 specialized visual display module, etc. Those modules 09 could be located, if not plugged directly into the telephone set or located meters away, even as far as 11 one hundred meters or more from the basic telephone 12 set.
13 The requirement to locate a peripheral 14 module a significant distance from the telephone set 15 using a high data rate bus presents a significant 16 problem. The high data rate bus requires shielding in 17 order to minimize radio frequency emissions. This is 18 costly and presents installation problems involving a 19 thick cable. It has been found that with the 20 connection of the peripherals to the digital telephone 21 set when the peripherals are located a signicant 22 distance from the telephone set, and especially when 23 there are several peripherals connected to the 24 telephone set, even with shielded cable the amount of 25 radio frequency emissions increases to an intolerable 26 level, interfering with the operation of nearby 27 equipment and exceeding national standards.
28 The present invention is a data transfer 29 apparatus which connects to the high speed bus of the telephone set or other 2B+D data signal generating 31 apparatus or other ISDN high data rate signal 32 generating apparatus, which converts the signal to a 33 low data rate. Similar converting apparatus is 34 connected to the high speed data interface at each of the peripherals. The telephone set, or other 36 corresponding central terminal, and the peripherals 37 thereby communicate between themselves by means of a 38 low data rate serial bus. With conditioning of the 201~2 01 _ 3 _ 02 data pulse edges of signals transmitted on the low 03 data rate bus, an unshielded bus cable can be used 04 without generating adverse levels of radio frequency 05 emissions. Indeed, rather than using a shielded 06 cable, inexpensive standard four wire telephone cable 07 can be used. This results in considerable cost 08 reduction, minimization of interference with other 09 equipment, and the ability to add additional peripheral equipment in a modular manner at minimum 11 cost, while obtaining the benefits of ISDN and meeting 12 the CCITT 2B+D channel standard external to the low 13 data rate serial bus.
14 The above advantages are obtained in an embodiment of the invention which is a data transfer 16 apparatus comprising first and second shift registers 17 each having similar capacities, apparatus for writing 18 incoming data from a first high data rate bus into the 19 first shift register during a first predetermined time interval at a high bit rate, apparatus for reading the 21 data stored in the first shift register onto a low 22 data rate bus for outward transmission during a second 23 predetermined time interval at a low bit rate, 24 apparatus for writing incoming data from the low data rate bus into the second shift register during the 26 interval when data stored in the first shift register 27 is being read, apparatus for reading outgoing data 28 from the second shift register to the first high data 29 rate bus during the interval when data stored in the first shift register is being written, apparatus for 31 providing a high bit rate clock signal, apparatus for 32 providing a low bit rate clock signal, apparatus for 33 clocking both first and second shift registers using 34 the high bit rate clock signal during the first predetermined time interval, and apparatus for 36 clocking both first and second shift registers using 37 the low bit rate clock signal during the second 38 predetermined time interval, the clocking intervals of 20190~2 02 the low and high bit rate clock signals alternating 03 with each other.
04 Another embodiment of the invention is a 05 data transfer apparatus between a terminal such as a 06 telephone set having a first high bit rate serial data 07 bus and plural peripherals, comprising a first 08 converter connected to the data bus for converting 09 high bit rate incoming data signals carried by the data bus to low bit rate signals and low bit rate 11 incoming data signals to high bit rate outing data 12 signals, plural second converters each at a peripheral 13 for converting low bit rate incoming data signals to 14 high bit rate outgoing data signals and high bit rate incoming data signals to low bit rate outgoing data 16 signals, each of the converters comprising first and 17 second shift registers each having the capacity of a 18 data frame, apparatus for writing incoming data 19 signals from a high data rate bus connected thereto into the first shift register during a data frame time 21 interval at a high bit rate, apparatus for reading the 22 data stored in the first shift register onto a low 23 speed data rate bus for outward transmission during a 24 data frame time interval at a low bit rate, apparatus for writing incoming data from the low data rate bus 26 into the second shift register during the interval 27 when data stored in the first shift register is being 28 read, apparatus for reading data from the second shift 29 register to the high data rate bus connected thereto during the interval when data stored in the first 31 shift register is being written, apparatus for 32 providing a separate high bit rate clock signal for 33 each converter, apparatus for providing a separate low 34 bit rate clock signal for each converter, apparatus for clocking both first and second shift registers of 36 each converter using the respective high bit rate 37 clock signal during the high data rate data frame time 38 interval, and apparatus for clocking both first and 20lsao2 02 second shift registers of each converter using the 03 low bit rate clock signal during the low data rate 04 data frame time interval, the clocking intervals of 05 the low and high bit rate clock signals in each 06 converter alternating with each other, apparatus for 07 outwardly transmitting low data rate data between the 08 peripherals on the low data rate bus and for receiving 09 low data rate data from the low data rate data bus.
Preferably the clock at the peripheral 11 units is generated by synchronization to frames of 12 data received from the telephone set or terminal, 13 rather than on a clock pulse by clock pulse basis.
14 This ensures that no data will be lost due to a cycle slip caused by differences in clock frequencieS
16 between the telephone set and the peripheral units.
17 Rather than the shift registers having the 18 capacities of a frame of data, they could 19 alternatively have the capacities of data words, superframes, or some other convenient quantity.
21 However for the 2B+D standard, a frame containing the 22 2B+D channels is the preferred capacity.
23 A better understanding of the invention 24 will be obtained by reference to the detailed description below, and to the following figures, in 26 which:
27 Figure 1 is a basic block diagram 28 illustrating a system in which the invention is to be 29 used, Figure 2 is a basic block diagram of the 31 invention, 32 Figure 3 is a block diagram of the 33 converter at the telephone set or main terminal.
34 Figure 4 is a block diagram of the converter found in each of the remote terminals, and 36 Figure 5 is a timing diagram of data used 37 to illustrate the operation of the invention.
38 While the term telephone set will be used 02 below in the description, it is intended that the term 03 should be construed to mean any controlling terminal 04 which is to communicate with peripheral terminals 05 which have 2B+D interfaces or the equivalent for 06 implementing the invention.
07 Turning now to Figure 1, a key telephone 08 system control unit KSU 1 has trunks 2 connected to it 09 for communicating in a well known manner. In addition line circuits 3 which communicate also in an ISDN or 11 other digital based format are provided, to which 12 plural telephone sets such as telephone set 4 are 13 connected. Terminals or peripherals which provide 14 various functions, such as those described above, are connected to telephone set 4. The terminals 5 can be 16 located a significant distance from telephone set 4.
17 It is to the link between the telephone set 4 and 18 terminals 5 to which the present invention is 19 directed.
Figure 2 illustrates a block diagram of 21 such a link. Telephone set 4 contains a digital 22 network interface unit (DNIC) 6 which communicates 23 using a standard digital format via high data rate 24 link 7 to the KSU. ThuS each link 7 corresponds to a line circuit 3, what in analog terms would be called 26 the subscriber loop. The digital network interface 27 unit DNIC 6 is a known device, and is sold by Mitel 28 Corporation under the code type MT8972. The output of 29 the DNIC is a high data rate bus referred by Mitel Corporation in literature describing the MT8972 device 31 as an ST bus 8. Bus 8 is a high data rate bus which 32 is a variant of the CCITT standard 2s+D.
33 Each terminal 5 also has a corresponding 34 high speed bus interface 9, which corresponds to the bus 8 in data rate and standard data transmission 36 protocol.
37 Data signals in, for example, the ST bus 38 standard thus normally appear on bus 8, are - 2019~02 02 transmitted to terminals 5. Thus terminals 5 can 03 communicate with other peripherals, other devices, 04 etc. at the same data rate as if they were connected 05 directly to DNIC 6.
06 AS noted earlier, the distance of 07 terminals 5 from telephone set 4, and the number of 08 terminals 5 used has been found to cause objectionable 09 radio frequency emissions even when they are connected by means of shielded cables. The present invention 11 provides means for eliminating this problem.
12 In accordance with the present invention 13 the telephone set 4 contains a first converter 10.
14 Converter 10 is connected to high data rate serial bus 8 and converts the data thereon to low data rate 16 signals, which are applied to low data rate bus 11.
17 Converter 10 also receives low data rate 18 signals from bus 11 and converts them to high data 19 rate signals in the format carried by bus 8 for application to bus 8.
21 Each of the terminals 5 contains a 22 corresponding second converter 12 which receives low 23 data rate signals from bus 11 and converts them to 24 high data rate signals of the same format as the signals carried by bus 8, and applies them to 26 corresponding bus 9. Preferably the low bit rate 27 clock is obtained from the telephone set 4.
28 Figure 3 illustrates a preferred 29 embodiment of converter 10 in a more detailed block diagram. Refer also to the timing diagram of Figure 31 5. The DNIC 6 high data rate bus variant of the 2B+D
32 CCITT bus, referred to as an ST bus, has an STo 33 (output) line and STi (input) line, as well as a low 34 bit rate clock and frame pulse output line 14 (C4, F0).
36 Two 24 bit shift registers 15 and 16 each 37 having capacity of a 2B+D + 2 unused bits + C + 2 38 unused bits are used. High speed (data rate) data 02 signal on the STo line is applied to shift register 03 15. The clock on one of the leads of line 14 and the 04 frame pulse FO on the second lead of line 14 are 05 applied to clock control and synchronization circuit 06 17. When the frame pulse appears, the clock control 07 and synchronization circuit 17 applies a clock signal 08 at the high data rate (2,048 kb/sec) to shift register 09 15. A frame of the high data rate signal is as a result serially written into the shift register 15.
11 The STo bus carries four data channels in 12 a frame referred to as D, C, B, and B, the D and two B
13 channels corresponding to the D and two B channels of 14 the CCITT standard. As may be seen from the signal timing diagram in Figure 5, at the left hand side of 16 the top diagram, the shift register loads first the D, 17 2 unused bits, then the C plus 3 unused bits, then the 18 two B channels, in sequence. At the above-noted high 19 speed data rate, this takes 15.6 microseconds, as shown on the diagram.
21 The low bit rate (e.g. 256 Kb/sec) clock 22 from line 14 at the output of circuit 17 is counted in 23 counter and control circuit 18, which, after counting 24 the clock counts corresponding to the number of bits of each 2B+C+D data word, applies a clock control 26 signal (level change) to the clock control and 27 synchronization circuit 17. As a result, circuit 17 28 switches its clock to a low data rate, i.e.
29 256 Kb/sec. This clock is applied to shift register 15.
31 Because the format of the Mitel system 32 ST-BUS~ is 8 bits for the D and C channels, 4 bits in 33 each channel are ignored. The circuit switches after 34 32 bits. However other protocols may be used, within the scope of the invention.
36 Circuit 17 also applies a read control 37 signal to the shift register, which terminates its 38 writing mode and causes reading of the stored data - 20~9Q0~
01 _ 9 _ 02 therein at 256 kb/sec. This data is read out to edge 03 conditioner 19, which reduces the rate of change (the 04 rise and fall times) of the edges of the data pulses 05 read from shift register 15, and rolls the corners of 06 the data pulses, in order to remove high frequency 07 components therefrom, and thereby to reduce or 08 eliminate radio frequency harmonics. The output of 09 the edge conditioning circuit is applied to the low data rate bus lead llA.
11 While shift register 15 is controlled by 12 circuit 17 to read data that has been stored therein, 13 shift register 16 is controlled by circuit 17 to write 14 data received from the low data rate bus lead 11B.
15 Data appearing thereon at the same data rate as on 16 line llA, received from the peripherals, is written 17 into shift register 16, which is clocked at the same 18 rate as shift register 15. Therefore while shift 19 register 15 is outputting data at the low data rate to 20 low data rate bus lead llA, shift register 16 is 21 reading low data rate data into it from the low data 22 rate bus lead 4B, as may be seen in Figure 5. BUS
23 lead 11B is Schmitt triggered at its input to reduce 24 false signals due to noise on the line.
Following the high data rate writing 26 activity in shift register 15 of the D, C, B and B
27 channels described above, the low data rate channels 28 are transmitted over the following interval of 93.8 29 microseconds. An interval of 15.6 microseconds following the termination of the low data rate 31 transmission, labelled "not active" follows. The 32 inactive period is preferred to be left idle to allow 33 for frame synchronization due to clock frequency and 34 phase differences, etc. It therefore forms a variable buffered interval.
36 The counter and control circuit 18 counts 37 the clock pulses (e.g. 32) applied to shift register 38 15 by clock control and synchronization 17, and 201~)2 02 following that count applies a clock control signal to 03 clock control and synchronization circuit 17 to cause 04 it to switch it to clocking at the high data rate of 05 2,048 kb/sec after waiting for the start of the next 06 data frame as indicated by a pulse on the F0 lead.
07 Shift register 15, having been emptied of data, as a 08 result writes signals received from the STo lead, as 09 before, having received a write enable signal from circuit 17 generated at the clock rate change line.
11 The shift register 16 also receives a read enable 12 signal from circuit 17 generated at the same time, 13 which causes it to read its data out at the clock 14 speed of circuit 17 applied to both shift registers, i.e. at the high data rate of 2,048 kb/sec. The high 16 data rate signal is applied from shift register signal 17 16 through multiplexer 20, if used, to the input lead 18 STi of the ST bus. The signal is applied to DNIC 6, 19 to be transmitted to the key system unit 1.
The clock signal from circuit 17 during 21 the low data speed bus active intervals, is applied to 22 an edge conditioner 21, which controls the rise and 23 fall edges of the clock pulses in a manner similar to 24 that of edge conditioner 19, and applies the clock pulses to the clock lead llC of the low speed bus.
26 Following the count of 32 clock pulses 27 applied to shift registers 15 and 16, the counter and 28 control circuit 18 applies another control signal to 29 circuit 17 which again enables shift register 15 to read and again reduces the clock rate to the slow bit 31 rate, i.e. 256 kb/sec. The sequence then repeats, as 32 may be seen in the top row of Figure 5. The shift 33 register 15 first writes (Tx ST-BUS In) at the high 34 bit rate, then reads to the low speed bus at the low bit rate. When the data is being read to the low bit 36 rate bus from shift register 15, it is written (row RX
37 in Figure 5) from the low bit rate bus into register 38 16.
2~19~û2 02 It should be noted that the output enable 03 control of shift registers 15 and 16 could 04 alternatively be made from circuit 18, rather than from 05 circuit 17.
06 Control circuitry 22 also interfaces the 07 STo line, which provides a D request/channel contention 08 line 23, and a channel selection control signal to 09 multiplexer 20. Multiplexer 20 allows multiplexing of the converter high data rate signal from the low data 11 rate bus to be interleaved with other high rate data 12 from control circuit 22, which controls the multiplexer 13 based on instructions from the KSU and monitoring the 14 signal on the D channel request/contention line 23.
Figure 4 illustrates a preferred embodiment 16 of a peripheral terminal 5. Each terminal 5 contains 17 two 24 bit shift registers 24 and 25, which correspond 18 and are similar to shift registers 16 and 15 19 respectively. A clock control and synchronization circuit 17 and counter and control circuit 18 21 correspond to clock control and synchronization circuit 22 17 and counter and control circuit 18 illustrated in 23 Figure 3.
24 Data received on low speed bus lead llC is applied to shift register 24, which is clocked at low 26 speed by the clock control and synchronization circuit 27 17. 24 bits are received, corresponding to a frame of 28 the D, C, B and B channels. The output of shift 29 register 24 is also enabled in a similar manner as described above, to output 32 bits of data from lead 31 llA.
32 The reading sequence of the four channels 33 at low speed is shown in lines of data shown in Figure 34 5, in the upper row referenced Rx (1,1,1,1,2,2,2,2, etc.).
36 The counter and control circuit 18 counts 37 the 32 clock pulses and then applies a clock control 38 signal in a manner similar to that described above to 201900~
02 clock control and synchronization circuit 17. This 03 causes circuit 17 to change its clock rate to the 04 higher bit rate, and to apply clock signals to shift 05 registers 24 and 25 at the high data rate 2,048 06 kb/sec. Circuit 18 also applies a signal to shift 07 register 24 to cause it to read, and to circuit 17, 08 causing it to generate an F0 pulse indicating the 09 beginning of the high data rate series of channels.
Shift register 24 therefore, at the high data rate, 11 applies the signal stored therein to the high speed 12 bus interface lead 9, which corresponds to the STo 13 lead of the ST bus at the output of DNIC 6.
14 At the same time high speed bus data is applied to the input of shift register 25, and is 16 written to it at the high data rate.
17 Counter and clock circuit 18 having 18 counted 32 clock pulses, then again applies a clock 19 control signal to clock control and synchronization circuit 17, which applies a read enable signal to 21 shift register 25 and changes its clock rate to the 22 lower rate, the 256 Kbsec. When the clock on llC
23 again becomes active, the shift register 25 reads all 24 of the bits of data stored therein and applies them through edge conditioner 26 to low speed bus data lead 26 llB. Edge conditioner 26 operates similar to edge 27 conditioner 19, reducing or eliminating radio 28 frequency components which would otherwise be 29 generated by high slope and sharp cornered data pulses. The resulting signals on lead llB are 31 received by shift register 16 in converter 10 (Figure 32 3).
33 It may be seen therefore that the circuit 34 of Figure 4 operates similar to the corresponding circuit in converter 10.
36 The D channel contention line 23 from 37 circuit 22 (Figure 3) is applied to an enable input of 38 peripheral 5, whereby any of the terminals 5 can 2019~02 -02 request transmission during any particular time 03 interval. This is controlled by the Other Terminal 04 and Control circuitry 22 in a well known manner for 05 selecting which of several terminal 5 signal 06 generators should transmit and receive during a 07 particular time interval.
08 With reference to Figure 4, a locally 09 generated high speed clock signal (4 mHZ) is applied to clock control and synchronization circuit 17 on 11 lead 27. The clock generated in clock control and 12 synchronization circuit 17 (Figure 3), edge 13 conditioned, appearing on interface clock lead llC, is 14 also applied to clock control and synchronization circuit 17. The clock control and synchronization 16 circuit 17 counts the clock pulses on line llC. At 17 the end of the counted twenty-fourth clock edge, 18 signifying the last data bit of the frame, of the 19 clock, a frame pulse is generated, which is applied to line 28. Following definition of the frame edge, the 21 local high speed clock signal from lead 27 is applied 22 on the clock C2 lead 29, for synchronization of other 23 circuits in the peripheral 5, and also to provide the 24 shift clock pulses at the high speed to shift registers 24 and 25, whereupon the data is read at 26 high data rate from register 24 to the bus lead 9.
27 While there will be a phase difference 28 between the high speed local clock signal on lead 27 29 and the low speed data applied to lead llB, the phase shift time will virtually never be longer than 1 bit 31 interval. Therefore due to the high to low and low to 32 high speed conversion, the system is phase difference 33 tolerant, and it is not necessary to utilize a phase 34 locked loop or similar structure to exactly phase lock each of the peripherals to the telephone set converter 36 clock control and synchronization circuit 17. The 37 cost of the peripherals is thus substantially less 38 than would otherwise be expected.
2019~02 02 A person understanding this invention may 03 now conceive of other alternatives or embodiments 04 using the principles described herein. All are 05 considered to be within the sphere and scope of the 06 invention as defined in the claims appended hereto.
06 Control circuitry 22 also interfaces the 07 STo line, which provides a D request/channel contention 08 line 23, and a channel selection control signal to 09 multiplexer 20. Multiplexer 20 allows multiplexing of the converter high data rate signal from the low data 11 rate bus to be interleaved with other high rate data 12 from control circuit 22, which controls the multiplexer 13 based on instructions from the KSU and monitoring the 14 signal on the D channel request/contention line 23.
Figure 4 illustrates a preferred embodiment 16 of a peripheral terminal 5. Each terminal 5 contains 17 two 24 bit shift registers 24 and 25, which correspond 18 and are similar to shift registers 16 and 15 19 respectively. A clock control and synchronization circuit 17 and counter and control circuit 18 21 correspond to clock control and synchronization circuit 22 17 and counter and control circuit 18 illustrated in 23 Figure 3.
24 Data received on low speed bus lead llC is applied to shift register 24, which is clocked at low 26 speed by the clock control and synchronization circuit 27 17. 24 bits are received, corresponding to a frame of 28 the D, C, B and B channels. The output of shift 29 register 24 is also enabled in a similar manner as described above, to output 32 bits of data from lead 31 llA.
32 The reading sequence of the four channels 33 at low speed is shown in lines of data shown in Figure 34 5, in the upper row referenced Rx (1,1,1,1,2,2,2,2, etc.).
36 The counter and control circuit 18 counts 37 the 32 clock pulses and then applies a clock control 38 signal in a manner similar to that described above to 201900~
02 clock control and synchronization circuit 17. This 03 causes circuit 17 to change its clock rate to the 04 higher bit rate, and to apply clock signals to shift 05 registers 24 and 25 at the high data rate 2,048 06 kb/sec. Circuit 18 also applies a signal to shift 07 register 24 to cause it to read, and to circuit 17, 08 causing it to generate an F0 pulse indicating the 09 beginning of the high data rate series of channels.
Shift register 24 therefore, at the high data rate, 11 applies the signal stored therein to the high speed 12 bus interface lead 9, which corresponds to the STo 13 lead of the ST bus at the output of DNIC 6.
14 At the same time high speed bus data is applied to the input of shift register 25, and is 16 written to it at the high data rate.
17 Counter and clock circuit 18 having 18 counted 32 clock pulses, then again applies a clock 19 control signal to clock control and synchronization circuit 17, which applies a read enable signal to 21 shift register 25 and changes its clock rate to the 22 lower rate, the 256 Kbsec. When the clock on llC
23 again becomes active, the shift register 25 reads all 24 of the bits of data stored therein and applies them through edge conditioner 26 to low speed bus data lead 26 llB. Edge conditioner 26 operates similar to edge 27 conditioner 19, reducing or eliminating radio 28 frequency components which would otherwise be 29 generated by high slope and sharp cornered data pulses. The resulting signals on lead llB are 31 received by shift register 16 in converter 10 (Figure 32 3).
33 It may be seen therefore that the circuit 34 of Figure 4 operates similar to the corresponding circuit in converter 10.
36 The D channel contention line 23 from 37 circuit 22 (Figure 3) is applied to an enable input of 38 peripheral 5, whereby any of the terminals 5 can 2019~02 -02 request transmission during any particular time 03 interval. This is controlled by the Other Terminal 04 and Control circuitry 22 in a well known manner for 05 selecting which of several terminal 5 signal 06 generators should transmit and receive during a 07 particular time interval.
08 With reference to Figure 4, a locally 09 generated high speed clock signal (4 mHZ) is applied to clock control and synchronization circuit 17 on 11 lead 27. The clock generated in clock control and 12 synchronization circuit 17 (Figure 3), edge 13 conditioned, appearing on interface clock lead llC, is 14 also applied to clock control and synchronization circuit 17. The clock control and synchronization 16 circuit 17 counts the clock pulses on line llC. At 17 the end of the counted twenty-fourth clock edge, 18 signifying the last data bit of the frame, of the 19 clock, a frame pulse is generated, which is applied to line 28. Following definition of the frame edge, the 21 local high speed clock signal from lead 27 is applied 22 on the clock C2 lead 29, for synchronization of other 23 circuits in the peripheral 5, and also to provide the 24 shift clock pulses at the high speed to shift registers 24 and 25, whereupon the data is read at 26 high data rate from register 24 to the bus lead 9.
27 While there will be a phase difference 28 between the high speed local clock signal on lead 27 29 and the low speed data applied to lead llB, the phase shift time will virtually never be longer than 1 bit 31 interval. Therefore due to the high to low and low to 32 high speed conversion, the system is phase difference 33 tolerant, and it is not necessary to utilize a phase 34 locked loop or similar structure to exactly phase lock each of the peripherals to the telephone set converter 36 clock control and synchronization circuit 17. The 37 cost of the peripherals is thus substantially less 38 than would otherwise be expected.
2019~02 02 A person understanding this invention may 03 now conceive of other alternatives or embodiments 04 using the principles described herein. All are 05 considered to be within the sphere and scope of the 06 invention as defined in the claims appended hereto.
Claims (13)
1. Data transfer means between a digital telephone set, a first high bit rate serial data bus and plural peripherals comprising:
(a) means for outwardly transmitting low data rate data between the telephone set and the peripherals on a low data rate bus and for receiving low data rate data from the low data rate bus.
(b) a first converter connected to the data bus for converting high bit rate incoming data signals carried by the high bit rate data bus to said low bit rate signals for said outward transmission and for converting received low bit rate data signals to high bit rate signals for outward high bit rate transmission on the high bit rate data bus, (c) at least one second converter, at a peripheral, for converting low bit rate incoming data signals to high bit rate outgoing data signals and high bit rate incoming data signals to low bit rate outgoing data signals, each of said converters comprising:
(i) first and second shift registers each having capacity of a data frame, (ii) means for writing incoming data from a high data rate bus connected thereto into the first shift register during a high data rate frame time interval at a high bit rate, (iii) means for reading the data stored in the first shift register onto a low data bus for outward transmission during a low data rate frame time interval at a high low bit rate, (iv) means for writing incoming data from the low rate bus into the second shift register during the interval when data stored in the first shift register is being read, (v) means for reading data from the second shift register to the high data rate bus connected thereto during the interval when data stored in the first shift register is being written, (vi) means for providing a separate high bit rate clock signal for each converter, (vii) means for providing a low bit rate clock signal for each converter, (viii) means for clocking both first and second shift registers of each converter using the high bit rate clock signal during said high data rate frame time interval, and (ix) means for clocking both first and second shift registers of each converter using the low bit rate clock signal during said low data rate frame time interval, (x) the clocking intervals of the low and high bit rate clock signals in each converter alternating with each other, whereby said data is transferred frame by frame between high data rate data buses connected to the telephone set and said peripheral but along the low data rate data bus between the telephone set and said at least one peripheral.
(a) means for outwardly transmitting low data rate data between the telephone set and the peripherals on a low data rate bus and for receiving low data rate data from the low data rate bus.
(b) a first converter connected to the data bus for converting high bit rate incoming data signals carried by the high bit rate data bus to said low bit rate signals for said outward transmission and for converting received low bit rate data signals to high bit rate signals for outward high bit rate transmission on the high bit rate data bus, (c) at least one second converter, at a peripheral, for converting low bit rate incoming data signals to high bit rate outgoing data signals and high bit rate incoming data signals to low bit rate outgoing data signals, each of said converters comprising:
(i) first and second shift registers each having capacity of a data frame, (ii) means for writing incoming data from a high data rate bus connected thereto into the first shift register during a high data rate frame time interval at a high bit rate, (iii) means for reading the data stored in the first shift register onto a low data bus for outward transmission during a low data rate frame time interval at a high low bit rate, (iv) means for writing incoming data from the low rate bus into the second shift register during the interval when data stored in the first shift register is being read, (v) means for reading data from the second shift register to the high data rate bus connected thereto during the interval when data stored in the first shift register is being written, (vi) means for providing a separate high bit rate clock signal for each converter, (vii) means for providing a low bit rate clock signal for each converter, (viii) means for clocking both first and second shift registers of each converter using the high bit rate clock signal during said high data rate frame time interval, and (ix) means for clocking both first and second shift registers of each converter using the low bit rate clock signal during said low data rate frame time interval, (x) the clocking intervals of the low and high bit rate clock signals in each converter alternating with each other, whereby said data is transferred frame by frame between high data rate data buses connected to the telephone set and said peripheral but along the low data rate data bus between the telephone set and said at least one peripheral.
2. Data transfer means as defined in claim 1 in which the low data rate bus is an unshielded cable.
3. Data transfer means as defined in claim 1 or 2 including means for applying a low data rate clock signal from the first converter to the low data rate bus, and means at each second converter for receiving the low bit rate clock signal and providing a frame synchronizing signal on the high data rate bus connected thereto.
4. Data transfer means as defined in claim 1 or 2 including means for applying a low data rate clock signal from the first converter to the low data rate bus, and means in each second converter for receiving the low bit rate clock signal from the low bit rate bus and for synchronizing its shift registers to a frame of data words defined by the low bit rate clock signal.
5. Data transfer means as defined in claim 1 in which the low bit rate clock is derived from the telephone set.
6. Data transfer means as defined in claim 4 in which the low bit rate clock is derived from the telephone set.
7. Data transfer means comprising:
(a) first and second shift registers having similar capacities, (b) means for writing incoming data from a first high data rate bus into the first shift register during a first predetermined time interval, at a high bit rate, (c) means for reading the data stored in the first shift register onto a low data rate bus for outward transmission during a second predetermined time interval at a low bit rate, (d) means for writing incoming data from the low data rate bus into the second shift register during the interval when data stored in the first shift register is being read, (e) means for reading outgoing data from the second shift register to the first high data rate bus during the interval when data stored in the first shift register is being written, (f) means for providing a high bit rate clock signal, (g) means for providing a low bit rate clock signal, (h) means for clocking both first and second shift registers using the high bit rate clock signal during said first predetermined time interval, and (i) means for clocking both first and second shift registers using the low bit rate clock signal during said second predetermined time interval, (j) the clocking intervals of the low and high bit rate clock signals alternating with each other.
(a) first and second shift registers having similar capacities, (b) means for writing incoming data from a first high data rate bus into the first shift register during a first predetermined time interval, at a high bit rate, (c) means for reading the data stored in the first shift register onto a low data rate bus for outward transmission during a second predetermined time interval at a low bit rate, (d) means for writing incoming data from the low data rate bus into the second shift register during the interval when data stored in the first shift register is being read, (e) means for reading outgoing data from the second shift register to the first high data rate bus during the interval when data stored in the first shift register is being written, (f) means for providing a high bit rate clock signal, (g) means for providing a low bit rate clock signal, (h) means for clocking both first and second shift registers using the high bit rate clock signal during said first predetermined time interval, and (i) means for clocking both first and second shift registers using the low bit rate clock signal during said second predetermined time interval, (j) the clocking intervals of the low and high bit rate clock signals alternating with each other.
8. Data transfer means as defined in claim 1 or 2 further comprising means for conditioning data signals prior to being applied to the low data rate bus, to limit the high frequency components therefrom.
9. Data transfer means as defined in claim 1 in which the terminal is a telephone set.
10. Data transfer means as defined in claim 7, further comprising a second converter at a remote peripheral, the second converter being connected to a second high data rate bus and to the low data rate bus, comprising:
(a) a third shift register having similar capacity as the first shift register, (b) means for writing incoming data from the low data rate bus into the third shift register, (c) means for reading data from the third shift register to the second high data rate bus, (d) means for providing a high bit rate clock signal, (e) means for providing a low bit rate clock signal, (f) means for enabling the third shift register to write data and for clocking the third shift register with the low bit rate clock during said writing, (g) means for subsequently enabling the third shift register to read data and for clocking the third shift register with the high bit rate clock, whereby low bit rate data from the low bit rate bus is subsequently read at a high bit rate to the second high bit rate bus.
(a) a third shift register having similar capacity as the first shift register, (b) means for writing incoming data from the low data rate bus into the third shift register, (c) means for reading data from the third shift register to the second high data rate bus, (d) means for providing a high bit rate clock signal, (e) means for providing a low bit rate clock signal, (f) means for enabling the third shift register to write data and for clocking the third shift register with the low bit rate clock during said writing, (g) means for subsequently enabling the third shift register to read data and for clocking the third shift register with the high bit rate clock, whereby low bit rate data from the low bit rate bus is subsequently read at a high bit rate to the second high bit rate bus.
11. Data transfer means as defined in claim 10, in which the second converter is further comprised of:
(h) a fourth shift register having similar capacity as the third shift register, (i) means for writing incoming data from the second high data rate bus into the fourth shift register, (j) means for reading data from the fourth shift register to the low data rate bus, (k) means for enabling the fourth shift register to write data from the second high data rate bus and for clocking the fourth shift register with the high bit rate clock during said writing and during the clocking interval of the third shift register with the high bit rate clock, (1) means for enabling the fourth shift register to read data to the low data rate bus and for clocking the fourth shift register during said reading and during the clocking interval of the third shift register with the low bit rate clock, whereby the third and fourth shift registers are clocked together and read from and write to the low data rate bus during a similar time interval and read from and write to the second high data rate bus during a second similar time interval.
(h) a fourth shift register having similar capacity as the third shift register, (i) means for writing incoming data from the second high data rate bus into the fourth shift register, (j) means for reading data from the fourth shift register to the low data rate bus, (k) means for enabling the fourth shift register to write data from the second high data rate bus and for clocking the fourth shift register with the high bit rate clock during said writing and during the clocking interval of the third shift register with the high bit rate clock, (1) means for enabling the fourth shift register to read data to the low data rate bus and for clocking the fourth shift register during said reading and during the clocking interval of the third shift register with the low bit rate clock, whereby the third and fourth shift registers are clocked together and read from and write to the low data rate bus during a similar time interval and read from and write to the second high data rate bus during a second similar time interval.
12. Data transfer means as defined in claim 11 further comprising means for conditioning data signals prior to being applied to the low data rate bus, to limit the high frequency components thereof.
13. Data transfer means as defined in claim 12 including means for applying a low data rate synchronizing signal to the low data rate bus, and means at the second converter for receiving said synchronizing signal and for synchronizing the third and fourth shift registers to frames of words defined by said synchronizing signal.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA002019002A CA2019002C (en) | 1990-06-14 | 1990-06-14 | Data transfer between high bit rate buses via unshielded low bit rate bus |
| ITMI910709A IT1251744B (en) | 1990-06-14 | 1991-03-15 | DATA TRANSFER BETWEEN HIGH-SPEED TRANSMISSION BUS THROUGH A NON-SHIELDED LOW-SPEED BUS |
| GB9105522A GB2245127B (en) | 1990-06-14 | 1991-03-15 | Data transfer between high bit rate buses via unshielded low bit rate bus |
| DE4119533A DE4119533A1 (en) | 1990-06-14 | 1991-06-13 | METHOD AND DEVICE FOR TRANSMITTING DATA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA002019002A CA2019002C (en) | 1990-06-14 | 1990-06-14 | Data transfer between high bit rate buses via unshielded low bit rate bus |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002108836A Division CA2108836C (en) | 1990-06-14 | 1990-06-14 | Data transfer between high bit rate buses via unshielded low bit rate bus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2019002A1 CA2019002A1 (en) | 1991-12-14 |
| CA2019002C true CA2019002C (en) | 1994-04-19 |
Family
ID=4145230
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002019002A Expired - Lifetime CA2019002C (en) | 1990-06-14 | 1990-06-14 | Data transfer between high bit rate buses via unshielded low bit rate bus |
Country Status (4)
| Country | Link |
|---|---|
| CA (1) | CA2019002C (en) |
| DE (1) | DE4119533A1 (en) |
| GB (1) | GB2245127B (en) |
| IT (1) | IT1251744B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19926928A1 (en) * | 1999-06-14 | 2000-12-21 | Inst Halbleiterphysik Gmbh | Data transmission procedures |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4901342A (en) * | 1986-08-22 | 1990-02-13 | Jones Reese M | Local area network connecting computer products via long telephone lines |
| US5220561A (en) * | 1990-06-20 | 1993-06-15 | Mitel Corporation | Data transfer between high bit rate buses via unshielded low bit rate bus |
-
1990
- 1990-06-14 CA CA002019002A patent/CA2019002C/en not_active Expired - Lifetime
-
1991
- 1991-03-15 GB GB9105522A patent/GB2245127B/en not_active Expired - Fee Related
- 1991-03-15 IT ITMI910709A patent/IT1251744B/en active IP Right Grant
- 1991-06-13 DE DE4119533A patent/DE4119533A1/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| GB2245127A (en) | 1991-12-18 |
| IT1251744B (en) | 1995-05-23 |
| CA2019002A1 (en) | 1991-12-14 |
| ITMI910709A1 (en) | 1992-09-15 |
| GB2245127B (en) | 1995-01-04 |
| ITMI910709A0 (en) | 1991-03-15 |
| DE4119533A1 (en) | 1991-12-19 |
| GB9105522D0 (en) | 1991-05-01 |
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|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed | ||
| MKEC | Expiry (correction) |
Effective date: 20121202 |