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CA2000338A1 - Lead frame for a multiplicity of terminals - Google Patents

Lead frame for a multiplicity of terminals

Info

Publication number
CA2000338A1
CA2000338A1 CA002000338A CA2000338A CA2000338A1 CA 2000338 A1 CA2000338 A1 CA 2000338A1 CA 002000338 A CA002000338 A CA 002000338A CA 2000338 A CA2000338 A CA 2000338A CA 2000338 A1 CA2000338 A1 CA 2000338A1
Authority
CA
Canada
Prior art keywords
conductors
terminals
spacing
lead
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002000338A
Other languages
French (fr)
Inventor
Hugo Westerkamp
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LSI Logic Products GmbH
Original Assignee
LSI Logic Products GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LSI Logic Products GmbH filed Critical LSI Logic Products GmbH
Publication of CA2000338A1 publication Critical patent/CA2000338A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01088—Radium [Ra]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Laser Beam Processing (AREA)
  • Wire Bonding (AREA)
  • Lasers (AREA)

Abstract

Abstract of the Disclosure A lead frame for a multiplicity of terminals, in particular of large-scale integrated semiconductor chips, arranged in a very confined space and consisting of metallic conductors which converge from large outer spacings toward the terminals and can be connected to the terminals.
The lead frame allows a high number of terminals with a low degree of spacing of the conductors to be produced. The conductors are produced in the outer region by a conventional production method and at their ends pointing toward the terminals by laser cutting of a uniformly metallic material.

Description

; LEAD FRAME FOR A MULTIPLICITY OF TERMINALS

Backqround of the Invention Field of the Invention The present invention relates to a lead frame for a multiplicity of terminals, in particular of large-scale integrated semiconductor chips, arranged in a very confined space and consisting of metallic ~ ., conductors, which converge from large outer spacings toward the terminals and can be connected to the terminals.
Discussion of Related Art Such lead frames are used for contacting one ` or more large-scale integrated semiconductor chips.
On their outer edge, the semiconductor chips have bonding pads which, according to the current technique, are square and have an edge length of ~y go~m - 120~m and a spacing from pad to pad of at ~j least 30~m. The contact to the inner ends of the '~l conductors of the lead frames is usually established by bonding wires having a diameter of 25~m - 30~m.
The lead frames are usually produced with ` outer edge pieces which are parted or separated , ~' . ' ' ,,' j~

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~3Q~8 after positioning of the lead frame, so that the individual conductors of the lead frame are no longer electrically connected to one another.
Punching is the least expensive method available for the production of the lead frames.
Due to the relatively high tool costs, this production method is not flexible. For relatively high numbers of terminals, the complexity of the tools increases, with the result that problems of precision multiply. Therefore, this technique is used to realize terminal numbers up to about 120.
Another known method of producing these frames is etching, by which the desired structures - are etched out of a uniform metallic surface, so that the desired metallic conductors remain. The etching operation can be controlled in the usual way by photographic shadowing methods. Although this method is distinguished by low tool costs and by high flexibility, it leads to relatively high ; 20 production costs because automation has not yet succeeded on an economically significant scale.
Both methods lead to a minimal terminal width ~ and to a minimal clearance spacing between the ; terminals of the conductors on an order of magnitude of the material thickness, which is, for example, ` 150~m. The minimal terminal width of 150~m and the minimal spacing of likewise 150~ leads to a terminal grid of 300~m. On account of the limited length of the bonding wires, according to known ~ 30 techniques, a number of terminals of up to 160 can `~ be achieved with a square package of 28mm edge ~ '' , .
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Z~338 ..
length (EIAJ Standard). Higher numbers of terminals can be achieved only by expensive special package configurations. These special packages, so-called ` arrays, have the disadvantage however that they are not suited for modern non-thruplating insertion and soldering methods.
One known method of producing very small terminal groups is based on the use of a tape carrier material (e.g. polyimide), on which a terminal grid is produced by the positive or negative method and in assembly is connected directly to the chip by soldering. The amount of solder necessary for this is applied in a number of additional processes, starting from the chip. With this "tape automated bonding", terminal widths of 50~m with a spacing of 30~m, that is a grid pattern ~, of 80~m, can be realized. However, this method is relatively expensive and inflexible. High tape material and tool costs arise, which have to be funded anew with every change in chip design.
Therefore, a cost-effective production of relatively small numbers is not possible. Furthermore, these ~, products require special insertion techniques at the ` customer's premises.
., .-Summary of the Invention One object of the invention is to provide a lead frame of the type mentioned above which is -: inexpensive to produce and allows for a high number of terminals.
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According to the invention, this object is achieved by the metallic conductors being produced in an outer region by a conventional production method and at their ends pointing toward the terminals by laser cutting of uniform metallic . .
material.
According to the invention, for the first time a combination of more than one production method is undertaken for producing the conductors of the lead frame. The invention is based on the realization that the conventional methods are adequate for the larger spacings in the outer region -~ of the lead frames, meaning that the most favorable, usually the least expensive, method is selected for each application. The limitation of the interconnection density is due to the disadvantages ~ of the conventional methods, which do not allow a `~ reduction in the spacing between the terminal ends - of the conductors. According to the invention, a laser cutting method is employed at the inner end of ;~ the conductor track, so that once the conventional method has been applied to the outer ends of the conductors a uniform metallic surface remains on the inside, which can then be divided by laser cutting into the desired extensions of the conductors produced. Laser cutting is very flexible, but requires a relatively great deal of time. However, the time required is not critical for the production ~r of the lead frame according to the invention, because only the small sections at the inner end of the conductors are produced by laser cutting, while .:' .', ~
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- 2a~ 38 . .

ordinarily the greater length of the conductors is produced by the conventional quick methods, such as punching or etching.

Brief Description of the Drawings The invention is explained in more detail below with reference to the enclosed drawing, in which:
Figure 1 is a plan view showing conductors of a lead frame according to the invention, which conductors terminate adjacent a bonding pad, and Figure 2 is a plan view showing the conductors according to Figure 1 connected by bonding wires to terminal areas of a semiconductor chip.
~` '', Detailed Description of the Preferred Embodiments ^ Figure 1 illustrates a multiplicity of approximately star-shaped conductors 1, which are ~; relatively wide in the outer region of the lead frame and are separated from one another by likewise - 20 relatively wide intermediate spaces 2. Contacts cani~ be attached to the conductors 1 at their outer ends by conventional techniques.
;~ The conductors 1 are produced over a large - part of their length by a conventional technique, for example by etching or punching. Where the ` converging profile of the conductors 1 causes the width of the conductor track to reach a lower ..
, .':! , "; ;,. ' ' .'~ , ,, , ' ' :

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3~38 acceptable limit on the basis of minimal spacing 2 to be maintained, there is formed in the conductor track 1 a step 3, by which the conductor tracks are widened again and are separated by a very narrow spacing 2' of constant width. The spacings 2' of constant width are produced by laser cutting the originally uniformly formed metallic material within the step 3. Laser cutting allows very small widths of the spacings 2' to be realized, so that the grid spacing of the conductors 1 at the inner end of the lead frame corresponds approximately to the grid dimension of bonding pads 4 of a semiconductor chip 5 or is only slightly larger.
Figure 2 shows a semiconductor chip 5, which is positioned on a bonding pad 6 within the lead ; frame. The connection of the individual bonding ;~ pads 4 to the metallic conductors 1 is made by usual ; bonding wires 7.
On account of the small grid spacing arising at the inner end of the conductors due to the small width of the spacings 2', the conductors 1 can be ` led very closely up to the bonding pad 6, so that a high terminal assignment can be realized with short bonding wires.

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Claims (9)

1. An apparatus, comprising:
a bonding pad for receiving a semiconductor chip having a plurality of terminals;
a lead frame for connection to said terminals, said lead frame being arranged in a very confined space and comprising a plurality of metallic conductors which can be connected to the terminals, the metallic conductors having a relatively large spacing between them in an outer region and a relatively narrow spacing between them in an inner region adjacent said bonding pad, said relatively large spacing being produced by a first lead forming technique and said narrow spacing being produced by laser cutting a uniform metallic material.
2. An apparatus as claimed in claim 1, in which the metallic conductors are produced over the majority of their length by the first lead forming technique.
3. An apparatus comprising:
a bonding pad for receiving a semiconductor integrated circuit having a plurality of terminals;
a lead bed frame having a plurality of metallic conductors, said lead bed frame having an outer region in which said conductors are spaced by a first distance and having an inner region adjacent said bonding pad in which said conductors are spaced by a second distance which is smaller than said first distance, said lead bed frame also having a transition area in which said spacing between said conductors changes abruptly from said first distance to said second distance.
4. An apparatus as claimed in claim 3 wherein said second spacing is uniform.
5. An apparatus as claimed in claim 4 wherein said first spacing is uniform.
6. A method, comprising:
forming a bonding pad for receiving a semiconductor chip having a plurality of leads, forming a lead frame having a plurality of metallic conductors for connection to said semiconductor chip, said metallic conductors being formed in an outer region of said lead frame by a first lead forming technique and being formed in an inner region adjacent said bonding pad by laser cutting a metallic material.
7. A method as claimed in claim 6 wherein said first lead forming technique comprises etching a metallic material.
8. A method as claimed in claim 6 wherein said first lead forming technique comprises punching metallic material.
9. A method as claimed in claim 6 including forming a transition area on said lead frame in which the spacing between said conductors changes abruptly from a relatively wide spacing in said outer region to a relatively narrow spacing in said inner region.
CA002000338A 1988-10-10 1989-10-10 Lead frame for a multiplicity of terminals Abandoned CA2000338A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3834361A DE3834361A1 (en) 1988-10-10 1988-10-10 CONNECTION FRAME FOR A VARIETY OF CONNECTIONS
DEP3834361.4 1988-10-10

Publications (1)

Publication Number Publication Date
CA2000338A1 true CA2000338A1 (en) 1990-04-10

Family

ID=6364724

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002000338A Abandoned CA2000338A1 (en) 1988-10-10 1989-10-10 Lead frame for a multiplicity of terminals

Country Status (4)

Country Link
EP (1) EP0363679A3 (en)
JP (1) JPH02247089A (en)
CA (1) CA2000338A1 (en)
DE (1) DE3834361A1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4101790C1 (en) * 1991-01-18 1992-07-09 Technisch-Wissenschaftliche-Gesellschaft Thiede Und Partner Mbh, O-1530 Teltow, De Chip-support arrangement prodn. - in tape form, in dual-in-line format by film-bond technology
JPH05114685A (en) * 1991-10-23 1993-05-07 Mitsubishi Electric Corp Semiconductor device
WO1994013015A1 (en) * 1992-11-24 1994-06-09 Hitachi Construction Machinery Co., Ltd. Lead frame manufacturing method
US5580466A (en) * 1993-04-14 1996-12-03 Hitachi Construction Machinery Co., Ltd. Metal plate processing method, lead frame processing method, lead frame, semiconductor device manufacturing method, and semiconductor device
WO2004085108A1 (en) * 1993-08-05 2004-10-07 Nobuhiko Tada Lead frame machining method and lead frame machining apparatus
EP0644585A3 (en) * 1993-09-20 1995-10-11 Sumitomo Electric Industries Lead frame and method of manufacturing the same.
DE102023202636A1 (en) 2023-03-23 2024-09-26 Robert Bosch Gesellschaft mit beschränkter Haftung Method for producing a structured power module circuit carrier

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3110235A1 (en) * 1981-03-17 1982-10-21 Trumpf GmbH & Co, 7257 Ditzingen "METHOD AND DEVICE FOR FLAME-CUTTING BY MEANS OF A LASER BEAM"
JPS58169940A (en) * 1982-03-30 1983-10-06 Fujitsu Ltd Manufacture of semiconductor device
US4529958A (en) * 1983-05-02 1985-07-16 Dale Electronics, Inc. Electrical resistor
JPS6080260A (en) * 1983-10-07 1985-05-08 Hitachi Micro Comput Eng Ltd Lead frame for semiconductor device and manufacture thereof
JPS61216354A (en) * 1985-03-20 1986-09-26 Shinko Electric Ind Co Ltd Manufacture of lead frame
GB2178894B (en) * 1985-08-06 1988-07-27 Gen Electric Co Plc Preparation of fragile devices
DE3608410A1 (en) * 1986-03-13 1987-09-17 Siemens Ag Production of fine structures for semiconductor contacts
US4774635A (en) * 1986-05-27 1988-09-27 American Telephone And Telegraph Company At&T Bell Laboratories Semiconductor package with high density I/O lead connection
FR2624652B1 (en) * 1987-12-14 1990-08-31 Sgs Thomson Microelectronics METHOD OF PLACING ON AN SUPPORT, AN ELECTRONIC COMPONENT PROVIDED WITH ITS CONTACTS
JPH0777249B2 (en) * 1988-09-21 1995-08-16 日本電気株式会社 Lead frame manufacturing method

Also Published As

Publication number Publication date
DE3834361A1 (en) 1990-04-12
EP0363679A2 (en) 1990-04-18
EP0363679A3 (en) 1990-07-18
DE3834361C2 (en) 1990-08-16
JPH02247089A (en) 1990-10-02

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