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CA1301354C - Alias address support - Google Patents

Alias address support

Info

Publication number
CA1301354C
CA1301354C CA000577716A CA577716A CA1301354C CA 1301354 C CA1301354 C CA 1301354C CA 000577716 A CA000577716 A CA 000577716A CA 577716 A CA577716 A CA 577716A CA 1301354 C CA1301354 C CA 1301354C
Authority
CA
Canada
Prior art keywords
virtual
cache
virtual memory
memory
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CA000577716A
Other languages
English (en)
French (fr)
Inventor
William Van Loo
John Watkins
Joseph Moran
Ray Cheng
William Shannon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of CA1301354C publication Critical patent/CA1301354C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1063—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently virtually addressed
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/653—Page colouring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CA000577716A 1987-10-02 1988-09-16 Alias address support Expired - Fee Related CA1301354C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10463587A 1987-10-02 1987-10-02
US104,635 1987-10-02

Publications (1)

Publication Number Publication Date
CA1301354C true CA1301354C (en) 1992-05-19

Family

ID=22301527

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000577716A Expired - Fee Related CA1301354C (en) 1987-10-02 1988-09-16 Alias address support

Country Status (7)

Country Link
JP (1) JPH071489B2 (xx)
AU (1) AU609519B2 (xx)
CA (1) CA1301354C (xx)
DE (1) DE3832758C2 (xx)
FR (1) FR2621408A1 (xx)
GB (1) GB2210479B (xx)
HK (1) HK95493A (xx)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10761995B2 (en) 2018-04-28 2020-09-01 International Business Machines Corporation Integrated circuit and data processing system having a configurable cache directory for an accelerator

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5276798A (en) * 1990-09-14 1994-01-04 Hughes Aircraft Company Multifunction high performance graphics rendering processor
US5813046A (en) * 1993-11-09 1998-09-22 GMD--Forschungszentrum Informationstechnik GmbH Virtually indexable cache memory supporting synonyms
GB2293670A (en) * 1994-08-31 1996-04-03 Hewlett Packard Co Instruction cache
US6189074B1 (en) * 1997-03-19 2001-02-13 Advanced Micro Devices, Inc. Mechanism for storing system level attributes in a translation lookaside buffer
US6446189B1 (en) 1999-06-01 2002-09-03 Advanced Micro Devices, Inc. Computer system including a novel address translation mechanism
US6510508B1 (en) 2000-06-15 2003-01-21 Advanced Micro Devices, Inc. Translation lookaside buffer flush filter
US6665788B1 (en) 2001-07-13 2003-12-16 Advanced Micro Devices, Inc. Reducing latency for a relocation cache lookup and address mapping in a distributed memory system
US11853231B2 (en) 2021-06-24 2023-12-26 Ati Technologies Ulc Transmission of address translation type packets

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54148329A (en) * 1978-05-15 1979-11-20 Toshiba Corp Buffer memory control system and information processor containing buffer memory
JPS595482A (ja) * 1982-06-30 1984-01-12 Fujitsu Ltd キヤツシユバツフア装置管理方式
JPS62145341A (ja) * 1985-12-20 1987-06-29 Fujitsu Ltd キヤツシユメモリシステム
EP0282213A3 (en) * 1987-03-09 1991-04-24 AT&T Corp. Concurrent context memory management unit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10761995B2 (en) 2018-04-28 2020-09-01 International Business Machines Corporation Integrated circuit and data processing system having a configurable cache directory for an accelerator
US10846235B2 (en) 2018-04-28 2020-11-24 International Business Machines Corporation Integrated circuit and data processing system supporting attachment of a real address-agnostic accelerator
US11030110B2 (en) 2018-04-28 2021-06-08 International Business Machines Corporation Integrated circuit and data processing system supporting address aliasing in an accelerator
US11113204B2 (en) 2018-04-28 2021-09-07 International Business Machines Corporation Translation invalidation in a translation cache serving an accelerator

Also Published As

Publication number Publication date
JPH071489B2 (ja) 1995-01-11
GB8819017D0 (en) 1988-09-14
FR2621408B1 (xx) 1994-04-22
JPH01108651A (ja) 1989-04-25
AU609519B2 (en) 1991-05-02
AU2242288A (en) 1989-04-06
DE3832758C2 (de) 1996-05-30
FR2621408A1 (fr) 1989-04-07
DE3832758A1 (de) 1989-04-13
GB2210479A (en) 1989-06-07
GB2210479B (en) 1992-06-17
HK95493A (en) 1993-09-24

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Legal Events

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