CA1204876A - System for processing machine check interruption - Google Patents
System for processing machine check interruptionInfo
- Publication number
- CA1204876A CA1204876A CA000441404A CA441404A CA1204876A CA 1204876 A CA1204876 A CA 1204876A CA 000441404 A CA000441404 A CA 000441404A CA 441404 A CA441404 A CA 441404A CA 1204876 A CA1204876 A CA 1204876A
- Authority
- CA
- Canada
- Prior art keywords
- machine check
- interruption
- signal
- code
- condition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0793—Remedial or corrective actions
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
- Hardware Redundancy (AREA)
- Computer And Data Communications (AREA)
Abstract
SYSTEM FOR PROCESSING MACHINE CHECK INTERRUPTION
ABSTRACT OF THE DISCLOSURE
A system for processing machine check interruption using a data processor which outputs a machine check interruption signal by detecting the generation of a machine check condition and which performs interruption processing on the basis of the machine check interruption signal. The data processor comprises a specific code detector means which detects a specific interruption signal among the machine check interruption signals, a signal converting means for converting the machine check interruption signal into a modified code signal when the interruption signal generated by the machine check interruption is the above-mentioned specific code, and a control portion which assumes a disabled-waiting con-dition in response to the modified code signal, the operation of the data processor being stopped by rendering said control portion to be in a disabled--waiting condition when interruption of the above--mentioned specific code occurs.
ABSTRACT OF THE DISCLOSURE
A system for processing machine check interruption using a data processor which outputs a machine check interruption signal by detecting the generation of a machine check condition and which performs interruption processing on the basis of the machine check interruption signal. The data processor comprises a specific code detector means which detects a specific interruption signal among the machine check interruption signals, a signal converting means for converting the machine check interruption signal into a modified code signal when the interruption signal generated by the machine check interruption is the above-mentioned specific code, and a control portion which assumes a disabled-waiting con-dition in response to the modified code signal, the operation of the data processor being stopped by rendering said control portion to be in a disabled--waiting condition when interruption of the above--mentioned specific code occurs.
Description
SYSTEM FOR PROCESSING ~lACHINR CHECK INTERRUPTIOM
BACKGROUND OF THE INVENTION
(1) Field of the Invention The present invention relates to a system for processing machine check interruption and more particu-larly to a system for processing machine check inter-ruption using a data processor in which a machine check interruption code is analyzed when a machine check interruption occurs; and if the contents of the machine check interruption code show a condition in which the operation of the hardware thereafter is not guaran~eed, the data processor is rendered to be in a disabled--waiting condition.
BACKGROUND OF THE INVENTION
(1) Field of the Invention The present invention relates to a system for processing machine check interruption and more particu-larly to a system for processing machine check inter-ruption using a data processor in which a machine check interruption code is analyzed when a machine check interruption occurs; and if the contents of the machine check interruption code show a condition in which the operation of the hardware thereafter is not guaran~eed, the data processor is rendered to be in a disabled--waiting condition.
(2) Description of the Prior Art In a data processor, there are two main causes of machine check interruptions. One is an "exigent"
condition which greatly damages the system of the data processor, and the other is a "repressible" condition which is recoverd by a re-try. In an exigent condition, the central processing unit (CPU) is directly damaged, and, therefore, it becomes impossible to proceed with the execution of the instructions and with the proces-sing of the interruption. An exigent condition is of two types: instruction processing damage (PD) and system damage (SD). An erroneous operation which cannot be discriminated as a specific kind is indicated as SD.
The type SD includes SD occurring on a memory access route and SD occurring on a CPU route.
In a data processor, jobs are generally executed under the management of the operating system.
When the jobs are executed, if the above-mentioned SD
occurs, the interruption processing for the above--mentioned machine check is carried out by the software.
The type SD also includes damage which makes the operation of hardware unreliable, for example, damage resulting in the erroneous operation of a memory control ~Z~ 6 unit (MCU) which controls the memory access operation.
However, the software sometimes does not judge such damage to be a system breakdown condition when the cause thereof is a certain kind but executes the processing so as to interrupt, i.e., to end abnormally, only the job at that time and to move on to the next iob. However, if a machine check error of the type SD occurs in the MCU, for example, if an address parity error occurs in a main storage unit .(MSU) when data is written into the MSU, the e~ecution of subsequent jobs is not guaranteed.
In this case, since the software executes some proces-sing, it appears as if correct processing is carried out although the result of the execution is not guaranteed.
Therefore, there is the danger of trouble, such as an unexpected change of the processed data, occurring.
It is desirable that the hardware immediately assume a check-stop condition when the above-mentioned erroneous operation occurs. In conventional hardware, however, since rendering the hardware to be in the check-stop mode is controlled for every type of damage, SD in any portion, i.e., SD in the CPU, SD in the MCU, or SD in another portion, leads to the same check-stop condition. Therefore, an erroneous operation in the CPU
of the type SD which usually does not lead to a system breakdown this time does lead to a system breakdown, and the data processing is disturbed. It is also possible to design the system so that the check-stop mode is deactivated and the system breakdown condition does not occur due to a machine check interruption of the type SD.
In this case, however, when SD occurs in the MCU, for example, when an address parity error is detected in the write-in operation to the main storage unit, processing is executed on the basis of erroneous data and the result obtained by processing is not guaranteed.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide, in order to solve the above-mentioned problems, a system for processing machine check interruption in which the machine check interruption code is converted into another data code in accordance with the portion which assumes a machine check condition and in accordance with the content of the machine check condition, thereby causing the software to assume a disabled-waiting condition and making the data processing reliable.
According to the present invention, there is provided a system for processing machine check inter-ruption using a data processor which outputs a machinecheck interruption signal by detecting the generation of a machine check condition and which performs inter~
ruption processing on the basis of the machine check interruption signal, characterized in that the data processor comprises a specific code detector means which detects a specific interruption signal among the machine check interruption signals, a signal converting means for converting the machine check interruption signal into a modified code signal when the interruption signal generated by the machine check interruption is the above-mentioned specific code, and a control portion which assumes a disabled-waiting condition in response to the modified code signal, the operation of the data processor being stopped by rendering the control portion to be in a disabled-waiting condition when interruption of the above-mentioned specific code occurs.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a block circuit diagram illustrating a data processor used in a system as an embodiment of the present invention.
Figure 2 is a block circuit diagram illustrating in detail the structure of a signal generating portion and a control portion included in the data processor of Fig. 1.
DESCRIPTION OF THE PREFERRED EMBODIMENT
The embodiment of the present invention is explained with reference to the attached drawings.
~20~
The data processor of Fig. 1 used in a system according to the present invention comprises a CPU 1, an MCU 2, and an MSU 3. The CPU 1 comprises, in addition to a general data processing portion (not shown), a signal generating portion 11, which generates a modified machine check interruption code in response to the occurrence of a machine check interruption, and a fault detecting portion 4, which generates a machine check interruption signal when a fault is detected in the CPU l. The MCU 2 also comprises a fault detecting portion 5 generating a machine check interruption signal when a fault is detected in the MCU 2. The MSU 3 comprises a control portion 20 which includes a register 19 for storing a machine check interruption code (here-inafter referred to as an MCIC register) and a machine check processing routine.
Figure 2 illustrates in detail the structure of the signal generating portion ll and the control portion 20 used in the data processor of Fig. l.
As is illustrated in Fig. 2, the signal generating portion 11 comprises a machine check detecting and holding portion 12, a control circuit 13 for converting the machine check interruption code (hereinafter referred to as an MCIC converting circuit), a code register 14, a 25 decoder 15, a selector 16, a holding portion 17 for converted data of a machine check interruption code (hereinafter referred to as an MCIC conversion data portion), and a write-in portion l~ for a machine check interruption code (hereinafter referred to as an MCIC
write-in portion). The control portion 20 in the MSU 3 includes, as was previously mentioned, the MCIC register 19 and the machine check processing routine.
In the signal generating portion ll, the machine check detecting and holding portion 12 detects the generation of a machine check in-terruption signal and holds the machine check interruption signal. The machine check interruption signal includes information on where -the machine check interruption signal is generated and on the cause of the generation thereof.
This information is analyzed in a debugging process so as to determine what kind of abnormal phenomenon is S generated in each portion of the data processor.
The MCIC converting circuit 13 selects the output of the selector 16 so that either the output signal from the machine check detecting and holding portion 12 or the output signal from the MCIC conversion data portion 17 is output therefrom. The MCIC converting circuit 13 usually controls the selector 16 so that the machine check interruption signal sent from the machine check detecting and holdlng portion 12 is output from the selector 16. However, when the MCIC converting circuit 13 receives the conversion command from the decoder 15, it controls the selector 16 so that the output signal sent from the MCIC conversion data portion 17 is output therefrom.
The decoder lS detects the condition that the machine check interruption signal sent from the machine check detecting and holding por-tion 12 indicates a state in which the erroneous device and the content data of the device show a condition in which operation of the hardware is unreliable, for example, a condition in which an address parity error is detected when data is written into a main storage unit. If the decoder 15 detects such a condition, it transmits a converting command output "1" to the MCIC converting circuit 13.
The kinds of machine check interruption signals which lead to the generation of the converting command output "1" are previously determined.
The MCIC conversion data portion 17 usually outputs all "O"s, and, therefore, when the all "O"s signal is outupt from the selector 16, the machine check proces-sing routine of the control portion 20 cannot at allanalyze where the machine check interruption signal is generated from or -the cause of the generation thereof ~2~
because of the all "O"s signal. Therefore, continuation of execution of the machine check lnterruption processing becomes impossible and the data processor assumes a disabled-waiting condition.
The control portion 20 stores control programs necessary to control the various operations of the data processor and performs various control processings by using them. The control portion 20 also stores the machine check processing routine.
The operation of the system according to the present invention is explained with reference to Figs. 1 and 2.
When a fault occurs during the execution of the data processing in a data processo~ and the fault detecting portion 4 or 5 outputs a machine check inter-ruption signal, the machine check detecting and holding portion 12 detects the machine check interruption signal and temporarily memorizes it. The machine check inter-ruption signal is then sent from the machine check detecting and holding portion 12 to the code register 14 and the selector 16. If the machine check interruption signal stored in the code register 14 shows an error in the CPU 1 by which the data processor is not led to a system breakdown state, the decoder 15 outputs an "0"
signal. Therefore, the MCIC converting circuit 13 controls the selector 16 so that it outputs a machine check interruption signal. The machine check inter-rupkion signal is written into an output register (not shown) by the MCIC write-in portion 18 and is transmitted to the MCIC register 19 of the control portion 20. In the control portion 20, the place where the interruption signal is generated and the cause of the generated interruption are analyzed by the machine check proces-sing routine on the basis of the machine check inter-ruption signal, debugging thereby being executed.
As a result of analysis of the machine checkinterruption signal, if the decoder 15 judges that the 7~
machine check interruption signal is one of the signals showing a condition in which the operation of the hardware from now on is not reliable~ such as the erroneous operation of the MCU, the decoder 15 outputs the conversion command output "1". In response to the conversion command output "1", the MCIC converting circuit 13 controls the selector 16 so that the selector outputs the all "O"s signal sent from the MCIC conversion data portion 17 in place of the machine check inter-ruption signal transmitted from the machine checkdetecting and holding portion 12. The all "O"s signal is sent to the MCIC register 19 via the MCIC write-in portion 18, and the machine check processing routine of the control portion 20 analyzes the signal stored in the MCIC register 19. However, since the content of the MCIC register 19 is all "O"s and since it is impossible to analyze the place and the cause of the generation of the fault, it is impossible for the data processor to continue the processing for the machine check inter-ruption. Therefore, the data processor assumes adisabled-waiting condition and stops.
According to the present invention, it is discrimi-nated whether or not the machine check interruption signal corresponds to a condition in which operation of the hardware from now on is reliable or not. If it is discriminated that the signal corresponds to a condition in which operation of the hardware is unreliable, the hardware processing is stopped. Therefore, the data processing is reliably effected.
condition which greatly damages the system of the data processor, and the other is a "repressible" condition which is recoverd by a re-try. In an exigent condition, the central processing unit (CPU) is directly damaged, and, therefore, it becomes impossible to proceed with the execution of the instructions and with the proces-sing of the interruption. An exigent condition is of two types: instruction processing damage (PD) and system damage (SD). An erroneous operation which cannot be discriminated as a specific kind is indicated as SD.
The type SD includes SD occurring on a memory access route and SD occurring on a CPU route.
In a data processor, jobs are generally executed under the management of the operating system.
When the jobs are executed, if the above-mentioned SD
occurs, the interruption processing for the above--mentioned machine check is carried out by the software.
The type SD also includes damage which makes the operation of hardware unreliable, for example, damage resulting in the erroneous operation of a memory control ~Z~ 6 unit (MCU) which controls the memory access operation.
However, the software sometimes does not judge such damage to be a system breakdown condition when the cause thereof is a certain kind but executes the processing so as to interrupt, i.e., to end abnormally, only the job at that time and to move on to the next iob. However, if a machine check error of the type SD occurs in the MCU, for example, if an address parity error occurs in a main storage unit .(MSU) when data is written into the MSU, the e~ecution of subsequent jobs is not guaranteed.
In this case, since the software executes some proces-sing, it appears as if correct processing is carried out although the result of the execution is not guaranteed.
Therefore, there is the danger of trouble, such as an unexpected change of the processed data, occurring.
It is desirable that the hardware immediately assume a check-stop condition when the above-mentioned erroneous operation occurs. In conventional hardware, however, since rendering the hardware to be in the check-stop mode is controlled for every type of damage, SD in any portion, i.e., SD in the CPU, SD in the MCU, or SD in another portion, leads to the same check-stop condition. Therefore, an erroneous operation in the CPU
of the type SD which usually does not lead to a system breakdown this time does lead to a system breakdown, and the data processing is disturbed. It is also possible to design the system so that the check-stop mode is deactivated and the system breakdown condition does not occur due to a machine check interruption of the type SD.
In this case, however, when SD occurs in the MCU, for example, when an address parity error is detected in the write-in operation to the main storage unit, processing is executed on the basis of erroneous data and the result obtained by processing is not guaranteed.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide, in order to solve the above-mentioned problems, a system for processing machine check interruption in which the machine check interruption code is converted into another data code in accordance with the portion which assumes a machine check condition and in accordance with the content of the machine check condition, thereby causing the software to assume a disabled-waiting condition and making the data processing reliable.
According to the present invention, there is provided a system for processing machine check inter-ruption using a data processor which outputs a machinecheck interruption signal by detecting the generation of a machine check condition and which performs inter~
ruption processing on the basis of the machine check interruption signal, characterized in that the data processor comprises a specific code detector means which detects a specific interruption signal among the machine check interruption signals, a signal converting means for converting the machine check interruption signal into a modified code signal when the interruption signal generated by the machine check interruption is the above-mentioned specific code, and a control portion which assumes a disabled-waiting condition in response to the modified code signal, the operation of the data processor being stopped by rendering the control portion to be in a disabled-waiting condition when interruption of the above-mentioned specific code occurs.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a block circuit diagram illustrating a data processor used in a system as an embodiment of the present invention.
Figure 2 is a block circuit diagram illustrating in detail the structure of a signal generating portion and a control portion included in the data processor of Fig. 1.
DESCRIPTION OF THE PREFERRED EMBODIMENT
The embodiment of the present invention is explained with reference to the attached drawings.
~20~
The data processor of Fig. 1 used in a system according to the present invention comprises a CPU 1, an MCU 2, and an MSU 3. The CPU 1 comprises, in addition to a general data processing portion (not shown), a signal generating portion 11, which generates a modified machine check interruption code in response to the occurrence of a machine check interruption, and a fault detecting portion 4, which generates a machine check interruption signal when a fault is detected in the CPU l. The MCU 2 also comprises a fault detecting portion 5 generating a machine check interruption signal when a fault is detected in the MCU 2. The MSU 3 comprises a control portion 20 which includes a register 19 for storing a machine check interruption code (here-inafter referred to as an MCIC register) and a machine check processing routine.
Figure 2 illustrates in detail the structure of the signal generating portion ll and the control portion 20 used in the data processor of Fig. l.
As is illustrated in Fig. 2, the signal generating portion 11 comprises a machine check detecting and holding portion 12, a control circuit 13 for converting the machine check interruption code (hereinafter referred to as an MCIC converting circuit), a code register 14, a 25 decoder 15, a selector 16, a holding portion 17 for converted data of a machine check interruption code (hereinafter referred to as an MCIC conversion data portion), and a write-in portion l~ for a machine check interruption code (hereinafter referred to as an MCIC
write-in portion). The control portion 20 in the MSU 3 includes, as was previously mentioned, the MCIC register 19 and the machine check processing routine.
In the signal generating portion ll, the machine check detecting and holding portion 12 detects the generation of a machine check in-terruption signal and holds the machine check interruption signal. The machine check interruption signal includes information on where -the machine check interruption signal is generated and on the cause of the generation thereof.
This information is analyzed in a debugging process so as to determine what kind of abnormal phenomenon is S generated in each portion of the data processor.
The MCIC converting circuit 13 selects the output of the selector 16 so that either the output signal from the machine check detecting and holding portion 12 or the output signal from the MCIC conversion data portion 17 is output therefrom. The MCIC converting circuit 13 usually controls the selector 16 so that the machine check interruption signal sent from the machine check detecting and holdlng portion 12 is output from the selector 16. However, when the MCIC converting circuit 13 receives the conversion command from the decoder 15, it controls the selector 16 so that the output signal sent from the MCIC conversion data portion 17 is output therefrom.
The decoder lS detects the condition that the machine check interruption signal sent from the machine check detecting and holding por-tion 12 indicates a state in which the erroneous device and the content data of the device show a condition in which operation of the hardware is unreliable, for example, a condition in which an address parity error is detected when data is written into a main storage unit. If the decoder 15 detects such a condition, it transmits a converting command output "1" to the MCIC converting circuit 13.
The kinds of machine check interruption signals which lead to the generation of the converting command output "1" are previously determined.
The MCIC conversion data portion 17 usually outputs all "O"s, and, therefore, when the all "O"s signal is outupt from the selector 16, the machine check proces-sing routine of the control portion 20 cannot at allanalyze where the machine check interruption signal is generated from or -the cause of the generation thereof ~2~
because of the all "O"s signal. Therefore, continuation of execution of the machine check lnterruption processing becomes impossible and the data processor assumes a disabled-waiting condition.
The control portion 20 stores control programs necessary to control the various operations of the data processor and performs various control processings by using them. The control portion 20 also stores the machine check processing routine.
The operation of the system according to the present invention is explained with reference to Figs. 1 and 2.
When a fault occurs during the execution of the data processing in a data processo~ and the fault detecting portion 4 or 5 outputs a machine check inter-ruption signal, the machine check detecting and holding portion 12 detects the machine check interruption signal and temporarily memorizes it. The machine check inter-ruption signal is then sent from the machine check detecting and holding portion 12 to the code register 14 and the selector 16. If the machine check interruption signal stored in the code register 14 shows an error in the CPU 1 by which the data processor is not led to a system breakdown state, the decoder 15 outputs an "0"
signal. Therefore, the MCIC converting circuit 13 controls the selector 16 so that it outputs a machine check interruption signal. The machine check inter-rupkion signal is written into an output register (not shown) by the MCIC write-in portion 18 and is transmitted to the MCIC register 19 of the control portion 20. In the control portion 20, the place where the interruption signal is generated and the cause of the generated interruption are analyzed by the machine check proces-sing routine on the basis of the machine check inter-ruption signal, debugging thereby being executed.
As a result of analysis of the machine checkinterruption signal, if the decoder 15 judges that the 7~
machine check interruption signal is one of the signals showing a condition in which the operation of the hardware from now on is not reliable~ such as the erroneous operation of the MCU, the decoder 15 outputs the conversion command output "1". In response to the conversion command output "1", the MCIC converting circuit 13 controls the selector 16 so that the selector outputs the all "O"s signal sent from the MCIC conversion data portion 17 in place of the machine check inter-ruption signal transmitted from the machine checkdetecting and holding portion 12. The all "O"s signal is sent to the MCIC register 19 via the MCIC write-in portion 18, and the machine check processing routine of the control portion 20 analyzes the signal stored in the MCIC register 19. However, since the content of the MCIC register 19 is all "O"s and since it is impossible to analyze the place and the cause of the generation of the fault, it is impossible for the data processor to continue the processing for the machine check inter-ruption. Therefore, the data processor assumes adisabled-waiting condition and stops.
According to the present invention, it is discrimi-nated whether or not the machine check interruption signal corresponds to a condition in which operation of the hardware from now on is reliable or not. If it is discriminated that the signal corresponds to a condition in which operation of the hardware is unreliable, the hardware processing is stopped. Therefore, the data processing is reliably effected.
Claims (3)
1. A system for processing machine check inter-ruption using a data processor which outputs a machine check interruption signal by detecting the generation of a machine check condition and performs interruption processing on the basis of said machine check inter-ruption signal, characterized in that said data proces-sor comprises a specific code detector means which detects a specific interruption signal among the machine check interruption signals, a signal converting means for converting the machine check interruption signal into a modified code signal when the interruption signal generated by the machine check interruption is the above-mentioned specific code, and a control portion which assumes a disabled-waiting condition in response to said modified code signal, the operation of said data processor being stopped by rendering said control portion to be in a disabled-waiting condition when interruption of the above-mentioned specific code occurs.
2. A system according to claim 1, wherein said specific code is generated when a machine check condition is detected in a memory control unit.
3. A system according to claim 1, wherein said modified code signal is an all "0"s code.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57228855A JPS59116858A (en) | 1982-12-23 | 1982-12-23 | Machine check interruption processing system |
| JP57-228855 | 1982-12-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1204876A true CA1204876A (en) | 1986-05-20 |
Family
ID=16882929
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000441404A Expired CA1204876A (en) | 1982-12-23 | 1983-11-17 | System for processing machine check interruption |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US4587654A (en) |
| EP (1) | EP0112672B1 (en) |
| JP (1) | JPS59116858A (en) |
| KR (1) | KR890001796B1 (en) |
| AU (1) | AU544915B2 (en) |
| BR (1) | BR8307085A (en) |
| CA (1) | CA1204876A (en) |
| DE (1) | DE3380369D1 (en) |
| ES (1) | ES528305A0 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4916697A (en) * | 1988-06-24 | 1990-04-10 | International Business Machines Corporation | Apparatus for partitioned clock stopping in response to classified processor errors |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3229251A (en) * | 1962-03-26 | 1966-01-11 | Ibm | Computer error stop system |
| US3555517A (en) * | 1968-10-30 | 1971-01-12 | Ibm | Early error detection system for data processing machine |
| US3707714A (en) * | 1971-01-08 | 1972-12-26 | Honeywell Inc | Multiple error detector |
| JPS5519000B2 (en) * | 1973-07-11 | 1980-05-22 | ||
| JPS50117336A (en) * | 1973-11-30 | 1975-09-13 | ||
| IT1046598B (en) * | 1974-05-16 | 1980-07-31 | Honeywell Inf Systems | INTERFACE FOR CONNECTION OF PERIPHERAL EQUIPMENT TO A COMPUTER PROVIDED WITH SIGNALING AND DISTINCTION MECHANISMS TRANSLATING TYPES OF ERROR |
| JPS51146143A (en) * | 1975-06-11 | 1976-12-15 | Hitachi Ltd | Wedging process mode when logic device generates error action |
| US4044337A (en) * | 1975-12-23 | 1977-08-23 | International Business Machines Corporation | Instruction retry mechanism for a data processing system |
| JPS6032217B2 (en) * | 1979-04-02 | 1985-07-26 | 日産自動車株式会社 | Control computer failsafe device |
| DE3036926C2 (en) * | 1980-09-30 | 1984-07-26 | Siemens AG, 1000 Berlin und 8000 München | Method and arrangement for controlling the workflow in data processing systems with microprogram control |
| JPS57159353A (en) * | 1981-03-28 | 1982-10-01 | Fujitsu Ltd | Failure processing system |
-
1982
- 1982-12-23 JP JP57228855A patent/JPS59116858A/en active Granted
-
1983
- 1983-11-17 AU AU21466/83A patent/AU544915B2/en not_active Ceased
- 1983-11-17 CA CA000441404A patent/CA1204876A/en not_active Expired
- 1983-11-23 US US06/554,730 patent/US4587654A/en not_active Expired - Fee Related
- 1983-12-05 KR KR1019830005757A patent/KR890001796B1/en not_active IP Right Cessation
- 1983-12-08 DE DE8383307470T patent/DE3380369D1/en not_active Expired
- 1983-12-08 EP EP83307470A patent/EP0112672B1/en not_active Expired
- 1983-12-22 BR BR8307085A patent/BR8307085A/en not_active IP Right Cessation
- 1983-12-22 ES ES528305A patent/ES528305A0/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| EP0112672B1 (en) | 1989-08-09 |
| AU2146683A (en) | 1984-06-28 |
| JPS6322339B2 (en) | 1988-05-11 |
| EP0112672A3 (en) | 1987-05-13 |
| ES8501902A1 (en) | 1984-12-01 |
| KR840007188A (en) | 1984-12-05 |
| ES528305A0 (en) | 1984-12-01 |
| AU544915B2 (en) | 1985-06-20 |
| JPS59116858A (en) | 1984-07-05 |
| EP0112672A2 (en) | 1984-07-04 |
| KR890001796B1 (en) | 1989-05-22 |
| BR8307085A (en) | 1984-07-31 |
| DE3380369D1 (en) | 1989-09-14 |
| US4587654A (en) | 1986-05-06 |
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