CA1202119A - System for spatially transforming images - Google Patents

Abstract

Abstract of the Disclosure A system for spatially transforming images by separate transformation of each dimension of the image is exemplified by a raster scan television system which includes for each color component a transposing memory providing a change of scan direction from horizontal to vertical, a vertical transformation system transforming in the vertical direction the vertically scanned video information, a second transposing memory coupled to receive vertically transformed video information and provide a change of scan direction from vertical back to horizontal, and a horizontal transformation system coupled to horizontally transform the horizontally scanned video signal to produce a color component output signal. The transformation system is controlled by a transform composer factorizor which receive input commands designating X and Y pretranslations, X and Y
size control, Z axis rotation angles, and X and Y post translations to produce a commanded composite transfor-mation which is then factored into horizontal and vertical components

Description

SYSTEM FOR SPATIALLY TRANSFORMING IMAGES
Bac~ground of the Invention 1. Field of the Invention This invention relates to systems for providing location transformations in a multi-dimensional coordinate system using separate transformations for each coordinate of the system and more particularly to a system providing spatial transformations of a two-dimensional video image ~, in a raster scan television system.

2. Discussion of the Prior Art Methods of producing multi-dimensional spatial transformations have been developed and are discussed in references such as Principles of Interactive Computer Graphics by William M. Newman and Robert E. Sproull, McGraw-Hill Book Company, second edition 1979, Trans-mission And Display of Pictorial Information, by D. E.
Pearson, A Halstead Press ~oo~, 1975 and "A Digital ! Signal Processing Approach to Interpolation", by i~; Ronald W. Schaefer and Lawrence R. RobineE, Proc. IEEE, Vol. 61, pp. 692-702, June 1973. However, for trans-formations which lnvolve rotation, perspective repre-sentations, or other transformations which involve more than simple unidirectional t:ranslations, or scaling the transformation process involves multi-dimensional spatial filtering and interpolation operations. Consequently, a video image transformation process requires complex and time consuming processing for each picture element of the transformed video image. Transformations are thus rendered impractical in terms of cost of data processing time for complex images such as raster scan television displays. The long processing times required further make the real time processing of a continuous stream of television frames virtually impossible with present day technology.
Nevertheless, a practical system for transforming multi-dlmensional visual images has an important demand for such diverse purposes as producing special effects in tele-vision programming or transforming a satellite picture of the earth which is distorted by the curvature of the earth into a flat pictorial representation.
Summary of the Invention The present invention relates to a processor for generating frames of video data samples from a sequence of interlaced video fields of video data samples corresponding to respective picture elements in lines in raster scan order in which spacially alternate lines of a frame are in respective temporally successive fields with a pair of successive fields forming a frame, said sequence including a most recent field, a second most recent field and a third most recent field, the processor comprising a motion detector responsive to video data samples in at least the most recent field and the third most recent field for comparing video data samples corresponding to the same spatial posi-tion in each of the two fields of data samples, the motion detector generating a motion signal as a function of the difference between the compared data samples;
and a circuit coupled to receive the most recent field and the second most recent field of data samples and the motion signal, and upon receiving each most recent field to output a deinterl.aced frame of data samples comprising the most recent field of data samples and data samples for the lines inter-mediate those of the most recent field forrned from (A) the average of data samples for respective adjacent picture elements in the :respective adjacent lines of the rnost recent field, and (B) respective lines of the kh/`
r ' Z~l~
second most recent fleld, as a function of the motion si~nal.
A svstem for spatiallv transforming images in accordance with the invention greatlv reduces conventional processing time and demands bV separately and sequentially transforming the image for each dimension of the coordinate system in which it e~ists. The multidimensional filtering required bv the composite operation for the case of a vldeo image can be accomplished on a real time basis one dimension at a time concurrently with the separate and sequential transformation operations. In an e~ample represented bv an image transformation system for real time television applications, each color com~onent of the raster scan video siqnal is passed through a serial sequence of processing elements including a horizontal to vertical transposing memory, a vertical transformation system, a vertical to horizon-tal transposing memory, and a horizontal transformation svstem to generate as an output kh/\'~i~

~x~

-3 the transformed component of the video signal. Each video component of the video signal is operated upon separately and in parallel and the operations may be substantially identical except that in some cases it may be possible to utilize slower, less expensive circuitry in the case of a color component having a narrow bandwidth compared to other color componentC.
The general principles of separating the image into unidimensional serial transformations is the same for all color components.
In the case of the video television signal, a transform composer receives c~ ~nds identifying sub-transformations such as X, Y and Z pretranslations, X, Y and Z size control, X, Y and Z axis rotation angles, and X, Y and Z post translations to generate a com-posite affine, three dimensional transformation. The three dimensional composite affine transformation is converted to a two dimensional projective transfor-mation by division by the Z coordinate. The factorizor then factors this projective transformation into two one dimensional projective transformations which control the main elements of the data processing path through a vertical address generator and a horizontal address generator. The factorizor develops the uni~
dimensional vertical transformation characteristics rcquired for each vertical column of a display in response to the inp~st commands and communicates this informatlon to the vertical address generator which in turn controls the horizontal to vertical transposing memory and vertlcal transformation system to produce the commanded imcsge transformation for the vertical direction. Similarly, the factorizor also generates the required ho~izontal transformation information which is commursicat~d to a horizontal address generator to control the vertical to horizontal transposing memory and horizontal transformation system to produce th~ commanded horizontal transformations upon data I ..

4-which has already been vertically transformed.
Brief Description of the Drawings A better understanding of the invention may be r had from a consideration of the following detailed de-r~ scription taken in conjunction with the accompanying drawings, in which:
Fig. 1 is a block diagram representation of a spatial transformation system in accordance with the in-vention;
Figs. 2A, 2B, 2C and 2D are pictorial repxe-sentations that are useful in understanding transpo-sition;
Fig. 3 is a block diagram representation of the spatial transformation system;
Fig. 4 is a block diagram of a transposing frame store for the spatial transformation system shown in Fig. l;
Fig. 5 is a memory map for the transposing frame store shown in Fig, 4;
Fig. 6 is a schematic and block diagram repre-sentation of addressing circuitry for the transposing frame store shown in Fig. 4;
Figs. 7A and 7B are block diagram repre-sentations of a deinterlace filter;
Fig. 8 is a block diagram representation of a predecimator;
Fig. 9 is a block diagram representation of a filter for the prcdecimator shown in Fig. 8;
Fig. 10 is a schematic and block diagram representation of an intcrpolation decimation filter;
Fig. 11 is a schematic and block diagram representation o a vertical source address generator;
Fig. 12 Ls a schematic and block diagram representation of a horizontal source address gener-ator;
Fig. 13 is a block diagram representation ofa digital special effects system in accordance with the .

-5-invention;
Fig. 14 is a block diaqram representation o~
the control panel for the system shown in Fig. 13;
Fig. 15 is a block diagram representation of a horizontal to vertical transposing memory shown in Fig. 13;
Fig. 16 is a block diagram representation of a field store memory for the memory shown in Fig. 15;
Fig. 17 is a block diagram representation of an addres5 and timing circuit for the field store memory shown in Fig. 16;
Fig. 18 is a block diagram representation of a motion sensitive de-interlace filter for the system shown in Fig. 13; and Fig. 19 is a block diagram representation of an advantageous embodiment of chroma predecimation and interpolation decimation filters for the system shown in Fig. 13.
Detailed Description Referring now to Fig. 1, a spatial transfor-mation system 10 in accordance with the invention which , operates separately upon each dimension of a coordinate transformation is shown in the specific embodiment of a transformation system for a standard raster scan tele-v,ision video signal. The transformation system 10 includes three color component processors 12-14, one for each of the Y, I and Q color components of a color television video si~nal. It will be appreciated that other representations for the television such as red, green, blue or Y, U, V signal could be used alter-natively. Each of the component processors 13 and 14 ~.
may be implemented as duplicates of the component processor 12 which is shown in greater detail in Fig. 1 and which will be described in greater detail herein.
The Y component p,rocessor 12 receives as an input a Y digital video component of a video image in raster scan television order and is passed serially ~., 2'~1~

-6-through a signal processing path 16 which includes a horizontal to vertical transposing memory 18, a vertical transformation system 20, a vertical to horizon~al transposing memory 22, and a horizontal transformation system 4 to produce a digital Y video output component which has been fully transformed in two dimensions, one dimension at a time. A transform compose and factorizor 26 receives operator input commands and in response thereto generates transformation information for the separate vertical and horizontal directions which is communicated to a vertical address generator 28 and a horizontal address generator 30 respectively. Because the image transformations for each of the color com-ponents are substantially identical, the vertical and horizontal transformation information may also be communicated to I component processor 13 and Q com-ponent processor 1~ without need for duplication of the transform composer 26 for each color component. A
timing and control circuit 32 develops basic timing and control signals for use throughout the spatial transfor-mation system 10 in response to an incoming synchro-ni~ation signal.
Theory of Spatial Transformation We describe a procedure for spatially trans-forming a two dimensional sampled image. Commonexamples of spatial transformations are translation, contraction and expansion, rotation and perspective projecti.on. The concept however is quite general and includes any odd warping of an image such as that produced by a ish-eye lens or a fun house mirror.
Ilathematically an image is determined by three functions of position that give the intensities o the three color componbnts at each point witllin the boundary of the image. We denote our original or 3S source image as si~u,v) for i = 1,2,3 ~2) where u and v are linearly independent coordinates that

-7-range over the area of the picture and i selects one of primary color co~ponents. The transformed target image will be written as ti~x,y) (4) S where x and y range over the area of the target. A
spatial transformation is a relation that ties x and y to u and v such that the following is true ti(x,y) = si(u,v) (6) The primary intensities at each point (x,y) in the target are determined by those at some point (u,v) in the source. For each (x,y) there should be only one (u,v~ to avoid the possibility of specifying two in-tensities for the same primary at the same point; thus the relation between them is a function of (x,y):
(u,v) = f(x,y) or u = fu(x,y) (8) v = fV(X'Y) in component form. ~ny spatial transformation can be completely specified by giving its u and v components fu and fv. These functions simply tell where to look in the source to find the primary intensities at a point in the target. Many spatial transformations are invertible and are given by (x,y) = f l(u,v) x = fx l(u,v) (10) y = f -l(u v) These functions tell where in the target to move each source intensity. Since a transformation is the same ~, for each primary we will drop the subscripts and write one representative equation for what is actually a group of three. We then have t(x,y) = s(u,v) = s(fu(x,y),fv(x,y)) (12) If we are given a transformation in the form o eq.
~10) we must first invert f 1 to get a relation of the form in (8) to be able to compute target points with eq. (12).
The problem of two dimensional spatial trans-formation is considerahly simplified by the discovery that many transformations can be factored into a product of two one dimensional transformations. The factor-ization is derived as follows. What we seek is an intermediate r such that t(x,y) = s(u,~(u,y)) (14) 10 then t(x,y) = r(fu(x,y),y) (15) with g(u,y) = v The image r is produced from s by motion only in the second coordina-te direction, since the first parameter in the equation relating the two is the same. Similarly r transforms into t by motion only in the first co-ordinate direction. To find g we have r(u,y) = s(u,v) = s(u,fv(x,y)) and fu(x,y) = u For every y we can define a one dimensional function fuy(x) fU(X~Y) u ~16) If this function is invertible we may write x = fuy (u) and substitute this into fv to get g(u,y) = v = fv~X~Y) = fv(fuy ~u),y) ~18) Two important examples of spatial transfor-mations are the affine and projective. An affine transEormation in two dimensions is given by fu~x~Y) = ~llX ~ al2Y ~ al3 v~x,Y) = a21x ~ a22Y ~ a23 (20) in ~hree dimensions by ' fU(x,y,Z) = allX ~ al2Y ~ al3Z + al4 fv~x,y,z) = a21x ~ a22Y + ~23Z ~ ~24 f ~x,y,z) = a31x ~ a32Y ~ a33z ~ a34 ~22) and in general by fi(x) = ~-1 aij j i,j+l R t24) It is known that affine transformation of dimension N
are isomorphic to N + 1 dimensional matrices of the form 11 12 '-al,N l,N+l 10 . . . . (26 N,l N,2---aN,N N,N+l . O 0 therefore the composite of two affine transform'ations lS can be calculated by taking the product of their res-pective matrices. Thus a general affine transformation can be built out of a product of simpler ones. Also the inverse of a transformation is found by inverting its matrix.
To use the matrix on an N-vector x, the vector is first mapped to an N+l-vector (x,l) by appendin~
a 1 as its N+lth coordinate. The mat,rix M is then applied to this new vector forming an N+lth dimensional result. This is projected back to N space by dropping t,he N+l h coordinate which was undisturbed by M. As a two dimensional example we have the transformation in ~20). In matrix form this is the 3x3 array all al2 al3 ~ - a21 ~22 a23 ,0 0 We map ~x,y) to the three vector (x,y,l) and apply M
-U ! !all al2 al3" X1 U = allx+al2y+al3 v - la21 a22 a23 Y v = a21X+a22Y~a23 1 ~ lo o 1 1, 1= 1 ., Dropping the third equation, which is an identity, we are left with (u,v).
If M is invertible we may express tx,y) as a O
function of (u,v) S x u y = M 1 v 1 , This is normally how transformations are specified.
For calculation purposes though, we are given indi-vidual target coordinates (x,y) and must find what (u,v) in the source contributes intensity to that location.
Translation, scaling, rotation and shearing are all special cases of affine transformation. These four taken together can produce all possible affine mappings. The matrices and formulas for these are shown below for the two dimensional case. The transfor-mations are described verbally in the source to target direction and we first show the M 1 that corresponds to ~o that description. Translation of each source point ~u,v) by a vector (TX,Ty) to a ~ -M = 1 0 TXlfx l(u,v) = u + T
O 1 Ty fy (u,v) = v ~ Ty ,0 0 1 ', Matxix for source as a function Pf target:
M 1 0 x~ u( 'Y) O 1 -Ty ! fV~X~Y) = y - Ty "0 0 Expansion by factors 9x and Sy M 1 ~ Sx O fx ~u,v) = u.Sx 0 9y 0 fy ~u,v) = v.Sy M = ~ fu(x~Y) = ~/SX
S fv(x,Y) = y/Sy O O
Clockwise rotation by an angle M =' cos ~ sin 9 fx (u,v) = u cos ~ - v sin ~
-sin ~ cos a o fy~l (u,v) = u sin a + v cos a l O
M = cos 3 -sin ~ 0 fu(x,y) = x cos ~ - y sin ~
sin ~ cos a 0 fv(x,y) = x sin g + y cos a Right shear of x coordinate by an angle M-l = ~l tan fx l(u,v) = u + v tan`t 0 1 0 fy l(u,v) = v M = 1 -tan~l 0~ fu(x,y) = x - y tanl O 1 fv~x,y) = Y
,.0 0 1, Note the simple relationship between each of these matrices and their inverses. If we are given a sequence of operations speciied in the source to target di-rection and need the M corresponding to the composite target to source transform, we may find this M by inverting each matrix in the sequence and concatenating in the revers~ order according to the formula 2; ~AB) l = B-lA-1 inste~d of inverting the composite directly. As an examp].e, suppose we wish to rotate our so~rce, then ., translate it. The M 1 for this is the product l 0 TXl cos ~ sin ~ 0 M l _ o l Tyl -sin ~ cos a o o o 1 i O . o J -or eos ~ sin 4 Tx M = -sin a cos ~ Ty O 0 Then eos 4 -sin 4 -Txcos~+Tysin4 M = sin 4 cos 4 -Txsin~-Tycos~

by direct ealeulation using cofactors since det M 1 = 1.
This same result can be had by taking the reversed produe-tion of inverse eos 4 -sin 4 0 1 -Tx M = sin 4 cos 4 0 0 1 -Ty _ o O lj O 0 Three dimensional affine transforms behave analogously except that there are three matrices for rotations ab~ut X, Y ancl Z and three for shears along those axes.
Projeetive transformations are given by the general form N
f.(x) = ~=1 aljx~ ai,N+
N
~j=l aN+l,jX; aN+l,N~l These transformatiolls are isomorphie to the set of all N+l dimensional square matrices. Affine transfor-mations are thus special eases of projective ones.
'l`he distortion of distanee produeed when a three d.imensional scene is projected onto a flat plane by a lens can be modeled by a projective transfor-mation. In fact, analysis of that distortion, ealledperspective, was the impetus for the creation of pro-jeetive geometry.
Perspeetive distortion is quite familiar to anyone involved in art, arehiteeture, photography, I

drafting, computer graphics, etc. A two dimensional perspective projection of a three dimensional scene is produced by dividing X and Y coordinates of each point in the original by its Z value, where Z points in the direction of view of the lens. Thus X' X = z, (X', Y', Z') = coordinates of point in 3-D scene Y = ~zl (x,y) = coordinates of image of point in 2-D view plane This mapping collapses all points lying on a line passing through the focal point of the lens onto a single point in the view plane.
We can construct a two-dimensional projective transformation from a three dimensional affine one.
The transformation models the image formed by a camera viewing a flat picture that has been rotated, sheared, scaled and translated to locations throughout 3-space.
We start with an image in the u,v plane and map the points in it to the 3-space coordinate (u,v,0) and apply an affine transformation of the form (22) to obtain an (x',y',z'). Dividing by z' we have x = al1u+al2v+al4 (28) and a21U+a22v+a24 (29) The a13, a23 and a33 terms are missing since w is zero in this case. Equations (28) and (29) are specifi-cations or an ~x 1(u,v) and fy l(u,v). We want to invert and factor this transformation to obtain the fu(x,y) and g(u,y) nceded in equations (14) and (15).
Since we are starting with inverses the procedure for factorization is somewhat different from that described above. We firs~ solve (2) for v to get y(u,y) di-rectly.

a22V+ (a21U+a~4) Y = a32V+ (a31U+a34) _(a31u+a34) y ( 21 24 = g~u,Y) (30 Substituting for v in (28) solving for u we have after some manipulation u ~ 22 34 2~a32)X + (al4a32 al2a34)y + (al2a24-al4a2 ) ( 21 32 a22a31)X + (al2a3l~alla32)y + (alla22-al2a2l) (31) If the terms a3l and a32 are zero and a34 equals one, the projection reduces to an affine transformation within the plane and we have x = allU+al2V+al4 y = a;~lU-~a22V+a24 v = g(u,x) - Y ( 21u+a24) (32) _~

( a22x+ -al2Y+(al2a24-al4a22) (33) A three dimensional affine transformation from a source ar.ray having three dimensional variables u, v and w to a target array having dimensional variables x, y and z would be defined by the generalized equation:
x all al2 al3 al4 Y a21 a22 a23 a24 (34) æ a31 a32 a33 a34 w 0 0 0 1 1 ~;
. ll u + al2 v + al3 w ~ al4 (3s) Ya21 u ~ a22 v -~ a23 w -~ a24 (36) 31 u ~ a32 v + a33 w -~ a 4 ~37) Although the actual manipulations become quite extensive and are therefore hereafter omitted, it will be appreciated that equation (37) can be solved for u to produce u = gl (v, t~, z) ~38) Determining u at each possible combination of values of v, w and æ and using u as a source address to obtain data corresponding to each source add~ess, a three dimensional first intermediate array of data is es-tablished having the coordinates v, w and z. The target dimension z has now been substituted for the source.di-mension w.
Next, substituting equation (38) into equations (35) and (36) to eliminate u, the result is x = g2 (v, w, z) (39) y = ~3 (v, w, z) (40) Equation (40) can now be solved for v to obtain v = hl (w, y, z) (41) Determining v for each possible combination ofvalues of w, y and z and using the determined a values as array address locations to obtain data from the first intermediate v, w, z array, a second intermediate array o data is established having dimensions w, y and z and values at coordinate points thereof corresponding to the addressed locations in the first intermediate array.
The final target matrix of data having di-mensions x, y and z is obtained by substituting equation (41) into equation (39) to eliminate v~ The result is x = h (w, y, z) ~42) Solving e~uation (42) for w we obtain w = .il (x, y, z) (43) The values oE w can be determined for all possible combinations of values x, y and z and used as source address locations within the second intermediate w, y, z array to obtain data from the second inter~
mediate a.rray and establish the three dimensional target array T~x, y, z) as the values obtained from the second intermediate array at the locations defined by w, y and z for each possible combination o values x, y and z.

~s~

Discussion of Real Time Video Image Transformation Systems The preferred embodiment of the device accepts separate digitized versions of the Y, I and Q color components of a horizontal left to right scan NTSC tele-vision signal. This signal is 525 line, 2 to 1 inter-laced, 8 bits per pixel, with a field rate of 60 Hz.
Vertical scan is from top to bottom. The Y or l-l~;n~nce signal is sampled at g times the NTSC color subcarrier 10 frequency of 3.579545 MHz ~fsc) The I and Q signals are sampled at the subcarrier rate. We discuss the transformation o~ the Y signal first. I and Q are handled similarly.
The period between Y pixels is 1/(4fsc) or 15 approx. 70 nS. There are exactly 910 pixels per 63.5 uS
horizontal scan line. Only 486 of the 525 lines in a frame contain active picture data, the rest are devoted to retrace blanking. O
The 8 bit parallel, byte serial, data stream enters the first transposing memory. This block contains three memories, each large enough to hold one active field of data. Every field the memory containing the oldest data is used as a buffer to store the current field while the previous two fields are read simul-taneously from the other two for processing. This ar-rangement prevents timing conflicts that occur when trying to write new data to a memory that still contains parts of an old field not yet processed. Only that data representing visible picture is stored, thus each memory contains 243 lines of 768 pixels. The main function of the transposing memory 18 is to change the direction o scan of the fields stored within it. Each field memory is written in horizontal order as shown in Fig. 2~, but can bc read in vertical order as 768 columns of 243 pixels as shown in Fig. 2B. Thisproduces a digital data stream representing a vertically scanned version of the input data. The horizontal and vertical dimensions of the picture are interchanged by this means. ~hat was the left to right direction in the original becomes top to bottom and what was top to bottom becomes left to right. The output data stream can be considered as a horizontal scan of the original image mirrored about its vertical center line and rotated about its Z axis 90 counterclockwise as illustrated in Figs.
2a-2D. In this manner vertical processing of the input data can be achieved by operating on the output data with a device only capable of transformation along the direction of scan. Vertical processing of the original horizontally scanned signal is difficult because vertically adjacent samples are separated widely in time. After transposition, howevex, vertically adjacent samples are close together while horizontal ones are far apart.
Referring now to Fig. 3, two 70 nS data streams representing the two fields previous to the current input field leave a transposing memory 18 to enter a deinter- ,~
lace filter 600. These two fields together contain infor-mation describing the entire spatial area of the image, except that one field was scanned 1/60 second earlier than the other. The deinterlace filter 600 blends the two fields to create a new frame that appears to have been scanned at a time midway between them. The filter effectively operates at twice the original data rate of 4fsc. The deinterlace filter 600 is implemented as two filters in parallel and data from these filters is carried in two 70 nS streams. Throughout the machine, paralleling of data paths, memory modules and computational elements is used to prevent the data rate required on any single path from rising above 4fsc~ while still retaining the enormous total rates required for real time proces-sing. The machine is built with commonly available Schottky T~L logic devices which can comfortably respond to a 70 nS clock. The predecimation filter 700 has a triple line buffer memory, one memory absorbs the present column of data while the previous column is read from another. The thixd stores intermediate results.
The predecimator 700 provides coarse size change by powers of two in the direction of scan. Each column .is processed by the filter multiple times. Every pass of the filter reduces the length of the column by a factor of two until it is only one pixel long. Each pass takes half the time of the last and produces half as many pixels, therefore the total amount of pixels produced in-cluding the original is twice the length of a column sin^e the sum of 1 ~ 1/2 + 1/4 + 1/8 + .... = 2. The predecimator output rate is thus twice its input rate and we require four 70 nS streams to carry its output to the interpolator-decimator filter.
An interpolator 800 has a double line buEfer, each side of which is long enough to contain a column and all of its predecimated copies. The filter can interpolate between two pixels to a resolution of 1/64 of a pixel and vary its low pdSS frequency response on a point by point basis over a range appropriate for the smooth compression of a column to half its normal si~e.
Compressi.ons to less than hal size are done by selecting one of the predecimated versions for interpolation and filtering. For example, if it is desired to compress the picture to 1/15 normal si~e the interpolator would select the 1/8 size decimated copy and interpolate and filter it to shrin~c it further by a factor of 8/lS, a number be-tween 1 and 1/2.
Referring now to Fig. 9, the transposing frame store 18 includes three ield buffer components 50-52 designated respectively field buffer 0, field buffer 1, and field buffer 2. Two multiplexers 5~., 56 are coupled to outpu~ bytes of video field information from one of the field buffer components 50-52 in response to selection si~nals from a memory address and control circuit 58.
Memory address and control circuit 58 also provides address and control information to each of eight com-ponents of each of the frame buffer stores 50-52, ~' The field buffer stores 50-52 operate on a continuous revolving basis in which one of the three field buffers receives an incoming field of data while the other two field buffers provide a newest complete field of data and a next oldest complete field of data to the newer and older field multiplexers 54, 56 res-pectively. A rrame start signal provides the identifi-cation of the beginning of a frame interval while the pixel clock signal provides a basic clock signal at the incoming data rate.
The revolving nature of the field buffers 50-52 and the multiplex selection can be better understood by looking at what happens at three successive field time periods beginning with an arbitrarily selected field time N. At field time N field buffer 0 is selected to have incoming bytes of video data written therein while field buffer 1 outputs the oldest frame through older field multiplexer 56 and field buffer 2 outputs the n.ewer field through newer field multiplexer 54.
At the next field time, N-~1, field buffer l becomes the write field buffer while field buffer 2 outputs the older field through older field multiplexer 56 and field buffer 0 outputs the newer field through newer field multiplexer 54.
At the next field time N-~2, field buffer 2 becomes the write buffer while field buffer 0 outputs the older field through older field multiplexer 56 and field huffer Sl outputs the newer field through newer field multiplexer 5~.
At the next field time, N+3, the cycle repeats itsel~ with field tim0 N+3 being identical to field time N. It will be appreciated that during each cycle ~`
of three fie~ld times each field buffer is written into once and then read out through newer field multiplexer.
54 and then read out through older multiplexer 56. As a result, the older field multiplexer S6 always outputs field N-2 while newer field multiplexer 54 always ~r~

outputs field N-l where field N is considered to be the field which is currently being written into one of the field buffers 50-52. The two most recent stored fields are thus continuously output to the next stage and are updated ror each new field time.
Read and write accessing of the frame buffers 50-52 is complicated somewhat by the fact that practi-cally available memory storage chips cannot read and write at the 70 nanosecond pixel clock rate. In order to accommodate the required bandwidth, each of the field buffers is implemented as 8 modules of 32K x 8 memory. By sequentially accessing the 8 modules, each individual module has 8 pixel clock periods to read and write a byte of data corresponding to a sampled pixel location. However, in order to assure proper sequencing of the memory modules for both the horizontal and vertical accessing which are required to obtain a horizontal to vertical transposition, care must be _ taken in implementing the addressing scheme.
One advantageous addressing scheme is shown by way of example for field buffer 50 in ~igs. 5 and 6.
Fi~. 5 illustrates the lower addresses of an address map for field buffer 50. The 1 byte memory components 0-7 are represented vertically in ascending order from top to bottom while hardware memory word addresses ascend from left to right as indicated immediately above the map. Howeverv, for convenience of address implementation these rnemory addresses may be further divided into row and column addresses which are in-dicated above the chip address in Fig. ~.
Horizontal accessing of the first row is themost strai~htforward. Hori~ontal accessing begins with address 0 of component 0 and proceeds through the components in sequence. After address 0 has been written in module 7 the column address is incremented with pixel trow, column) position t0,8) bein~ accessed at word 1 of module 0. The 768 pixels of the ~irst row of a field are written into the first 96 word positions of the memory modules in sequential order.
In the event of a vertical access, it must be remembered that the 2 pixels located at column 0 and rows 1 and 2 will be accessed in sequential order.
Care must therefore be taken that these two pixels are stored in sequential memory modules and not in the same memory module. This is accomplished by storing pixel 1,0 in module 1 with the word address being skipped to address 128 which corresponds to a resetting of the column address to 0. The memory modules are then again accessed in sequence with a wraparound to component 0 before the word address is incremented to column address 1 which corresponds to chip address 129.
Similarly, for the second row the first pixel of the second row must be stored in module 2 and the modules then continue to be accessed in sequence with a wrap-around until the word address is incremented after _, module 1 has been accessed. The starting module for 20 the first pixel of a row continues to be incremented in similar fashion until all 8 components have received the first pixel of a row. The process then recycles with component 0 receiving the first pixel of row 8.
When making vertical accesses to the frame 25 buffer, the components are again accessed in sequence except that the row address is now incremented for each pixel. At the beginning of each new column, the row address is returned to 0 and the column address is incremented to 1. It will be observed that pixel 0,0 30 occurs at row 0 column 0, component 0; pixel ljO occurs at row 1, column 0, component 1 and pixel 2,0 occurs at row 2, column 0, component 0. This addressing ar- v rangement thus meets the requirement that the compo-nents of the frame buffer can be accessed sequentially 35 for both vertical and horizontal accessing.
An advantageous implementation of this ad-dressing scheme is shown in Fig. 6 wherein the frame 2~
.

-22~

buffer 50 includes eight 32K x 8 storage modules desig-nated module 0-7. Each module has a corresponding data latch and an address latch. The least significant address bits 0-6 are provided by a 7 bit column counter 70 w'nile the most significant 8 address bits 7-15 are presented by an 8 bit row counter 72. Row counter 72 is reset at each field start and incremented for each pixel in a vertical mode and at row start in a hori~
zontal mode. The column counter 70 is reset to 0 at field start and at row start when in a horizontal mode and is incremented in response to the maximum count output of a 3 bit counter 74. Counter 74 is coupled to be reset at eield start and is clocked by the pixel clock signal. The count enable input to counter 74 is continuously enabled in a horizontal access mode and is enabled at column start for a vertical mode. Conse-quently, the column counter 70 is incremented for every eighth pixel cloc~ in a horizontal mode and for every ,~
eighth column in a vertical mode.
Selection for the 32K x 8 modules 0-7 is controlled by a 3 bit counter 80, a 3 bit counter 82, and a 3 to 8 module select decoder 84. Three bit counter B2 is incremented at the pixel clock rate to control the sequential accessing of the individual Z5 memory modules. The output of counter 82 is decoded by decoder 34 to select one of the eight modules in sequence for the simultaneous loading of the,data latch and address latch for the selected module. Three bit counter 80 provides the required staggered module offset at row or column start. Counter 80 is reset at field start and is incremented in a horizontal mode at row start and in a vertical mode at column start, ~' Three bit counter 82 is loaded at column start or row start with the contents of 3 bit counter 80 immediately prior to incrementing.
It should be noted that the addressing of the field buffers 50-52 is described in terms of vertical ~L~Z~2~

-~3-mode accessing and horizontal mode accessing. Under most circumstances these frame buffers provide a trans-portation by being accessed in a horizontal mode for writing and in a vertical mode for reading~ ~owever, under some circums~ances the frame buffers may be accessed in a horizontal mode for both reading and writing. The failure to provide a transportation at frame store 18 coupled with a transposition at frame store 22 effectively imposes a 90 rotation upon the video image. ~s an image is rotated .oward 90 the image effectively becomes mapped into a line of 0 width and resolution is lost. However, the resolution of the video image can be better preserved for large angle rotations by transposing the image at only one of the frame stores 18 and 22 and then imposing a negative rotation of between 0 and 45 to account for the differ-ence between the desired rotation angle and the 90 rotation imposed by failing to provide a transposition at frame store 18.
Transposing frame store 22 of Fig. 1 is implemented in a manner substantially identical to frame store 18 except that frame store 22 requires only two field buffers. A field of data is written verti-cally into one buffer while a previously written field is read horizontally out of the other buffer. The two buffers are then interchanged with the one buffer being read horizontally while the other buffer is written vertically.
The deinterlace filter 600 of Fig. 3 is illustrated in Figs. 7A and 7B. Filter 600 includes a 2 byte wide three stacJe shift register 602, a filter component 60~, and multipl~xers 606, 608. The even and odd line data frorn the transposing frame buffers 50-52 is clocked at the pixel rate through the shift register 602 having stages R0-R5 which are numbered in scan sequential order for interlaced vertically scanned data Erom the transposing frame store 18. Although the i connections are not explicitly shown for simplicity, the purpose of the shift register 602 is to make the contents of each stage R0-R5 available to filter 60q.
Multiplexers 606, 608 respond to a vertical scan signal to select odd and even outputs respectively from filter 604 when data is being output from frame store 18 in vertical scan order. When data is being output in horizontal scan order multiple~ers 608 selects the output of register stage R2 to drive the even byte data stream while multiplexer 606 selects the output of register stage R3 to drive the odd data byte stream.
In the event of horizontal accessing of the frame store 18 a similar deinterlace filter subsequent to the vertical to horizontal transposing frame store provides deinterlace filtering.
The filter 604 contains substantially identical components for the even and odd data streams each of which provide a -1/8, 2/8, 6/8, 2/8 and -1/8 filtering function. ~' Each of the two odd and even components of filter 60 is advantageously implemented as shown in 7B with multiply by two functions 610, 611 multiply by four function 612, four addition functions 614-617, one subtraction function 618 and a divide by eight function 620. It will be noticed that the multiply and divide functions are implemented as powers of two and that they can therefore be easily accomplished by merely shiftin~3 the relative positions of the data bit lines for incoming and outgoing data streams. The inputs to the even and odd data stream filters are indicated by the information shown in the even and odd columns of shift register 602. Each element in the table refers ~, to a shift register stage within shift register 602 whose output is connected to a filter input as indicated.
Referring now to Fig. 8, the predecimator 700 includes five line buffers designated line buffer 0 throuc3h line buffer ~, each of which has a 256 word x 32 bit storage capacity. Line buffers 0-3 each receive two 8 bit data streams from multiplexers 702-705 res~
pectively. Each of the multiplexers 702-705 is capable of selecting one of four input signals and placing the selected input signals on one of the 8 bit buses to its corresponding line buffer. In some modes o~ operation the two 8 bit bus inputs to the line buffers are driven in parallel. The multiplexers 702-703 must thus be capable of either se'ecting two of the four input byte streams or one of the four input byte streams depending upon the mode of operation. Line buffer 4 receives two

8 bit data streams as even and odd outputs from a filter 708.
~ 32 bit wide 5 to 1 multiplexer 710 provides a 32 bit output which is split into four 8 bit data lS streams and communlcated to a 4 byte wide 3 stage shi~t regi.ster 712. Data is loaded into the line buffers and in such an order that it may be read out to fill the 12 bytes o~ shift register 712 with a serial sequence of J, pixel information for a scan line. That is, each register stage of shift register 712 stores 1 pixel of information and the pixel information is arranyed in raster scan order as designated by the numbering of the registers R0-Rll. Registers R8-Rll provide data output to the next stage of the transformation system as well ~5 as data output to the second stage of the shift register containing registers R~-R7. The purpose of shift register 712 is to make available to filter 708 12 bytes of sequential pixel inform~tion in a predetermined order. Although not explicitly shown for simplicity, the outputs of each of the registers R0-Rll are com-municated to filter 708.
~ ilter 708 actually contains two separate filters operating in parallel. One of the filters generates even numbered plxel data at the pixel rate while the other generates odd numbered pixel data at the pixel rate. The even and odd outputs 716, 718 thus provide eedback data at twice the pixel rate in -~6-combination. A disable sisnal may be utilized to drive an output disable input to multiplexer 710 at the end of the processin~ for a scan line to cause zeros to be loaded into shift register 712. This loading of zeros creates an aesthetic blending by filter 708 at the end of a scan line and prevents information from the end of a scan l ne from affecting information at the beginning of the next scan line. Six extra clock signals are provided at the end o~ each scan line pass through the filter 708 before data is input through multiplexer 710 for the next scan line to clear the pipeline of the predecimator system, and particularly the shift register 712.
While the wide distribution of the four scan line signals stored by the line buffers 0-4 in order to accommodate different operating modes makes the pre-decimator 700 appear complex, its operation is actually quite straightforward. In the normal mode of operation ~, vertical scan line information from corresponding vertical scan lines of a pair of sequential fields is received over the even and odd input lines and gated into line buffer 0. Because these even and odd input lines represent data from consecutive fields, they each carry alternate pixels for a frame. That is, for a cJiven scan line column, the pixel information for rows 0 and l appear on the even and odd bus respectively followed by pixel information for rows 2 and 3 on the even and odd bus respectively followed by the pixel information for rows ~ and S on the even and odd bus and so forth. Multiplexer 702 connects the upper output stream 720 to the even input b~s and simultane-ously connects output stream 722 to the odd input bus.
Gating at the input latches to line buffer 0 directs the eirst or row 0 pixel information to byte position 0 of the input data latch while the row l pixel infor~
mation on bus 722 is gated to byte position l o~ the input data latch. At the next pixel clock period th~

.

pixel information for frame row 2 appearing on bus 720 is gated to the position 2 input data latch and the frame row 3 pixel information appearing on bus 722 is gated to the position 3 input data latch. The ~irst four pixel bytes are thus stored in the input data latch in sequential scan order at the end of 2 pixel clock times with the data being written into address word location 0 and the input data buffer being re-loaded with pixel information for row positions 4-7 during the third and fourth pixel clock times for storage at address word location 1. It is thus seen that a vertical scan column from a pair of sequential fields is deinterlaced and stored in line buffer 0 in raster scan order during a vertical line scan time period which will be designated scan time N to provide a frame of reference.
During this same vertical scan time and simultaneously with the writing of a frame scan line '~
into buffer 0, previously written vertical scan line information is read from line buffer 2 four bytes at a time and output through 5 to 1 multiplexer 710 to the first stage of shift register 712 comprising registers R8-Rll. Subsequent 4 byte words are read from line buffer 2 and shifted through shift register 712 at each ~5 pixel clock time. Since the data read out oE line buffer 2 and shifted through shift register 712 contains a 4 byte parallel data stream, the effective bandwidth of this data transfer operation is four times the pixel rate. ~ilter 708 responds to the data content of the indivldual byte re~isters R0~~11 in shift register 712 to output 2 bytes of data designated even and odd on bus lines 716 and 718 at the pixel rate. Since the input scan line information to line buffer 0 and the even and odd output information from filter 708 each contain 2 bytes in parallel while the information being read from line buffer 2 contains 4 bytes in parallel, the line buffer output information has twice the effective bandwidth of the other two data streams.
Line buffer 4 is gated to provide to its input data latch alternate bytes from the even and odd data streams from filter 708 in a manner similar to the gating of even and odd frame data into line buffer 0.
Consequently, as 4 byte sequences of input pixel infor-ma-tion are loaded into line buffer 0 four byte sequences of filtered information from filter 708 are loaded into line buffer 4. At the point in time during a scan line cycle where half of the pixels for the incoming vertical scan line has been loaded into line buffer 0, half of a scan line worth of pixel information from filter 708 will have been loaded into line buffer 4 since the bandwidth of the two data stream inputs to line buffer 0 and line buffer 4 are the same, i.e. twice the pixel rate. However, while line buffers 0 and 4 are being loaded at twice the pixel rate, line buffer 2 is being output at four times the pixel rate so tha' as half lines of pixel information are loaded into line buffers 0 and 9 a complete line of pixel information has been passed through shift register 712 and processed by filter 708. ~he half line of data stored in line buffer 1 thus represents a 2:1 compression ratio since the processing of a full line of information has resulted 2S in the storage of a half line of information.
It will be noted that during the first half o the scan line period the full, uncompressed pixel information was transferred through shift register 712 and presented to down path circuitry for possible use thereby by the o~tputs of shift register stages ~8-Rll.
~hus, even though a 2:1 data compression has taken place the original data may be stored and preserved for further use by the down path circuitry. During the next one-fourth of the scan line time period ~time one-half to three-fourths) line buffer 0 continues to receive pixels of video input information in scan line order while line buffers 2 and 4 are interchanged. The 2:1 compressed data is read out of line buffer 4 at four times the pixel clock rate, passed through shift register 712 to filter 708 for compression processing and written into line bufer 2. As the 2:1 compressed data is read from line buffer 4 and passed through shift register 712 it also is made available for storage and later use by down path circuitry through the data outputs from registers R8-Rll. At the end of three-quarters of the vertical scan line period, a scan line of 4:1 compressed data has been loaded into line buffer 2. During the next one-eighth of a line scan period the 4:1 compressed data is read out of line buffer 2 and in response 8:1 compressed data is stored in line buffer ~. This proccss of sequentially further com-pression hy two with alternate storage in line buffer 2and line buffer 4 is continued to the end of vertical scan line time period at which a complete vertical Erame line has been loaded into buffer 0 and the scan line being circulated through filter 708 has been .compressed to a single pixel or byte.
This predecimating thus provides down path circuitry with a selection of scan line information which has been processed in a high quality filtering process and having compression ratios in powers of two~
This predecimating performs much of the burden which would otherwise be incurred by the vertical transfor-mation circuitry to provi~de an improved final fully transformed video image for a given data resolution of the data transEorm~tion system. For example, if a compression ratio o 17:1 is required, the transfor-mation system may select from the predecimated data having a compaction ratio o 16:1 and provide only a very small aclditional compaction required to increa~e the ratio to 17:1.
At the end of vertical scan line time period N a new vertical scan li.ne time period N + 1 begins with multiplexer 704 gating a next vertical scan line pair of even and odd field data into line buffer 2 in sequential order just as the previous scan line had been written into line buffer 0. At the same time, a flip-flopping data exchange begins between line buffer 0 and line buffer 4 with the scan line data being predecimated to provide sequential compressions by factors of two as the scan line data is recirculated through shift register 712 and filter 708 as previously done for the data stored in line buffer 2 during vertical scan line time N. ~or the next vertical line time period N ~ 2 the cycle is repeated with the incoming scan line pixel data stream being loaded into line buffer 0 while the contents of line buffer 2 are pre-decimated.
lS In the mode of operation wherein data is received on the even and odd input buses in horizontal rather than vertical scan line order the data buffering process must be slightly different because each even _, and odd input carries a complete sequence of pixel low information by itself rather than information for alternate pi~el locations as was the case for the interlaced vertical scan line information. Complete even row data is on the even line while complete odd row data is on the odd line. For this mode of operation multiplexers 702 and 703 operate to select and gate the even and odd incoming horizontal data streams to line buffer 0 and line buffer 1 respectively. Multiplexer 702 causes the even line incoming data stream to be alternatcly gated onto upper bus 720 and lower bus 722 to permit the loading of the incoming pixels into the 4 byte input data buffer for line buffer 0 in sequential scan order. Similarly, multiplexer 703 operates to a].ternately gate the incoming odd horizontal scan line information onto upper bus line 724 and lower bus line 72~ to permit the loading of the odd horizontal scan line information into line buffer 1 in sequential scan order. While each of the line buffers 0 and 1 are now loaded at the pixel rate instead of twice the pixel rate for the vertical scan mode of operation, the total incoming data rate remains at twice the pixel rate since two line buffers are used in parallel instead of one. As the horizontal scan time interval continues previously loaded data is read out of line buffer 2 at four times the pixel rate, passed through shift register 712 and filter 708 to be s-tored by line buffer 4 with a 2:1 compaction ratio. Since the data is read out of line buffer 2 at four times the rate that data is being written into each of the line buffers 0 and 1, a ~ull scan line of data will have been read out of line buffer 2 and passed through filter 70B by the time one-fourth of a line of data has been stored in each of the line buffers 0 and 1. The original contents of line buffer 2 will have been fully predecimated by the time line buffers 0 and 1 are each loaded with one-haIf of a line of information. During the second half of the -' horizontal line time interval the previously written contents of line buffer 3 are predecimated. During the next horizontal scan line time period interval horizontal scan line information is written sequentially into line bu~fer 2 and line buffer 3 for even and odd scan line row information respectively while the previously stored contents of the line buffer 0 are predecimated during a first hal of the scan line time period interval and the previously stored contents of line buffer 1 are predecimated during the second half of the scan line time period interval. It is thus apparent that the predecimation process is substantially the same for both vertical and horizontal scanning although the buffering of the incoming data must be somewhat diEferent to account for the diferences in the inter-laced and non-interlaced incoming video data streams.
Pilter 708 contains two parallel filters providing a -1/16, 0, 5/16, 1/2, 5/16, 0, -1/16 filtering function and are identical except for their input ~>

connections within shift register 712.
~ highly advantageous implementation for filter 708 is illustrated in Fig. 9 to which reference is now made. While only one ~ilter 708 is shown, it will be appreciated that duplicate even and odd filters are employed with their inputs connected to the res-pective even and odd registers indicated by the table at the inputs to the ilter. It will be known that the filter is very conveniently implemented with four 10 adders 730-733 and a single subtractor 734. No actual multiplication or addition is required since the multiply blocks 736 and 737 and the divide block 738 are implemented in powers of two to permit the operations to be accomplished by merely shifting the relative bit positions of the incoming and outgoing data information.
Because of the elimination of actual multiply and divide operations, the filter 708 can be implemented at far less expense than conventional seven point filters and can operate at the 70 nanosecond pixel clock rate.

., 2~ ~ ~

Interpolation decimation filter 800 and 906 are essentially the same and are representatively illustrated by interpolation decimation ~ilter 800 as shown in Fig. 10 to which reference is now made.
Filter 800 provides the ultimate functional relationship between the source or input video data and the target data in the vertical dimension.
Vertical source address generator 912 ~Fig.
3) calculates and supplies to interpolation decimation filter 800 a sequence of vertical pixel source addresses corresponding to a sequence of output target video data in response to the vertical target address counter 914 and transform composer and factorizer 916. The addresse~
supplied by vertical source address generator 912 have a resolution of 1/64 pixel and includes a 4 bit magnifi-cation factor parameter of between 0 (for a 1/1.99 sized image or larger) and 15 (for predecimated data compressed by 215 or more). Interpolation decimation filter 800 supplies a video data value calculated from four pixel locations appearing on each side of the source address. Sixteen ilter functions are available for calculating the output video data value. One is selected in response to a four bit parameter alpha in accordance with the desired compaction ratio provided by interpolation decimation filter 800 in addition to a selected predecimation compaction.
A two line double buffer 809 is implemented in 8 segments 801 808 and receives video data ~ bytes parallel from the R8-Rll data outputs of predecimator 30 700 (Figs. 3 and 8). ~or each vertical scan line of a frame the received data includes a full line of video data plus all of the predecimated copies of the full line which copies occupy a second full line of data.
Hence, there~ .is a need for storing two lines of data in each half of the double buffer 809. The double buffering permits a new two lines of video data to be received while the immediately preceding two lines of data are operated upon to provide one line of target image video data.
As video data is received by dou~le buffer 809 the first four bytes are stored respec~ively in the four segments 801-804, the second four bytes are stored respectively in the four segments 805-808, the third four bytes are stored respectively in the four segments 801-804 and so forth. ~he eight part segmentation of the double input buffer 801-808 thus assures that the pixel data for the four adjacent pixel locations on each side of an address point (8 total) can be read in parallel from the double input buffer.
A barrel shifter 810 receives the 8 bytes of pixel data from double input buffer 809, circulates the data to a desired position in response to the three least significant bits of the nonfractional portion of the source address and presents the circulated vïdeo data to an eight segment multiplier 820 having segments 821-828. The data is circulated such that the pixel data corresponding to the nonfractional portion of the source address is presented to a central multiplier segment 824. The pixel data for the three pixels sequentially to the left thereof are presented to segments 823, 822 and 821 while the pixel data for the four pixels to the right are presented to segments 825-828 respectively. The eight multiplier segments 821-828 thus receive as first~ inputs 8 bits of video data for each of 8 sequential pixel locations centered about the source address point.
~;ultiplier segments 821-828 each receive as a second input An eight bit coefficient or weighting function from an 8 segme~t coefficient memory 830 having segments 831-838. Each segment is configured as 1024 words of eight bits each. The coefficient memory 830 receives as a partial ~ddress the six bit fr~ctional part of the source pixel address. These six bits provide a phase factor 0 which deines the one of 64 subpixel points for the 1/64 pixel 2~1~

xesolution of the source address. A filter funetion may thus be centered about the subpixel source address with the pixel data being weighted in accordance with its position on a filter function curve relative to the 5 subpixel address.
The coefficient memory 830 further reeeives four bits of adclress in accordance with the parameter alplla which is related to the magnification produced by interpolator decimation filter 800. Coefficient memor~
830 may thus contain 16 different filter functions for each of the 64 subpixel source addresses. The filter function may thus be tailored to the degree of magni~ica-tion (compaction) provided by interpolation decimation filter 800. For examplé, if the output target image is to be at least as large as the selected original or predecimated copy of the source image, it may be desirable to use a filter function which heavily weishts video data for pixel locations very close to the source address. On the other hand, if compaction approaching ]/2 is desired, a filter function siving at least some weight to all eight pixel locations near the source address may be desirable. It will be recalled that the predecimator 700 provides compaction by all practical powers of 1/2 so that the further compaction provided by interpolation decimation filter 800 can always be by a magnification factor greater than 1/2.
An addressing circuit 840 is illustratively represented by a segment 8~1, which is one of eight segments provicling address inputs to the eight double 30 buEfer memory segments B01-808 respectively. Address segment 8~1 includes an adder 851, a magnification factor ROM 861 and a carry ROM 871. Adder 851 receives as a first input the nonractional part of the souree address divided by eight. Division by eight i9 of course accomplished by merely shifting off the three least significant bits of the integer portion of the source address. The four bit magfactor parameter i~

~P~

presented as an address input to ROM 861 which generates an address shift in accordance with the magnification factor. If the target image is to be larger than half the size of the source image magfactor is zero and the full size copy of the source image is output to barrel shifter 810. For a tarqet image compressed to between 1/4 and 1/2 the size of the source image the ROr~ 861 translates the source address to the half size predeci-mated copy of the source image and so forth.
Carry ROM 871 receives the three least signifi-cant bits of the integer part of the source address and selectively provides a carry output to increment the translated buffer memory 809 word address when the three least significant bits designate a number between g and 7 inclusive. This selective incrementin~ accom-modates situations where the desired eight pixels cross a word boundary for buffer memory 809. It will be noted ` that the addresses for segments 806~ must be _, selectively decremented rather than incremented.
As an example, assume that the source address is 25 5/64 (binary 00011001.000101) for a full size taryet image. The divide by 8 pixel address input to adder 851 thus becomes 3 (Binary 00011). Magfactor = 0 will designate a full size image and the output of ROM
861 to adder 851 will be zero. ~or the given address it is desired to read from buffer memory 809 video data for pixel locations 22-29. The data for pixels 24-29 is stored at word location 3, buffer segments 801-806, while data for pixel locations 22 and 23 is stored at word location 2 in buffer segments 807 and 808 respec-tively. C-ROM 871 thus outputs a zero in response to a 1 (binary 001) inpu-t and buffer address word 3 is presented to segment 801 by adder 851. Similarl~
segments 802-806 will receive address word 3 from their respective address circuits 840 and segments 807 and 808 will receive a decremented address word 2.
Data for the pixel defined by the integral -3~-portion of the source address (pixel 25) is output from segment 802 and is circulated downward (as shown) two places by barrel shifter 810 in response to the three least significant address bits (001) so that data for the designated source pixel is presented to multiplier segment 824. Coefficient memory 830 can thus be programmed with the assumption that the video data for the eight pixels about a source point will always be presented in ascending order to multiplier segments 821-828. The same effect could be accomplished by eliminating barrel shifter 810 and adding three address inputs to coefficient memory 830 with each of the segments receiving additional programming to accommodate the eight possible locations where the data for the designated source pixel might occur.
The multipliers 821-828 of arithmetic network 812 thlls receive the 8 pixels of video data from barrel shifter 810, multiply the pixels by their appropriate coefficient factor from coefficient memory 830 segments 831-838 and output the results to a summing network 881-887 which sums the eight products to generate the pixel of video data corresponding to the input source address. The resulting s-tream of pixel data from interpolation decimation filter 800 is fully processed in the vertical dimension and is then presented to the vertical to horizontal transposing memory 900 for the initiation of processing in the horizontal dimension separately from the processing in the vertical dimension.
Referring now to Fig. 3, interpolation decima-tion filter 800 receives vertical lines of the source image. ~ven if the video data is read out horizontally from H to V transposing memory 18, the video data is still tre~ted as a vertical scan. The net effect is a 90 rotation and mirror imaging which is compensated by transform composer and factorizor 916.
It will be recalled that x and y are used to identify pixel locations within the target or output image while u and v are used to identify pixel locations within the source image. At interpolation decimation filter 800 each vertical scan line corresponds to a constant u value with the u value being incremented for each sequential vertical scan line starting with zero and moving from left to right. For each vertical scan line interpolation decimation filter 800 receives a sequence of v address inputs from vertical sourc.e address generator 912 specifying a sequence of pixel addresses within a scan line for a sequence of video data pixels. Interpolation decimation filter 800 responds to each v address received by outputing a pixel of video data as a function of the pixels positioned about the v point in the vertical scan line.
Equation 31 defines v as a function of u and y and a number of constants from an "a" matrix (Table I) which defines the desired relationship between the target and source images. During each vertical retrace time between fields the transform composer and factorizor 20 916 calculates the required matrix constants in response to operator input con~ands and supplies them to vertical address generator 912. Vertical address generator 912 itself generates the u and y terms by in effect starting at zero for the first pixel of the first scan line and 25 incrementing y for each successive pixel and incrementing u for each successive vertical scan line.
Similarly, for the horizontal dimension horizontal address generator 908 receives the appropriate "a" matrix constants from transform composer and factorizer 30 916 and calculates the horizontal source addresses u for each horizontal scan line in accordance with equation v 31 as a function of x and y. X and y are, in effect, established by starting at 0,0 for the first pixel of eacll field and incrementing x for each pixel and increment-35 ing y for each horizontal scan line.
While the vertical and horizontal addresses v and u could of course be generated from the equations therefor by microprocessors, it would be very difficult to accomplish this at the 70 n sec pixel rate. The vertical source address generator 912 and horizontal source address generator 908 are special purpose circuits for calculating the v and u equations 30, 31 at the pixel rate. It is of interest to note that video data enters interpolation decimation filter 800 at twice the pixel rate because of de-interlacing but passes through the remainder of the system at the pixel rate. The vertical and horizontal source addresses need thereEore be generate~ at only the pixel rate and not twice the pixel rate.
Referring now to Fig. 11, the vertical source address generator 912 includes a numerator calculation circuit 914, a dPn~-nator calculation circuit 916, a divider circuit 918 to divide the numerator by the ' denominator and a timing and control circuit 920 for generating the various timing and control signals used throughout the vertical source address generator 912.
A previous v register 924 receives and temporar-ily stores each vertical address v. A subtractor 926 subtracts the stored previous v address from the current v address to generate an 18 bit difference parameter on signal path 928. The most significant bit of the 17 bit difference parameter is a sign bit while ' the six least significant bits represent a fractional part. The difference parameter is used as an estimate of the derivative of v with respect to time from which terms Magfactor and Alpha are derived.
A magfactor ROM 930 receives the integer portion o~ the difference parameter and outputs the term ma~factor as the integer part of the log base 2 of the absolute value of the difference parameter. ~agfactor equals 0,~or difference parameters of 0-1.99, 1 for .
difference parameters 2.00-3.99, 2 for difference p~rameters of ~.00-15.99 and so forth. Only absolute values are considered. Magfac,tor commands interpolation ~'P~3ll~9 decimation filter 800 to use a particular predecimated copy and is communicated to a barrel shifter 934 which shifts (divides) the vertical source address by a number of blt positions equal to magfactor to produce an adjusted source address. When a predecimated copy or a line of data is selected having compaction by a given power of 2, the source address must be divided by the same power of 2 for compatibility and barrel shifter 934 performs this function.
The difference parameter is the reciprocal of the magnification of the target image relative to the source image. Por example a double si~e target image will produce difference parameters of 0.5 while a half size target ima~e will produce difference parameters of 2.0 and so forth. The difference parameter is thus a measure oE the magnification (including compaction) of the target imaye relative to the source image. Barrel shifter 136 receives the difference parameter and shifts it toward l~ss significant bit positions by a number of bit positions indicated by the parameter magfactor to generate an interpolator difference signal in signal path 938 which represents the magnifica-tion (compaction) which must be performed by interpolation decimation filter 800 over and above that perormed by a predecimated copy selected by the parameter magfactor.
A parameter interpolator difference is used as an address input to alplla ROM 938 which responds by generating a 4 bit parameter, alpha, which selects one of lS filter functlons for use by interpolation decimation fi.lter 800. To improve target image quality it is desirable to use different filter functions for different degrees of magnification ~compaction) of the target image by the interpolation decimation filter. Filtering of the predecimated copies is handled by predecimation filter 700 so that only the additional filtering by interpolation decimation filter 800 is of interest at this polnt.

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For example, if the target image is to be full size or larger, a high peak, narrow filter function should be used which places great weight on the source pixels nearest to the vertical source address point.
As the target image is compacted by greater and greater amounts, the filter function should become flatter and broader, thus putting less weight on pixels immediately adjacent the source address point and more weight on pixels farther from the source address point.
Interpolation decimation filter 800 provides all degrees of image enlargement but a m~x;ml-m compaction by a factor of 1.99. Any additional compaction would be accomplished by selecting a smaller predecimated copy. ~or example, compaction of the target image by a factor of 16 would be accomplished by selecting the fourth predecimated copy (magfactor equal 16) and by introducing a compaction factor of 1 in the interpolation decimation filter 800 (no further compaction). The _~
term magfactor would be 4, the difference parameter would be 16 and the interpolator different parameter would be 1. For compaction of the original image by 32 the fifth predecimated copy would be selected, magfactor would be 5, the difference parameter would be 32 and the interpolator difference parameter would be 1. For compaction of the original image by the factor of 15.4, the third pîedecimated copy would be selected, mag-factor would be 4, the difference parameter would be 15.~ (binary 1111.011001), and the interpolator difference paralneter would be 1.92 (binary 1.111011).
~'he .integer part of the interpolator difference parameter on signal path 938 has a ~xim~m value oP 1 and its fractional part has 6 bits of accuracy. The .interpolation difference parameter thus has 7 bits and alpha RO~I 932 can have a size of 128 by ~. Since a single filter function is adequate for all degrees of image enlargement, full size and slight compaction, it is desirable to divide the range of the interpolation 1, -~2-difference parameter between 1.00 and 1.99 into 16 equal parts along a logarithmic scale with each part being assigned a different alpha parameter and a corresponding filter function.
The alpha ROM 932 is thus loaded to output 0 for addresses 0-1.04 (binary 1.000011), 1 for input addresses 1.05-1.09 (Binary 1,000100 to 1,000110); 2 for input addresses 1.10 to 1.14 (binary 1.000111 to 1.011001) and so forth up to 15 for input addresses 10 1.91 to 1.99 (binary 1.111010 to 1.111111). A different filter function can thus be provided for each of the 16 values of alpha ranginc3 from narrow and steep for alpha equal 0 to broad and flat for alpha equal 15. The same filter function is thus used for full size images, enlarged images and the largest sized group of compacted images.
The vertical source address generator 912 in-cludes a numerator circuit 914, a denominator circuit 916, ~' and a divider and denormalization circuit 918 which divides the output of the numerator circuit 914 by the output of the denominator circuit 916 and then denormalizes the quo-tient before outputing the vertical address, ~r, to barrel shifter 934. A timing and control circuit 920 responds to cc ~n~ls received from vertical target address counters 914 on signal paths 940 which indicate the end of a frame interval as well as information from transform deposer and factorizer 916 received on a communication bus 942 to generate the various timing and control signals used througllout the vertical source address generator 912. It will be appreciated that the actual circuitry of the source address generator has been represented in a simpli- ~.
fied form for clarity of explanation. For example, multi-plexers 9~4, 946 and 94~ can be implemented through selective gating of tristate logic circuits rather than as separate integrated circuits called multiplexers and data can be sequentially loaded one byte at a time into 32 bits (94 byte) data registers 950, 951, 952, 953, 954, and 955 -~3-where the communication bus 942 includes for example an 8 bit data bus from an 8 bit microprocessor. Data register 956 is also a 32 bit xegister while bias data register 957 may be implemented as an 8 bit register.
It will be recalled that vertical source address generator 12 solves equation 30 to generate vertical source addresses at the pixel rate. During each vertical retrace time interval transform composer and factorizer 916 loads the constants for equation 30 into corresponding registers of vertical source address generator 912 over communication bus 942. For e~ample, the numerator con-stants a31, a3~, a21, and a24 are loaded respectively into 32 bit registers 950, 951, 952 and 953. Timing and con-trol circuit 920 renders the select A inputs of multi-15 plexers 944 and 946 at logic zero during this interval to permit the data to be communicated to the inputs of regis-ters 951 and 953. Thereafter the select A inputs are set to logic 1 so that register 951 receives data from a 32 bit adder 960 throu~h ~ input of multiplexer 944 while register 953 receives data ~rom a 32 bit adder 962 through the A
input of multiple~er 946.
Similarly, during the vertical retrace vertical constant a32 is loaded into 32 bit register 954 and con-stant -a22 is loaded into 32 bit register 955 through the ~ input to multiplexer 948. Tllereafter, the select A
input to multiplexer 948 is set to logic 1 so that data may be communicated from 32 bit adder 964 through the A
input of multi.plexer 948 to the input of data register 955.
It will be appreciated that adder 960 receives inputs from the outpu~ of a31 reqister 950 as well as register 951 to present the sum of these inputs to the ~' main input of multiplexer 944. Similarly, adder 952 adds the output of a21 register 952 to the output of register 953. Numerator circuit 914 further includes an adder 966 which adds the output of register 951 to the output of register 956 and presents the sum back to the input of re~ister 956. A subtractor circuit 968 subtracts the output a register of 956 from the output of reyister 953 to generate a difference signal which is the solution to the numerator portion of equation 30 and which is presented to divider circuit 918. Adder circuit 964 adds the output of a32 register 954 to the output of register 916. The output of register 916 becomes the solution to the denominator portion of equation 30 and is also presented to divider circuit 918.
As a ,rame of reference pixel time intervals will be defined as a function of u and y corresponding to the vertical addresses, v(u,y), such that at the output of numerator circuit 914 and the output of denominator circuit 916 data for a given pixel address shall be valid at the occurrence of a corresponding pixel clock transition. For example, at pixel clock time to o~ data shall be valid for the pixel corresponding to vertical source address vO 0 and at pixel clock time 2,Z data shall be valid`for pixel source address v2 2 and so forth. It will be appreciated that at the vertical source address generator 912 verti~cal addresses are measured in terms of the target image pixel locations y while horizontal addresses are measured in terms of the first image pixel locations u.
- During the vertical retrace interval register 956 is cleared while constants are loaded into the other registers. Looking at equation 30, it will be observed that for the irst pixel clock time to o~ the variables u and y will both be 0 so~that the solution to v is a24 divided by -a2~. Since register 953 has been preloaded with constant a2~ while register 956 has been cleared dur-ing the vertical retrace interval, at time to o subtractor 968 generates the appropri~te numerator term a24 as the out-put of numerator circuit 914. Similarly, register 916 has been preloaded with the constant -a22 and outputs this term as the proper denominator term for equation 30.
Clock si~nal CK3 loads register 956 with the output of adder 966 at each pixel clock time. Thus, at pixel clock time to 0 register 956 is loaded with the sum of 0 ~ (1) (a34). The output of register 956 thus repre-sents the proper value of u = 0 and y = 1 for the first portion of the numerator of equation 30 at the second clock time to 1 Clock signal CK3 is active at this time and at each a~ditional pixel clock time so that the constant a34 stored in register 951 is added to the contents of register 956 at each pixel clock time. Since y is incremented at each pixel clock time, the next result is multiplication of a3~ by y by means for successive additions. That is, the output of the first portion of the numerator of equa~
tion 30 for y = 0, 1, 2, 3, 4 etc. is generated at the output of register 956 by adding to register 956 the value a31 u = a34 0 times, 1 times, 2 times, 3 times, 4 times, and so forth respectively. In a similar manner, the regis-ter 951 is clocked with clock signal CK2 during an intervalbetween successive line scans so that register 951 stores the constant a34 during the first line scan for line 0, the value a34 + (1) (a31) during the second linè scan for vertical line 1, a34 -~ (2) (a31) for the third line, vertical line 2, and so forth. The output of register 951 thus continually represents the term a31u + a34. This value is added to the contents of the register 956 at each pixel clock time so that the effect is the same as multiplying the output of register 951 by y as y is incre-ment~lly stepped throu~h successive pixel locations withina vertical line scan. Between each successive line scan the register 956 must be cleared or reset to reflect the new vertical line scan s~tarting position of y = 0.
This general concept of repeatedly adding or accumulatin~ a term at the pixel clock rate to accomplish multiplica~lon by y and repeatedly adding a term at a line clock rate to accomplish multlplication by u is used throughout the vertical source address generator line 12.
In the horizontal source address generator 908 a similar technique is used with successive additions at the pixel clock rate being utilized to accomplish multiplication by x and successive additions at the horizontal line clock rate ., ,.

o46-being utilized to accomplish multiplication by y.
It will be observed that the second term of thenumerator is generated at the output of register 953 which is initially loaded with a constant a24 before the beginning of each ~ield time and then clocked with signal CK5 at the vertical line clock rate between each successive vertical line scan so that the output of register 953 represents a24 + a21u. Similarly, the clock sisnal input to register 955, C~7, is activated to initially load the constant -a22 to register 955 and then to add the term a32 to the contents of register 955 at the pixel clock rate so that the output of register 955 represents the value a32y - a22. This is the denominator of e~uation 30. A
barrel shiEter 970 receives the successive 32 bit words of 1~ video data for successive pixel addresses and operates in conjunction with an exponent detector 972 to convert the numerator into a floating point form with the output of barrel shifter 970 providing 16 bits of data representing the mantissa of the numerator and exponent detector 972 outputing 8 bits representing the exponent of the numerator term. Conversion to the floating point representation eliminates the need to carry leading 0's and permits the 16 bit output of barrel shiter 970 to carry the most significant 16 bits of actual numerical data. In à
similar manner the barrel sh.ifter 974 and exponent detector 976 convert the denominator term to a floating point repre-sentation. A reciprocal circuit 978 receives the 16 bit mantissa of the tlenominator term and outputs the reciprocal thereo. One su~gested approach for accomplishing this reciprocation at the 70 NSEC pixel clock rate is to utilize the most significant 8 bits o the denominator term to address a conversion table storing reciprocal values and to utilize the least significant 8 bits of the denominator term to generate a linear interpolation between adjacent values in the reciprocal table. The reciprocated mantissa of tht-~ denominator is multiplies by the mantissa o the numerator in a hardware multiplier 980 and the product is presented to a barrel shi~ter 982. A subtractor 984 sub-tracts the exponent of the denominator from the exponent of the numerator to accomplish the division function and an adder 986 adds the difference to a bias term which is S stored in bias register 957 before the beginning of each field scan time. The A constants are selectively shifted for optimum utilization of the 32 bit capacity of numerator circuit 914 and denominator 916 prior to loading into the corresponding register 950-955 before the start of each field scan time, A constant corresponding to the number of shift places of these constants is loaded into bias register 957 for addition to the output of subtractor 98 to denormalize the exponent term to correctly represent the actual valLIe of the vertical address, This denormalized exponent term is output by adder 986 to barrel shifter 982 for a proper shifting operation to provide a conversion back to a 16 bit fixed point number representation at the output of barrel shifter 982. This output of barrel shifter 982 is the actual fi~ed point representation of the actual vertical address without adjusgment for pre-decimation. As explained above, barrel shifter 934 receives this vertical address and adjusts it by division of a selected power of 2 to provide an adjustment to accommodate a particular selected predecimated copy of the video data. It will be appreciated that the bias term stored in bias register 957 can be either positive or negative, depending upon the values of the terms from the a matrix. These values will vary with the particular manipulation of the video image which is being commanded.
An advantageous arrangement of the horizontal source address generator 908 for solving equation 31 i9 shown in Fig. 12. Horizontal source address generator 908 includes a numerator circuit 1002, a denominator circuit 1004, a divider circuit 1006 which may be identical to divider circuit 918, and a timing and control circuit 1008.
Horizontal source address generator 908 also includes an adjustment circuit 1010 which is substantially identical to the adjustment,circuit for vertical source address yener-ator 912 and converts the horiziontal source address, u, output from divider circuit 1006 into an adjusted horizo~-tal source address, uadj. Adjustment circuit 1010 aos generates the parameter magfactor and alpha for the hori-zontal interpolation decimation filter 906. The,numerator circuit 1002 includes registers 1012, 1014, and 1016 which are preloaded with data from the transform composer and factorizer 916 prior to a field scan time. The data is .
received over communication bus line 42. ~ multiplexer 1018 permits register 1016 to be loaded alternatively from an adder 1020 or from the communication bus 942. A regis-ter 1024 is selectively loaded with the output of an adder 1026. The numerator of equation 31 has the general form ~x ~ By + C where A = a~2 a34 - a24 a32; w 14 32 12 a34 and C = al2 a24 ~ al4 a22- During prefield scan time initiation the parameter C is loaded into register 16 while B is loaded into register 1014.
Clock signal CK21 is generated by timing and control cir-cuit 1008 at the horizontal line clock rate so that theoutput of register 1016 continually presents the value of C + By which is the last two terms of the numerator of equation 31. Register 1024 is clocked by clock si~nal CK23 from timing and control circuit 1008 at the pixel clock rate so as to be continually updated to generate the quantity Ax which is added to the quantity C + By by an adder 1028 to output the numerator portion of equation 31 to division at normali~ation circuit 1006.
~he denominator circuit 1004 has exactly the same form as numerator circuit 1002 except that the constant A, B and C are replaced by the constants D, E and F'where D = a21 a32 ~ a22 a31; E = al2 a31 - all a32 and F = all a22 ~ al2 a21. An adder 1020 outputs the denomina-tor,value to division and normali~ation circuit 1006.
Since denominator circuit 1004 is essentially identical to numerator circuit 1002 it will not be further described.
It is thus apparent that division and normalization r~

circuit 1006 ou'puts the denormali~ed horizontal source address u to the adjustment circuit 1010. Adjustment cir-cuit 1010 in turn generates signal uadj, the horizontal magfactor parameter, and the horizontal alpha parameter in a manner analogous to the vertical source address genera-tor 912 which has been described above.
Returning to Fig. 3, a vertical to horizontal transposing memory 900 i9 substantially the same as trans-posing memory 18. It requires only two field buffers and always writes vertically and reads horizontally.
A horizontal deinterlace filter 902 is normally inactive as deinterlacing is performed by filter 600. ~ow-ever in the event of horizontal reading from transposing memory 18, deinterlace filter 902 must perform the deinter-lace function. It requires only one filter componentwhich may be the same as either of the two filter compon-ents for deinterlace filter 600. _ ~ predecimation filter 904 receives an 8 bitstxeam of video data from deinterlace filter 902 and per-forms a predecimatlon operation substantially the same asthat performed by predecimation filter 700. Predecimation filter 904 requires only 3 line buffers.
Interpolation decimation filter 906 receives a two byte stream o~ information from predecimation filter 90~. It is substantially the same as vertical interpola-tion decimation filter except that for adjustments that result from receiving data at one-half the data rate of filter aoo.
The data rate through the system is reduced by or!e~half at the interpolation decimation filter 800. Up to this point the system is processing two fields at once to maintaill a composite frame available for interpolation.
Interpolation decimation filter 800 need only produce a single field each 1/60 of a second.
3S ~orizontal source address generator 90a imple~
ments a function defining the source address along a hori-zontal scan line as a function of the target pixel row and column location. Elorizontal target address counter 910 provides target position information in horizontal raster scan order. This enables processing of an r intermediate image stored in transposing memory 9Q0.
Vertical address generator 912 defines source addresses along a vertical scan line. Vertical target address coun-ter 914 provides target position information for the vertical scan into the intermediate transposing memory 900.
~ransform composer and factorizer 916 receives transformation commands and implements the equation shown in Table II at the end of this patent to produce transform parameters to control the horizontal and vertical source address generators 912, 908. ~hese parameters are calcu-lated by a data processor within factorizer 916 once every field.
Horizontal interpolator decimator filter 906 implements the function:

s(l~0) = ~ s (i-k) h ( G~ , 0, k) k=-4 where s is a source data value at integral sample points k is the integer part of the source address of the point to be interpolated 0 is the fractional part of the source address of the point to be interpolated h is the impulse response of the interpolating function. h is determined according to the equation , ~f (k-0) 8 sin ~ ~ (k-~) sin 8 h (~, 0, k) a ~rr2 ~k_0) 2 where ~ is a number between 1/2 and 1 representing the cutof of this lowpass response.
The horizontal address generator calculates the function listed in eq. ~31) where x is the target pixel number and Y is the scan line address. The vertical ad-dres~ generator calculates the function listed in eq. ~31).

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Referring now to ~ig. 13, a digital special effects system 1300 for color televlsion video signals includes an array processor 1302 for channel 1, as well as array processors 1304 for channels 2, 3 and 4 coupled to receive an input video signal for each channel. A
video switcher 1306 receives the transformed video signals for each of the four channels and outputs them in a co~nanded combination. For example, all four channels might be combined to form a single output on channel A, channels 1 and 2 might be combined to form output channel C while channels 3 and 4 are combined to form output channel D, or each transformed channel input to switches 1306 might be output having separate channels.
A panel processor 1308 is implemented as a Z8000 microcomputer based microprocessor system and operates in conjunction with the control panel 1310 to receive operator co~nands. These commands are communicated tb high level controller 131~ which is also a ~8000 microprocessor based processor and which has a multiplier 1316 coupled thereto to enhance its arithmetic capabili-ties. High level controller 1314 receives and stores sequences o~ transformation states from panel processor 1308. During operation, high level controller 1314 provides trar.sformation commands to a transform composer and factorizer 1318 at the field rate. ~ligh level controller 131~ outputs the stored com;nand states at the appropriate set times corresponding thereto and between the set times interpolates between the immediately precediny and succeeding states for each control parameter.
Hic~h level controller 131~ thus permits the digital special effects system 1300 to provide a smooth, controlled and repeatable special effect that could not be obtained by operator manipulation on a real time basis. By defining special effect states at the set points, and interpolating between the set points, a smooth image manipula-tion effect can be realized while defining only a relatively few set points and without the need for separately defining the special effect parameters at each field.
High level controller 1314 receives from panel processor 1308 and stores, data for a plurality of set points. Twenty-five or more set points are available and they will be referred to herein as knots.
At each knot thexe is stored a parameter specifying the state at that knot for each image manipulation variable.
There is also stored at each knot a number indicating the relative time between know and a next knot. Initially, this number represents a number of field times. ~owever, an overall effect run time can be modified. The interpola-tion equation for each parameter is a function of a single independent variable. When an effect is run, the value of this single variable is passed to the high level controller 1314 from the panel processor 1308. The value of this vari- _ able is modified in each field. It is by adjusting the amount of this modification that the overall run time of an effect is controlled.
The high level controller 1314 provides to trans-form composer and factori~er 1318 for each field time, data commanding each variable for each access of the variable for the given field time. At the knots, the stored param-~5 eler conditions are commanded. Between knots, each param-eter is interpolated between its state at the preceding and succeeding knots with a third degree polynomial e~ua-tion, the coefficients of which are computed in terms of the value of the parameter at the current and succeeding knots and the value of the slope or first derivative of the parameter with respect to time at the current and succeeding knots.
The slopes at each knot for each parameter are determined by first testing to see if the value is changed relative to the immediately succeeding knot. If not, the slope is set to zero and the parameter is assumed to be constant between the current and succeeding knots. In the --s~i--event that the parameter changes, the cubic spline interpo-lation technique is utilized to obtain the slope. A
discussion o~ cubic spline interpolation is provided by Carl deBor, A Practical Guide To Splines, pp. 49~57, Springer~Verlag (New York, 1978). In addition, the slope for each parameter is set to zero at the first and last knots of an effect.
The use of knots with interknot interpolatîon permits a user to specify a highly complex and continuously changing video effect by merely specifying desired video transformation states at a relatively few key knot points and without need to specify each field transformation condi-tion. Furthermore, pre~establishment of exact states and times provides a precision far superior to that which could be obtained through real time operator control while the specification of the overall run time permits the effect to exactly match a given time slot such as 15, 30 or 60 second commercial. This preprogramming also permits a plurality of video channels to be precisely synchronized.
Unless otherwise specified, a parameter at a given knot assumes the value of the corresponding parameter at the preceding knot unless the current knot is the first knot in which case the value of the parameter is set to its nominal value and the time between knots is assumed to be zero. In practical applications it may be desixable to implement two adjacent knots with zero time between them.
For example, it may be desirable to implement an image rotation over a given time interval and to then implement a sudden and stepwise change of the axis of rotation with-out a corresponding sudden change in the video image.
This could be implemented for example by specifying first , and second knots with a given gradual rotation function between them. A third knot could then be established at the same time as the second knot by specifying zero time for the second knot with a translated axis of rotation~A smooth transition could then occur about the new axis of rotation between the third knot and a fourth knot establishing a terminal or intermediate condition of rotation.
~ he channel 1 array processor is generally similar to that shown in ~ig. 3 with certain modifications being implemented which have been found to reduce cost without seriously degrading transformation quality. In particular, the I and Q chroma components of the video signal are sampled at 1/4 the approximately 70 nanosecond sampling rate of the Y or luminance component. This enables certain economies such as less expensive, lower speed integrated circuits to be utilized as well as less data storage capacity so long as care is exercised to assure consistency of the processing of the different video components.
The channel 1 array processor includes a luminance or Y proceQsing system 1320, a first chrominance or I processing system 1322, and a second chrominance or Q processing system 1324. A vertical source address generator 1326 and a horizontal source address generator 1328 provide common addresses to the Y, I and Q processing systems 1320, 1322 and 1324 respectively. The address generators 1326 and 1328 may be substantially identical to the corresponding vertical and horizontal source address generators 912 and 908 as shown in Fig. 3.
A horizon~al-to-vertical transposing memory 1330 includes five field stores which operate on a cyclical rotating basis with one of the stores receiving and storing incoming video luminance data while the other four stores output the four most recently received fields of video data on output paths A, B, C and D with the most recent field appearing on path A and the fourth most recent field appearing on path D. The individual field buffers of memory 1330 are written into as data is received in a normal horizontal raster scan order and may be read in either the same order or alternatively in an order providing a vertical raster scan of the data from top to bottom and from left to -56~
right. During normal operation data is written into memory 1333 horizontally and read out vertically and this mode will be assumed unless otherwise specified.
A deinterlace filter 1332 receives the four streams of data from transposing memory 1330 and continu-ously converts the most recent field to a deinterlaced complete frame of data by outputing a second field of data which completes the alternate missing lines of the most recent field of data. Deinterlace filter 1332 includes a motion detector which causes the second most recent field of data to be output as the intermediate lines of the most recent field in the absence of detected motion. If motion is detected, the average of the pixel locations in the most recent field imrnediately above and below a given intermediate line of the most recent field is used to define the intermediate line.
This interpolation or averaging of data between lines of -' the most recent field has the effect of decreasing the spatial resolution of the output frame of video data but eliminates a double image effect which occurs when two successive fields of data are combined to form a single frame of data which is deemed to occur or ha~e occurred at a single instant in time. In contrast to the arrangement of Fig. 3, deinterlace filter 1332 operates whether ox not H to V transposing memory 1330 is operated in a transposing mode. It will be recalled that the nontransposing mode is utilized for rotations about the Z axis of 45 to 135 and 225 to 335.
Predecimation filter 1334 receives the video data from deinterlace filter 1332 and makes available to vertical interpolation decimation filter 1336 a full size copy thereof as well as 1/2, 1/4 and 1/8 sized copies thereof.
A vertical interpolation decimation filter 1336 receive~
an appropriate sized copy of each field of video data Erom predecimation filter 1334 and responds to vertical source addresses from vertical source address generator 1326 to either select vertical data points or interpret between data points in the vertical direction to output a video image which has been transformed in the vertical dimension.
Vertical interpolation decimation filter 1336 utilizes the full size copy of each field when specified magnification in the vertical direction results in an output image greater than the incoming image, the same size as the in-coming image, or greatex than 1/2 the size of the incoming image. The half size copy is used for 1/4 to 1/2 sized images, the 1/4 sized copy is used for 1/8 to 1/q sized images and the 1/8 sized copy is used for images less than 1/8 normal size. In the event that transposing memory 1330 is oeprating in a non-transposing mode, vertical interpola-tion decimation filter 1336 treats the image as though it had been vertically scanned even though it in fact was horizontally scanned. Operation is thus substantially the same for both modes of operation except that-an image which has been truly vertically scanned will have only 425;pixels per line while the horizontally scanned image will have .768 pixels per line in the NTSC format. Filter 20 1336 may be implemented substantially as filter 800 (Fig.
2) although an economically advantageous arrangement for the lower bandwidth choma components is described below in conjunction with Fig. 19.
A vertical-to-horizontal transposing memory 1328 receives the partially transformed image array data from vertical interpolation decimation filter 1336 and imposes a vertical-to-horizontal transposition.
Data is read into transposing memory 1338 in a vertical raster scan order and read out in a horizontal raster scan order at a single field rate of about 70 ~ISEC per pixel.
A predecimation filter 1342 may be implemented substantially identically to filter 1334. It recei~es data from U to H transposing memory 1338 and outputs 35 both a full size copy and 1/2, 1~4 and 1/8 sized copiès to a horizontal interpolation decimation filter 1344.
Horizontal interpolation decimation filter -~8-1344 responds to horizontal source addresses from horizontal source address generator 1328 to complete interpolation decimation filtering in the horizontal direction to output the luminance component of the transformed video image. Horizontal interpolation decimation filter 1344 may be implemented substantially identically with vertical interpolation decimation filter 1336.
An advantageous arrangement of control panel 1310 is illustrated in Fig. 14 and includes a three axes rate control joystick 1410, two status displays 1412, 1414 pro-viding feedback to a panel operator, and several groups of pushbutton or key switch controlsO By utilizir.g the key switch groups to s~ecify modes, channels, and functions, a relatively complex set of controls can be implemented with a single three axes rate-control joystick 1410. ~ith the joystick in the return or neutral position, no change of _, status occurs. With the joystick pushed to the right the selected X parameter is increased and continues to increase so long as the joystick is held to the right. The farther to the right the joystick is moved the faster the parameter increases. Similarly, the parameter decreases as the joy-stick is pushed to the left. The Y and Z axes operate in a similar manner. Motion of the joystick upward towards the top of the ~ig. 14 as shown represents an increase in the Y axeis parameter while motion downward commands a decrease. For the Z axis control, counterclockwise rota-tion commands an increase in the parameter while clockwise rotation commands a decrease. Wl~ile electrical connections have been omitted for clarity, it will be appreciated that the joystick as well as each of the key switches and the status displays is connected for communication with the panel processor 1308.
A channel select group of switches 141a permits selection of one of four available channels for control of the associate video image. The last channel key selection determines the channel to which the transformation co ~nds ~ql~2~l~

pertain. A clear group of switches 1420 permit the clear-ing of selected axes or alternatively a master clear for all axes back to the normal or input video state for a currently selected parameter. For example, if positioning ~translation) has been selected and the joystick moved to the right to cause the video image to move to the right, actuation of the clear X key will cause the image to return to its normal location. A mode select group of keys 1422 determines the overall operating mode of the transformation system and also facilitates the implementation of special features. Selection of the program key places the system in the program mode to permit the entry of transformation commands at each of the available knots starting with the first knot. Actuation of the rightward pointing arrow causes the selected knot number to be incremented while selection of the leftward pointing arrow causes the current knot number to be decremented.
Actuation of the run key places the system in a run mode with a stored sequence of knots being executed.
Actuation of the test key places the system in a test mode of operation in which diagnostic programs within the various microprocessor subsystems test for and indi-cate error conditions. Actuation of the duration key followed by one or more keys from a number key group 1~24 specifies a total time in fields for an operating sequence.
In program mode, the duration function specifies the transition time in field from the current to the succeeding knot. A pair of keys labeled store effect and recall effect permit an entire effect or sequence of knots to be stored on a floppy disck and then recalled. The number group 1424 also includes enter and recall keys. This enter ~.
key permits a selected number to be entered in storage and terminates number entry. The recall key zeros the number being entered to allow erasure of errors.
~ parameter selection group 1926 determines the meaning of the various axes of the joystick. An aspect/
skew key causes the video image to be selectively enlarged or decreased in size in the horiziontal and vertical directions in xesponse to motion of the joystick in the X
and Y direction respectively. At the same time, the Z
axis control of joystick 1410 may be utilized to introduce a skewing of the video image. That is, the top of the image is translated relative to the bottom of the image so as to ,urn squares into parallelograms.
The axis select key positions in three dimensions the point about which image rotations occur. When this function is selected, a cursor is displayed to assist the user in positioning the point of rotation. All rotations occur about one of three mutually perpendicular axes pass-ing through this center of rotation.
The locate key permits positioning in three dimensions of the incoming image.
A blur key permits the video image to be selectively defocused. Only the 2y or ~ axis control of joystick 1410 is effective upon actuation of this key.
~ position/size key permits horizontal and vertical translation of the output video image relative to the input video image using the X and Y axes while the Z axis control of the joystick controls the size of the output video image relative to the size of the input video image.
.~ rotate key permits control of three dimensional rotations of the image about the center point. Each of the Joystick axes controls a corresponding axis of rota-tion. Vertical movement controls rotation a~out the X
axis, horiziontal movements controls rotation about the Y
axis and rotation of the joystick causes rotation of the image about the Z axis. Any reasonable number of rota~
tions may be specified. For example, zero rotations may be specified at one given knot with ten rotations being specified at the next knot. The interpolating capability of the high level controller 1314 will then cause ten rotations to occur between the given and the next knot.
Multiple rotations are accomplished by actuating the l9 joystick to cause rotation about a desire axis and main-taining the joystick actuated until the desired number of rotations have been countedO
A depth of perspective key is effective only with the Z axis of the joystick to control the rate at which objects become smaller as they move rearward of the plane of the initial video image or larger as they move forward of this plane, as by rotation about the X axis. mhis can be visualized by imagining the video image rotating about an X axis at the bottom of the image. As the image rotates away from the viewer the top portion of the image becomes farther from the initial plane and hence smaller. The depth of perspective key permits control over the rate at which the image hecomes smaller relative to the ansle of rotation.
A L~M HUE SAT key permits specification of the background color of the output video image in regions not occupied by the initial image. For example, in the above perspective rotation example, as the top of the image rotates away from the plane of the viewing screen, the top of the image becomes smaller and the upper right and upper ~ -left hand corners of the viewing screen are no longer occupied by the initial image. The LUM ~UE SAT key per-mits the Y, Z and X axes respectively of the joystick 1410 to control the corresponding components of the background video image. This control over the background image can be especially useful when used in conjunction with a switcher 1306 which is programmed to respond to color or luminance keys to substitute video data of one channel for video data of another channel when putting together a com-posite image for a single channel.
A programming group of keys 1~28 facilitates the programming of the various knots fGr a given video effect.
Actuation of an insert knot key permits a new knot to be in serted between the current and previous knots while the remove knot key similarly permits a preprogrammed knot to be deleted from a sequence of knots. Actuation of a save knot key causes all of the parameters at a given knot with exception of the rotations to be stored for later recall by actuation of the recall knot key. This save and recall feature is useful where the parameter state at a given knot is to be duplicated at a subsequent knot. Some or all of the parameters can of course be changed after duplication.
Actuation of the pause knot key causes execution of the - effect to halt at the current knot during run mode and await further user commands. A loop key actuation followed by selection of a duration number through the number key group 1424 causes a loop back from the last knot to the first knot of an effect. The duration of the transition from last to first knot is taken to be the number entered by the user after selecting the loop key. The loop back causes the intermediate sequence of knot states to be con-tinuously and sequentially executed until the actuation of the stop key terminates the continuous loop sequence.
A freeze update rate key permits the specifica-tion through the number key group 1424 of the number of fields that a frozen video image will be held before being updated. This is, if the freeze update key is followed by the number 8 key, on every 8th field two new video frames will be sampled and held until the next update time.
In effect, the horizontal-to-vertical transposing memory 1330 is inhibited from receiving a new in?ut video field until the specified number of input video fields have occurred.
As an example of entering an effect for a given channel, assume an example in which the full size picture is to shrink to one-half size at midscreen, rotate 360 about the Y axis with perspective and then return to full size. After selecting the desired channel with switch group 1418, for example channel 1, the program switch in group 1422 is actuated to set all conditions to an initialized state yielding a full size picture, without any manipulation supplied. This initial picture condition is now the first knot point of the effect. The save knot Z~3 key in group 1428 is now actuated to preserve the initial condition for later use at the end of the effect where the effect is to be returned to the initial condition.
A duration time is now specified through the number keyboard 1424 to define the time to the next or second knot, For example, the number 600 will cause the first knot time to be 600 field times or ten seconds.
During this first 10 second interval the "zoom" from,full size to half size will occur. The knot number is dis-played on status display 1412 and as the knot time dura-tion number is entered it appears on status display 141~.
In general, the status display reflects the present knot as well as the state of a selected parameter. The forward or rightward pointing arrow in group 1422 is now actuated to cause incrementing to the next or second knot state.
Actuation of this key closes the programming for the events of the first knot and opens the second ~not for _, programming.
The 2D position size key i5 now actuated from group 1426 and the joystick can now be used to position the picture on the screen according to the XY movements o 'the joystick or can change picture size according to move-ment of the rotating knob atop the joystick in the Z or axis. For the present example the XY position is to remain constant while the joystick knob is rotated until the picture reaches one-half size. A duration time is now specified for the time to the next or third knot, which in this case will specify the time of the picture rotation.
The duration button is actuated and a time such as 300 3~ field times or 5 seconds is entered. ~1ith the programming of the second knot complete, the forward key is again actuated to close the second knot and open the third knot.
The third knot is to define a,360 rotation of the half-size picture about its Y axis with some three dimensional perspective effects added. The rotate key in group 1426 is now actuated to make the joystlck active in rotatin~
the picture about any of its three axes. In the present example the joystick is moved in a horizontal direction to the right to rotate the picture about its Y axis Moving the joystick in a vertical direction would cause rotation about the X axis while rotation of the joystick knob in the Z or 0 axis would rotate the picture about its Z axis.
In the present example, the joystick is moved to the right and held utnil the image has rotated through a sufficient angle to permit observation o the perspective efect, for e~ample 30-45~. It should be appreciated that the rota-tion is required since the perspective ef~ect is notobservable until the image is rotated out of the plane of the viewing screen. ~7ith the image partially rotated, the joystick is released and the depth of perspective key is actuated in group 1426. The joystick ~ ~ontrol is now active in controlling the amount of perspective desired and the desired amount of perspective is added to the picture. The rotate ~utton is now again actuated and the picture rotation through the desired full 360 is completed by holding the joystick to the right until the rotation has occurred as viewed on the screen. A duration time is now specified for knot 3 by actuating the duration key and a set o~
number keys within group 1424. In this example let us assume that the time is entered as 600 field times corresponding to 10 seconds. In this case the 10 seconds will specify the time to knot 4 which is the unity or unaltexed pictuxe state. Thus during the final 10 second interval the picture will zoom back to full size.
The advance arrow key is now selected to close knot 3 and open the final ~not 4. The recall knot button is actuated from programming group 1428 to store the previously stored initial full size or unity paxameters in the current knot point 4. The efect is now complete and can be stored on disk by selecting the store effect button from the Jnode control 1422. Further editing of the effects in terms of durations and manipulation changes or additions can also be made by returning to additional ~nots, inserting additional knots at selected locations, or deleting knots.
Alternatively, the total run time of the total effect can be modified without changing the relative time durations between each knot point. For example, the commanded run time of the effect is 25 seconds. ~owever, the total run time can be easily increased to 30 seconds, as for a 30 second commercial by actuating the duration key in group 1422 and then entering 1800 through keyboard 1424. Effectively each of the individual ~not times is consequently increased by 30/25. That is, the first knot time will be effectively increased from 600 field times to 720 field times, the second knot point will be effectively increased from 300 field times to 360 field times and the third knot will be effectively increased from 600 field times to 720 field times. This will result in a total run time for the effect of 30 seconds as commanded.
Referring now to Fig. 15, the horizontal-to-vertical transposing memory 1330 includes a distributor 1502, Eive field stores 1510-1514 labeled 0-4, a 5:4 multiplexer 1520, and an address and control circuit 1522 connected to provide address and control signals to the other components of transposing memory 1330.
Although the field stores 1510-1514 are shown separately for the luminance component, they advantageously function synchronously and with common addressing the I and Z
chrominance component field stores as explained herein-after.
Distributor 1502 receives a component of standard color television video data such as the y or luminance component as an input and stores successive fields of the input data in successive ones of the field stores 1510-1514 on a cyclic basis~ After all f~ve field stores have been filled distributor 1502 continues to direct the incoming field of data to the field store storing the oldest field of data. As a result, the five field stores 1510-1514 always store the most recent four fields of data while the fi~th most recent field of data is overwritten by incoming new data.
~ lultiplexer 1520 receives the outputs of the five field stores and in turn outputs the data from the four most recently stored fields on four output lines on a cyclic basis such that the most recent field is output on path A, the second most recent field is output on path B, the third most recent field is output on path C, and the fourth most recent field is output on path D. The four most recent fields of video data are thus made available on a continuous basis to deinter-lace filter 1332.
As with horizontal to vertical transposingmemory 18, transposing memory 1330 always receives data for storage in a horizontal scan direction. In a normal mode of operation the stored fields of data are transposed and output in a vertical scan direction and in a special mode of operation the memory 1330 may operate in a nontransposing mode to output the video data in a horizontal scan direction just as it has been read in.
An example of an ad~antageous arrangement of the memory 1600 for field store 0 corresponding to store 1510 in Fig. 15 and corresponding stores for the I and Q processing systems 1322, 1324 is illustrated in Figs, 16 and 17. The memory for the luminance signal component contains eight memory components designated Y0-Y7. Each of these components is 32 words deep by 1 ~, pixel or 8 bits wide. The memory 1600 operates on a 1~0 nanosecond cycle storing two luminance pixels at a time. During each memory cycle an early pixel is stored in one of memory components Y0, Y2, Y4, or Y6 while a next subsequent or late pixel is stored in one of four late components Yl, Y3, Y5 or Y7. Prior to 1~?~

writing into memory a first luminance pixel of data is stored in Y input early register 1602 in response to the Y input early strobe signal YIES. And the following pixel is stored in Y input late register 1604 in response to the Y input late strobe signal YILS. During this same two pixel time period the row and column addresses are strobed into the memory components Y0-Y7 to prepare the memory for immediate writing of the two pixels of data upon receipt of the late pixel by Y input late register 1604 Because the cycle time for economically a~ailable memory components is longer than 140 nanose~onds, the memory components are utilized in a four phase rotating configuration. During a first 140 nanosecond memory cycle phase 1 signals cause the storage of data in components Y0 and Yl. During a second phase data is stored in components Y2 and Y3, during a third phase data is stored in memory components Y4 and Y5 and during a fourth phase data is stored in memory components Y6 and Y7. For the fifth cycle the address inputs are incremented and the rotating cycle repeats itself beginning with modules Y0 and Yl storing information during phase 1. It is thus seen that for each of the memory modules a time period of 4 x 140 nanoseconds or 560 nanoseconds is available for each data access cycle and this is well within the capabilities of economically available memory chips.
During readout the memory components are operated in substantially the same way except that 30 during a 140 nanosecond memory cycle data from one of the early memory components Y0, Y2, Y4 or Y6 is stored in Y output early register 1.606 in response to Y output early strobe signal YOES and data from one of the late modules Yl, Y3, Y5 or Y7 is stored in Y output late register 1608 in response to Y output late strobe signal, YOLS. Subsequently, the two pixels of data are serialized to make them available sequentially on a Y

2~1~

output signal line YO by first enabling the output of Y
output enable register 1606 with a Y output early enable strobe signal, YOEES and then 70 nanoseconds later enabling the output of Y output late register 1608 with a Y output late enable signal YOLES. During readout the memory components Y0-Y7 continue to operate on the same four phase rotating basis. If readout is to be in a row scan direction, operation is substantially identical to writing except that the memory components receive a read command rather than a write c~ ~nd.
The memory arrangement shown in Pig. 16 further includes two memory components I2 and I7 for the I chrominance video signal component and two memory components Q2 and Q7 for the Q chrominance video signal component. Since the chrominance signal components are sampled at one-fourth the rate of the lllmin~nce components, only two memory modules are required for each of the chrominance signal components compared to eight memory modules for the luminance signal components. The I and Q chrominance components operate exactly in parallel except for the data which is received or read out and fuxther, the I2 and Q2 components operate in parallel with the Y2 luminance memory component while the I7 and Q7 components operate synchronously in parallel with the Y7 luminance memory component. This synchronous parallel manner of operation permits the chrominance memory components to share the address and timing signals which are generated for the luminance components.
Because the I2 and Q2 components are synchronized with the phase two Y2 component while the I7 and Q7 components are synchronized with the phase four Y7 memory component, the effect is that each of the chrominance field stores appears to operate as two 1120 nanosecond memories phased 180 degrees apart. In any event, the net result is that one pixel of I and one pixel of Q chr~ in~nce data is stored for each fourth pixel of luminance data.
It is essential for proper operation of the field store I

0 that the chrominance memory components be synchronized with the proper luminance memory components so that in both the horizontal scan and vertical scan readout modes chrominance data will be output at a uniform rate at one-fourth the luminance 70 nanosecond rate. That this goal is accomplished can be seen by looking at Table II.
Table II is an address table illustrating the manner in which data is stored in the Y memory components.
Although not separately indicated for each chrominance component, it will be appreciated that for each pixel of luminance data stored in Y memory components C2 and C7, correspondiny pixels of chrominance data will be stored in chrominance memory components I2, ~2 and I7, Q7 as indicated collectively for the two components by the chrominance pixels C0,0; C0,1, etc. at the two righthand columns of the table.
~ or synchronizing and timing purposes it is convenient to sometimes start operations prior to the initial address storage location. Therefore, in order to avoid the recognition of negative addresses, data is ~ -stored beginning with address location 16 x 112 =
1,792. As data is written into field store 0 in a horizontal row scan mode, data for pixels P0,0 and P0,1 arrive sequentially on Y input line YI and are stored in Y input early register 1602 and Y input late register 1604 respectively. As these first two pixels of data are written into register 1602 and 1604, the row and column addresses are strobed into phase 1 memory components Y0 and Yl. As the first phase 1 memory cycle continues pixels P0,2 and P0,3 are sequentially strobed into Y
input early register 1602 and Y input late register 1604 respectively. A phase 2 memory cycle then begins with the two pixels being stored respectively in component Y2 and Y3. The process continues through the first raster scan line with the memory phases being recycled back to phase l to store pixels P0,8 and P0,9 in memory address location 17 x 112 = 2016 after pixels P0,6 and P0,7 are stored in components 6 and 7 at address 1792 during phase 4. An address map allocates 112 x 8 = 896 pixels for each horizontal scan row in memory module address space. This is sufficient to accommodate the 768 pixels in an NTSC horizontal scan line as well as the greater number of pixels in a PAL scan line without changing the memory design. It will be appreciated that I and Q chrominance pixels are simultaneously stored along with luminance pixels P0,2, P0,7, P0,10 and so forth. After all pixels for the first raster scan row have been stored, preparations are made during the horizontal retrace interval for storage of the second raster scan row. Phasing is returned to phase 1 regardless of which phase stored the last pixel of the first row. However, field store sequencing begins one pixel time early for row 2. As a result, the Y input early register 1602 is strobed one pixel time before actual video data is available and is loaded with don't care information designated X in Table II. 70 nano-seconds later Y input late register 16 is strobed to receive data for pixel 1, 0. Data storage thereafter continues in a normal manner with the chr-- ;nAnce portions of the field store storing data at phase 2 and phase 4 operating times.
As data for the third raster scan row is received, the timing cycle begins two pixel times early so that don't care data is written into memory components Y0 and Yl during phase time 1. During phase time 2 pixels P2,0 and P2,1 are written into components Y2 and Y3. During the same phase 2 chrominance pixel 2,0 is written into chrominance memories I2 and Q2. This same manner of operation continues with the memory starting time being advanced by one pixel time for each additional row until the eighth raster scan row has been stored.
As the ninth raster scan row ~ro~ 8) is received the address inputs are incremented to 2,688 and the starting times are returned to the initial timing relationship so that only valid plcture data is stored with pixels P8, 0 and P8, 1 being stored in modules Y0 and Y1 during time phase 1. The time staggering process then repeats itself with one pixel of don't care data being written at the beginning of row 9, two pixels of don't care data being written at the beginning of the tenth row and so forth.
The staggering of the starting times on a modulo 8 basis for sequential raster scan rows during reading assures that pixels of video data for different rows of a single column are stored in the eight memory modules on a module 8 staggered basis so that they can be sequentially available during readout in a column scan mode. Por example, durin~ the first vertical scan memory cycle time address 1792 is provided to Y input early module Y0 while address 1904 is provided to Y
output late module Yl. During the phase 2 memory cycle ,, time addresses 2016 and 2128 are provided respectively to the early and late modules with pixel P2,0 being read from module Y2 and pixel P3,0 being read from module Y3. During the next phase time pixels P~,0 and P5,0 are read and so forth. Upon reading the seventh and eighth vertical column pixels, the cycle repeats itself as there is a return to phase 1 to read pixel P8,0 from module Y0 and pixel P9,0 from module Yl. Por the second column memory operation begins one pixel time early just as for the second row. As a result, during the first phase 1 cycle time don't care information is read from module Y0 while pixel P0,1 is read from module Yl. During the following phase 2 time interval pixel Pl,l is read from module ~2 while pixel P2,1 is read from module Y3. This process continues within a modulo 8 recycle manner until all data for column l has been read.
Reading of the third column, which is designated column 2, then begins two pixels times early with don't care data being read from modules Y0 and Yl during phase time 1 with pixels P2,0 and P2,1 being read from modules Y2 and Y3 during phase time 2. It will be appreciated that the proper synchronous phasing of the chrominance storage components at phase times two and four will cause a chrominance pixel to be read for every fourth luminance pixel to maintain the proper chrominance one-fourth sampling rate during both row scan and column scan memory operations.
At the same time, the selected field store configuration makes hardware implementation of the address and co~trol circuitry relatively easy. The phase times are merely reset to one at the beginning of each row or column scan readout and then recirculated on a modulo 4 basis (modulo 8 basis for the memory components since they are operated two in parallel).
2y starting memory operations for each successive row or column one pixel time earlier on a modulo 8 basis, the staggering of the pixel storage locations is auto-matically accomplished to permit proper sequentialaccess of the memories for stored pixel data on either a row scan or a column scan basis.
One slight complication which must be accounted for is the crossing over of an address boundary at staggered phase intervals during readout in a column scan mode. When reading column 0, each successive pixel occurs in a successive module location in a corresponding memory address location for a row group of addresses. That is, each successive address is incremented by 112 to provide addresses 1192, 1904, 2016, 2128, 22~0 and so forth~ As column 1 is read out, however, this successive incrementing of the addresses by 112 is proper only until pixel Pl,7 must be read from module Y0 at address location 1905 instead of location 1904. This is a departure from the straight-forward addressing scheme which requiras an incrementing of the otherwise normal address for reading the 7th, .~

15th, 23rd, and sc forth pixels. Similarly, for column 2, the address must be incremented for reading the 6th and 7th, 14th and 15th, 22nd and 23rd etc. pixels. For column 3, the address must be ineremented for the 5th, 6th, and 7th pixels, the 13th, 14th, and 15th pixels, the 21st, 22nd and 23rd pixels and so forth. It is thus seen that for each progressive column the inere-menting of the address must begin one pixel time earlier on a modulo 8 basis and eontinue until an eighth, sixteenth, twenty-fourth, ete. pixel has been read. No inerementing is required for eolumns 0, 8, 16, ete. As deseribed below, this staggered inerementing is aeeom-plished with the address and eontrol cireuitry by establishing an increment signal during vertical scan memory operations which is set progressiitely one pixel time earlier on a modulo 8 basis for sueeessive eolumns and always terminated at a modulo 8 address boundary.
Referring now to Fig. 17, there is shown the ,, address and timing circuitry 1700 for field store 0.
It will be appreciated that field stores 1-4 are substan-tially identical to field store 0. The address and timing eireuitry 17Q0 includes a timing generator 1702, timing and control eircuitry 1704, a 7-bit horizontal address eounter 1706, a 9-bit vertieal address eounter 25 17Q8, and an address map cireuit 1710. Synehronization of the field store with incoming data is provided by a line blank elock signal which goes high shortly after the last pixel of each vertieal or horizontal sean line and goes low again shortly before the first pixel time of the next sean line and a vertieal clock signal, V
CLOCK which produees a one pixel wide pulse immediately after the last pixel of a field.

Consequently, at the end of a field signal V CLOCK asynchronously resets a 3 bit modulo 8 counter 1720 during the vertical retrace interval following each field. The zero output is communicated to a 1 read only memory 1722 which responds by outputing a 4 bit count to the 4 load inputs to a presettable counter 1724, which responds to a 70 NSEC pixel rate clock signal. Counter 1724 is loaded with count 5 in response to signal Line Blank CK until this signal terminates shortly before the beginning of each scan line. Counter 1720 then immedi-ately begins counting toward 15. At count 15 the terminal count output generates a timing and control enable signal T&C Enable which disables further counting until counter 1724 is reloaded during the next line blank interval.
The termination of the line blanX signal is synchronized with the incoming video data such that the 10 pixel clock times required to count from 5 to terminal count 15 equals the system pipe line delay times required by~timing and control circuit 1704 before activating 20 field store 1600 with register strobe signals and phase 1 row and column address strobe signals. Store 1600 is thus properly synchronized to receive and store the first and subsequent pixels of data for the first scan line.
After the end of the first scan line signal line blank clock goes high to increment counter 1720 tocount 1 and load counter 1724 with count 6 which is now output by ROM 1722 in response to count 1 from counter 1724. Because counter 1724 starts 1 count higher its terminal count output is generated one pixel time sooner and memory 1600 begins operation one pixel time prior to valid data. If writing, don't care data is written into component 0 of memory 1600. If reading, the output data is simply ignored because it arrives prior to the time at which valid video data is recognized.
Following the second scan line counter 1720 is again incremented and ROM 1722 causes a count of 7 to be loaded into counter 1724 so that two pixels of don't care data are written into or read from emory 1600 prior to the valid data time. This manner of operation continues until counter 1720 is incremental to count 7 prior to the 3th scan line (scan line 7 when starting at 0) to ca~se 5 count 12 to be loaded into counter 1724. This causes 7 pixels of don't care data to be written into or read from memory 1600 with the first valid pixel then occurring in association with modeul 7 during phase 4. After the 8th scan line and before the 9th scan line, counter 1720 is clock, causing it to overflow to count zero and repeat the above cycle.
This process of starting one pixel time earlier for each scan line on a repeatable modulo 8 ~asis auto matically accounts for the stepping or staggering of memory locations required for transposition on a high speed basis whether reading or writing, in a vertical scan mode or a horizontal scan mode. The operation of the address counting and timing circuitry remains ~' essentially the same as timing generator 1702 provides the accounting for the required stepping of starting address locations.
Because the 8 modules of field store memory 1600 store 8 pixels for each address location, horizontal address counter 1706 is incremented in a horizontal direction once every eighth column position. It is clocked by signal CK~I which in the horizontal mode occurs every 560 NSEC at 1/~ the pixel rate. In the vertical mode the signal CKH is derived as the Line 4-7 output of counter 1720 which means that counter 1706 is incremented after every eighth vertical scan line. This is the equivqlent of every eighth pixel in a horizontal scan ~.
mode. Horizontal address counter 1706 has its D inputs CK connected to logic zero and its load input connected to provide reset to zero in response to signal LDH which is V ClOCX in the vertical mode and Line Blank CK in the horizontal mode. Hence, in the vertical mode horizontal counter is reset at the end of each field and in the horizontal mode it is reset after each line.
Vertical address counter 1708 is a 9 bit counter having its clock input connected to signal C~V, which is derived from the 70 nsec Input Hold CR signal in the vertical mode and from the Line Blank CK signal in the horizontal mode, It is thus incremented for each new horizontal line (vertical position) regardless of the mode.
A signal LDV causes counter 1708 to be periodi-cally reset with the four least significant bits beingderived from ROM 1722 and the more significant bits being reset to zero. At the beginning of a field vertical counter 1708 is preset to 16 to provide a small offset which avoids the use of negative numbers under some cir-cumstances. In the horizontal mode ~OM 1722 responds toan address input signal H Mode to always preset counter 1706 to count 16.
However, in the vertical mode the preset state of counter 1706 depends upon the column count stored by counter 1720. For the first column vertical address counter 1708 is preset to 16. For the second column it is preset to count 15. It will be recalled that for the second column in the vertical mode the fi--st pixel represents don't care data. Since counter 1708 is clocked at the pixel rate, by the time the second pixel arrives (representing the first pixel of video data), vertical address counter 1708 has been incremented to starting address count 16.
This manner of operation continues in the vertical mode with the counter 1708 being preset to incre-mentally smaller counts for each new vertical scan line until count 9 is loaded before the start of the ei~hth scan line. By the start of the 9th scan line, counter 1720 recycles to zero and the process repeats.
An address map 1710 receives the counts for counters 1706, 1708 and corrects for the failure of the number of pixels in a line to fall on a modulo 2 boundary . .
.:~
.

in order to reduce wasted address space. The address map if readily implemented with adders to produce the func-tio~ address = H/8 + 128V - 16V + C = ~1/8 ~ 112V ~ C. r The multiplications fall on modulo 2 boundaries and can 5 therefoxe be accomplished with binary shifts. The C or carry input is connected to occasionally increment the least significant address bit to accommodate a special situation in the vertical mode. The spacing of 112 in the vertical direction allows 8 x 112 or 896 pixels per 10 horizontal scan line. This is sufficient for the PAL
standard as well as NT5C.
The carry input is generated by the Q output of a flip-flop 1726 which has the D input connected to sisnal H ~lode, the preset input connected to the output of a decoder 1728, the clock input connected to a 560 nsec (8 pi~el time) clock signal which is synchronized with the starting address for each scan line memory operation, whether don't care or actual video date.
~lip-flop 1726 is active only in the vertical mode and 20 remains inactive in the hori~ontal mode.
In the vertical mode flip-flop 1726 is loaded with logic zero to generate a carry every eighth pixel starting with the beginning of storage. It is preset to terminate the carry input every eighth pixel as vertical counter 1708 crosses a modulo 8 boundary. Decoder 1728 is enabled for every pixel time in the vertical mode by CKV which is drive by the 70 nsec input hold CK signal.
In the horizontal mode encoder 1728 is enabled by the Line Blank CK signal during each blanking time.
As column zero is scanned in the vertical mode signal 560 NS~C CK clocks flip-flop 1726 but counter 1708 is at count 16, a modulo 8 boundary and decoder 1728 immediately presets flip-flop 1726 before its output is effective to cause an address increment. This is repeated for every eighth pixel. ~or column 1 flip-flop 1726 is clocked at cycle start while counter 1708 is set to 15.
The carry input is thus active while the don't care pixel ~q~

read during the blanking interval. At the next pixel time counter 1708 is incremented to 16 and flip-flop 1726 is preset to terminate the carry command. However, after pixel P7,1 (8 pixel times after start or 50 NSEC) is read, flip-flop 1726 is clocked to reset it and cause an address increment for pixel P7,1. Looking at Table II
it will be seen that this address increment properly addresses the data for this pixel.
For column 2, memory 1600 operation begins 2 pixels early and the last two pixels of each block of 8 receive an incremen~al address. Eor column 3 the last three pixels in each block of 8 receive an incremented address until for column 7 (the eighth column) the last 7 pixels in each group of eight receive an incremented address. ~he cycle then repeats itself with no incxements being commanded for column 8.
While the memory 1600 operates at a 2 pixel parallel 140 NSEC clock rate, the addresses for each of the two active memory modules during a memory cycle can be different. Address map 1710 must therefore provide alternate early and late addresses at the pixel rate.
During each 140 NSEC cycle the early address is loaded into an early address hold buffer 1730. Seventy nano-seconds later the late address is loaded into the early address hold buffer 1730 and a late address buffer register 1732. At the same time, the early address previously loaded into hold buffer 1730 is loaded into an early address buffer 173~ for presentation to memory 1600. During the next 70 NSEC clock period the late address loaded into hold buffer 1730 is simply lost as the next early address is loaded into buffer 1730. In this way the correct address is presented to memory 1600 for each of the two modules which are active during a 140 NSEC phase time.
In the horizontal mode there are relatively few scan lines with a large number of pixels per line.
In the vertical mode there are more scan lines but with ~?~

fewer pixels per line. Consequently there are al50 more blanking intervals, but with a shorter duration for each intexval. As a result, it has been found to be advantageous when implementing memory 1100 with dynamic memory chips to perform 1 refresh cycle during each blanhing interval in the vertical mode but 2 refresh cycles in the horizontal mode.
Referring now to ~ig. ~, deinterlace filter 1332 includes a motion detector 1802 and a deinterlacing or frame generating circuit 1804 which outputs a complete frame of data at the field rate. For each field time, the newest stored field is always Cl1tpUt as half of the video data and the intermediate lines of the newest or most recent field are supplied from the second most recent field if no motion is detected by moticn detector 1802.
The occurrence of motion tends to create a double image of the moving object when two different fields sampled 1/60 of a second apart are merged into a frame representing a single instant in time. Hence, in response to the detection of motion by motion detector lB02, the intermediate lines of the new field which are output on the data path designated old field are taken as the avera~e of the pixel above and below each success-ive pixel in an intermediate line. This averaging ofupper and lower pixels to generate an intermediate line of pixels has the effect of reducing bandwidth by approximately 1/2 in the vertical direction, but presents a more pleasing image than the double image effect which occurs when two successive fields are combined during the occurrence of motion.
A subtractor 1810 receives the newest field on input A and the third newest field on input C and subtracts the data of the third newest field from the data representing the newest field on a sequential pixel by pixel basis with the diffexence being stored in a bit register 18120 A threshold detector 1814 I

responds to the difference outputs of register 1812 and outputs a logic 1 signal whenever the difference exceeds a selected threshold such as 8 out of 256 possible states. A 1 bit register 1816 stores the motion indica-tion output from threshold detector 1814 for presentationto an OR gate 1820 and for further presentation to a 1 pixel delay circuit 1818 whose output is also presented to OR gate 1820. Similarly, a subtractor 1830 sub-tracts the pixel data for the fourth oldest field on input D from the pixel data for the comparable second oldest field on input B and presents the difference to an 8 bit register 1832. A threshold detector 1834 responds to the difference output stored by register 1832 and outputs a logic 1 signal whenever this differ-ence exceeds a siven threshold such as 8 out of 256 states. This threshold output represents an indication of motion which is stored by 1 bit register 1836, the output of which is passed through a 1 pixel delay circuit 1838 to OR gate 1820. The 12 pixel time delays 20 through registers 1812, 1816 and 1832, 1836 plus the extra time delays through delay circuits 1818 and 1838 are synchronized with delays inserted in the video data path such tha~ the detection of motion at a pixel location in the newest field causes the pixels thereabove and therebelow to be generated as the average of thetwo pixels in the newest field vertically above and below the pixel being generated. If motion is detected at a pixel location in the second newest field, only that single pixel location is genexated as the average of the pixels immediately above and below the generated pixel as a result. Delay circuits 1818 and 1838 respond to a pixel signal during a vertical scan to provide a 1 pixel delay and to a line signal during a horizontal scan to provide a 1 line delay since vertically adjacent pixels will be separated by a line scan time in the horizontal scan mode.

~?;~

The pixel data for the newest field on path A
is passed through two 8 bit registers 1840, 1842 which compensate for delays of registers 1812 and 1416 in the motion detector, to a delay circuit 1844. Delay circuit 1844 responds to a pixel/line delay input from a timing and control circuit 1850 to provide a 1 pixel delay during a vertical scan normal mode of operation. The output of delay circuit 1844 represents the video data for the new field portion of the frames of data which are output at the field rate. An adder circuit 1846 adds the input and output to delay circuit 1844, deletes the least significant bit of the sum to effectively divide it by 2 and provide an average, and ~c licates the average to the A input of a multiplexer 1848. The B input is coupled to the output of a multiplexer 1866.
The select A input to multiplexer 1848 is coupled to the output of OR gate 1820 to receive the motion detec-tion signal. Hence, in the presence of the motion signal the alternate lines of the output frame of data from the new field lines (old field data) are output by multiplexer 1848 as the average of the video data above and below the pixel of data which is being synthesized.
This output of multiplexer 1848 is designated old field.
The second newest field of data appearing on path B is shifted to two 8 bit registers 1860 and 1862 which compensate for the delays occurring in corre-sponding 8 bit registers 1832 and 1836 of the motion detector circuit 1802 to the input of a delay circuit 1864. During a normal vertical scan mode of operation delay circuit 1864 provides a 1 pixel delay in response to the pixel/line signal from timing and control circuit 1850. The output of delay circuit 1864 is communicated to the A input of multiplexer 1866.
Consequently, in the absence of a motion signal from OR
gate 1820, the old field video data which interlace~
the lines of the new field viaeo data to form a complete frame of data i.s taken from the second oldest field of data coming in on path B.
During a special mode of operation in which the transposing memory 1330 outputs data in a horizontal scan rather than a vertical scan direction, the pixel/line signals must command the delay circuits 1818, 1838, 1844, 1864 and 1880 to store or delay a complete line of data in order that an incoming pixel of data may be matched with the pixel i~mediately above it in the, incoming field (the incoming pixel will be matched with a pixel two lines above it in a frame). The proper corresponding vertically juxtaposed pixel data may thus be averaged in adder 18~6 for presentation to the A
input of multiplexer 1848. Delay line 1864 provides a one line delay during the hori~ontal scan mode of operation to provide compatibility with the one line delay which must occur in delay circuit 1844.
Deinterlace filter 1332 thus outputs complete frames of data at the field rate with the newest field of data beiny continuously output on the new field path and with the intermediate horizontal lines of data appearing on the old field output path as either the second oldest field of data when motion is not detected or the average of the two vertically adjacent pixels in the new field of data when motion is detected. It will be appreciated that in a vertical scan mode the time sequential new field and old field outputs will represent vertically adjacent pairs of pixel data. That is, when an even line field is the newest field being received, the new field and old field lines will carry respectively data for pixels 00 and 10 followed by 20 and 30 fo]lowed by ~0 and 50 and so forth. In a horizontal scan mode of operation the new field and old field will carry data for vertically adjacent complete lines of data.
That is, when the newest input field is an even field the sequence of data will be for pixel locations 00 and 10 for the newest and second newest field data followed ~IP'~

by 01 and 11 followed b~ 02 and 12 and so forth until the first two lines of a frame of data have been output. Afte.r the 0 and first lines have been output the second and third lines will be output and so forth.
When the newest field is an even field representing lines 0, 2, 4, etc~, the old field contains lines 1, 3, 5, etc~ with the old field pixel representing data 1 line below the corresponding new field pixel. The timing relationship of adder 1846 is such that when motion is detected, the old field is generated as the average of data in the current line and the subsequent line For example, in the vertical mode the new field pixel P0,2 is output with pixel P0,3 formed as the average of pixels P0,2 and P0,4.
However, were the new field to be an odd field, this timing relationship would result in a pixel P0,3 being output with pixel P0,2 formed as the average of pixels P0,3 and P0,5 rather than pixels P0,1 and P0~3 as would be desired. This relationship is corrected by bypassing the delay circuits 1838 and 186~ when the newest field is an odd field. This in effect produces output data pairs for row pairs don't care, 0 and 1, 2 and 3, 4 etc., and ensures that the motion detection signal in respec-t to motion in the second newest field is properly synchronized. As a result the proper timing relationship is restored such that the old field data is one line below the corresponding new field data and the old field data is properly derived by averaging the current pix21 and the pixel for the line below it in the new field.
To ensure such proper synchronization such selective bypassing of the delay circuit 1838 may be effected by a multiplexer 1839 having its A input connected to the output of the delay 1838 and its B
input connected to the input o the delay 1838, its Select A input being connected to the signal Even Field to select the A input for an even f.ield and the B input Eor an odd ~ield.

-83~-A multiplexer 1866 is connected to selectively bypass delay 1864 with the A input connected to the output of delay 1864 and the B input connected to the input of delay 1864. The Select A input is connected to signal Even Field to select the A input for an even field and the B input for an odd f.ield. This selects ~he proper deinterlaced data from the from second most recent field in the absence of motion.

-8~-, Referring now to Fig. 19, the chroma predecima-tion and interpolation decimation filters 1900 are essentially the same for both the vertical and horizontal portions of the system. While the chroma system could utiliæe filters constructed similarly to predecimation filters 1334 and vertical interpolation decimation filter 1336, the bandwidth for the chroma data is only one-fourth that of the luminance data and the arrangement of Fig, 19 takes account of the corresponding lower data speed to provide a lower cost implementation.
Chroma predecimation and interpolation decimation filters 1900 include a pair of line buffer memory segments 1902, 1904, a write address circuit 1906 which provides write addresses to the buffer segments 1902, 1904 as data is received from the preceding transposing memory corresponding to the H to V transposing memory 1330 or V to H transposing memory 1338 in the luminance data path. Write address circuit 1906 also supplies addresses as data is ~ritten back into line buffer segments 1902, 1904 after having been stored and then read out and predecimated by a predecimation filter 1908. Line buffer segments 1902 and 1904 operate in par'allel to double the speed of memory 1600. Line buffer segments 1902, 1904 actually store three lines of video data with the storage for each line including both a full size copy and a predecimated partial sized copies thereof including half size,, one-fourth size and one-eighth size.
The filters 1900 operate continuously on the three lines of data in an interleaved fashion. At one line storage location an incoming line of video data i5 stored so as to replace the oldest line of video ~ata. ~.
At the same time the newest complete line of video data is predecimated by predecimation filter 1908 and the second newest line of complete data which, represents the newest line of completely predecimated data, is output by interpolation decimation filter 1910.

I

Memory segments 1902, 1904 operate on a 560 nanosecond cycle consisting of eight 70 nanosecond subcycles. During a given memory cycle incoming data is received and stored in registers 1920 and 1921.
During the first half of the next cycle and before the early pixel of data is received for tne next cycle, the two pixels stored in registers 1920 and 1921 are written into the line buffer segments 1902, 1904. Similarly, two pixels of data processed by predecimation filter 1908 are stored by early and late registers 1924, 1925 pending the writing of the predecimated data stored therein back into line buffer segments 1902, 1904. The eight subcycle re2eating sequence for each cycle of each 560 nanosecond cycle of line buffer segments 1902, 1904 occurs as follows.
1. Interpolate. That is, read out two pixels of video data to early and late pixel interpolation decimation buffer registers 1928, 1929 for use by interpolation filter 1910~
2. Readout two pixels of data for predecimation filter 1908 and store a pixel of predecimated pixel data in early predecimated data buffer register 1924.
3. Interpolate. Readout a second pair of pixels for storage in registers 1928, 1929.
2S 4 Write the two pixels of incoming data stored in registers 1920 and 1921 into line buffer memory segments 1902, 1904 at the next sequential address location in theVcurrent incoming line section of the memory address space.
5 Interpolate, with two more pixels of video data being written into buffer registers 1928, 1929.
6. Readout a pair of pixels for predecimation filtex 1908 with a pixel of predecimated data being written into late predecimated data buffer register 1925.
7. Interpolate by reading out two more pixels of data for storage by interpolation buf~er registers 1928, 1929.
8. Write two pixels of predecimated data which have previously been stored in early and late predecimation registers 1924, 1925 into buffer memory segments 1902, 1904. It will be noted that the clocking and output enabling of the buffer registers shown in Fig. 19 have been omitted for clarity. However, such clocking and gating can be readily implemented according to the schedule indicated above.
Predecimation filter 1908 provides a 2:1 compaction for each passage of the data therethrough.
It is opexated on a cyclic basis much as the manner of operation of predecimation filter 700. First the full size copy of a line of data is passed thxough filter 1908 and reduced to half size. ~hen the half size copy is reduced to one-fourth size followed by the reduction of ~he one-fourth size copy to one-eighth size.
Further size reduc.ions would of course be possible but ,, are not implemented in the present embodiment of the invention. The predecimation filter 1908 may be advan-tageously implemented as a 5 point filter utili7ing the sequential weighting factors of 3/32, 8/32, 10/32, 8/32, and 3/32.
Operation of the interpolation decimation filter 1910 is substantially the same as interpolation decimation filter 800 as shown in Fig. 10 except that coefficient store 1932 outputs a weighting coefficient to multiplier 1333 which is varied according to the relative position of a pixel of data within all of the pixels which are being weighted to provide the filter function rather than using the barrel shifter 810 to prealign the video data to match a predetermined filter function weighting. In effect, this shifting of relative 35 pixel data positions is accommodated through the ad- -dressing of coefficient store 1932 rather than through the actual shifting of the video data. A read address processor 1334 provides the read addresses to line buffer memory segments 1902, 1904. As data is read out for pre-decimation by filter 1908, the addresses are merely se-quentially advanced first throu~h the full size data, then through the half size data, and then through the one-fourth size data as the one-eighth size predecimated data is formed.
For interpolation, the read address processor 1334 receives source addresses from source address generator 1326 and responds to each source address by ad-dressing four pixels of data which surround the source address. The principle of implementation is essentially the same as the address circuitry for line buffer ~09 except that a 4 point filter is utilized instead of an 8 point filter. The addresses for the line buffer seg-ments 1902, 1904 must be selectively incremented or decremented as necessary to accommodate the actual address location of the required pixel of video data for a given source address.
Interpolation decimation filter 1910 operates on single pixels of video data being interpolated on a 70 nanosecond cycle which matches the rate of two pixels of data received by buffer registers 1928, 1929 from line buffer segments 1902, 1904 every 140 nanoseconds.
25 Filter 1910 is a 4 point filter and thus outputs one pixel of data every 280 nanoseconds, which is consistent with the one~fourth sampling rate and bandwidth of the chroma data.
After the storage of two pixels of video data 30 in buffer registers 1928, 1929 at the end or the first memory subcycle, during the second memory subcycle multi-plier 1333 multiples the value of the pixels stored in register 1928 times a coeEficient value from storage 1932 with the results being stored in register 1940 at the end of subcycle two. Simultaneously, at the end of subcycle two an accumulating register 1942 is cleared.
During memory subcycle three the line buffer segments -aa-1902, 1904 output two more pixels of interpolation decimation data and multiplier 1333 multiplies the value of the pixel data stored by register 1929 by a new coefficient provided by coefficient store 1932. At the end of subcycle three, the two new pixels of data are clocked into buffer registers 1928, 1929 as the output of multiplier 1333 is clocked into register 1940 and the output of adder 194q, which represents the sum of the contents Gf register 1940 and accumulator 1942, are clocked into accumulator 1942. Since accumula~or 1942 had been prevlously cleared, iA this case the contents of register 1940 are stored in accumulator 1942. This represents the first pixel of a 4 point filter cycle. During memory subcycle three multiplier 1333 multiplies the third pixel of the cycle in register 1928 by a proper coefficient and adder 1944 adds the first pixel of the cycle stored in register 1942 to the second pixel of the cycle stored in register 1940. At the;end of memory subcycle four the third pixel is stored in register 1940 and the sum of the first two pixels is stored in accumulator 1942. During memory subcycle five the line buffers 1902, 1904 readout another pair of pixels as multiplier 1333 multiplies the pixel pxeviously stored in register 1929 by its proper coefficient and adder l9g4 produces the sum of the first two pixels stored in accumulator 194~ plus the third pixel stored in register 1940. At the end of the fifth memory cycle the three pixel sum at the output of adder 1944 is stored in accumulator register 1942, the fourth weighted pixel is stored in register 19~0 and the first two pixels for the next filter cycle are stored in buffer registers 1928, 1929.
During memory subcycle six multiplier 1333 multiplies the pixel data in register 1928 by an ap-propriate coefficient from store 1932 while adder 1944 adds the three pixel sum accumulated in register 1942 to the fourth weighted pixel stored in register lg40.

!

.. ..

At the end of memory cycle six the four pixel sum output from adder 1944 is loaded into an output buffer register 1946, accumulator register 1942 is cleared and the first weighted pixel for the second output pixel is stored in register 1940.
The above described interpolation decimation filter cycle thus continues to repeat itself with two 280 nanosecond filter cycles occurring for each 560 nanosecond memory cycle. The weighting factor provided by coefficient store 1932 is selected to provide a desired filter function which depends upon the particular full size or partial size predecimated copy which is - being utilized as the source data, the amount of further size reduction or enlargement provided by interpolation filter 1910, and the location of the source address point relative to the pixel.

, I

TABLE II
- ADDRESS T~BLE
~ ~2 0.3 . ~`. . 02 04 ADDRESS Y0 Yl Y2 Y3 Y4 Y5 Y6 Y7 C2 C7 1,7~2 P0,0 P0,1 P0,2 P0,4PO,q P0,5 P0,6 P0,7 C0,0 C0,1 1,793 P0,8 P0,9 P0,10 P0,11 P0,12 P0,13 P0,14 P0,15 C0,2 C0,3 1,794 P0,16 P0,17 P0,18 PO,lg P0,~0 P0,21 P0,22 ro, 23 C0,4 C0,5 1,904 X Pl,0 Pl,l Pl,10 Pl,ll Pl,12 Pl,13 Pl,14 Cl,0 Cl,l 1,905 Pl,7 Pl,8 Pl,9 Pl,10 Pl,ll Pl,12 Pl,13 Pl,14 Cl,2 C1,3 -~
1,906 Pl,15 Pl,16 Pl,17 Pl,18 Pl,l9 Pl,20 Pl,21 Pl,22 Cl,4 C1,5 2,016 X X P2,0 P2,1 P2,2 P2,3 P2,~ P2,5 C2,0 C2,1 2,017 P2,6 P2,7 P2,8 P2,9P2,1Q P2,11 P2,12 P2,13 C2,2 C2,3 2,018 P2,14 P2,15 P2,16 P2,17 P2,18 P2,19 P2,20 P2,21 C2,4 C2,5 2,128 X X X P3,0 P3,1 P3,2 P3,3 P3,4 C3,0 C3,1 2,129 P3,5 P3,6 P3,7 P3,~3 P3,9 P3,10 P3,11 P3,12 C3,2 C3,3 2,130 P3,13 P3,14 P3,15 P3,16 P3,17 P3,18 P3,19 P3,20 C3,4 C3,5 2,240 X X X X P4,0 P4,1P4,2 P4,3 X C4,0 2,241 Pq,4 P4,5 P4,6 P4,7P4,8 P4,9 P4,10 P4,11 C4,1 C4,2 2,242 P4,12 P4,13 P4,14 P4,15 P4,16 P4,17 P4,18 P4,19 C4,3 C4,4 \

':

I

,__ 02 . ~3 0~4 ~2 04 ADDP~SS Y0 Yl Y2- Y3 Y4 Y5Y6 Y7 -~ C7 2,352 X X X X X P5,0 P5,1 P5,2 X C5,0 2,353 P5,3 P5,4 P5,5 P5,6 P5,7 P5,~P5,9 P5,10 C5,1 C5,2 2,354P5,11 P5,12 P5,13 P5,14 . P5,15 P5,16 P5,1~ P5,18 C5,3 C5,~

2,464X X X X X X P6,0 P6,1 X C6,0 2,465P6,2 P6,3 P6,4 P6,5 P6,6 P6,7 P~,8 P6,9C6,1 C6,2 2,466P6,10 P6,11 P6,12 P6,13 P6,14 P6,15 P6,16 P6,17 ~6,3 C6,4 2,576 X X X X X . X X P7,0 X C7,0 2,577 P7,1 P7,2 P7,3 P7,4 P7,5 P7,6P7,7 P7,8 C7,1 C7,2 2,578 P7,9 P7,1~ P7,11 P7,12 P7,13 P7,14 P7,15 P7,16 C7,3 C7,4 2,688 P8,0 P8,1 P8,2 P8,3 P8,4 P8,5P8,6 P8,7 C8,0 C8,1 2,689 P~,8 P8,9 P8,10 P8,11 P8,12 P8,13 P8,14 P8,~5 C8,2 C8,3 2,690P8,16 P8,17 P8,18 P8,19 P8,20 P8,21 P8,22 P8,23 C8,4 C8,5 !.

While there have been shown and described above various arrangements of a digital special e~fect~
system and digital transformation systems in accordance with the invention, it will be appreciated that the invention is not limited thereto. Accordingly any modifications, variations or equivalent arrangements within the scope o~ the attached claims should be considered to be within the scope of the invention.

,~

,

Claims (65)

The embodiments in which an exclusive property or privilege is claimed are defined as follows:

1. A processor for generating frames of video data samples from a sequence of interlaced video fields of video data samples corresponding to respective picture elements in lines in raster scan order in which spatially alternate lines of a frame are in respective temporally successive fields with a pair of successive fields forming a frame, said sequence including a most recent field, a second most recent field and a third most recent field, said processor comprising a motion detector responsive to video data samples in at least said most recent field and said third most recent field for comparing video data samples corresponding to the same spatial position in each of said two fields of data samples, the motion detector generating a motion signal as a function of the difference between said compared data samples; and a circuit coupled to receive said most recent field and said second most recent field of data samples and the motion signal, and upon receiving each most recent said field to output a deinterlaced frame of data samples comprising the most recent field of data samples and data samples for the lines intermediate those of the most recent field formed from (A) the average of data samples for respective adjacent picture elements in the respective adjacent lines of the most recent field, and (B) respective lines of the second most recent field, as a function of said motion signal.

2. A processor according to claim 1 wherein said circuit comprises means responsive to said data samples of the most recent field for developing average data samples corresponding to respective picture elements of said intermediate lines, said average data samples corresponding to the average of data samples for respective adjacent picture elements in the respective adjacent lines of the most recent field, means responsive to said motion signal for developing intermediate data samples as a blend of (A) respective average data samples, and (B) respective data samples corresponding to picture elements in respective lines of the second most recent field, in proportions determined by said motion signal, and means for outputting deinterlaced frames of data samples comprising the most recent field of data samples in respect to every other line and said intermediate data samples in respect to the intermediate lines thereof.

3. A processor according to claim 2 wherein said sequence includes a fourth most recent field, and said motion detector includes means responsive to video data samples in said second most recent field and said fourth most recent field for comparing video data samples corresponding to the same spatial position in each of said two fields of data samples, said motion detector generating a said motion signal as a function of the difference between said compared data samples of said second and fourth most recent fields.

4. A processor according to claim 3 wherein, in respect to generating said motion signal as a function of the difference between data samples in said most recent and third most recent fields, said motion detector includes means for generating said signal in respect to intermediate lines both spatially preceding and spatially succeeding the spatial position giving rise to said motion signal.

5. A processor according to claim 4 wherein said proportions are limited to 0 and 1.

6. A processor according to claim 5 wherein said motion detector generates a motion signal greater than 0 when the difference between said compared data samples exceeds a threshold amount, and said means responsive to said motion signal comprises a multiplexer selecting between (A) respective average data samples, and (B) respective data samples corresponding to picture elements in respective lines of the second most recent field.

7. A processor according to claim 6 wherein the motion detector comprises a first subtractor coupled to subtract data samples corresponding to sequential picture elements of the third most recent field from corresponding data samples of the most recent field, a second subtractor coupled to subtract data samples corresponding to sequential picture elements of the fourth most recent field from corresponding data samples of said second most recent field, first and second threshold detectors coupled to receive the respective difference outputs of the first and second subtractors and generate first and second preliminary motion signal outputs whenever a respective difference output exceeds a threshold amount, a first delay circuit for selectively delaying the first preliminary motion signal by one picture element or one line time depending upon the sequence of said data samples to generate a delayed first preliminary motion signal, a second delay circuit for selectively delaying the second preliminary motion signal by said one picture element or one line time to generate a delayed second preliminary motion signal, and an OR gate coupled to generate a signal corresponding to said motion signal in response to the occurrence of the first preliminary motion signal, the delayed first preliminary motion signal or the delayed second preliminary motion signal.

8. A processor according to claim 7 including first and second difference registers coupled to store the respective subtractor difference outputs.

9. A processor according to claim 7 comprising five field stores coupled to receive and store sequential fields of data samples as they are received, the fields being stored in the field stores on a sequential rotating basis with the oldest stored field being replaced by a newest incoming field as it is received, the field stores being coupled to output to said motion detector the first through fourth newest fields in parallel in raster scan order as each incoming field is received and to output to said circuit the most recent and second most recent fields in parallel in raster scan order as each incoming field is received.

10. A processor according to any one of claims 6, 7 and 9, wherein said circuit further comprises a delay circuit for selectively delaying the data samples for the second newest field by one picture element or one line time depending upon the sequence of said data samples, and a selector circuit coupled to select data samples from the output of the delay circuit when the first most recent field is an even field containing the first line of a frame and to select data samples from the input to the delay when the most recent field is an odd field containing the second line of a frame, said selected data samples comprising (B) said respective lines of the second most recent field.

11. A processor according to claim 5 wherein the motion detector comprises a first subtractor coupled to subtract data samples corresponding to sequential picture elements of the third most recent field from corresponding data samples of the most recent field, a second subtractor coupled to subtract data samples corresponding to sequential picture elements of the fourth most recent field from corresponding data samples of said second most recent field, first and second threshold detectors coupled to receive the respective difference outputs of the first and second subtractors and generate first and second preliminary motion signal outputs whenever a respective difference output exceeds a threshold amount, a first delay circuit for selectively delaying the first preliminary motion signal by one picture element or one line time depending upon the sequence of said data samples to generate a delayed first preliminary motion signal, a second delay circuit for selectively delaying the second preliminary motion signal by said one picture element or one line time to generate a delayed second preliminary motion signal, and an OR gate coupled to generate a signal corresponding to said motion signal in response to the occurrence of the first preliminary motion signal, the delayed first preliminary motion signal or the delayed second preliminary motion signal.

12. A processor according to claim 11 comprising five field stores coupled to receive and store sequential fields of data samples as they are received, the fields being stored in the field stores on a sequential rotating basis with the oldest stored field being replaced by a newest incoming field as it is received, the field stores being coupled to output to said motion detector the first through fourth newest fields in parallel in raster scan order as each incoming field is received and to output to said circuit the most recent and second most recent fields in parallel in raster scan order as each incoming field is received.

13. A processor according to any one of claims 5, 11 and 12, wherein said circuit further comprises a delay circuit for selectively delaying the data samples for the second newest field by one picture element or one line time depending upon the sequence of said data samples, and a selector circuit coupled to select data samples from the output of the delay circuit when the first most recent field is an even field containing the first line of a frame and to select data samples from the input to the delay when the most recent field is an odd field containing the second line of a frame, said selected data samples comprising (B) said respective lines of the second most recent field.

14. A processor according to claim 4 wherein the motion detector comprises a first subtractor coupled to subtract data samples corresponding to sequential picture elements of the third most recent field from corresponding data samples of the most recent field, a second subtractor coupled to subtract data samples corresponding to sequential picture elements of the fourth most recent field from corresponding data samples of said second most recent field, first and second threshold detectors coupled to receive the respective difference outputs of the first and second subtractors and generate first and second preliminary motion signal outputs whenever a respective difference output exceeds a threshold amount, a first delay circuit for selectively delaying the first preliminary motion signal by one picture element or one line time depending upon the sequence of said data samples to generate a delayed first preliminary motion signal, a second delay circuit for selectively delaying the second preliminary motion signal by said one picture element or one line time to generate a delayed second preliminary motion signal, and an OR gate coupled to generate a signal corresponding to said motion signal in response to the occurrence of the first preliminary motion signal, the delayed first preliminary motion signal or the delayed second preliminary motion signal.

15. A processor according to claim 14 comprising five field stores coupled to receive and store sequential fields of data samples as they are received, the fields being stored in the field stores on a sequential rotating basis with the oldest stored field being replaced by a newest incoming field as it is received, the field stores being coupled to output to said motion detector the first through fourth newest fields in parallel in raster scan order as each incoming field is received and to output to said circuit the most recent and second most recent fields in parallel in raster scan order as each incoming field is received.

16. A processor according to any one of claims 4, 14 and 15 wherein said circuit further comprises a delay circuit for selectively delaying the data samples for the second newest field by one picture element or one line time depending upon the sequences of said data samples and a selector circuit coupled to select data samples from the output of the delay circuit when the first most recent field is an even field containing the first line of a frame and to select data samples from the input to the delay when the most recent field is an odd field containing the second line of a frame and to output to said circuit the most recent, said selected data samples comprising (B) said respective lines of the second most recent field.

17. A processor according to claim 3 wherein said proportions are limited to 0 and 1.

18. A processor according to claim 17 wherein said motion detector generates a motion signal greater than 0 when the difference between said compared data samples exceeds a threshold amount, and said means responsive to said motion signal comprises a multiplexer selecting between (A) respective average data samples, and (B) respective data samples corresponding to picture elements in respective lines of the second most recent field.

19. A processor according to claim 18 wherein the motion detector comprises a first subtractor coupled to subtract data samples corresponding to sequential picture elements of the third most recent field from corresponding data samples of the most recent field, a second subtractor coupled to subtract data samples corresponding to sequential picture elements of the fourth most recent field from corresponding data samples of said second most recent field, first and second threshold detectors coupled to receive the respective difference outputs of the first and second subtractors and generate first and second preliminary motion signal outputs whenever a respective difference output exceeds a threshold amount, a first delay circuit for selectively delaying the first preliminary motion signal by one picture element or one line time depending upon the sequence of said data samples to generate a delayed first preliminary motion signal, a second delay circuit for selectively delaying the second preliminary motion signal by said one picture element or one line time to generate a delayed second preliminary motion signal, and an OR gate coupled to generate a signal corresponding to said motion signal in response to the occurrence of the first preliminary motion signal, the delayed first preliminary motion signal or the delayed second preliminary motion signal.

20. A processor according to claim 19 comprising five field stores coupled to receive and store sequential fields of data samples as they are received, the fields being stored in the field stores on a sequential rotating basis with the oldest stored field being replaced by a newest incoming field as it is received, the field stores being coupled to output to said motion detector the first through fourth newest fields in parallel in raster scan order as each incoming field is received and to output to said circuit the most recent and second most recent fields in parallel in raster scan order as each incoming field is received.

21. A processor according to any one of claims 18, 19 and 20 wherein said circuit further comprises a delay circuit for selectively delaying the data samples for the second newest field by one picture element or one line time depending upon the sequence of said data samples, and a selector circuit coupled to select data samples from the output of the delay circuit when the first most recent field is an even field containing the first line of a frame and to select data samples from the input to the delay when the most recent field is an odd field containing the second line of a frame, said selected data samples comprising (B) said respective lines of the second most recent field.

22. A processor according to claim 17 wherein the motion detector comprises a first subtractor coupled to subtract data samples corresponding to sequential picture elements of the third most recent field from corresponding data samples of the most recent field, a second subtractor coupled to subtract data samples corresponding to sequential picture elements of the fourth most recent field from corresponding data samples of said second most recent field, first and second threshold detectors coupled to receive the respective difference outputs of the first and second subtractors and generate first and second preliminary motion signal outputs whenever a respective difference output exceeds a threshold amount, a first delay circuit for selectively delaying the first preliminary motion signal by one picture element or one line time depending upon the sequence of said data samples to generate a delayed first preliminary motion signal, a second delay circuit for selectively delaying the second preliminary motion signal by said one picture element or one line time to generate a delayed second preliminary motion signal, and an OR gate coupled to generate a signal corresponding to said motion signal in response to the occurrence of the first preliminary motion signal, the delayed first preliminary motion signal or the delayed second preliminary motion signal.

23. A processor according to claim 22 comprising five field stores coupled to receive and store sequential fields of data samples as they are received, the fields being stored in the field stores on a sequential rotating basis with the oldest stored field being replaced by a newest incoming field as it is received, the field stores being coupled to output to said motion detector the first through fourth newest fields in parallel in raster scan order as each incoming field is received and to output to said circuit the most recent and second most recent fields in parallel in raster scan order as each incoming field is received.

24. A processor according to any one of claims 17, 22 and 23, wherein said circuit further comprises a delay circuit for selectively delaying the data samples for the second newest field by one picture element or one line time depending upon the sequence of said data samples, and a selector circuit coupled to select data samples from the output of the delay circuit when the first most recent field is an even field containing the first line of a frame and to select data samples from the input to the delay when the most recent field is an odd field containing the second line of a frame, said selected data samples comprising (B) said respective lines of the second most recent field.

25. A processor according to claim 3 wherein the motion detector comprises a first subtractor coupled to subtract data samples corresponding to sequential picture elements of the third most recent field from corresponding data samples of the most recent field, a second subtractor coupled to subtract data samples corresponding to sequential picture elements of the fourth most recent field from corresponding data samples of said second most recent field, first and second threshold detectors coupled to receive the respective difference outputs of the first and second subtractors and generate first and second preliminary motion signal outputs whenever a respective difference output exceeds a threshold amount, a first delay circuit for selectively delaying the first preliminary motion signal by one picture element or one line time depending upon the sequence of said data samples to generate a delayed first preliminary motion signal, a second delay circuit for selectively delaying the second preliminary motion signal by said one picture element or one line time to generate a delayed second preliminary motion signal, and an OR gate coupled to generate a signal corresponding to said motion signal in response to the occurrence of the first preliminary motion signal, the delayed first preliminary motion signal or the delayed second preliminary motion signal.

26. A processor according to claim 25 comprising five field stores coupled to receive and store sequential fields of data samples as they are received, the fields being stored in the field stores on a sequential rotating basis with the oldest stored field being replaced by a newest incoming field as it is received, the field stores being coupled to output to said motion detector the first through fourth newest fields in parallel in raster scan order as each incoming field is received and to output to said circuit the most recent and second most recent fields in parallel in raster scan order as each incoming field is received.

27. A processor according to any one of claims 3, 25 and 26, wherein said circuit further comprises a delay circuit for selectively delaying the data samples for the second newest field by one picture element or one line time depending upon the sequence of said data samples, and a selector circuit coupled to select data samples from the output of the delay circuit when the first most recent field is an even field containing the first line of a frame and to select data samples from the input to the delay when the most recent field is an odd field containing the second line of a frame, said selected data samples comprising (B) said respective lines of the second most recent field.

28. A processor according to claim 4 comprising five field stores coupled to receive and store sequential fields of data samples as they are received, the fields being stored in the field stores on a sequential rotating basis with the oldest stored field being replaced by a newest incoming field as it is received, the field stores being coupled to output to said motion detector the first through fourth newest fields in parallel in raster scan order as each incoming field is received and to output to said circuit the most recent and second most recent fields in parallel in raster scan order as each incoming field is received.

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29. A processor according to claim 5 comprising five field stores coupled to receive and store sequential fields of data samples as they are received, the fields being stored in the field stores on a sequential rotating basis with the oldest stored field being replaced by a newest incoming field as it is received, the field stores being coupled to output to said motion detector the first through fourth newest fields in parallel in raster scan order as each incoming field is received and to output to said circuit the most recent and second most recent fields in parallel in raster scan order as each incoming field is received.

30. A processor according to claim 6 comprising five field stores coupled to receive and store sequential fields of data samples as they are received, the fields being stored in the field stores on a sequential rotating basis with the oldest stored field being replaced by a newest incoming field as it is received, the field stores being coupled to output to said motion detector the first through fourth newest fields in parallel in raster scan order as each incoming field is received and to output to said circuit the most recent and second most recent fields in parallel in raster scan order as each incoming field is received.

31. A processor according to any one of claims 28, 29 and 30, wherein said circuit further comprises a delay circuit for selectively delaying the data samples for the second newest field by one picture element or one line time depending upon the sequence of said data samples, and a selector circuit coupled to select data samples from the output of the delay circuit when the first most recent field is an even field containing the first line of a frame and to select data samples from the input to the delay when the most recent field is an odd field containing the second line of a frame, said selected data samples comprising (B) said respective lines of the second most recent field.

32. A processor according to claim 17 comprising five field stores coupled to receive and store sequential fields of data samples as they are received, the fields being stored in the field stores on a sequential rotating basis with the oldest stored field being replaced by a newest incoming field as it is received, the field stores being coupled to output to said motion detector the first through fourth newest fields in parallel in raster scan order as each incoming field is received and to output to said circuit the most recent and second most recent fields in parallel in raster scan order as each incoming field is received.

33. A processor according to claim 18 comprising five field stores coupled to receive and store sequential fields of data samples as they are received, the fields being stored in the field stores on a sequential rotating basis with the oldest stored field being replaced by a newest incoming field as it is received, the field stores being coupled to output to said motion detector the first through fourth newest fields in parallel in raster scan order as each incoming field is received and to output to said circuit the most recent and second most recent fields in parallel in raster scan order as each incoming field is received.

34. A processor according to claim 3 comprising five field stores coupled to receive and store sequential fields of data samples as they are received, the fields being stored in the field stores on a sequential rotating basis with the oldest stored field being replaced by a newest incoming field as it is received, the field stores being coupled to output to said motion detector the first through fourth newest fields in parallel in raster scan order as each incoming field is received and to output to said circuit the most recent and second most recent fields in parallel in raster scan order as each incoming field is received.

35. A processor according to any one of claims 32, 33 and 34, wherein said circuit further comprises a delay circuit for selectively delaying the data samples for the second newest field by one picture element or one line time depending upon the sequence of said data samples, and a selector circuit coupled to select data samples from the output of the delay circuit when the first most recent field is an even field containing the first line of a frame and to select data samples from the input to the delay when the most recent field is an odd field containing the second line of a frame, said selected data samples comprising (B) said respective lines of the second most recent field.

36. A processor according to claim 2 wherein, in respect to generating said motion signal as a function of the difference between data samples in said most recent and third most recent fields, said motion detector includes means for generating said signal in respect to intermediate lines both spatially preceding and spatially succeeding the spatial position giving rise to said motion signal.

37. A processor according to claim 36 wherein said proportions are limited to 0 and 1.

38. A processor according to claim 37 wherein said motion detector generates a motion signal greater than 0 when the difference between said compared data samples exceeds a threshold amount, and said means responsive to said motion signal comprises a multiplexer selecting between (A) respective average data samples, and (B) respective data samples corresponding to picture elements in respective lines of the second most recent field.

39. A processor according to any one of claims 36, 37 and 38, wherein said circuit further comprises a delay circuit for selectively delaying the data samples for the second newest field by one picture element or one line time depending upon the sequence of said data samples, and a selector circuit coupled to select data samples from the output of the delay circuit when the first most recent field is an even field containing the first line of a frame and to select data samples from the input to the delay when the most recent field is an odd field containing the second line of a frame, said selected data samples comprising (B) said respective lines of the second most recent field.

40. A processor according to claim 36 comprising five field stores coupled to receive and store sequential fields of data samples as they are received, the fields being stored in the field stores on a sequential rotating basis with the oldest stored field being replaced by a newest incoming field as it is received, the field stores being coupled to output to said motion detector the first through fourth newest fields in parallel in raster scan order as each incoming field is received and to output to said circuit the most recent and second most recent fields in parallel in raster scan order as each incoming field is received.

41. A processor according to claim 37 comprising five field stores coupled to receive and store sequential fields of data samples as they are received, the fields being stored in the field stores on a sequential rotating basis with the oldest stored field being replaced by a newest incoming field as it is received, the field stores being coupled to output to said motion detector the first through fourth newest fields in parallel in raster scan order as each incoming field is received and to output to said circuit the most recent and second most recent fields in parallel in raster scan order as each incoming field is received.

42. A processor according to claim 38 comprising five field stores coupled to receive and store sequential fields of data samples as they are received, the fields being stored in the field stores on a sequential rotating basis with the oldest stored field being replaced by a newest incoming field as it is received, the field stores being coupled to output to said motion detector the first through fourth newest fields in parallel in raster scan order as each incoming field is received and to output to said circuit the most recent and second most recent fields in parallel in raster scan order as each incoming field is received.

43. A processor according to any one of claims 40, 41 and 42, wherein said circuit further comprises a delay circuit for selectively delaying the data samples for the second newest field by one picture element or one line time depending upon the sequence of said data samples, and a selector circuit coupled to select data samples from the output of the delay circuit when the first most recent field is an even field containing the first line of a frame and to select data samples from the input to the delay when the most recent field is an odd field containing the second line of a frame, said selected data samples comprising (B) said respective lines of the second most recent field.

44. A processor according to claim 2 wherein said proportions are limited to 0 and 1.

45. A processor according to claim 44 wherein said motion detector generates a motion signal greater than 0 when the difference between said compared data samples exceeds a threshold amount, and said means responsive to said motion signal comprises a multiplexer selecting between (A) respective average data samples, and (B) respective data samples corresponding to picture elements in respective lines of the second most recent field.

46. A processor according to any one of claims 2, 44 and 45, wherein said circuit further comprises a delay circuit for selectively delaying the data samples for the second newest field by one picture element or one line time depending upon the sequence of said data samples, and a selector circuit coupled to select data samples from the output of the delay circuit when the first most recent field is an even field containing the first line of a frame and to select data samples from the input to the delay when the most recent field is an odd field containing the second line of a frame, said selected data samples comprising (B) said respective lines of the second most recent field.

47. A processor according to claim 44 comprising five field stores coupled to receive and store sequential fields of data samples as they are received, the fields being stored in the field stores on a sequential rotating basis with the oldest stored field being replaced by a newest incoming field as it is received, the field stores being coupled to output to said motion detector the first through fourth newest fields in parallel in raster scan order as each incoming field is received and to output to said circuit the most recent and second most recent fields in parallel in raster scan order as each incoming field is received.

48. A processor according to claim 45 comprising five field stores coupled to receive and store sequential fields of data samples as they are received, the fields being stored in the field stores on a sequential rotating basis with the oldest stored field being replaced by a newest incoming field as it is received, the field stores being coupled to output to said motion detector the first through fourth newest fields in parallel in raster scan order as each incoming field is received and to output to said circuit the most recent and second most recent fields in parallel in raster scan order as each incoming field is received.

49. A processor according to any one of claims 1, 47 and 48, wherein said circuit further comprises a delay circuit for selectively delaying the data samples for the second newest field by one picture element or one line time depending upon the sequence of said data samples, and a selector circuit coupled to select data samples from the output of the delay circuit when the first most recent field is an even field containing the first line of a frame and to select data samples from the input to the delay when the most recent field is an odd field containing the second line of a frame, said selected data samples comprising (B) said respective lines of the second most recent field.

50. A processor according to claim 1 wherein said sequence includes a fourth most recent field, and said motion detector includes means responsive to video data samples in said second most recent field and said fourth most recent field for comparing video data samples corresponding to the same spatial position in each of said two fields of data samples, said motion detector generating a said motion signal as a function of the difference between said compared data samples of said second and fourth most recent fields.

51. A processor according to claim 50 wherein, in respect to generating said motion signal as a function of the difference between data samples in said most recent and third most recent fields, said motion detector includes means for generating said signal in respect to intermediate lines both spatially preceding and spatially succeeding the spatial position giving rise to said motion signal.

52. A processor according to claim 51 wherein the motion detector comprises a first subtractor coupled to subtract data samples corresponding to sequential picture elements of the third most recent field from corresponding data samples of the most recent field, a second subtractor coupled to subtract data samples corresponding to sequential picture elements of the fourth most recent field from corresponding data samples of said second most recent field, first and second threshold detectors coupled to receive the respective difference outputs of the first and second subtractors and generate first and second preliminary motion signal outputs whenever a respective difference output exceeds a threshold amount, a first delay circuit for selectively delaying the first preliminary motion signal by one picture element or one line time depending upon the sequence of said data samples to generate a delayed first preliminary motion signal, a second delay circuit for selectively delaying the second preliminary motion signal by said one picture element or one line time to generate a delayed second preliminary motion signal, and an OR gate coupled to generate a signal corresponding to said motion signal in response to the occurrence of the first preliminary motion signal, the delayed first preliminary motion signal or the delayed second preliminary motion signal.

53. A processor according to claim 52 comprising five field stores coupled to receive and store sequential fields of data samples as they are received, the fields being stored in the field stores on a sequential rotating basis with the oldest stored field being replaced by a newest incoming field as it is received, the field stores being coupled to output to said motion detector the first through fourth newest fields in parallel in raster scan order as each incoming field is received and to output to said circuit the most recent and second most recent fields in parallel in raster scan order as each incoming field is received.

54. A processor according to any one of claims 51, 52 and 53, wherein said circuit further comprises a delay circuit for selectively delaying the data samples for the second newest field by one picture element or one line time depending upon the sequence of said data samples, and a selector circuit coupled to select data samples from the output of the delay circuit when the first most recent field is an even field containing the first line of a frame and to select data samples from the input to the delay when the most recent field is an odd field containing the second line of a frame, said selected data samples comprising (B) said respective lines of the second most recent field.

55. A processor according to claim 50 wherein the motion detector comprises a first subtractor coupled to subtract data samples corresponding to sequential picture elements of the third most recent field from corresponding data samples of the most recent field, a second subtractor coupled to subtract data samples corresponding to sequential picture elements of the fourth most recent field from corresponding data samples of said second most recent field, first and second threshold detectors coupled to receive the respective difference outputs of the first and second subtractors and generate first and second preliminary motion signal outputs whenever a respective difference output exceeds a threshold amount, a first delay circuit for selectively delaying the first preliminary motion signal by one picture element or one line time depending upon the sequence of said data samples to generate a delayed first preliminary motion signal, a second delay circuit for selectively delaying the second preliminary motion signal by said one picture element or one line time to generate a delayed second preliminary motion signal, and an OR gate coupled to generate a signal corresponding to said motion signal in response to the occurrence of the first preliminary motion signal, the delayed first preliminary motion signal or the delayed second preliminary motion signal.

56. A processor according to claim 55 comprising five field stores coupled to receive and store sequential fields of data samples as they are received, the fields being stored in the field stores on a sequential rotating basis with the oldest stored field being replaced by a newest incoming field as it is received, the field stores being coupled to output to said motion detector the first through fourth newest fields in parallel in raster scan order as each incoming field is received and to output to said circuit the most recent and second most recent fields in parallel in raster scan order as each incoming field is received.

57. A processor according to any one of claims 50, 55 and 56, wherein said circuit further comprises a delay circuit for selectively delaying the data samples for the second newest field by one picture element or one line time depending upon the sequence of said data samples, and a selector circuit coupled to select data samples from the output of the delay circuit when the first most recent field is an even field containing the first line of a frame and to select data samples from the input to the delay when the most recent field is an odd field containing the second line of a frame, said selected data samples comprising (B) said respective lines of the second most recent field.

58. A processor according to claim 50 comprising five field stores coupled to receive and store sequential fields of data samples as they are received, the fields being stored in the field stores on a sequential rotating basis with the oldest stored field being replaced by a newest incoming field as it is received, the field stores being coupled to output to said motion detector the first through fourth newest fields in parallel in raster scan order as each incoming field is received and to output to said circuit the most recent and second most recent fields in parallel in raster scan order as each incoming field is received.

59. A processor according to claim 51 comprising five field stores coupled to receive and store sequential fields of data samples as they are received, the fields being stored in the field stores on a sequential rotating basis with the oldest stored field being replaced by a newest incoming field as it is received, the field stores being coupled to output to said motion detector the first through fourth newest fields in parallel in raster scan order as each incoming field is received and to output to said circuit the most recent and second most recent fields in parallel in raster scan order as each incoming field is received.

60. A processor according to claim 1 comprising five field stores coupled to receive and store sequential fields of data samples as they are received, the fields being stored in the field stores on a sequential rotating basis with the oldest stored field being replaced by a newest incoming field as it is received, the field stores being coupled to output to said motion detector the first through fourth newest fields in parallel in raster scan order as each incoming field is received and to output to said circuit the most recent and second most recent fields in parallel in raster scan order as each incoming field is received.

61. A processor according to any one of claims 58, 59 and 60, wherein said circuit further comprises a delay circuit for selectively delaying the data samples for the second newest field by one picture element or one line time depending upon the sequence of said data samples, and a selector circuit coupled to select data samples from the output of the delay circuit when the first most recent field is an even field containing the first line of a frame and to select data samples from the input to the delay when the most recent field is an odd field containing the second line of a frame, said selected data samples comprising (B) said respective lines of the second most recent field.

62. A processor according to claim 1 wherein, in respect to generating said motion signal as a function of the difference between data samples in said most recent and third most recent fields, said motion detector includes means for generating said signal in respect to intermediate lines both spatially preceding and spatially succeeding the spatial position giving rise to said motion signal.

63. A processor according to claim 1 wherein said proportions are limited to 0 and 1.

64. A processor according to claim 63 wherein said motion detector generates a motion signal greater than 0 when the difference between said compared data samples exceeds a threshold amount, and said means responsive to said motion signal comprises a multiplexer selecting between (A) respective average data samples, and (B) respective data samples corresponding to picture elements in respective lines of the second most recent field.

65. A processor according to any one of claims 62, 63 and 64, wherein said circuit further comprises a delay circuit for selectively delaying the data samples for the second newest field by one picture element or one line time depending upon the sequence of said data samples, and a selector circuit coupled to select data samples from the output of the delay circuit when the first most recent field is an even field containing the first line of a frame and to select data samples from the input to the delay when the most recent field is an odd field containing the second line of a frame, said selected data samples comprising (B) said respective lines of the second most recent field.