CA1128626A - Data communication system - Google Patents
Data communication systemInfo
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- CA1128626A CA1128626A CA382,194A CA382194A CA1128626A CA 1128626 A CA1128626 A CA 1128626A CA 382194 A CA382194 A CA 382194A CA 1128626 A CA1128626 A CA 1128626A
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Abstract
DATA COMMUNICATION SYSTEM
ABSTRACT
A data communication system for use in the control and monitoring of mobile stations, for example, in a bus monitoring system, from a central station over a communication channel carrying both data and voice information. Information is encoded into digital messages having a start code followed by one or more data blocks. The start code identifies the beginning of the data block that follows and enables syn-chronization of clock circuitry to the received data frequency.
The data blocks have N digital words with M binary bits where one word is a parity word and N-1 words are data words. Each of the data words has a data portion and parity portion coded for correction of at least one error. Relia-bility is enhanced by a data detector which discriminates between data and noise or voice to provide an indication of the presence of data. In transmitting the digital messages, the bits of the N words in each data block are interleaved to provide protection against error bursts.
ABSTRACT
A data communication system for use in the control and monitoring of mobile stations, for example, in a bus monitoring system, from a central station over a communication channel carrying both data and voice information. Information is encoded into digital messages having a start code followed by one or more data blocks. The start code identifies the beginning of the data block that follows and enables syn-chronization of clock circuitry to the received data frequency.
The data blocks have N digital words with M binary bits where one word is a parity word and N-1 words are data words. Each of the data words has a data portion and parity portion coded for correction of at least one error. Relia-bility is enhanced by a data detector which discriminates between data and noise or voice to provide an indication of the presence of data. In transmitting the digital messages, the bits of the N words in each data block are interleaved to provide protection against error bursts.
Description
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Background of the_Invention 1. Fiield of the Invention This invention relates to a data communication system, O and, more particularly, to an improved method and apparatus ~or a data communication system utilizing a coded digital signalling system.
27 Description of the Pxior Ar~ `
: In order to expand the capacity of a communication system, one may add more communication channels to ~he ~ 77943 ~Z86Z6 system or increase the amount of information carried on each of the existing communication channe]s. Since the number of communication channels is limited for most systems, it has been more practical to increase the amount of information carried on each communication channel by various methods, for example, multiplexing and digital techniques. The communication systems using these concentrating techniques must be reliable to insure that the information is not lost.
The reliability of communication syst~ms using digital messages may be enhanced by using such techniques as error correcting coaes and multiple transmissions of the digital messages. However, prior art communication systems, such as radio communication systems, are still prone to burst errors and have yet to realize optimal usage of error correcting and detecting techniques in a bandwith limite~ system. This is especially the case with radio communication systems where interference and fading must be accommodated.
For the foregoing and other shortcomings and problems, there has been a long felt need for an improved data com-O munication system.
Summar~ of the Invention Accordingly, it is a general object of the present invention to provide an improved data communication system.
It a further object of the present invention to provide a more reliable data communication system.
It is still a further object of the present invention to provide an improved data communication system that pro-vides random and burst error protection and correction.
It is yet a further object of the present invention to provide an improved data communication system that can .
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~M-77943 , recognize the presence of noise or voice to pro~ide additonal protection against the reception of invalid digital messages.
In accordance with the present invention, the afore-mentioned problems and shortcomings of the prior art are overcome and the stated and other objects are attained by an improved digital data communication system that includes a central station and a plurality of mobile stations. The system may further include one or more fixed stations for providing relevant information, such as geographical location information, to the mobile stations. Communication channels of the system may carry voice between the operator of the mobile station and the dispatcher at the central station without affecting the reliability of the digital message transmissions.
In accordance with a feature of the present invention, digital messages are transmitted after a start code of a predetermined nature. The digital message is formated into ; at least one data block having N digital words, each word having M binary bits, where M and N are integer numbers.
~0 The start code has a predetermined number of binary bits, for example thirty-two, organized in a highly correlatable pattern for defining the beginning of the first data block of the ditital message. The N digital word~ of a data block include at least one parity word and N-l data words. Each of the data words has a data portion and a parity portion coded for correction of at least one bit which is in error in the data portion. For example, the parity portion can be coded according to a Hamming code. The parity word has M
binary bits which are each derived according to a predetermined ~10 format from the group of corresponding bits taken from the N-l data words. The parity word may be chosen so that it _ 3 - :
does not include long strings of logical zero or logical one bits. This is beneficial in limiting the low frequency content of the digital message and pxoviding bit transitions to enable synchronization to the data frequencyO
According to an ~ or~t feature of the present invention, a detector of a coded digital message ls provided that can discriminate data from noise, voice, or music. The data detector includes means for decoding the digital message;
means for recovering the bit frequency of the digital message;
means for multiplying the digital message and the bit frequency and providing a multiplied output signal; a bandpass filter for passing a band of frequencies between a predetermined lower and upper frequency; and output means for providing an indication of the presence of the digital message when the magnitude of the output signal from the bandpass filter is less than a predetermined magnitude. The data detector can be operated sLmultaneously with the reception of data, and if valid data is not indicated by the data detector, the received data is discarded. Thus, the reliability of the data communication system of the present invention is enhanced by the data detector.
~ ccording to yet another feature of the present invention;
a clock circuitry for continuously synchronizing to the bit frequency of the digital message is provided that includes means for sensing bit transitions of the digital message and providing a pulse output signal for each bit transition and an oscillator for providing a digital clock signal having a predetermined duty cycle and a free running frequency substantially the same as the bit frequency of the digital message. The oscillator is responsive to the pulse output signal for correcting the phase of the digital clock signal in proportion to ~he phase difference between the bit fre~uency ~l~LZ8~26 and the digital clock signal. Once synchronization to the bit frequency is substantially attained, the oscillator means is no longer responsive to the pulse output signals. The clock circuitry synchronizes to the digital messages rapidly such that a minimum of bit errors are introduced. With a correlatable start code having a predetermined number of bit transitions, the clock circuitry can synchronize with minimal introduction of bit errors so that the start code is still recognizable.
More particularly, there is provided:
A clock circuitry continuously synchronizable to a digital data signal serially transmitted by a data clock . signal having a predetermined frequency, comprising:
delay means coupled to the digital data signal for providing a delayed digital data signal delayed with respect to the digital data signal by a predetermined time interval;
first combining means for combining the digital data signal and the delayed digital data signal to provide a bit transition pulse signal for each bit transition of the digital data signal;
oscillator means for providing an oscillator clock signal having a free-running frequency substantially the same ~`~
as the frequency of the data clock signal, said oscillator `~
means further including Schmitt trigger gatiny means for provid-ing the oscillator clock signal and buffer gating means capaci-tively coupled to the oscillator clock signal from the Schmitt trigger gating means for providing a clock-transition pulse signal for each predetermined logical state change of the oscil-lator clock signal, and second combining means for combining the bit-transition pulse signals and clock-transition pulse signals to provide a phase correction signal and applying the phase correction signal to the Schmitt trigger gating means for synchronizing `
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the phase of the oscillator clock signal to the phase of the data clock signal.
- Additional features, objects and advantages of the data communication system in accordance with the present inven-tion will be more clearly apprehended from the following detailed description together with the accompanying drawing.
Brief Description of the Drawings ____ ___ _ _ Fig. 1 illustrates a data communication system in accordance with the present invention.
Fig. 2 illustrates a typical transmission of data having a start code followed by three data blocks.
Fig. 3 illustrates a 7 x 7 digital data block which has 24 data bits, numbered Dl through D24; 18 parity bits, numbered Pl through P18; and 7 vertical parity bits, numbered VPl through VP7.
Figs. 4A and 4B illustrate partial waveforms of a digital message where a frequency-shift keying ~FSK) waveform is shown in Fig. 4A and the corresponding data waveform is shown in Fig. 4B.
Fig. 5 illustrates a block diagram of a modem for the data communication system of the present invention.
Fig. 6 illustrates a graph of the error voltage re-sulting from data and noise inputs to the phase locked loop for the modem of Fig. 5.
., ~ 5a-. - , .. ., ., ~ . , -286~ Ei Fig. 7 illustrates an embodiment of the data-operated-squelch circuitry for the modem of Fig. 5.
Fig. 8 illustrates an embodiment of the data clock circuitry for the modem of Fig. 5.
Fig. 9 illustrates logical state assignments which may be utilized for the parity portion of the digital messages.
Fig. 10 illustrates a flow chart of a subprogram of the stored program in the modem of Fig. 5 for receiving digital messages.
`10 Fig. 11 illustrates a flow chart of a subprogram of the stored program in the modem of Fig. 5 for transmitting digital messages.
Description of the Preferred Embodiment . .
Referring to Fig. 1, a data communication system embodying the present invention is illustrated where infor-mation is communicated by digital messages between a central station 20, a mobile station 21 and a fixed station 22 over radio channels. The exemplary embodiment is a computer-controlled vehicle monitoring system which is described in US Patent 3,644,883, entitled "Automatic Vehicle Monitoring~
.~ Identification, Location, Alarm and Voice Communication System", by W. M. Borman et al. In this system, the central station 20 is a command and control station that is operated by a dispatcher, the mobile station 21 is a bl~s and the fixed station 22 is a signpost having a predetermined location code. The bus stores the signpost location code when it passes in close proximity to the particular signpost, and relays that information to the command and control station ~or providing the dispatcher with the approximate location ~0 of the bus along its route of t~avel. The bus also com-municates alarm, status and additional information to the - l_77943 ~Z86~6 command and control station over the communication channel.
Voice communications may also take place between the driver of the bus and the dispatcher. Information is communicated between the bus and the command and control station by digital messages, as will be explained hereinafter. Details of the vehicle location system are also described in the Motorola, Inc. instruction manual entitled, "METROCOM Transit Data System and Location System," published by Motorola Sexvice Publications, 1976, Schaumburg, Illinois.
~O The above referenced vehicle monitoring system communicates digital messages between the central station 20, the mobile station 21, and the fixed station 22 which are coded according to audio frequency- shift keying (AFSK) at a frequency of 500 bits per second (500 baud). The information in the digital message is repeated twice and the repetitions are compared at the receiving station for error detection purposes.
However, no error correction or burst error protection is provided.
In Fig. 1, the central station 20 is made up of a radio 0 tranceiver 30, a modem 31, a voice unit 34, and a computer, or microcomputer 32 and its associated peripherals, data storage unit 33, printer 35, display 36 and keyboard 37. A
dispatcher enters information by way of the keyboard 37.
The entered information is converted to a digital message by the computer 32, coded by the modem 31 and transmitted over a radio channel 47 to the mobile station 21 by the transceiver 30. Both transmitted and received digital messages are visually displayed to the dispatcher in ~he display 36, which may be any of a number of displays including alphabetic, 0 graphical, or digital displays.
;, ~ 7 ~_M- 7 7 9 4 3 ~12~36;Z6 The mobile station 21 includes a modem 40, a transceiver 42, a location xeceivex 41 and a control head 43. An operator of the mobile station 21 can talk to the dispatcher by means of the control head 43. Digital messages ar~ coded by the modem 40 and transmitted over the radio channel 47 by the transceiver 42 both automatically and in response to operator directives entered into the control head 43. The location receiver 41 receives a predetermined location code from a fixed station 21 over radio channel 48, which is coded by the modem 40 for transmission to the central station 20.
The fixed station 22 includes a radio transmitter 45 and a location-code encoder 46. Fixed stations 22 are located along the route of the mobile station 21 and are each uniquely assigned a predetermined location code for identifying the particular fixed station 22. The fixed station 22 continuously transmits its predetermined location code on a location radio channel 48 which is different from the data radio channel 47. When a mobile station 21 comes so in close proximity to the fixed station 22, it receives the predetermined location code from the particular fixed station 22 and relays it to the central station 20 auto~
matically. Thus, the positlon of the mobile station 21 along its route of travel can be determined by the central station 20.
The improved data communication system of the present ~.
invention utilizes a signalling system which enhances the reliability of the aforementioned vehicle monitoring system and other prior art systems. Referring to Fig. 2, the O digital message is preceded by a start code 90 after which ` one or more data blocks 91~ 92 and 93 are transmitted. The .. , . -- t~ -- .
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, CM-77~43 start c~de is preferably a correlatable pattern of binary bits that defines the beginning of the first data bl~ck 91 and enables synchroniza~ion to the data fre~uency.
- The start code for use in the data communication system of the present invention is the 32 bit code with the following bit sequence: :
0000101010101101001010~110011011.
The particular data rate utilized i n tlhe data co~nunication system of the present invention ~ay be ~ny practical frequency 10 selected to meet the system requirements ~na specifications.
The data blocks 91, 92 and 93 are organized into a 7 x 7 block of binary bits, although any practical number of words and binary bits can be utilized to practice the present invention. In Fig. 3, the 7 x 7 data block 80 contains 24 15 data bits, numbered Dl through D24; 18 parity bits numbered Pl through P18; ~nd 7 parity bits hereinafter de~ignated ~ vertical parity bits, numbered VPl through YP7.
u A digital word is a horizontal group of bits, for example, Dl through D4 and Pl through P3 being the first digi~al 20 word~ Thus, each word consi~t~ of a ~our-bit data portio~
and a three-bit parity portion. The parity portion is encoded according to a ~zmming code ~or correcting o~e ~rror in the correspona~ng data portion of ~he digit~l w~rd. The particular parity l~its as~ociated with the ~lata portion~ o~
25 the digital words ~re li6~ed i~ F~g. 9, where each digi al word ~ at le~t a P.a~rrming d~3tanc:e of ~ree fro~ the oth~r lig~tal ~ords.
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~ he parity bits of the digital words are selected to satisfy the matrix equation HT = 0, where H is a rectangular 3 x 7 matrix and T is a 1 x 7 column matrix made up of a digital word from the data block, for example the first digital word of the data block 80 in Fig. 3 w~uld be Dl, D2, D3, D4, Pl, P2, P3. For the H matrix shown below, the following equations result for the firs~ digital word where the + sign indicates modulo 2 addition.
.0 D2 For H = 0110011 and T = D4 1010101 Pl then HT = 0 = D4 + Pl + P2 ~ P~
. D2 ~ D3 + P2 ~ P3 Dl + D3 + Pl + P3 If HT ~ O, then a single bit error is assumed to be present and an error correction algorit~m may be performed to correct the erroneous bit.
The matrix organization o the data words is readily adapted to processing by a computer or microcomputer. In :~
the data communication system of the present invention, the receiving and transmitting of the digital messages is per~ormed by a microcomputer having a stored program, utilizing the algori~
depicted in the flow d~ts of Figs. 10 and 11.
The bits of the vertical parity word, which are VP1-VP7 (see Fig. 3), are each derived from the group of six bits in its respective column, for example, VPl is derived from Dl, DS, D9, D13, D17 and D210 The vertical pari~y bits are derived according to a predetermined format such that none of the col~mns of bits contain all zeros or all ones. For instance, the vertical parity bit can be selected t~ be a .'- . .
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~~77943 ~Z862~
logical one when all other bits in its respective column are logical zeros, and or all other conditions the vertical parity bit is a logical zero. By selecting the vertical parity bits in this manner, the low frequency content of the transmitted data block is reduced, which allows a correspond-ing reduction in the bandwith of the modem which decreases low frequency noise interference. In addition, the vertical parity bits enable the detection of a double error in at least one of the digital words. The vertical parity bits obtained in the aforementioned mannex forms a parity word for the system.
The digital message, transmitted over the communication channel as shown in Fig. 2, is interleaved during trans-mission to provide burst error protection. Interleaving of the digital message is accomplished by transmitting the columns of binary bits (see Fig. 3) sequentially, instead of transmitting one entire digital word after another. For example, the data block 80 of Fig. 3 would be transmitted in the following se~uence; Dl, D5, D9, D13, D17, D21, VPl, D2, ~0 D6, etc. Interleaving the bits of the digital message results in a maximum fade margin o~ 7 consecutive erroneous bits. If 7 consecutive bits are in error, then each data word has at most one bit in error which is correctable by use of the Hamming code.
The digital messages are transmitted over the com-munication channel by means of coherent audio frequency-shift keying. Coherent operation is characterized by trans-~" mission of audio tones which are rationally related to each other, with transmission of each bi~ initiated at a constant and defined phase relationship. Further, the digital messagesare transmitted by means of minimum shift keying (MSR).
~;~ Minimum shift keying operation is characterized by the audio .
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M-77943 1 lZ86Z~ , ; tone for the logical one state being equal to the data frequency and the audio tone representing the logical zero state being equal to 1 1/2 times the data frequency. Each data bit starts and ends on a zero crossing of the respec-tive tones. In the preferred em~odiment, the tones selected are 1000 Hz for a mark and 1500 Hz for a space. A mark corresponds to a data bit having a logical one state and a space corresponds to a data bit having a logical zero state.
Referring to Figs. 4a and 4b, a portion of a digital message is shown where Fig. 4a i5 a waveform of the MSK data and Fig. 4b is a waveform of the demodulated data.
By using MSK with tones of 1000 Hz and 1500 Hz, the spectral energy is contained substantially within the band of frequencies from 800 Hz to 1700 Hz. Such a bandwith is compatible with data communications systems operating over radio communication channels or telephone wire lines. In the preferred embodiment, the frequency of the data which is referred to as 1000 baud, in actuality, is 1075.28 baud which was selected as close as possible to 1000 baud while still being compatible with the frequency of operation of the microcomputer in the modem~
Referring to Fig. 5, a block diagram illustrates more clearly an embodiment of a modem for the data communication system of the present invention. The MSK input data is first connected to the input filter shown 50. The purpose of this filter is to provide somé pre-filterin~ action to limit the input bandwith to only that occupied by the MSK
illput data and to reject noise falling outside this band.
~ For example, it may be comprised of four poles of high '`30 frequency at 1800 ~z and two poles of low frequency roll off, thereby providing an input filter which is generally a bandpass filter occupying the band 800 ~z to 1700 Hz. The .
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M-77943 ~Z~6~
output of the input filter 50 is then amplified and limited by the limiter 51. The purpose of the limiter 51 is to provide a square wave signal to the phase comparator 52 of the phase locked loop 70. Therefore, the MSK input data is translated into zero-crossing information by the lImiter 51, which is then processed by the phase locked loop 70.
The phase locked loop 70 includes a phase comparator 52, a loop filter 53, a voltage controlled oscillator (VCO) 54 and a divider 55. The phase comparator 52 compares the incoming phase of the limited MSK input data to that of the VCO 54 through the divider 55. It then provides an output voltage to the loop filter 53 indicating that the frequency of the VCO 54 is either too high or too low for correcting the frequency of the voltage control oscillator.
The loop filter 53 is tailored to reject noise which ma~ be introduced by either the phase locked loop 70 itself or the MSK input data through a noisy signal. The bandwidth of the loop filter 53 is therefore controlled to be only ~ that necessary for the data, which is approximately 500 Hz ? ~0 for MSK input data at 1000 baud. The loop filter 53 not only limits the bandwidth in the phase locked loop 70, but also maintains the stability of the phase locked loop 70.
The error voltage 73 from the loop filter 53 is then fed into the VCO 54. The output of the VCO 54 is approximately sixteen times the frequency of the MSK input data and is fed into a divider 55 for dividing the VCO output by sixteen.
Operating the VCO 54 at sixteen times the frequency o the ~` MSK input da~a provides better protection against noise and allows improved operation of the phase locked loop 70.
~30 The error voltage 73 from the loop filter 53 contains the recovered data together with high frequency components.
The errox voltage 73 is coupled to the data-operated squelch :.
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circuitry 71 and a data filter 6Q. The data filter 60 is a low pass filter for removing the input data from the error voltage 73, where the data is contained substantially within the frequency band from 0 Hz to 500 Hz. The data filter 60 ` is optimized to closely match the characteristics of input data carried on the error voltage 73.
The data limiter 61 then provides mark and space (see Figs. 4A and 4B) information by a conventional bit slicing pro-cess. If the input data is more generally of mark frequency, the output of the data limiter 61 is a logical one. If the input data is generally more of a space frequency, the output of the data limiter 61 is a logical zero. The output of the data limiter 61 is the recovered input data which is coupled to the data clock circuitry 72 and the microcomputer 64. The data clock circuitry 72 utilizes the transitions of the recovered input data from the data limiter 61 for synchronizing to the input data frequency. The data sync pulse 62 provides a sync pulse for each transition of the recove.red input data. The sync pulses are applied to the data clock 63 for phase synchronizing the data clock 63 to the data frequency. In the absence of sync pulses, the data clock 63 free runs at the data frequencyt 1000 ` baud in the exemplary embodiment. The output of the data clock 63 is approximately a 1000 Hz square wave with fifty percent duty cycle and is applied to the microcomputer 64. An ex~mplary embo-` diment of the blocks 62 and 63 of the data clock circuitry 72 is illustrated in detail in Fig. 8.
`~ The data-operated-squelch (DOS~ circuitry 71 includes ~` a squelch filter 57, a detector and ~,te~rator 58 and a Schmitt trigger 59. The output of the Schmitt trigger is a logical zero when data has been detected and is applied to the micro-computer 64. The data-operated-squelch circuitry 71, a~curately discriminates data from noise, voice, or music. An exemplary ` embodiment of the blocks 57, 5B and 59 of the DOS circuitry 71 i~; is illustrated in detail in Fig. 7.
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A computer ~tesn~ which contrc~ls the 5 eration of the modem, includes a microcomputer 64, a c:ry5t~1 o~;cillator 65, keyboard 66, a display 67, and a location da~a interface 6R. The computer ~y5tem 1::2U~ utili2e any of a rl~ber of 5 commercially available microcomputers or computers, ~or èx~mple, the Motorola~qC6801 or the combination of the MC6802 and MC6846. The crystal oscillator 65 provides ~he operatïng fre~uency fox the microcomputer 64. ~he ~icro-computer 64 receivss operator inIorma~ n ~rom ~he keyboard 10 66 and location da~ca fror~ ~he loc~tion dat;~ rfac:e 68 and provi des information to ~n operator in ~he display 67 0 The keyboard 66, display 67 and lo~ation datzl interface 68 (see ~foreme~tio~ed Uo5~ Patent 3,644,~83) ~re interconnected with the ~nicroco~nputa,r 64 via ~ddress and d ta bus .15 lines in a conventional manner. Furthermore, all interface con-nections to the ~ crocomputer 64 ~an ge readily ccomplished by one skilled in ~he art by conventional technigues. For example, where the ~ crocomputer 64 is ~he ~C6801, one ~ay refer to ~he published specifica~ion ~or ~he ~C6801 ~o de~e ~ ne ~peci~ic interconnections to the MC6801 por~s. When using an MC6801, ~he <~ key~oard 66, display ~7 a~d locatio~ data in~erface 68 ~ay be connec~ed ~o parallel ~ddress and data por~s, whlle ~h2 encode ~ilter 56, DO5 circuitry 71, dat~ lLmi~es 61 and elock circui~ry 72 may ~e connected ~o ~ingl~-line i~pu~ou~put-port~.
` 25 ~or re~eiv~ng digit~l ~essa~es, ~he ~$cxo~omputer 64 : assemblQs.and de-interle~ves ~he recovered i~put data from the d ta limiter 61 as def~n~d by the recover~d data ~re;
quency from the dat~ clock 63. ~f an indication ~hat ~ata . ., ~ 1B pre~ent iR not re~eived rom ~he ~ataroper~ted-sgu~lch .` 30 circuitry 71, the re~ived digital me~sage will ~e ignored.
Also, if the recover~d input data b~s ~ore th~n on~ error in ~t le~st one WOr~9 the xsceiv~ d~it~l me~ i8 i~al~d.
For tran~ sion of i~ ation the m~cro~o~put~r 64 ~ ~.
arranges the information into a digital message having a start code followed by requisite data blocks and applies the di-gital message in MSK format to the encode filter 56. The encode filter 56 takes the digital waveform from the micro-computer 64 and provides the sinusoidal MSK output data for transmission on ~he communication channel.
The data operated sguelch ~DOS) circuitry 71 of Fig. 5 is illustrated more clearly in the embodiment shown in Fig~
7. The DOS circuitry utilizes the error voltage of a phase 10 locked loop for discriminating data from noise, voicet or music. When noise is present, ~he error voltage is greater and has an essentially flat fre~uency response characteristic .
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-15a-8M-77943 ~Z86~
121, as shown by the dotted line in Fig. 6. However, when data is present and the phase locked loop is locked, the frequency characteristic 120 of the error voltage will have components below 500 cycles a substantially dead band from 500 Hz to approximately 1700 Hz and noise and harmonics above 2000 Hz. The components of the error voltage above 2000 Hz are caused by the maintenance capability within the phase locked loop itself. But, there is a dead band centered generally around 1000 Hz only when data is pre~ent and under no other conditions. This dead band then can be used to provide an indication of data. As the strength of the MSK
input data gets lower and lower, the data frequency charactPr-istic 120 gradually approaches the noise frequency character-istic 121. The foregoing is also true of voice signals, music, inter-modulation distortion or other interfering ~" signals. Thus, the DOS circuitry can determine the differ-ence between data and anything else from the frequency ~` characteristic 120 of the error voltage in the vicinity of 1000 Hz. In the preferred embodiment of the system, the DOS
~0 circuitry 71 can be essentially 100 percent effective in differentiating between noise and data and is greater than 99 percent effective in distinguishing between voice and data.
Referring to Fig. 7, the DOS circuitry 71 includes a squelch filter 5 ?, a detector and integrator 58, and a Schmitt trigger 59. A bandpass filter 57 i5 used to filter out the dead-band portion of the error voltage. The band-pass filter 57 is of reasonably low Q centered at around ~ 1000 Hz. The output signal from the filter 57 is then : 30 detected and integrated by the detector and integrator 58~
The output of the detector and integrator 58 is applied to the Schmitt trigger or comparator 59 which then provides a . :
~-77943 ~2~
digital output signal that is a logical zero indicating the presence of data when the output of the detector and integra-tor is below a predetermined threshold level. The DOS
circuitry 71 can be made from conventional circuitry by one sXilled in the art.
The DOS output signal indicates the presence of valid data to the microcomputer 64 of the modem (see Fig. 5). The reliability of the data communication system is enhanced since the DOS circuitry substantially reduces the probability of falsing due to noise, voice, music, or other interfering signals.
; The data clock cicuitry 72 of Fig. 5 is more clearly illustrated in the embodiment shown in Fig. 8. The data clock circuitry 72 includes a data sync pulse circuit 62 and a data clock circuit 63. The data sync pulse circuit 6Z
provides a data sync pulse 150 derived from the recovered input data. The data sync pulse 150 is a narrow pulse ~-~ occurring at each transition of recovered input data, that ; is, on a mark to a space transition, data sync pulse 150 occurs and on a space to mark transition, data sync pulse 150 occurs. The data sync pulse 150 can be generated from the xecovered input data by a conventional circuit using an exclusive-or gate 154. The data sync pulse 150 is applied to the data clock circuit 63 to synchronize the phase of the data clock to the frequency of the recovered input data.
The data clock circuit 63 utilizes a Schmitt tri~ger gate 155 which is arranged as an oscillator and free runs at the data frequency, 1000 Hz. A phantom sync pulse 151 is derived ~rom the data clock signal by gate 156 and associated electrical components. The phantom sync pulse 151 is a narrow pulse occurring at the data d ock frequency on the transition from logical one to logical zero of the data - clock signal.
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CM-77943 ~ ~ ~
8~6 The phantom sync pulse 151 is combined by logical or means, diodes in the embodiment of Fig. 8, with the data sync pulse 150 to provide composite signal 152. If the recovered input data is in synchronization with the data clock signal, no correction to the Schmitt trigger oscil-lator 155 is needed, nor is wanted. The phantom sync pulse 151 will cover up the data sync pulse 150 when synchronism is reached so that the data clock signal is not subjec~ to small corrections. If the recovered input data and data clock are not in synchronism, then the data sync pulse 150 is uncovered with respect to the phantom sync pulse 151.
The further apart these two sync pulses 150 and 151 are, the ` more correction is provided by composite signal 152 to the Schmitt trigger oscilIator 155. This operation provides the benefits of an adaptive phase locked loop without the . stability problems associated with such a phase locked loop.
Furthermore, the data clock circuitry 63 provides the advantageous operation of an infinitely adaptive phase locked loop, that is, if the correction required between the incoming data and the phase of the data cloc~ is low, no correction is provided. As more correction is needed, more correction is provided up to a maximum amount of correction.
Due to the variable correction capability, the time xequired ; for sync~ronization of the clock recovery circuitry 63 is minLmized.
Figs. tO and 11 illustrate flow charts of sub-pr~grams of the modem stored program fo~ receiving and transmitting : digital messageS, respectively~ me flcw charts of Fig. 10 and 11 represent the logi~ sequences of operations that mus~ be performed in order to receive and transmit digital messages, respec~ively. The flow charts of Figs. 10 and 11 are explicit descriptionS of the microcomputer algorithms necessary to achieve the desired function By referring to the flow chartg o~ Figs. 10 and 11, one of ordinary - skill in the programming ar~ may code the appropriate combination 18~
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of instructions for a par~icular microcomputer to satisfy the operations called for in each block of the respective flow charts-The coding of the flow charts of Pigs. 10 and 11 may be accomplished in any suitable manner using the instructions of the particular microcomputer, for example, such as the instructions of the ~C6801. The operations and processes specified in each block of the flow charts of Figs. 10 and 11 are further supplemented in ~he foregoing description.-In Fig. 10, the flow chart of the subprogram for receiving a digital message begins at START terminal 300. Preceding to box 301, the start code is received and stored in the memory of the microcomputer. Next, when the entire start code has been received, the ~ .
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-18a-start code is checked and correlated with the predetermined start code stored in the memory of the microcomputer, as shown in box 302~ In the preferred embodiment~ the start ` code can have as many as five bits out of 32 bits which are in error and still recognize the received start code.
Preceding to decision box 303, if the start code is correctly received, the YES branch 305 is taken to decision box 306, otherwise the NO brançh 304 is taken to return along path 319 to box 301.
~` 10 The reception of the start code has provided sufficient time for the data-opera~ed-squelch circuitry to detect the presence of valid data. In decision box 306, if the data-operated-squelch circuitry has been activated, the YES
branch 308 is taken to box 309, otherwise the NO branch 307 is taken to return along path 319 to box 301.
Next, the data blocks following the start code are received and stored into the memory of the microcomputer, as shown in box 309. Depending on the configuration of the data communication system, one or more data blocks are received before proceeding to the decision box 310. Next, ; at decision box 310, if the data-operated-squelch circuitry .. is still activated, the YES path 312 is taken to box 313, otherwise a NO path 311 is taken to return along path 319 to ;~
box 301.
- According to box 313, the received data blocks are corrected using .the parity portion of each data word to correct the respective data portion. Finally, a vertical parity word is generated fox each corrected data block, as shown in box 314. Then in decision box 315, the generated vertical parity word is compared with the received vertical parity word and i they are identical, YES branch 317 is taken to terminal 318, otherwise the NO branch 316 is taken CM-77943 ~286~6 to return along path 319 to box 301. A valid digital message has been received when reaching the CONTINUE terminal 318 which is the end of this subprogram.
In Fig. 11, a flow chart of a subpro~ram for trans-mitting a digital message begins at the start terminal 400 and proceeds to box 401. First, the start code which is stored in a predetermined location in the microcomputer memory is transmitted with an MSK bit pa~tern. Next in box 402, the selected data block is transmitted in an MSK format also. Proceeding to decision box 403, if the last data block has been transmitted, YES branch 405 is taken to RETURN terminal 406, otherwise NO branch 404 is taken to ` return to box 402. RETURN terminal 406, the end o~ this subprogram, is reached when all of the data blocks for a particular digital message have been transmitted.
:.~ Severàl features of the data communications system in accordance with the present invention have a wider applica-bility which can be advantageously utilized in any communica-tion system. For example, the use of MSK si~nalling has provided optimum bit error performance with a minimum of frequency bandwith. The digital messages can be readily expanded to provide any number of data blocks. System reliability has been provided by use of the error correcting code, interleaving the data bits during transmission, and the data-operated-squelch circuitry 71 for discriminating between data and noise or voice. The data-operated-squelch circuitry 71 permits the communication channel to be used for both data and voice without degradation in system reliability. Data clock circuitry 72 has been provided that adaptively sychronizes to the data frequency and operates at the data frequency when synchronizing information is not available. These and other features described hereinabove .
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CM-77943 ~8626 ., .
can be advantageously utilized in any system for reliably communicating information.
The foregoing embodiments have been intended as illustra-~; tions of the principles of the present invention. Accordingly, other modifications, uses and embodiments can be devised by ~` those skilled in the art without departing from the spirit and scope of the principles of the present invention.
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Background of the_Invention 1. Fiield of the Invention This invention relates to a data communication system, O and, more particularly, to an improved method and apparatus ~or a data communication system utilizing a coded digital signalling system.
27 Description of the Pxior Ar~ `
: In order to expand the capacity of a communication system, one may add more communication channels to ~he ~ 77943 ~Z86Z6 system or increase the amount of information carried on each of the existing communication channe]s. Since the number of communication channels is limited for most systems, it has been more practical to increase the amount of information carried on each communication channel by various methods, for example, multiplexing and digital techniques. The communication systems using these concentrating techniques must be reliable to insure that the information is not lost.
The reliability of communication syst~ms using digital messages may be enhanced by using such techniques as error correcting coaes and multiple transmissions of the digital messages. However, prior art communication systems, such as radio communication systems, are still prone to burst errors and have yet to realize optimal usage of error correcting and detecting techniques in a bandwith limite~ system. This is especially the case with radio communication systems where interference and fading must be accommodated.
For the foregoing and other shortcomings and problems, there has been a long felt need for an improved data com-O munication system.
Summar~ of the Invention Accordingly, it is a general object of the present invention to provide an improved data communication system.
It a further object of the present invention to provide a more reliable data communication system.
It is still a further object of the present invention to provide an improved data communication system that pro-vides random and burst error protection and correction.
It is yet a further object of the present invention to provide an improved data communication system that can .
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~M-77943 , recognize the presence of noise or voice to pro~ide additonal protection against the reception of invalid digital messages.
In accordance with the present invention, the afore-mentioned problems and shortcomings of the prior art are overcome and the stated and other objects are attained by an improved digital data communication system that includes a central station and a plurality of mobile stations. The system may further include one or more fixed stations for providing relevant information, such as geographical location information, to the mobile stations. Communication channels of the system may carry voice between the operator of the mobile station and the dispatcher at the central station without affecting the reliability of the digital message transmissions.
In accordance with a feature of the present invention, digital messages are transmitted after a start code of a predetermined nature. The digital message is formated into ; at least one data block having N digital words, each word having M binary bits, where M and N are integer numbers.
~0 The start code has a predetermined number of binary bits, for example thirty-two, organized in a highly correlatable pattern for defining the beginning of the first data block of the ditital message. The N digital word~ of a data block include at least one parity word and N-l data words. Each of the data words has a data portion and a parity portion coded for correction of at least one bit which is in error in the data portion. For example, the parity portion can be coded according to a Hamming code. The parity word has M
binary bits which are each derived according to a predetermined ~10 format from the group of corresponding bits taken from the N-l data words. The parity word may be chosen so that it _ 3 - :
does not include long strings of logical zero or logical one bits. This is beneficial in limiting the low frequency content of the digital message and pxoviding bit transitions to enable synchronization to the data frequencyO
According to an ~ or~t feature of the present invention, a detector of a coded digital message ls provided that can discriminate data from noise, voice, or music. The data detector includes means for decoding the digital message;
means for recovering the bit frequency of the digital message;
means for multiplying the digital message and the bit frequency and providing a multiplied output signal; a bandpass filter for passing a band of frequencies between a predetermined lower and upper frequency; and output means for providing an indication of the presence of the digital message when the magnitude of the output signal from the bandpass filter is less than a predetermined magnitude. The data detector can be operated sLmultaneously with the reception of data, and if valid data is not indicated by the data detector, the received data is discarded. Thus, the reliability of the data communication system of the present invention is enhanced by the data detector.
~ ccording to yet another feature of the present invention;
a clock circuitry for continuously synchronizing to the bit frequency of the digital message is provided that includes means for sensing bit transitions of the digital message and providing a pulse output signal for each bit transition and an oscillator for providing a digital clock signal having a predetermined duty cycle and a free running frequency substantially the same as the bit frequency of the digital message. The oscillator is responsive to the pulse output signal for correcting the phase of the digital clock signal in proportion to ~he phase difference between the bit fre~uency ~l~LZ8~26 and the digital clock signal. Once synchronization to the bit frequency is substantially attained, the oscillator means is no longer responsive to the pulse output signals. The clock circuitry synchronizes to the digital messages rapidly such that a minimum of bit errors are introduced. With a correlatable start code having a predetermined number of bit transitions, the clock circuitry can synchronize with minimal introduction of bit errors so that the start code is still recognizable.
More particularly, there is provided:
A clock circuitry continuously synchronizable to a digital data signal serially transmitted by a data clock . signal having a predetermined frequency, comprising:
delay means coupled to the digital data signal for providing a delayed digital data signal delayed with respect to the digital data signal by a predetermined time interval;
first combining means for combining the digital data signal and the delayed digital data signal to provide a bit transition pulse signal for each bit transition of the digital data signal;
oscillator means for providing an oscillator clock signal having a free-running frequency substantially the same ~`~
as the frequency of the data clock signal, said oscillator `~
means further including Schmitt trigger gatiny means for provid-ing the oscillator clock signal and buffer gating means capaci-tively coupled to the oscillator clock signal from the Schmitt trigger gating means for providing a clock-transition pulse signal for each predetermined logical state change of the oscil-lator clock signal, and second combining means for combining the bit-transition pulse signals and clock-transition pulse signals to provide a phase correction signal and applying the phase correction signal to the Schmitt trigger gating means for synchronizing `
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the phase of the oscillator clock signal to the phase of the data clock signal.
- Additional features, objects and advantages of the data communication system in accordance with the present inven-tion will be more clearly apprehended from the following detailed description together with the accompanying drawing.
Brief Description of the Drawings ____ ___ _ _ Fig. 1 illustrates a data communication system in accordance with the present invention.
Fig. 2 illustrates a typical transmission of data having a start code followed by three data blocks.
Fig. 3 illustrates a 7 x 7 digital data block which has 24 data bits, numbered Dl through D24; 18 parity bits, numbered Pl through P18; and 7 vertical parity bits, numbered VPl through VP7.
Figs. 4A and 4B illustrate partial waveforms of a digital message where a frequency-shift keying ~FSK) waveform is shown in Fig. 4A and the corresponding data waveform is shown in Fig. 4B.
Fig. 5 illustrates a block diagram of a modem for the data communication system of the present invention.
Fig. 6 illustrates a graph of the error voltage re-sulting from data and noise inputs to the phase locked loop for the modem of Fig. 5.
., ~ 5a-. - , .. ., ., ~ . , -286~ Ei Fig. 7 illustrates an embodiment of the data-operated-squelch circuitry for the modem of Fig. 5.
Fig. 8 illustrates an embodiment of the data clock circuitry for the modem of Fig. 5.
Fig. 9 illustrates logical state assignments which may be utilized for the parity portion of the digital messages.
Fig. 10 illustrates a flow chart of a subprogram of the stored program in the modem of Fig. 5 for receiving digital messages.
`10 Fig. 11 illustrates a flow chart of a subprogram of the stored program in the modem of Fig. 5 for transmitting digital messages.
Description of the Preferred Embodiment . .
Referring to Fig. 1, a data communication system embodying the present invention is illustrated where infor-mation is communicated by digital messages between a central station 20, a mobile station 21 and a fixed station 22 over radio channels. The exemplary embodiment is a computer-controlled vehicle monitoring system which is described in US Patent 3,644,883, entitled "Automatic Vehicle Monitoring~
.~ Identification, Location, Alarm and Voice Communication System", by W. M. Borman et al. In this system, the central station 20 is a command and control station that is operated by a dispatcher, the mobile station 21 is a bl~s and the fixed station 22 is a signpost having a predetermined location code. The bus stores the signpost location code when it passes in close proximity to the particular signpost, and relays that information to the command and control station ~or providing the dispatcher with the approximate location ~0 of the bus along its route of t~avel. The bus also com-municates alarm, status and additional information to the - l_77943 ~Z86~6 command and control station over the communication channel.
Voice communications may also take place between the driver of the bus and the dispatcher. Information is communicated between the bus and the command and control station by digital messages, as will be explained hereinafter. Details of the vehicle location system are also described in the Motorola, Inc. instruction manual entitled, "METROCOM Transit Data System and Location System," published by Motorola Sexvice Publications, 1976, Schaumburg, Illinois.
~O The above referenced vehicle monitoring system communicates digital messages between the central station 20, the mobile station 21, and the fixed station 22 which are coded according to audio frequency- shift keying (AFSK) at a frequency of 500 bits per second (500 baud). The information in the digital message is repeated twice and the repetitions are compared at the receiving station for error detection purposes.
However, no error correction or burst error protection is provided.
In Fig. 1, the central station 20 is made up of a radio 0 tranceiver 30, a modem 31, a voice unit 34, and a computer, or microcomputer 32 and its associated peripherals, data storage unit 33, printer 35, display 36 and keyboard 37. A
dispatcher enters information by way of the keyboard 37.
The entered information is converted to a digital message by the computer 32, coded by the modem 31 and transmitted over a radio channel 47 to the mobile station 21 by the transceiver 30. Both transmitted and received digital messages are visually displayed to the dispatcher in ~he display 36, which may be any of a number of displays including alphabetic, 0 graphical, or digital displays.
;, ~ 7 ~_M- 7 7 9 4 3 ~12~36;Z6 The mobile station 21 includes a modem 40, a transceiver 42, a location xeceivex 41 and a control head 43. An operator of the mobile station 21 can talk to the dispatcher by means of the control head 43. Digital messages ar~ coded by the modem 40 and transmitted over the radio channel 47 by the transceiver 42 both automatically and in response to operator directives entered into the control head 43. The location receiver 41 receives a predetermined location code from a fixed station 21 over radio channel 48, which is coded by the modem 40 for transmission to the central station 20.
The fixed station 22 includes a radio transmitter 45 and a location-code encoder 46. Fixed stations 22 are located along the route of the mobile station 21 and are each uniquely assigned a predetermined location code for identifying the particular fixed station 22. The fixed station 22 continuously transmits its predetermined location code on a location radio channel 48 which is different from the data radio channel 47. When a mobile station 21 comes so in close proximity to the fixed station 22, it receives the predetermined location code from the particular fixed station 22 and relays it to the central station 20 auto~
matically. Thus, the positlon of the mobile station 21 along its route of travel can be determined by the central station 20.
The improved data communication system of the present ~.
invention utilizes a signalling system which enhances the reliability of the aforementioned vehicle monitoring system and other prior art systems. Referring to Fig. 2, the O digital message is preceded by a start code 90 after which ` one or more data blocks 91~ 92 and 93 are transmitted. The .. , . -- t~ -- .
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, CM-77~43 start c~de is preferably a correlatable pattern of binary bits that defines the beginning of the first data bl~ck 91 and enables synchroniza~ion to the data fre~uency.
- The start code for use in the data communication system of the present invention is the 32 bit code with the following bit sequence: :
0000101010101101001010~110011011.
The particular data rate utilized i n tlhe data co~nunication system of the present invention ~ay be ~ny practical frequency 10 selected to meet the system requirements ~na specifications.
The data blocks 91, 92 and 93 are organized into a 7 x 7 block of binary bits, although any practical number of words and binary bits can be utilized to practice the present invention. In Fig. 3, the 7 x 7 data block 80 contains 24 15 data bits, numbered Dl through D24; 18 parity bits numbered Pl through P18; ~nd 7 parity bits hereinafter de~ignated ~ vertical parity bits, numbered VPl through YP7.
u A digital word is a horizontal group of bits, for example, Dl through D4 and Pl through P3 being the first digi~al 20 word~ Thus, each word consi~t~ of a ~our-bit data portio~
and a three-bit parity portion. The parity portion is encoded according to a ~zmming code ~or correcting o~e ~rror in the correspona~ng data portion of ~he digit~l w~rd. The particular parity l~its as~ociated with the ~lata portion~ o~
25 the digital words ~re li6~ed i~ F~g. 9, where each digi al word ~ at le~t a P.a~rrming d~3tanc:e of ~ree fro~ the oth~r lig~tal ~ords.
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~ he parity bits of the digital words are selected to satisfy the matrix equation HT = 0, where H is a rectangular 3 x 7 matrix and T is a 1 x 7 column matrix made up of a digital word from the data block, for example the first digital word of the data block 80 in Fig. 3 w~uld be Dl, D2, D3, D4, Pl, P2, P3. For the H matrix shown below, the following equations result for the firs~ digital word where the + sign indicates modulo 2 addition.
.0 D2 For H = 0110011 and T = D4 1010101 Pl then HT = 0 = D4 + Pl + P2 ~ P~
. D2 ~ D3 + P2 ~ P3 Dl + D3 + Pl + P3 If HT ~ O, then a single bit error is assumed to be present and an error correction algorit~m may be performed to correct the erroneous bit.
The matrix organization o the data words is readily adapted to processing by a computer or microcomputer. In :~
the data communication system of the present invention, the receiving and transmitting of the digital messages is per~ormed by a microcomputer having a stored program, utilizing the algori~
depicted in the flow d~ts of Figs. 10 and 11.
The bits of the vertical parity word, which are VP1-VP7 (see Fig. 3), are each derived from the group of six bits in its respective column, for example, VPl is derived from Dl, DS, D9, D13, D17 and D210 The vertical pari~y bits are derived according to a predetermined format such that none of the col~mns of bits contain all zeros or all ones. For instance, the vertical parity bit can be selected t~ be a .'- . .
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~~77943 ~Z862~
logical one when all other bits in its respective column are logical zeros, and or all other conditions the vertical parity bit is a logical zero. By selecting the vertical parity bits in this manner, the low frequency content of the transmitted data block is reduced, which allows a correspond-ing reduction in the bandwith of the modem which decreases low frequency noise interference. In addition, the vertical parity bits enable the detection of a double error in at least one of the digital words. The vertical parity bits obtained in the aforementioned mannex forms a parity word for the system.
The digital message, transmitted over the communication channel as shown in Fig. 2, is interleaved during trans-mission to provide burst error protection. Interleaving of the digital message is accomplished by transmitting the columns of binary bits (see Fig. 3) sequentially, instead of transmitting one entire digital word after another. For example, the data block 80 of Fig. 3 would be transmitted in the following se~uence; Dl, D5, D9, D13, D17, D21, VPl, D2, ~0 D6, etc. Interleaving the bits of the digital message results in a maximum fade margin o~ 7 consecutive erroneous bits. If 7 consecutive bits are in error, then each data word has at most one bit in error which is correctable by use of the Hamming code.
The digital messages are transmitted over the com-munication channel by means of coherent audio frequency-shift keying. Coherent operation is characterized by trans-~" mission of audio tones which are rationally related to each other, with transmission of each bi~ initiated at a constant and defined phase relationship. Further, the digital messagesare transmitted by means of minimum shift keying (MSR).
~;~ Minimum shift keying operation is characterized by the audio .
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M-77943 1 lZ86Z~ , ; tone for the logical one state being equal to the data frequency and the audio tone representing the logical zero state being equal to 1 1/2 times the data frequency. Each data bit starts and ends on a zero crossing of the respec-tive tones. In the preferred em~odiment, the tones selected are 1000 Hz for a mark and 1500 Hz for a space. A mark corresponds to a data bit having a logical one state and a space corresponds to a data bit having a logical zero state.
Referring to Figs. 4a and 4b, a portion of a digital message is shown where Fig. 4a i5 a waveform of the MSK data and Fig. 4b is a waveform of the demodulated data.
By using MSK with tones of 1000 Hz and 1500 Hz, the spectral energy is contained substantially within the band of frequencies from 800 Hz to 1700 Hz. Such a bandwith is compatible with data communications systems operating over radio communication channels or telephone wire lines. In the preferred embodiment, the frequency of the data which is referred to as 1000 baud, in actuality, is 1075.28 baud which was selected as close as possible to 1000 baud while still being compatible with the frequency of operation of the microcomputer in the modem~
Referring to Fig. 5, a block diagram illustrates more clearly an embodiment of a modem for the data communication system of the present invention. The MSK input data is first connected to the input filter shown 50. The purpose of this filter is to provide somé pre-filterin~ action to limit the input bandwith to only that occupied by the MSK
illput data and to reject noise falling outside this band.
~ For example, it may be comprised of four poles of high '`30 frequency at 1800 ~z and two poles of low frequency roll off, thereby providing an input filter which is generally a bandpass filter occupying the band 800 ~z to 1700 Hz. The .
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M-77943 ~Z~6~
output of the input filter 50 is then amplified and limited by the limiter 51. The purpose of the limiter 51 is to provide a square wave signal to the phase comparator 52 of the phase locked loop 70. Therefore, the MSK input data is translated into zero-crossing information by the lImiter 51, which is then processed by the phase locked loop 70.
The phase locked loop 70 includes a phase comparator 52, a loop filter 53, a voltage controlled oscillator (VCO) 54 and a divider 55. The phase comparator 52 compares the incoming phase of the limited MSK input data to that of the VCO 54 through the divider 55. It then provides an output voltage to the loop filter 53 indicating that the frequency of the VCO 54 is either too high or too low for correcting the frequency of the voltage control oscillator.
The loop filter 53 is tailored to reject noise which ma~ be introduced by either the phase locked loop 70 itself or the MSK input data through a noisy signal. The bandwidth of the loop filter 53 is therefore controlled to be only ~ that necessary for the data, which is approximately 500 Hz ? ~0 for MSK input data at 1000 baud. The loop filter 53 not only limits the bandwidth in the phase locked loop 70, but also maintains the stability of the phase locked loop 70.
The error voltage 73 from the loop filter 53 is then fed into the VCO 54. The output of the VCO 54 is approximately sixteen times the frequency of the MSK input data and is fed into a divider 55 for dividing the VCO output by sixteen.
Operating the VCO 54 at sixteen times the frequency o the ~` MSK input da~a provides better protection against noise and allows improved operation of the phase locked loop 70.
~30 The error voltage 73 from the loop filter 53 contains the recovered data together with high frequency components.
The errox voltage 73 is coupled to the data-operated squelch :.
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circuitry 71 and a data filter 6Q. The data filter 60 is a low pass filter for removing the input data from the error voltage 73, where the data is contained substantially within the frequency band from 0 Hz to 500 Hz. The data filter 60 ` is optimized to closely match the characteristics of input data carried on the error voltage 73.
The data limiter 61 then provides mark and space (see Figs. 4A and 4B) information by a conventional bit slicing pro-cess. If the input data is more generally of mark frequency, the output of the data limiter 61 is a logical one. If the input data is generally more of a space frequency, the output of the data limiter 61 is a logical zero. The output of the data limiter 61 is the recovered input data which is coupled to the data clock circuitry 72 and the microcomputer 64. The data clock circuitry 72 utilizes the transitions of the recovered input data from the data limiter 61 for synchronizing to the input data frequency. The data sync pulse 62 provides a sync pulse for each transition of the recove.red input data. The sync pulses are applied to the data clock 63 for phase synchronizing the data clock 63 to the data frequency. In the absence of sync pulses, the data clock 63 free runs at the data frequencyt 1000 ` baud in the exemplary embodiment. The output of the data clock 63 is approximately a 1000 Hz square wave with fifty percent duty cycle and is applied to the microcomputer 64. An ex~mplary embo-` diment of the blocks 62 and 63 of the data clock circuitry 72 is illustrated in detail in Fig. 8.
`~ The data-operated-squelch (DOS~ circuitry 71 includes ~` a squelch filter 57, a detector and ~,te~rator 58 and a Schmitt trigger 59. The output of the Schmitt trigger is a logical zero when data has been detected and is applied to the micro-computer 64. The data-operated-squelch circuitry 71, a~curately discriminates data from noise, voice, or music. An exemplary ` embodiment of the blocks 57, 5B and 59 of the DOS circuitry 71 i~; is illustrated in detail in Fig. 7.
8~
A computer ~tesn~ which contrc~ls the 5 eration of the modem, includes a microcomputer 64, a c:ry5t~1 o~;cillator 65, keyboard 66, a display 67, and a location da~a interface 6R. The computer ~y5tem 1::2U~ utili2e any of a rl~ber of 5 commercially available microcomputers or computers, ~or èx~mple, the Motorola~qC6801 or the combination of the MC6802 and MC6846. The crystal oscillator 65 provides ~he operatïng fre~uency fox the microcomputer 64. ~he ~icro-computer 64 receivss operator inIorma~ n ~rom ~he keyboard 10 66 and location da~ca fror~ ~he loc~tion dat;~ rfac:e 68 and provi des information to ~n operator in ~he display 67 0 The keyboard 66, display 67 and lo~ation datzl interface 68 (see ~foreme~tio~ed Uo5~ Patent 3,644,~83) ~re interconnected with the ~nicroco~nputa,r 64 via ~ddress and d ta bus .15 lines in a conventional manner. Furthermore, all interface con-nections to the ~ crocomputer 64 ~an ge readily ccomplished by one skilled in ~he art by conventional technigues. For example, where the ~ crocomputer 64 is ~he ~C6801, one ~ay refer to ~he published specifica~ion ~or ~he ~C6801 ~o de~e ~ ne ~peci~ic interconnections to the MC6801 por~s. When using an MC6801, ~he <~ key~oard 66, display ~7 a~d locatio~ data in~erface 68 ~ay be connec~ed ~o parallel ~ddress and data por~s, whlle ~h2 encode ~ilter 56, DO5 circuitry 71, dat~ lLmi~es 61 and elock circui~ry 72 may ~e connected ~o ~ingl~-line i~pu~ou~put-port~.
` 25 ~or re~eiv~ng digit~l ~essa~es, ~he ~$cxo~omputer 64 : assemblQs.and de-interle~ves ~he recovered i~put data from the d ta limiter 61 as def~n~d by the recover~d data ~re;
quency from the dat~ clock 63. ~f an indication ~hat ~ata . ., ~ 1B pre~ent iR not re~eived rom ~he ~ataroper~ted-sgu~lch .` 30 circuitry 71, the re~ived digital me~sage will ~e ignored.
Also, if the recover~d input data b~s ~ore th~n on~ error in ~t le~st one WOr~9 the xsceiv~ d~it~l me~ i8 i~al~d.
For tran~ sion of i~ ation the m~cro~o~put~r 64 ~ ~.
arranges the information into a digital message having a start code followed by requisite data blocks and applies the di-gital message in MSK format to the encode filter 56. The encode filter 56 takes the digital waveform from the micro-computer 64 and provides the sinusoidal MSK output data for transmission on ~he communication channel.
The data operated sguelch ~DOS) circuitry 71 of Fig. 5 is illustrated more clearly in the embodiment shown in Fig~
7. The DOS circuitry utilizes the error voltage of a phase 10 locked loop for discriminating data from noise, voicet or music. When noise is present, ~he error voltage is greater and has an essentially flat fre~uency response characteristic .
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-15a-8M-77943 ~Z86~
121, as shown by the dotted line in Fig. 6. However, when data is present and the phase locked loop is locked, the frequency characteristic 120 of the error voltage will have components below 500 cycles a substantially dead band from 500 Hz to approximately 1700 Hz and noise and harmonics above 2000 Hz. The components of the error voltage above 2000 Hz are caused by the maintenance capability within the phase locked loop itself. But, there is a dead band centered generally around 1000 Hz only when data is pre~ent and under no other conditions. This dead band then can be used to provide an indication of data. As the strength of the MSK
input data gets lower and lower, the data frequency charactPr-istic 120 gradually approaches the noise frequency character-istic 121. The foregoing is also true of voice signals, music, inter-modulation distortion or other interfering ~" signals. Thus, the DOS circuitry can determine the differ-ence between data and anything else from the frequency ~` characteristic 120 of the error voltage in the vicinity of 1000 Hz. In the preferred embodiment of the system, the DOS
~0 circuitry 71 can be essentially 100 percent effective in differentiating between noise and data and is greater than 99 percent effective in distinguishing between voice and data.
Referring to Fig. 7, the DOS circuitry 71 includes a squelch filter 5 ?, a detector and integrator 58, and a Schmitt trigger 59. A bandpass filter 57 i5 used to filter out the dead-band portion of the error voltage. The band-pass filter 57 is of reasonably low Q centered at around ~ 1000 Hz. The output signal from the filter 57 is then : 30 detected and integrated by the detector and integrator 58~
The output of the detector and integrator 58 is applied to the Schmitt trigger or comparator 59 which then provides a . :
~-77943 ~2~
digital output signal that is a logical zero indicating the presence of data when the output of the detector and integra-tor is below a predetermined threshold level. The DOS
circuitry 71 can be made from conventional circuitry by one sXilled in the art.
The DOS output signal indicates the presence of valid data to the microcomputer 64 of the modem (see Fig. 5). The reliability of the data communication system is enhanced since the DOS circuitry substantially reduces the probability of falsing due to noise, voice, music, or other interfering signals.
; The data clock cicuitry 72 of Fig. 5 is more clearly illustrated in the embodiment shown in Fig. 8. The data clock circuitry 72 includes a data sync pulse circuit 62 and a data clock circuit 63. The data sync pulse circuit 6Z
provides a data sync pulse 150 derived from the recovered input data. The data sync pulse 150 is a narrow pulse ~-~ occurring at each transition of recovered input data, that ; is, on a mark to a space transition, data sync pulse 150 occurs and on a space to mark transition, data sync pulse 150 occurs. The data sync pulse 150 can be generated from the xecovered input data by a conventional circuit using an exclusive-or gate 154. The data sync pulse 150 is applied to the data clock circuit 63 to synchronize the phase of the data clock to the frequency of the recovered input data.
The data clock circuit 63 utilizes a Schmitt tri~ger gate 155 which is arranged as an oscillator and free runs at the data frequency, 1000 Hz. A phantom sync pulse 151 is derived ~rom the data clock signal by gate 156 and associated electrical components. The phantom sync pulse 151 is a narrow pulse occurring at the data d ock frequency on the transition from logical one to logical zero of the data - clock signal.
. ~' ' '~
CM-77943 ~ ~ ~
8~6 The phantom sync pulse 151 is combined by logical or means, diodes in the embodiment of Fig. 8, with the data sync pulse 150 to provide composite signal 152. If the recovered input data is in synchronization with the data clock signal, no correction to the Schmitt trigger oscil-lator 155 is needed, nor is wanted. The phantom sync pulse 151 will cover up the data sync pulse 150 when synchronism is reached so that the data clock signal is not subjec~ to small corrections. If the recovered input data and data clock are not in synchronism, then the data sync pulse 150 is uncovered with respect to the phantom sync pulse 151.
The further apart these two sync pulses 150 and 151 are, the ` more correction is provided by composite signal 152 to the Schmitt trigger oscilIator 155. This operation provides the benefits of an adaptive phase locked loop without the . stability problems associated with such a phase locked loop.
Furthermore, the data clock circuitry 63 provides the advantageous operation of an infinitely adaptive phase locked loop, that is, if the correction required between the incoming data and the phase of the data cloc~ is low, no correction is provided. As more correction is needed, more correction is provided up to a maximum amount of correction.
Due to the variable correction capability, the time xequired ; for sync~ronization of the clock recovery circuitry 63 is minLmized.
Figs. tO and 11 illustrate flow charts of sub-pr~grams of the modem stored program fo~ receiving and transmitting : digital messageS, respectively~ me flcw charts of Fig. 10 and 11 represent the logi~ sequences of operations that mus~ be performed in order to receive and transmit digital messages, respec~ively. The flow charts of Figs. 10 and 11 are explicit descriptionS of the microcomputer algorithms necessary to achieve the desired function By referring to the flow chartg o~ Figs. 10 and 11, one of ordinary - skill in the programming ar~ may code the appropriate combination 18~
. .
of instructions for a par~icular microcomputer to satisfy the operations called for in each block of the respective flow charts-The coding of the flow charts of Pigs. 10 and 11 may be accomplished in any suitable manner using the instructions of the particular microcomputer, for example, such as the instructions of the ~C6801. The operations and processes specified in each block of the flow charts of Figs. 10 and 11 are further supplemented in ~he foregoing description.-In Fig. 10, the flow chart of the subprogram for receiving a digital message begins at START terminal 300. Preceding to box 301, the start code is received and stored in the memory of the microcomputer. Next, when the entire start code has been received, the ~ .
. .
.
-18a-start code is checked and correlated with the predetermined start code stored in the memory of the microcomputer, as shown in box 302~ In the preferred embodiment~ the start ` code can have as many as five bits out of 32 bits which are in error and still recognize the received start code.
Preceding to decision box 303, if the start code is correctly received, the YES branch 305 is taken to decision box 306, otherwise the NO brançh 304 is taken to return along path 319 to box 301.
~` 10 The reception of the start code has provided sufficient time for the data-opera~ed-squelch circuitry to detect the presence of valid data. In decision box 306, if the data-operated-squelch circuitry has been activated, the YES
branch 308 is taken to box 309, otherwise the NO branch 307 is taken to return along path 319 to box 301.
Next, the data blocks following the start code are received and stored into the memory of the microcomputer, as shown in box 309. Depending on the configuration of the data communication system, one or more data blocks are received before proceeding to the decision box 310. Next, ; at decision box 310, if the data-operated-squelch circuitry .. is still activated, the YES path 312 is taken to box 313, otherwise a NO path 311 is taken to return along path 319 to ;~
box 301.
- According to box 313, the received data blocks are corrected using .the parity portion of each data word to correct the respective data portion. Finally, a vertical parity word is generated fox each corrected data block, as shown in box 314. Then in decision box 315, the generated vertical parity word is compared with the received vertical parity word and i they are identical, YES branch 317 is taken to terminal 318, otherwise the NO branch 316 is taken CM-77943 ~286~6 to return along path 319 to box 301. A valid digital message has been received when reaching the CONTINUE terminal 318 which is the end of this subprogram.
In Fig. 11, a flow chart of a subpro~ram for trans-mitting a digital message begins at the start terminal 400 and proceeds to box 401. First, the start code which is stored in a predetermined location in the microcomputer memory is transmitted with an MSK bit pa~tern. Next in box 402, the selected data block is transmitted in an MSK format also. Proceeding to decision box 403, if the last data block has been transmitted, YES branch 405 is taken to RETURN terminal 406, otherwise NO branch 404 is taken to ` return to box 402. RETURN terminal 406, the end o~ this subprogram, is reached when all of the data blocks for a particular digital message have been transmitted.
:.~ Severàl features of the data communications system in accordance with the present invention have a wider applica-bility which can be advantageously utilized in any communica-tion system. For example, the use of MSK si~nalling has provided optimum bit error performance with a minimum of frequency bandwith. The digital messages can be readily expanded to provide any number of data blocks. System reliability has been provided by use of the error correcting code, interleaving the data bits during transmission, and the data-operated-squelch circuitry 71 for discriminating between data and noise or voice. The data-operated-squelch circuitry 71 permits the communication channel to be used for both data and voice without degradation in system reliability. Data clock circuitry 72 has been provided that adaptively sychronizes to the data frequency and operates at the data frequency when synchronizing information is not available. These and other features described hereinabove .
:.
CM-77943 ~8626 ., .
can be advantageously utilized in any system for reliably communicating information.
The foregoing embodiments have been intended as illustra-~; tions of the principles of the present invention. Accordingly, other modifications, uses and embodiments can be devised by ~` those skilled in the art without departing from the spirit and scope of the principles of the present invention.
~` .
: ~'; .
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."
Claims (3)
OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A clock circuitry continuously synchronizable to a digital data signal serially transmitted by a data clock sig-nal having a predetermined frequency, comprising:
delay means coupled to the digital data signal for providing a delayed digital data signal delayed with re-spect to the digital data signal by a predetermined time in-terval;
first combining means for combining the digital data signal and the delayed digital data signal to provide a bit transition pulse signal for each bit transition of the digital data signal;
oscillator means for providing an oscillator clock signal having a free-running frequency substantially the same as the frequency of the data clock signal, said oscillator means further including Schmitt trigger gating means for providing the oscillator clock signal and buffer gating means capacitively coupled to the oscillator clock signal from the Schmitt trigger gating means for providing a clock-transition pulse signal for each predetermined logical state change of the oscillator clock signal; and second combining means for combining the bit-transi-tion pulse signals and clock-transition pulse signals to provide a phase correction signal and applying the phase correction signal to the Schmitt trigger gating means for synchronizing the phase of the oscillator clock signal to the phase of the data clock signal.
delay means coupled to the digital data signal for providing a delayed digital data signal delayed with re-spect to the digital data signal by a predetermined time in-terval;
first combining means for combining the digital data signal and the delayed digital data signal to provide a bit transition pulse signal for each bit transition of the digital data signal;
oscillator means for providing an oscillator clock signal having a free-running frequency substantially the same as the frequency of the data clock signal, said oscillator means further including Schmitt trigger gating means for providing the oscillator clock signal and buffer gating means capacitively coupled to the oscillator clock signal from the Schmitt trigger gating means for providing a clock-transition pulse signal for each predetermined logical state change of the oscillator clock signal; and second combining means for combining the bit-transi-tion pulse signals and clock-transition pulse signals to provide a phase correction signal and applying the phase correction signal to the Schmitt trigger gating means for synchronizing the phase of the oscillator clock signal to the phase of the data clock signal.
2. The clock circuitry according to claim 1, wherein the first combining means is an exclusive-OR gate.
3. The clock circuitry according to Claim 2, wherein the second combining means includes first and second diodes each having cathode and anode terminals, the anode term-inal of the first diode being connected to the bit-transi-tion pulse signal from the exclusive-OR gate, the anode terminal of the second diode being connected to the clock-transition pulse signal from the buffer gating means, and the cathode terminals of the first and second diodes being commonly connected for providing the phase correction signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA382,194A CA1128626A (en) | 1977-09-06 | 1981-07-21 | Data communication system |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/830,531 US4156867A (en) | 1977-09-06 | 1977-09-06 | Data communication system with random and burst error protection and correction |
| CA382,194A CA1128626A (en) | 1977-09-06 | 1981-07-21 | Data communication system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1128626A true CA1128626A (en) | 1982-07-27 |
Family
ID=25669382
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA382,194A Expired CA1128626A (en) | 1977-09-06 | 1981-07-21 | Data communication system |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1128626A (en) |
-
1981
- 1981-07-21 CA CA382,194A patent/CA1128626A/en not_active Expired
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