CA1120611A

CA1120611A - Forming interconnections for multilevel interconnection metallurgy systems

Info

Publication number: CA1120611A
Application number: CA000337633A
Authority: CA
Inventors: Hormazdyar M. Dalal; Bisweswar Patnaik; Homi G. Sarkary
Original assignee: International Business Machines Corp
Current assignee: International Business Machines Corp
Priority date: 1978-12-29
Filing date: 1979-10-15
Publication date: 1982-03-23
Also published as: EP0013728B1; EP0013728A1; JPS5591843A; IT1165434B; IT7928131A0; DE2966841D1

Abstract

Abstract A method for forming feedthrough connections, or via studs, between levels of metallization which are typically formed atop semiconductor substrates. A
conductive pattern is formed which includes the first level metallurgy, an etch barrier and the feedthrough metallurgy in the desired first level metallurgical configuration. She via stud metal-lurgy alone is then patterned, preferably by reac-tive ion etching, using the etch barrier to prevent etching of the first level metallurgy. An insulator is then deposited around the via studs to form a planar layer of studs and insulator, after which a second level of metallization may be deposited.

Description

~lZ0611 FORMING INTERCONNECTIONS FOR MULTILEVEL
INTERCONNECTION METALLURGY SYSTEMS

BACKGROUND OF THE INV~NTION

Field of the Invention This invention relates to the fabrication of metal-lurgy atop substrates. More particularly, it re-lates to interconnection systems for metallurgy disposed atop semiconductor devices.

Description of the Prior Art The continuing improvements in semiconductor inte-grated circuit technology have resulted in the capability of forming increased numbers of transis-tors, resistors, etc., within a given semiconductor chip. For example, ion implantation has allowed the devices to be smaller, and imProved masking and isolation techniques have allowed the devices to be more closely spaced. This miniaturization has resulted in decreased costs and improved performance in integrated circuits. Unfortunately, many of the devices formed within the semiconductor must remain unused in the completed chip because of space re-quired for wiring the circuits together.

l~Z06il For example, a practical state-of-the-art integrated circuit chip, containing between 700 to 2,000 cir-cuits, typically utilizes less than 50 percent of the available circuits. The principal reason for this is the space which the wiring takes up on the surface of the chip. This interconnection metal-lurgy system atop the chip is extremely complex and the spacing between the wires is very tight. To achieve even a 50 percent efficiency of circuit utilizatiGn, at least two or three and possibly four separate levels of complex conductive patterns, each separated by one or more layers of dielectric mate-rial, are used.

Ordinarily, the first level conductive pattern on the chip surface interconnects the devices within the chips into circuits and also provides circuit-to-circuit interconnections. The second level conductive pattern conventionally completes the circuit-to-circuit connections and contains a por-tion of the power buses. The third level may beused for power and I/O connections to a support, such as a module, substrate or card. To intercon-nect each of these levels of metallization, it is necessary to form feedthrough conductive connec-tions, otherwise known as via studs, within thedielectric layers separating the metallization. The most common technique used today is to etch the dielectric layer atop one level of metallurgy to form feedthrough holes and then deposit the second metallurgy layer over the dielectric layer and into the via holes to contact the first metallurgy layer.
However, overetching of one dielectric layer due to mask misalignment, for example, may result in the etching of a lower dielectric layer. It has been necessary to provide increased areas of metallurgy at the via hole sites to prevent the overetching;

)611 however, this techni~ue also substantially increases the chip area required for the interconnection metallurgy.

One technique for solving this problem is found in U.S. Patent 3,844,831, issued in the names of E. E.
Cass et al, assigned to the same assignee as the present invention. This technique involves the use of dielectric layers with dissimilar etching char-acteristics, whereby an etchant ~Thich attacks one type of dielectric does not substantially affect the other. Although the Cass et al invention has been successful, dielectric etching ~er se is recognized as causing shorts, pinholes and contamination, no matter how controlled the process.

It would be more desirable to form interconnections between levels of metallurgy without the necessity of etching in the dielectric layers.

One technique for doing so is described in U.S.
Patent 4,029,562, issued in the names of B. C. Feng et al, and assigned to the same assignee as the present invention. The Feng et al process involves the depositing of the feedthrough pattern which includes a conventional functional metal and a cap of expendable material atop the conductive film pattern, say the first level of metallizationO The expendable material can be removed by an etchant which does not attack the conductive film. The in-sulator is then deposited atop the first level film as well as the feedthrough pattern by RF sputtering at a bias which is sufficiently high to cause sub-stantial reemission of the insulator. This covers the exposed substrate and thin film surfaces, as well as the expendable material, with the insulator .

,Q61~

but leaves the side surfaces of the expendable mate-rial exposed. The expendable material may then be chemically etched, so as to leave a completely insulated conductive film pattern and exposed feed-throughs so that the second level conductive patternmay be deposited atop the insulator to be intercon-nected to the first level by the feedthroughs.

Although the Feng et al invention has been success-ful, it nevertheless involves the prior art process of depositing the feedthrough atop the first level conductor. Because of this process, the feedthrough connections may exhibit poor mechanical strength and/or higher contact resistance, which results in poor manufacturing yields. It wvuld be more desir-able to form the via studs as integral parts of themetallurgy so as to eliminate the interface between the studs and the underlying metallurgy.

SUMMARY OF THE INVENTION

Accordingly, it is a primary object of our invention to form via studs which are integral parts of their associated conductive metallurgies.

It is another object of our invention to provide an improved process of forming interconnections between levels of metallurgy without the necessity of etching dielectric layers.

It is yet another object of our invention to provide improved techniques for reducing the area required for wiring patterns atop semiconductor chips and thereby improve the utilization of the semiconduc-tor.

llZO~l~

These and other objects of our invention are achieved by forming via studs in multilevel interconnection systems wherein the interface betweOen the studs and the underlying metallurgy is eliminated.

The process involves blanket-depositing both the first thin film, typically metal, an etch barrier, as well as the via stud thin film, typically metal.
This composite is then patterned by standard pro-cesses, preferably a lift-off process, and con-figured as the desired first-level conductive pat-tern. The via stud thin film alone is then pat-terned, preferably by reactive ion etching, using said etch barrier to prevent any etching of the first-level metal. This completes the formation of the studs.

Planar sputtered SiO2 around the via studs is then deposited. The SiO2 peaks formed on top of the via studs are preferentially etched, preferably by ion beam etching in an ion beam system, taking advantage of the differential etching due to the angular dependency of the ion beam.

- This series of steps completes the basic process, which may be repeated for other levels of metalli-zation.

In one preferred embodiment, the underlying metal-lurgy comprises aluminum, copper-doped aluminum, or copper-doped aluminum with silicon added. The etch barrier is preferably chrome, and the via studs are preferably formed from aluminum-copper.

11'~061:1 BRIEF DESCRIPTION OF THE DRAWING

Figure 1 is a partially sectioned, perspective view of a portion of an integrated circuit fabricated in accordance with our invention.

Figures 2A-2K are diagrammatic, cross-sectional views of a structure being fabricated in accordance with the preferred embodiments of our invention.

Figure 3 is a photomicrograph taken of a semicon-ductor chip showing via studs atop a first-level metallurgy which are formed in accordance with our invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Although our invention is described principally in terms of the first and second levels of metallurgy, it will be understood that it applies to any such level or combination of levels atop a substrate.

In Figure 1 there is shown a first-level metal stripe 19 which is connected through a dielectric layer 12 to impurity region 2 in a semiconductor body 1. A layer 18 is disposed between film 21 and region 2. For example, if aluminum or aluminum doped with copper is used as thin film 19, then a layer of barrier material, such as chrome, is used to prevent the interaction of the aluminum with the contact metallurgy, which is typically platinum silicide (not shown).

Stripe 19 represents a portion of a complex conduc-tive pattern atop chip 1 and is illustrated as being ~lZ()61~

relatively elongated for connection to a second level of metallization 30, as well as to other stripes (not shown) on the first level. A feed-through, or via stud, 21' interconnects film 12 and film 30 through a dielectric layer 28 which is preferably sputtered SiO2. Disposed atop and coex-tensive with layer 19 is layer 20 which has the function in the process as a barrier to the etching of layer 19 while stud 21' is being formed. A
second etch barrier layer 31 is disposed atop layer 30. Typically, another via stud or a number of them (not illustrated) are disposed atop layer 31. The process for forming this type of interconnection is described in detail with respect to Figures 2A-2K.

As will be understood by those skilled in the semi-conductor art, body (chip) 1 contains many thousands of impurity regions. The surface conductive pat-terns function both to interconnect these regions into circuits as well as to connect these circuits with external connections off-chip.

Turning now to the process, Figures 2A and 2B illus-trate the preferred process for depositing thin film 19 in a desired first-level conductive portion atop layer 12. The preferred technique corresponds to that described in U.S. Patent 4,004,044, which issued in the names of Franco et al, and is assigned to the same assignee as the present application.
This process is illustrated in abbreviated form in Figures 2A and 2B and will be described below briefly. Alternate techniques for forming the metallurgy comprise standard wet or reactive ion (plasma) substractive etching processes which are well known to those of skill in the art. However, llZ06~'~

the lift-off technique described in the aforemen-tioned patent is capable of providing superior definition of metallurgy, thereby minimizing the area required for wiring.

Turning now to Figure 2A, the lift-off process com-mences with the blanket deposition of a thin layer of polyether sulfone (not shown) which facilitates the lift-off process. The use of polysulfone is a modification of the process described in the afore-mentioned patent to Franco et al and has been des-cribed in the article by Carr et al entitled "Strip-ping Promotor for Lift-Off Mask", IBM*Technical Disclosure Bulletin, Volume 19, No. 4, September 1976, p. 1226. Disposed atop the polysulfone layer is a layer 14 of an organic polymer material such as a novolak-resin-based positive resist which is baked to 210C to 230C to render it non-photosensitive.
Atop layer 14 is coated a methylsiloxane resin barrier layer 16 followed by a layer of a radiation sensitive resist tnot shown).

The resist layer is subjected to radiation and is developed in the standard manner to provide a pat-terned relief image. The resist mask is then used to permit selective removal of the underlying layers 14 and 16 to expose window 17 illustrated in Figure 2A. It will be understood that there are thousands of such windows formed in a single layer atop a semiconductor chip. Window 17 is merely exemplary.
The technique of forming the windows in layers 16 and 14 is described in great detai~ in the afore-mentioned Franco et al patent, and a further des-cription here would be unnecessarily redundant.
*Registered Trade Mark ~1~0~11 After the windows 17 are formed, a layer 18 of chrome is blanket-deposited atop a substrate and the lift-off mask. For convenience in this discussion the portions of the layers which are deposited atop the resist masks 16 and 14 are illustrated by the primed numeral of the numeral used to illustrate the metal which remains atop the substrate after the lift-off process has been completed.

As previously noted, the chrome acts as a diffusion barrier between aluminum and silicon. The chrome is not necessary for the practice of our invention and forms no part of our invention, per se. Products can and have been manufactured successfully without the use of an interface between the aluminum and the silicon. In particular, an alloy of aluminum-copper which is doped with a small amount of silicon can be deposited successfully atop a substrate of silicon without deleterious effects. Moreover, chrome is not the only barrier material which may be used.
For example, a composite layer of tantalum and chrome may be used. In addition, other metals such as titanium or tungsten or alloys thereof may also be used.

Returning now to Figure 2B, a layer of metal 19, which is preferably aluminum-copper, is deposited atop the ch~ome, preferably in the same evaporation chamber. Layer 19 operates as the functional first level thin film metallurgy.

Following the deposition of the aluminum, another layer of chrome 20 is deposited to a preferred thickness of around l,OOOA. Layer 20 acts as an etch barrier to the etching of layer 20 in subse-quent process steps. After the deposition of layer 11'~06il 20, another layer 21 is deposited. This layer is to function as the interconnection metallurgy or via stud connection. In our preferred process, layer 21 is also copper-doped aluminum.

In our preferred process, to assure good results the thickness of underlay resist layer 14 is approxi-mately 1.5 times the thickness of all of the metal layers 18-21. Conventionally, the thicknesses of the metal layers are as follows: chrome layer 18:1,000A, aluminum-copper layer l9:around 8,500A, chrome layer 20:1,000A, aluminum-copper layer 21:around 15,500A.

The remaining lift-off structure and overlying metal are quickly lifted off, using N-methylpyrrolidone or another suitable solvent to leave the patterned metal adherent to the surface of the semiconductor and the insulating layer 12, as shown in Figure 2C.

Chrome is not the only etch barrier which may be used, although it is most convenient. For example, Ta, Ti, W and other metals or alloys thereof may be used with good results.

In the next series of steps illustrated in Figures 2D, 2E and 2F, a second lift-off photoresist mask process is utilized to define the via stud pattern which will be formed from layer 21, which is at this point coextensive with underlying first metal layer 19. It is noted at this poir.t that the lift-off process here is utilized for pattern definition and not for the standard purpose of lifting off excess metal which had been blanket-deposited atop the resist.

061~

Turning now to Figure 2D, this masking process commences with the blanket deposition of an organic polymeric material 24 which is baked. Atop layer 24 is coated the methylsiloxane resin masking layer 25 followed by a layer 26 of a radiation-sensitive resist.

Layer 26 is exposed and developed to provide a pat-terned relief image which corresponds to the via stud pattern to be formed. The patterned resist is illustrated by the numeral 26' in Figure 2E.

The exposed and patterned layer 26' is then used as a mask for the reactive ion etching of resin masking layer 25 as described in U.S. Patent 4,004,044 to effectively transfer the openings of layer 26 to resin layer 25, as shown in Figure 2F.

Next, using layer 25' as a mask the polymeric masking layer 24 is apertured by reactive ion etch-ing in an oxygen gas ambient. If resist layer 26' has not been removed previously by a suitable sol-vent, the oxygen plasma serves to remove it. Theresulting structure is shown in Figure 2G where resist layer 24' and resin layer 25' together define the via studs to be formed in layer 21. Contrary to the desired structure in the usual lift-off process, no overhang is desired in layer 25' with respect to layer 24'.

In the next step illustrated in Figure 2H, via stud 21' is formed. The studs are formed in a commercial plasma or reactive ion etchiny chamber. With aluminum-copper used as the stud metallurgy, a gas mixture of Ar/C12 or Ar/CC14 is used. Other suit-able mixtures which do not attack SiO2 or silicon 1~0~11 nitride may also be used. The etch rate of aluminum-copper is approximately 1.7 to 2 times faster than photoresist layer 24'. The underlying layer 20 acts as an automatic etch stop because of the substantial differential etch rates between aluminum and chrome.
The etch rate of aluminum-copper in the aforemen-tioned gases is around 1,OOOA per minute, whereas the etch rate of chrome is around lOOA per minute.
After this step the remaining layers 24' and 25' are removed in the chamber using a mixture of CF4 and

2 which does not affect chrome layer 20; nor will it substantially affect aluminum-copper layer 21' disposed underneath resist layer 24'. Alterna-tively, resist layer 24' and 25' may be removed by immersion into a solvent, such as N-methylpyrro-lidone and a photoresist solvent.

The exposed metallurgy is then covered with an in-sulating layer 28, as shown in Figure 2I. The preferred technique for depositing layer 28 is by the driven or tuned anode RF deposition system, described, for example, in U.S. Patent 3,804,728 in the names of Lechaton et al or U.S. Patent 3,983,022 in the names of Auyang et al. Both of these patents are assigned to the same assignee as the present application.

The quartz peaks are then etched off and the upper surfaces of studs 21' are exposed.

It is preferable to utilize ion milling to remove the peaks atop the via studs preferentially. With the ion milling technique, typical conditions are an accelerating voltage of 1,000 volts with an angle of incidence of around 30-60 and a rotating substrate.
Another technique which may be used to form il'~O611 glass which is substantially planar around stud 21' is a blanket reactive ion etching of the SiO2 in a system which is capable of isotropic etching. Such machines are commercially available from the IPC or LFE corporation. Neither of these techniques are our invention, per se.

After the planarization, studs 21' are exposed whereas the underlying metal layers 18, l9 and 20 remain covered by oxide layer 28.

The second level of metallization may now be depo-sited atop insulator 28 so as to contact the via studs 21'. As with the first level of metalliza-tion, the second level comprises the functional metal 30, as well as an etch barrier 31. Preferably layer 30 comprises aluminum-doped copper, and layer 31 comprises chrome. The second level metallization may be patterned using the lift-off process des-cribed previously with respect to Figures 2A-2C.
Layer 33 disposed atop etch barrier 31 would then be patterned, as shown in Figures 2D-2I to form a stud which would interconnect the second level of metal-lization to the third level. The process can be continued for as many levels of metallization as are required.

Figure 3 is a photomicrograph illustrating via studs which we have actually formed on a semiconductor test site to demonstrate the invention. The entire test site comprised 2,000 first level metal tabs with two via studs in each tab. The mechanical strength of the studs was very high, and the contact resistance quite low.

061~

Although our invention has been particularly shown and described with reference to the preferred em-bodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.

For example, we have described numerous alternative techniques for forming the patterned metallization atop the semiconductor substrate. We prefer to use the lift-off process disclosed by Franco et al in U.S. Patent 4,004,044, but our invention is not limited to this. Other alternatives are available in U.S. Patents 3,873,361 and 3,892,943. These patents describe lift-off processes which we could use in the operation of our invention.

In addition, we have described numerous metallurgies which could be used for the interconnections and the etch barriers. Also, there are a number of etching processes available to pattern the metal in the desired wiring configurations.

We claim:

Claims

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A method for fabricating thin film interconnection patterns comprising:
depositing a composite comprising a first thin film, a second thin film, and an etch barrier material disposed between said first and second thin films;
patterning said composite to form a first patterned thin film layer on said substrate;
forming, on said second thin film, a patterned masking layer comprising a layer of organic polymeric material and a coating of a masking material disposed atop said organic polymeric material;
removing the exposed portion of said second thin film by reactive ion etching, said barrier material acting as an etch stop, whereby the remainder of said second thin film comprises a second patterned layer disposed atop said first patterned thin film layer;
removing said patterned masking layer;
depositing a third thin film layer atop said thin film patterned layers and said substrate; and exposing the upper surfaces of said second patterned layer by an etching process.

2. A method as in Claim 1 wherein said first and second thin films and said barrier material are conductors and said third thin film layer is an insulating layer.

3. A method as in Claim 2 wherein said insulating layer is silicon dioxide.

4. A method as in Claim 3 wherein said silicon dioxide is deposited by RF sputtering.

5. A method as in Claim 2 wherein said first and second thin films are selected from the group consisting of aluminum, aluminum-copper alloys and aluminum-copper-silicon alloys.

6. A method as in Claim 5 wherein said barrier material is selected from the group consisting of chrome, tantalum, titanium, tungsten and alloys thereof.

7. A method as in Claim 6 wherein said reactive ion etch-ing uses gases which include argon and chlorine.

8. A method as in Claim 1 wherein said etching process comprises ion milling.

9. A method as in Claim 1 wherein said etching process comprises reactive ion etching.

10. A method as in Claim 1 wherein:
the second patterned thin film layer is a feedthrough pattern for connecting the first patterned layer to one or more succeeding conductive layers.

11. A method for fabricating thin film interconnection pat-terns wherein one or more levels of said patterns are formed by the steps comprising:
depositing a composite comprising a first thin film, a second thin film, and an etch barrier material disposed between said first and second thin films;
patterning said composite to form a first patterned thin film layer on said substrate;
forming, on said second thin film, a patterned masking layer comprising a layer of organic polymeric material and a coating of a masking material disposed atop said organic polymeric material;
removing the exposed portion of said second thin film by reactive ion etching, said barrier material acting as an etch stop, whereby the remainder of said second thin film comprises a second patterned layer disposed atop said first patterned thin film layer;
removing said patterned masking layer;
depositing a third thin film layer atop said thin film patterned layers and said substrate; and exposing the upper surfaces of said second patterned layer by an etching process.

12. A method as in Claim 11 wherein said substrate itself comprises an underlying patterned thin film layer.

13. A method as in Claim 11 wherein said substrate includes a semiconductor body having impurity regions disposed therein which are interconnected to themselves and to external connec-tions by said patterns.

14. A method as in Claim 13 wherein said first and second thin films are conductors.

15. A method as in Claim 14 wherein said first and second thin films are selected from the group consisting of aluminum, aluminum-copper alloys and aluminum-copper-silicon alloys.

16. A method as in Claim 15 wherein said barrier material is selected from the group consisting of chrome, tantalum, titanium, tungsten and alloys thereof.