CA1193350A - Circuit structure - Google Patents
Circuit structureInfo
- Publication number
- CA1193350A CA1193350A CA000409603A CA409603A CA1193350A CA 1193350 A CA1193350 A CA 1193350A CA 000409603 A CA000409603 A CA 000409603A CA 409603 A CA409603 A CA 409603A CA 1193350 A CA1193350 A CA 1193350A
- Authority
- CA
- Canada
- Prior art keywords
- circuit
- mother
- board
- connectors
- cards
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K7/00—Constructional details common to different types of electric apparatus
- H05K7/14—Mounting supporting structure in casing or on frame or rack
- H05K7/1438—Back panels or connecting means therefor; Terminals; Coding means to avoid wrong insertion
- H05K7/1439—Back panel mother boards
- H05K7/1444—Complex or three-dimensional-arrangements; Stepped or dual mother boards
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
ABSTRACT
A three-dimensional circuit structure suited for a routing type electronic switcher matrix, for analog or digital signals, in which internal wire interconnections are not required. Plural parallel-disposed zero-insertion-force connectors are orthogonally related on opposite sides of mother-boards that divide tiers in the structure. Selected conductive pins of the connectors are electrically connected to make necessary interconnections. Printed circuit cards are inserted in the zero-insertion-force connectors for carrying a large plurality of solid-state, or equivalent, cross points, and are inter-connected by the selected conductive pins.
A three-dimensional circuit structure suited for a routing type electronic switcher matrix, for analog or digital signals, in which internal wire interconnections are not required. Plural parallel-disposed zero-insertion-force connectors are orthogonally related on opposite sides of mother-boards that divide tiers in the structure. Selected conductive pins of the connectors are electrically connected to make necessary interconnections. Printed circuit cards are inserted in the zero-insertion-force connectors for carrying a large plurality of solid-state, or equivalent, cross points, and are inter-connected by the selected conductive pins.
Description
3~g~
DESCRIPTION
"CIRCUIT STRUCTURE"
TECHNICAL FIELD
This invention pertalns to the mechanical arrangement of related multiple electrical circuits.
BACKGROUND ART
U.S. patent No. 3,206,648 discloses a quasi-three-dimensional structure in which electronic components areconnec-ted between metallic X and Z axis combs and Y axis buses in spaced relation.
However, elongated boxes (47) are provided hetween each tier through which the many inter-connecting wires 10 must be run.
A large number of insulating spacers (30) are used to support the combs and the buses. "Tridimensional cond-uctors functions are presented in a bldirec-tional manner."
(col 2, lines 40-1) Mother-boards are not mentioned, nor are zero-insertion-force connectors; these having been invented a few years a_ter the filing dated of this invention.
Obviously, -there is no suggestion of the coordinated connection of zero-insertion-force connector pins from 20 one side of a mother-board to the other.
In pa-tent 3,206,648 the signal paths are strictly two-dimensional, with control circuits only in the third __ dimension.
~.~ s,., ~
Uni.ted States patent No. 3l377,515 clisc]oses a two-tier cage for holdiny a pl.urality of circui-t cards and making connec-tions thereto. A plurality o:E f.inger pairs (30) on the cage mr-ke contact to each circuit ca:rd. The ci:rcuit arrangement is -two-dimensional and there is no mention of any scheme for connec-ting the finger pairs, one to another.
DISCLOSURE OF INVENTION
A three-dimensional mechanical disposition of an elec-trical. circuit having plural inputs and plural outputs. The s-tructure is arranged in tiers. It i.s comprised of circuit-carrying cards disposecl on edge between intervening mother-boards.
Zero-inser-tion--force (ZIY) connectors upon -~he mother-boards accept the ci.rcuit-carryi.ng cards, maki.ng selected contacts wi-th the circuits thereof.
Conductive p:i.ns of the ZIF connec-tors make common point electrical connections through the mother-boards. ZIF connec-tors of aL-terna-te tiers are or-thogonal.ly ar:rangec~.
rrhe structu:re el.imi.Tlates wire connec-tions between -ti.ers.
In summary, accord:ing -to a .Eirst hroacl aspect of -the p:resent inven-tion, there is provi.decl a three-dimensional c:ircuit s-tructure, comp:rising: (a) plura]. planar, spaced, s-tacked mother-boards, (b) firs-t plural, spaced, parallel-related zero-insertion-force elongated connectors upon one surface of each mother-board, (c) second plural, spaced, parallel-related zero-insertion-force elonga-ted connectors upon the opposite surface of each mother-board orthogona]ly rela-ted -to those on said one surface, (d) elec--trically conductive pins selec-tively extending through each said A~
mo-ther--board betwe~n said first ancl second connec-tors that elec-trically connect said connectors, and (e) circuit-carrying cards inse:r-ted in each said elongated connector and disposed perpen--dicularl.y to the mc)ther-board, whereby a circuit upon a said card inserted in a said :Eirst elongated connector is elee-trically connected to a circuit upon a said card inserted in a said second elongated connector.
The inven-tion will now be described i1 greater de-tail with reFerence to the accompanying drawings:
Figure 1 is a perspec-t,ive elevation view oE a three--tier -three-dimensional circuit structure.
F'igure 2 is a simplified diagram of the s-tructure o:E
Figure 1 showi.ng how the connec-tion scheme is implemented.
Figure 3 is an enlarged exploded detail oE -the three~
dimensional circuit s-tructure, :i.l'l.ustra-ting the or-thogonal aspec-t.
Figure ~ is a plan view o:E pin conneetion in-tersee-ti,ons.
F`igures 5, 6 and 7 are plan views o~: alte,rnate modes of i.ntersection connections.
~0 Figure ~ is a schematic diag:ram of a routing -type switcher tha-t ean be embodied in the three--dimensional eireuit s-trueture of this invention.
-2a-BEST MODE FOR C~RR~ING OUT THE INVENTIO~
The essential aspect of the inven-tion is shown in Fig.
where the pin connections through a mother-board are shown as black diamond shapes. These are electricall~ conductive areas that connect plural pins.
An illustrative complete structure is shown in Fiy. 1.
In Fig. 1, numeral l identifies the top or primary tier of plural circuit cards.
Similarly, numeral 2 identifies a middle or secondary tier of plural circuit cardsO Note that these are or-thog-nally (at right angles) arranged with respect to the disposition of the primary cards.
Further, numeral 3 identiEies the lower or tertiary tier of plural circuit cards. These are orthogonally 15 arranged with respect to the disposition of the secondary cards. This results in a parallel arrangement with respect to the primary cards.
Mother-board 4 is disposed between the primary and secondary tiers, and mother-board 5 between the secondary 20 and tertiary tiers. These two mother-boards are spaced apart in parallel relation by mechanical support 6, which may also be reproduced at the front and back sides of these mother boards for mechanical regidity. This has not been shown in Fig. 1 for sake of clarity.
~top mother-board ~ are first plural, spaced, parallel--related zero-insertion~force (ZIF) elonyated electrical connectors 7, 7 " 7", 7n; Eor example, eight of them.
These each suppor-t ancl make electrical contact to an equal number of printed circui-t cards 8, 8', 8", 8n. The circuit cards are supported mechanically by elongated guides 9, 9', 9", 9n.
In order that auxiliary electrical connections can be made to each circuit card, the same plurality of edge con-nectors 10 as circuit cards, i.e., 8n, are mounted upon rear 35 vertical wall 11, in individual alignment with each ZIF
connector 7n.
3~
A top planar frame-piece 12 is rigidly attached to wall 11, and may be similarly at-tached to sides at the le-ft and the right as well, for mechanical strength. These sides are not shown for sake of clarity; being of only ministerial significance.
In assembly, when the frame as a whole has been fabric-ated, -the several circuit cards 8, - 8n are pushed-inbetween corresponding ZIF connectors 7, _ 7n and guides 9, _ 9n until the contacts at the (left) end of the card enter edge con-nectors 10, etc. and are fully engaged.
The secondary -tier 2 is inherently the same as tier 1, save that the whole -tier is orthogonally related to tier 1.
The several parallel-disposed ZIF connectors 17, - 17 hold the several circuit cards 18, - 18n, which cards are also supported by ZIF connectors 27, - 27 The number of circuit cards in the second tier, say ten, is governed by the requirements of the over-all circuit oE
the structure. Plural edge connectors 20 are provided.
The third, or tertlary, tier 3 is inheren-tly the same as an inverted tier 1.
On the underside of mother-board 5 are located plural, spaced, parallel-related ZIF elongated connectors 23, 23', 23", 23n. These are aliglled with the prior series of such connectors 7, _ 7n atop mother-board ~1.
Connectors 23, - 23n each engage and make electrical contac-t with an equal nurnber of printed circuit cards 28, 28', 28", 28n. These circuit cards are supported rnechan-ically by elongated guides 29, 29', 29", 29n that are attached to a bottom planar frame-piece 22. The latter is the inverted ec~uivalent of frame-piece 12.
Similarly, auxiliary connections to circuit-cards 28,-28n are made to the same plurality of edge connectors 30 as there are circui-t cards. These connectors are mounted upon rear vertical wall 31, in individual alignment with each ZIF connector 23, - 23 Frame-piece 22 is rigidly attached to wall 31, which is also rigidly attached to mother-board 5. It may also be at-tached to sides at the leEt and the right as well, for mechanical strength. These sides are not shown, being oE only ministerial significance.
Each ZIF connector, such as 7 in Fig. 3, carries a large nu~ber of adjacent, but electrically separate, contacts 33 along both inner ver-tical surfaces. These mate with contacts upon a circuit card, such as contacts 34 (Fig. 1) upon card 8, Each contact 33 has a pin 35 that is mechanically and elect-rically mutually attached, one to the other; the pin extend-ing through the insulating material of the body of theconnec-tor.
These pins also pass through mother-board in a pattern that is shown at 4 in Fiy. 4, at 37 and 37A, for example, for ZIF connector 7. Items 37 and 37A are plated-through 15 holes; that is, the inner white area of each is a hole and -the surrounding black area is electroplating within the hole and at a larger area on each side of mother-board 4. Each pin 35 is forced into a hole 37, as in an arbor press, so that there is firm mechanical and electrical contact 20 between the electroplating within the hole and the pin.
Only certain pins are employed for connecting circuits on one circult card, as 8, to another circuit on another card, as 18. These are the pins that are pressed into the holes in the diamond-shaped conduc-tiv~ areas 40. The two 25 horizontally related holes are aligned with holes 37 and 37A, and so accept certain oE pins 35. The two vertically rel-ated holes are aligned with holes 41 and 41A, and so accept certain pins 39. Accordingly, four pins are connected together electrically Erom one ZIF connector to -the one adjacent to it on the opposite side of a mother-board, giving electrical contact redundancy.
Which pins are employed ~or connecting circuits from one circuit card to a related other card can be seen in the exploded view of Fig. 3. Two fc-ward pins 35 of ZIF connect-35 or 7 pass through a conductive area 40. Similarly, twoforward pins 42 of ZIF connector 17 pass through the same conductive area 40.
This establishes one connection between the tiers, such as connection 50 in Fig. 8. Numerous similax connections are also similarly established, for example, a total of 80 connections.
~ote that connection 50 is relatively long ln Fig. 8 because of -the normal drafting layout. However, the same connection in Fig. 4 is only a few millimeters (mm) long, from one pin to an adjacent pin in area ~0.
In Fig. 4 there are eight dotted "holes" surrounding conductive area 40A. These holes are absent around other areas, such as 40. This indicates that pins such as some of 35 and 39 are removed from the corresponding ZIF con-nectors to allow desired wor]cing room with respect to -the desired pins that enter area 40A, and other areas, such as 40.
Numerous aligned pins and holes 37, 37A, 41, 41A, etc.
are used as ground connections, establishing a desirable ground plane -to prevent circulating currents. A suitable bus connects the thus formed conductive plane to ground;
as to the frame at 6, ll, 2~, etc.
It is found that the very many pi.ns entering force-fit into the mo-ther-board hoLes is sufficient to form a rigid and permanent over-all structure. However, a pair of screws, as 52, are typically provided ~t each end to fasten each ZIF
connector to the mother-board, either by a tapped hole there-in, or by nuts (not shown~.
Fig. 5 shows an alternate arrangement of the conductive area 40 of Fig. 4. Two different types of ZIF connectors are predicated in Fig. 5, particularly as to having differ-30 ent spacing between companion rows. ~orizontally, the rowsof holes iden-tified as 55 are more widely spaced than the orthogonally disposed rows of holes identified as 56.
Conductive areas 57, 58, 59 and 60 typically connect rows 55 and 56 in groups of three pins~ This permits dual 35 paths -to be established, as for switching balanced audio signals or bidirectional streams of dataO
Fig. 6 shows another alternate conductive area arrange-ment. Four diagonal conductive traces on the mother-board connect two pins each, one for each row 55 and 56. This permits four paths to be established. The cross outline depic-ts an area that is not conductive; but areas 62 are.
Fig. 7 shows still a further arrangement. In the four central conductive holes 65 orepin from each of rows ~6 and ~7 occupies one hole. Adjacent pins are not removed.
A typical electrical application of the circuit struct-ure of this invention is fox a routing switcher. This is a device in which a number of inputs, say 100, can be connect-10 ed to any of 100 outputs by manipulating a push-button switchboard.
In Fig. lthe great many rectangular elements 70 are solid-state cross-points; that is, plural transistor dev-ices that accomplish signal transmission when "on" and 15 blocking signal transmission when "off".
These elements preferably have small inheren~ capac-itance, so that -the variation of "on" and "off" conditions do not significantly affect the whole circuit of which they are a part. Integrated circuit elements, suitable for -the 20 yigahertz Erequency range are suitable, such as the RCA
type CA3127E, which has very low inter-junction capacitances.
Typically three transistors are used for each cross-point, with an emi.t-ter-follower ou-tput. Thus constituted, the routi.ng switcher is suited for elther audio frequency or 25 video frequency signals.
The schematic circuit oE E~ig. 8 details how the elect-rical paths for switching are arranged.
An lnput 71 to -tier 1 enters a cross-point connec-tion 70` at "x". It proceeds therethrough and passes out of tier 1 on conductor 50. Conductor 50 in actuality is conductive area 40 of Fig. 3, as has been previously explained. The connection becomes input 72 in tier 2.
The signal output from tier 2 enters input 73 of tier 3, passes -to cross-point "~" thereof and out at output terminal 74.
Note that the signal that is processed passes through all of the three tiers. This is different than the prior art.
The "x" pa-th recited above is the normal path for a signal from input 71. Should this path not be available an alternate path via conductor 76 is available. This carries on through another circuit card 77 of the secondary group to second input 81 of ter-tiary card group 3, thence to output 74.
In normal use there are a number of inputs simultan-eously impressed upon group 1, with corresponding selected outputs. Being a -three stage routing switcher this appar-atus follows the Charles Clos type.
Card 78 in Fig. 8 represents card 2 of the primary group,wi-th an input at 79. This becomes an output of the primary tier and enters the second input 80 of the secondary tier card 2.
In the simpliEied diagram oE Fig. 2,-the top three cards 8, 8' and 8 are in primary tier 1 of Fig. 1~
Orthogonally related, cards 18, 18' and 18n are in -the secondary tier 2 o~ Fig. 1.
Further, cards 28, 28' and 28n having the alignment of the top three cards, are in the tertiary tier 3 of Fig~ 1.
Tracing input 1, this en-ters the first primary card 8 at 71. It progresses to ou-tput ~10, which is one of the conductive areas 40 shown in Fig. 4. Thence -to first sec-ondary card 18, at point 72. From there it passes through another conductive area 40 to Elrst tertiary card 28, at point 73. The signal exits card ~8 at output 74.
Other inputs take different but equivalent paths -through the routing switcher, as shown by the full and dotted lines and "x" points.
It will be recognized that the very short interconnect-ions in this structure via the conductive areas 40 results in a routing switcher, for an example, of superior elect-rical characteristics. Capacitance is low and inductance is very low. Also, the lack of relatively long wires run-35 ning in some proximity to other wires largely eliminates cross-talk !
Fig. lshows 8 circuit cards in primary tier 1, 10 cards in secondary tier 2, and 8 cards in tertiary tier 3. This 33~3 is no-t the only number of cards for the tiers. The number of cards depends upon the ultimate size of the switcher in terms of -the number of inputs and outputs -thereof.
~nother set of numbers embraces 10 cards in the primary tier, 19 cards in the secondary tier, and 10 cards in the tertiary tier.
The preferred manner of assembling the ZIF connectors is to first insert the individual contacts with the pins thereof in -the holes of the mother-board. Then -the housing;
i.e., the sides and bottom, is assembled with an arbor press and a jig.
The transistor cross-points specified for the exemplary routing switcher are unidirectional in signal flow. All signal flow is from an input -to an output.
Bidirectional signal flow can be obtained in an alter na-te construction in which tri-state buffer integrated circuits are substituted for the -transistor cross-points;
such as the 74LS365 hex. 3 state buffer. Also suitable are mechanical relays or silicon controlled rectifiers (SCRs).
Because oE the three stage (tier) construction and the very short inter-connections via conductive areas ~0, the size of the circuit structure of this invention is about one-fourth as large as conventional equipments of this type.
This is an importan-t practical advantage.
Each oE the ZIF connectors is provided with an end latch 21 (Fig. 1) of insulating material, which hinges open to allow the circuit card to enter the connector and is manually~closed over khe end of the card to retain it.
In Fig. l-the several solid-s-ta-te cross-polnt in-tegrated circuits 70 are shown as seven in number in each vertical row for the primary and tertiary tiers and six in number for the secondary tier.
In one typical embodiment there are ten primary matrices r nineteen secondary matrices, and ten tertiary 35 matrices. One primary card, as 7 has nineteen outputs each one of which becomes an input to a secondary card.
Each output of a secondary card becomes an input to a tertiary card.
However, the number of "x" point integrated circuits 70 may vary according to the extent of the switching requirements; for instance, ten in each vertical row.
A three stage routing switcher has been described to illustrate the circuit structure of this invention.
Five, seven, or even nine stage switchers can also be implemented by merely extending the technique that has 10 been taught.
The connections and circuit structure of -this invention are suited to carrying digital as well as analog signals.
DESCRIPTION
"CIRCUIT STRUCTURE"
TECHNICAL FIELD
This invention pertalns to the mechanical arrangement of related multiple electrical circuits.
BACKGROUND ART
U.S. patent No. 3,206,648 discloses a quasi-three-dimensional structure in which electronic components areconnec-ted between metallic X and Z axis combs and Y axis buses in spaced relation.
However, elongated boxes (47) are provided hetween each tier through which the many inter-connecting wires 10 must be run.
A large number of insulating spacers (30) are used to support the combs and the buses. "Tridimensional cond-uctors functions are presented in a bldirec-tional manner."
(col 2, lines 40-1) Mother-boards are not mentioned, nor are zero-insertion-force connectors; these having been invented a few years a_ter the filing dated of this invention.
Obviously, -there is no suggestion of the coordinated connection of zero-insertion-force connector pins from 20 one side of a mother-board to the other.
In pa-tent 3,206,648 the signal paths are strictly two-dimensional, with control circuits only in the third __ dimension.
~.~ s,., ~
Uni.ted States patent No. 3l377,515 clisc]oses a two-tier cage for holdiny a pl.urality of circui-t cards and making connec-tions thereto. A plurality o:E f.inger pairs (30) on the cage mr-ke contact to each circuit ca:rd. The ci:rcuit arrangement is -two-dimensional and there is no mention of any scheme for connec-ting the finger pairs, one to another.
DISCLOSURE OF INVENTION
A three-dimensional mechanical disposition of an elec-trical. circuit having plural inputs and plural outputs. The s-tructure is arranged in tiers. It i.s comprised of circuit-carrying cards disposecl on edge between intervening mother-boards.
Zero-inser-tion--force (ZIY) connectors upon -~he mother-boards accept the ci.rcuit-carryi.ng cards, maki.ng selected contacts wi-th the circuits thereof.
Conductive p:i.ns of the ZIF connec-tors make common point electrical connections through the mother-boards. ZIF connec-tors of aL-terna-te tiers are or-thogonal.ly ar:rangec~.
rrhe structu:re el.imi.Tlates wire connec-tions between -ti.ers.
In summary, accord:ing -to a .Eirst hroacl aspect of -the p:resent inven-tion, there is provi.decl a three-dimensional c:ircuit s-tructure, comp:rising: (a) plura]. planar, spaced, s-tacked mother-boards, (b) firs-t plural, spaced, parallel-related zero-insertion-force elongated connectors upon one surface of each mother-board, (c) second plural, spaced, parallel-related zero-insertion-force elonga-ted connectors upon the opposite surface of each mother-board orthogona]ly rela-ted -to those on said one surface, (d) elec--trically conductive pins selec-tively extending through each said A~
mo-ther--board betwe~n said first ancl second connec-tors that elec-trically connect said connectors, and (e) circuit-carrying cards inse:r-ted in each said elongated connector and disposed perpen--dicularl.y to the mc)ther-board, whereby a circuit upon a said card inserted in a said :Eirst elongated connector is elee-trically connected to a circuit upon a said card inserted in a said second elongated connector.
The inven-tion will now be described i1 greater de-tail with reFerence to the accompanying drawings:
Figure 1 is a perspec-t,ive elevation view oE a three--tier -three-dimensional circuit structure.
F'igure 2 is a simplified diagram of the s-tructure o:E
Figure 1 showi.ng how the connec-tion scheme is implemented.
Figure 3 is an enlarged exploded detail oE -the three~
dimensional circuit s-tructure, :i.l'l.ustra-ting the or-thogonal aspec-t.
Figure ~ is a plan view o:E pin conneetion in-tersee-ti,ons.
F`igures 5, 6 and 7 are plan views o~: alte,rnate modes of i.ntersection connections.
~0 Figure ~ is a schematic diag:ram of a routing -type switcher tha-t ean be embodied in the three--dimensional eireuit s-trueture of this invention.
-2a-BEST MODE FOR C~RR~ING OUT THE INVENTIO~
The essential aspect of the inven-tion is shown in Fig.
where the pin connections through a mother-board are shown as black diamond shapes. These are electricall~ conductive areas that connect plural pins.
An illustrative complete structure is shown in Fiy. 1.
In Fig. 1, numeral l identifies the top or primary tier of plural circuit cards.
Similarly, numeral 2 identifies a middle or secondary tier of plural circuit cardsO Note that these are or-thog-nally (at right angles) arranged with respect to the disposition of the primary cards.
Further, numeral 3 identiEies the lower or tertiary tier of plural circuit cards. These are orthogonally 15 arranged with respect to the disposition of the secondary cards. This results in a parallel arrangement with respect to the primary cards.
Mother-board 4 is disposed between the primary and secondary tiers, and mother-board 5 between the secondary 20 and tertiary tiers. These two mother-boards are spaced apart in parallel relation by mechanical support 6, which may also be reproduced at the front and back sides of these mother boards for mechanical regidity. This has not been shown in Fig. 1 for sake of clarity.
~top mother-board ~ are first plural, spaced, parallel--related zero-insertion~force (ZIF) elonyated electrical connectors 7, 7 " 7", 7n; Eor example, eight of them.
These each suppor-t ancl make electrical contact to an equal number of printed circui-t cards 8, 8', 8", 8n. The circuit cards are supported mechanically by elongated guides 9, 9', 9", 9n.
In order that auxiliary electrical connections can be made to each circuit card, the same plurality of edge con-nectors 10 as circuit cards, i.e., 8n, are mounted upon rear 35 vertical wall 11, in individual alignment with each ZIF
connector 7n.
3~
A top planar frame-piece 12 is rigidly attached to wall 11, and may be similarly at-tached to sides at the le-ft and the right as well, for mechanical strength. These sides are not shown for sake of clarity; being of only ministerial significance.
In assembly, when the frame as a whole has been fabric-ated, -the several circuit cards 8, - 8n are pushed-inbetween corresponding ZIF connectors 7, _ 7n and guides 9, _ 9n until the contacts at the (left) end of the card enter edge con-nectors 10, etc. and are fully engaged.
The secondary -tier 2 is inherently the same as tier 1, save that the whole -tier is orthogonally related to tier 1.
The several parallel-disposed ZIF connectors 17, - 17 hold the several circuit cards 18, - 18n, which cards are also supported by ZIF connectors 27, - 27 The number of circuit cards in the second tier, say ten, is governed by the requirements of the over-all circuit oE
the structure. Plural edge connectors 20 are provided.
The third, or tertlary, tier 3 is inheren-tly the same as an inverted tier 1.
On the underside of mother-board 5 are located plural, spaced, parallel-related ZIF elongated connectors 23, 23', 23", 23n. These are aliglled with the prior series of such connectors 7, _ 7n atop mother-board ~1.
Connectors 23, - 23n each engage and make electrical contac-t with an equal nurnber of printed circuit cards 28, 28', 28", 28n. These circuit cards are supported rnechan-ically by elongated guides 29, 29', 29", 29n that are attached to a bottom planar frame-piece 22. The latter is the inverted ec~uivalent of frame-piece 12.
Similarly, auxiliary connections to circuit-cards 28,-28n are made to the same plurality of edge connectors 30 as there are circui-t cards. These connectors are mounted upon rear vertical wall 31, in individual alignment with each ZIF connector 23, - 23 Frame-piece 22 is rigidly attached to wall 31, which is also rigidly attached to mother-board 5. It may also be at-tached to sides at the leEt and the right as well, for mechanical strength. These sides are not shown, being oE only ministerial significance.
Each ZIF connector, such as 7 in Fig. 3, carries a large nu~ber of adjacent, but electrically separate, contacts 33 along both inner ver-tical surfaces. These mate with contacts upon a circuit card, such as contacts 34 (Fig. 1) upon card 8, Each contact 33 has a pin 35 that is mechanically and elect-rically mutually attached, one to the other; the pin extend-ing through the insulating material of the body of theconnec-tor.
These pins also pass through mother-board in a pattern that is shown at 4 in Fiy. 4, at 37 and 37A, for example, for ZIF connector 7. Items 37 and 37A are plated-through 15 holes; that is, the inner white area of each is a hole and -the surrounding black area is electroplating within the hole and at a larger area on each side of mother-board 4. Each pin 35 is forced into a hole 37, as in an arbor press, so that there is firm mechanical and electrical contact 20 between the electroplating within the hole and the pin.
Only certain pins are employed for connecting circuits on one circult card, as 8, to another circuit on another card, as 18. These are the pins that are pressed into the holes in the diamond-shaped conduc-tiv~ areas 40. The two 25 horizontally related holes are aligned with holes 37 and 37A, and so accept certain oE pins 35. The two vertically rel-ated holes are aligned with holes 41 and 41A, and so accept certain pins 39. Accordingly, four pins are connected together electrically Erom one ZIF connector to -the one adjacent to it on the opposite side of a mother-board, giving electrical contact redundancy.
Which pins are employed ~or connecting circuits from one circuit card to a related other card can be seen in the exploded view of Fig. 3. Two fc-ward pins 35 of ZIF connect-35 or 7 pass through a conductive area 40. Similarly, twoforward pins 42 of ZIF connector 17 pass through the same conductive area 40.
This establishes one connection between the tiers, such as connection 50 in Fig. 8. Numerous similax connections are also similarly established, for example, a total of 80 connections.
~ote that connection 50 is relatively long ln Fig. 8 because of -the normal drafting layout. However, the same connection in Fig. 4 is only a few millimeters (mm) long, from one pin to an adjacent pin in area ~0.
In Fig. 4 there are eight dotted "holes" surrounding conductive area 40A. These holes are absent around other areas, such as 40. This indicates that pins such as some of 35 and 39 are removed from the corresponding ZIF con-nectors to allow desired wor]cing room with respect to -the desired pins that enter area 40A, and other areas, such as 40.
Numerous aligned pins and holes 37, 37A, 41, 41A, etc.
are used as ground connections, establishing a desirable ground plane -to prevent circulating currents. A suitable bus connects the thus formed conductive plane to ground;
as to the frame at 6, ll, 2~, etc.
It is found that the very many pi.ns entering force-fit into the mo-ther-board hoLes is sufficient to form a rigid and permanent over-all structure. However, a pair of screws, as 52, are typically provided ~t each end to fasten each ZIF
connector to the mother-board, either by a tapped hole there-in, or by nuts (not shown~.
Fig. 5 shows an alternate arrangement of the conductive area 40 of Fig. 4. Two different types of ZIF connectors are predicated in Fig. 5, particularly as to having differ-30 ent spacing between companion rows. ~orizontally, the rowsof holes iden-tified as 55 are more widely spaced than the orthogonally disposed rows of holes identified as 56.
Conductive areas 57, 58, 59 and 60 typically connect rows 55 and 56 in groups of three pins~ This permits dual 35 paths -to be established, as for switching balanced audio signals or bidirectional streams of dataO
Fig. 6 shows another alternate conductive area arrange-ment. Four diagonal conductive traces on the mother-board connect two pins each, one for each row 55 and 56. This permits four paths to be established. The cross outline depic-ts an area that is not conductive; but areas 62 are.
Fig. 7 shows still a further arrangement. In the four central conductive holes 65 orepin from each of rows ~6 and ~7 occupies one hole. Adjacent pins are not removed.
A typical electrical application of the circuit struct-ure of this invention is fox a routing switcher. This is a device in which a number of inputs, say 100, can be connect-10 ed to any of 100 outputs by manipulating a push-button switchboard.
In Fig. lthe great many rectangular elements 70 are solid-state cross-points; that is, plural transistor dev-ices that accomplish signal transmission when "on" and 15 blocking signal transmission when "off".
These elements preferably have small inheren~ capac-itance, so that -the variation of "on" and "off" conditions do not significantly affect the whole circuit of which they are a part. Integrated circuit elements, suitable for -the 20 yigahertz Erequency range are suitable, such as the RCA
type CA3127E, which has very low inter-junction capacitances.
Typically three transistors are used for each cross-point, with an emi.t-ter-follower ou-tput. Thus constituted, the routi.ng switcher is suited for elther audio frequency or 25 video frequency signals.
The schematic circuit oE E~ig. 8 details how the elect-rical paths for switching are arranged.
An lnput 71 to -tier 1 enters a cross-point connec-tion 70` at "x". It proceeds therethrough and passes out of tier 1 on conductor 50. Conductor 50 in actuality is conductive area 40 of Fig. 3, as has been previously explained. The connection becomes input 72 in tier 2.
The signal output from tier 2 enters input 73 of tier 3, passes -to cross-point "~" thereof and out at output terminal 74.
Note that the signal that is processed passes through all of the three tiers. This is different than the prior art.
The "x" pa-th recited above is the normal path for a signal from input 71. Should this path not be available an alternate path via conductor 76 is available. This carries on through another circuit card 77 of the secondary group to second input 81 of ter-tiary card group 3, thence to output 74.
In normal use there are a number of inputs simultan-eously impressed upon group 1, with corresponding selected outputs. Being a -three stage routing switcher this appar-atus follows the Charles Clos type.
Card 78 in Fig. 8 represents card 2 of the primary group,wi-th an input at 79. This becomes an output of the primary tier and enters the second input 80 of the secondary tier card 2.
In the simpliEied diagram oE Fig. 2,-the top three cards 8, 8' and 8 are in primary tier 1 of Fig. 1~
Orthogonally related, cards 18, 18' and 18n are in -the secondary tier 2 o~ Fig. 1.
Further, cards 28, 28' and 28n having the alignment of the top three cards, are in the tertiary tier 3 of Fig~ 1.
Tracing input 1, this en-ters the first primary card 8 at 71. It progresses to ou-tput ~10, which is one of the conductive areas 40 shown in Fig. 4. Thence -to first sec-ondary card 18, at point 72. From there it passes through another conductive area 40 to Elrst tertiary card 28, at point 73. The signal exits card ~8 at output 74.
Other inputs take different but equivalent paths -through the routing switcher, as shown by the full and dotted lines and "x" points.
It will be recognized that the very short interconnect-ions in this structure via the conductive areas 40 results in a routing switcher, for an example, of superior elect-rical characteristics. Capacitance is low and inductance is very low. Also, the lack of relatively long wires run-35 ning in some proximity to other wires largely eliminates cross-talk !
Fig. lshows 8 circuit cards in primary tier 1, 10 cards in secondary tier 2, and 8 cards in tertiary tier 3. This 33~3 is no-t the only number of cards for the tiers. The number of cards depends upon the ultimate size of the switcher in terms of -the number of inputs and outputs -thereof.
~nother set of numbers embraces 10 cards in the primary tier, 19 cards in the secondary tier, and 10 cards in the tertiary tier.
The preferred manner of assembling the ZIF connectors is to first insert the individual contacts with the pins thereof in -the holes of the mother-board. Then -the housing;
i.e., the sides and bottom, is assembled with an arbor press and a jig.
The transistor cross-points specified for the exemplary routing switcher are unidirectional in signal flow. All signal flow is from an input -to an output.
Bidirectional signal flow can be obtained in an alter na-te construction in which tri-state buffer integrated circuits are substituted for the -transistor cross-points;
such as the 74LS365 hex. 3 state buffer. Also suitable are mechanical relays or silicon controlled rectifiers (SCRs).
Because oE the three stage (tier) construction and the very short inter-connections via conductive areas ~0, the size of the circuit structure of this invention is about one-fourth as large as conventional equipments of this type.
This is an importan-t practical advantage.
Each oE the ZIF connectors is provided with an end latch 21 (Fig. 1) of insulating material, which hinges open to allow the circuit card to enter the connector and is manually~closed over khe end of the card to retain it.
In Fig. l-the several solid-s-ta-te cross-polnt in-tegrated circuits 70 are shown as seven in number in each vertical row for the primary and tertiary tiers and six in number for the secondary tier.
In one typical embodiment there are ten primary matrices r nineteen secondary matrices, and ten tertiary 35 matrices. One primary card, as 7 has nineteen outputs each one of which becomes an input to a secondary card.
Each output of a secondary card becomes an input to a tertiary card.
However, the number of "x" point integrated circuits 70 may vary according to the extent of the switching requirements; for instance, ten in each vertical row.
A three stage routing switcher has been described to illustrate the circuit structure of this invention.
Five, seven, or even nine stage switchers can also be implemented by merely extending the technique that has 10 been taught.
The connections and circuit structure of -this invention are suited to carrying digital as well as analog signals.
Claims (10)
1. A three-dimensional circuit structure, comprising;
(a) plural planar, spaced, stacked mother-boards, (b) first plural, spaced, parallel-related zero-insertion-force elongated connectors upon one surface of each mother-board, (c) second plural, spaced, parallel-related zero-insertion-force elongated connectors upon the opposite surface of each mother-board orthogonally related to those on said one surface, (d) electrically conductive pins selectively extending through each said mother-board between said first and second connectors that electrically connect said connectors, and (e) circuit-carrying cards inserted in each said elongated connector and disposed perpendicularly to the mother-board, whereby a circuit upon a said card inserted in a said first elongated connector is electrically connected to a circuit upon a said card inserted in a said second elongated connector.
(a) plural planar, spaced, stacked mother-boards, (b) first plural, spaced, parallel-related zero-insertion-force elongated connectors upon one surface of each mother-board, (c) second plural, spaced, parallel-related zero-insertion-force elongated connectors upon the opposite surface of each mother-board orthogonally related to those on said one surface, (d) electrically conductive pins selectively extending through each said mother-board between said first and second connectors that electrically connect said connectors, and (e) circuit-carrying cards inserted in each said elongated connector and disposed perpendicularly to the mother-board, whereby a circuit upon a said card inserted in a said first elongated connector is electrically connected to a circuit upon a said card inserted in a said second elongated connector.
2. The structure of claim 1, in which;
(a) the structure is repeated to a total of three tiers of circuit cards.
(a) the structure is repeated to a total of three tiers of circuit cards.
3. The structure of claim 1, in which;
(a) each said circuit-carrying card carries a plurality of matrix cross-point circuits forming a routing type switcher assembly.
(a) each said circuit-carrying card carries a plurality of matrix cross-point circuits forming a routing type switcher assembly.
4. The structure of claim 1, in which;
(a) alternate tiers have the same number of circuit cards, and (b) intervening tiers have a larger number of circuit cards.
(a) alternate tiers have the same number of circuit cards, and (b) intervening tiers have a larger number of circuit cards.
5. The structure of claim 4, in which;
(a) each circuit card in an alternate tier has the same number of cross-points, and (b) each circuit card in an intervening tier has a fewer number of cross-points.
(a) each circuit card in an alternate tier has the same number of cross-points, and (b) each circuit card in an intervening tier has a fewer number of cross-points.
6. The structure of claim 3, in which;
(a) each said cross-point circuit is a unidirectional solid-state device.
(a) each said cross-point circuit is a unidirectional solid-state device.
7. The structure of claim 3, in which;
(a) each said cross-point circuit is a bidirectional device.
(a) each said cross-point circuit is a bidirectional device.
8. The structure of claim 1, in which;
(a) conductive pins of at least one zero-insertion-force connector, and (b) conductive pins of a zero-insertion-force connector that crosses said one zero-insertion-force connector orthogonally, mutually electrically contact a conductive area upon a said mother-board.
(a) conductive pins of at least one zero-insertion-force connector, and (b) conductive pins of a zero-insertion-force connector that crosses said one zero-insertion-force connector orthogonally, mutually electrically contact a conductive area upon a said mother-board.
9. The structure of claim 8, in which;
(a) holes allowing said pins to extend through said mother-board are plated through to be electrically conducting and are electrically connected, selectively, to a said conductive area.
(a) holes allowing said pins to extend through said mother-board are plated through to be electrically conducting and are electrically connected, selectively, to a said conductive area.
10. The structure of claim 8, in which;
(a) plural conductive pins extending through said mother-board that are out of electrical contact with said conductive area are connected together electrically and to an electrical ground.
(a) plural conductive pins extending through said mother-board that are out of electrical contact with said conductive area are connected together electrically and to an electrical ground.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/US1982/000776 WO1983004466A1 (en) | 1982-06-07 | 1982-06-07 | Tiered orthogonal related 3-d printed boards circuit |
| US82-00776 | 1982-06-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1193350A true CA1193350A (en) | 1985-09-10 |
Family
ID=22168031
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000409603A Expired CA1193350A (en) | 1982-06-07 | 1982-08-17 | Circuit structure |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS59501031A (en) |
| CA (1) | CA1193350A (en) |
| DE (1) | DE3249507T1 (en) |
| GB (1) | GB2133223B (en) |
| WO (1) | WO1983004466A1 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB9100403D0 (en) * | 1991-01-09 | 1991-02-20 | Plessey Telecomm | Orthogonal interconnection |
| US5335146A (en) * | 1992-01-29 | 1994-08-02 | International Business Machines Corporation | High density packaging for device requiring large numbers of unique signals utilizing orthogonal plugging and zero insertion force connetors |
| US5352123A (en) * | 1992-06-08 | 1994-10-04 | Quickturn Systems, Incorporated | Switching midplane and interconnection system for interconnecting large numbers of signals |
| FI991028A (en) * | 1999-05-05 | 2000-11-06 | Nokia Networks Oy | Arrangement and procedure at cross node node stand |
| GB2381955B (en) | 2001-11-08 | 2005-06-22 | Sun Microsystems Inc | Electronic circuits |
| GB2381953B (en) * | 2001-11-08 | 2004-04-28 | Sun Microsystems Inc | Rack-mountable systems |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US2955236A (en) * | 1960-10-04 | Printed circuit package | ||
| US2799837A (en) * | 1957-07-16 | Connector strip and chassis for interconnecting | ||
| US2701346A (en) * | 1953-11-05 | 1955-02-01 | Hughes Aircraft Co | Connector for circuit cards |
| US3206648A (en) * | 1961-07-21 | 1965-09-14 | Bunker Ramo | Coordinate array structure |
| US3355722A (en) * | 1965-04-20 | 1967-11-28 | Ibm | Compact semi-permanent information storage unit |
| US3660803A (en) * | 1969-10-08 | 1972-05-02 | Ncr Co | Electrical connectors |
| US3668476A (en) * | 1970-09-11 | 1972-06-06 | Seeburg Corp | Self-locking enclosure for electronic circuitry and method of assembling the same |
| DE2214678C3 (en) * | 1972-03-25 | 1979-06-13 | Stocko Metallwarenfabriken Henkels Und Sohn, Gmbh & Co, 5600 Wuppertal | Plug-in card arrangement for electronic circuits |
| LU77607A1 (en) * | 1976-04-02 | 1977-10-03 | ||
| US4220382A (en) * | 1978-12-15 | 1980-09-02 | Amp Incorporated | Bussing connector |
-
1982
- 1982-06-07 WO PCT/US1982/000776 patent/WO1983004466A1/en active Application Filing
- 1982-06-07 JP JP57502196A patent/JPS59501031A/en active Granted
- 1982-06-07 DE DE19823249507 patent/DE3249507T1/en not_active Withdrawn
- 1982-06-07 GB GB08402267A patent/GB2133223B/en not_active Expired
- 1982-08-17 CA CA000409603A patent/CA1193350A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| GB2133223A (en) | 1984-07-18 |
| DE3249507T1 (en) | 1984-09-06 |
| JPS59501031A (en) | 1984-06-07 |
| JPH023559B2 (en) | 1990-01-24 |
| GB2133223B (en) | 1985-10-23 |
| WO1983004466A1 (en) | 1983-12-22 |
| GB8402267D0 (en) | 1984-02-29 |
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| MKEX | Expiry | ||
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