CA1191278A - Data retention circuit - Google Patents
Data retention circuitInfo
- Publication number
- CA1191278A CA1191278A CA000436808A CA436808A CA1191278A CA 1191278 A CA1191278 A CA 1191278A CA 000436808 A CA000436808 A CA 000436808A CA 436808 A CA436808 A CA 436808A CA 1191278 A CA1191278 A CA 1191278A
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- Prior art keywords
- data
- signal
- power
- counting
- port
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1441—Resetting or repowering
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Sources (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
DATA RETENTION CIRCUIT
Abstract of the Disclosure A circuit for retention of electrically encoded data is provided that synchronizes the functions of a processor unit generating the data and a memory unit storing the data during a power-down sequence. A voltage comparator provides a signal when power to the circuit drops below a predetermined level, and the signal actuates transfer of data from volatile Random Access Memory to non-volatile Electrically Erasable Programmable Read Only Memory. A logic gate synchronizes the functions of the voltage comparator, processor, and memory units such that data is transferred between volatile and non-volatile memory and the processor is reset only after the processor has completed the servicing of any interrupt routines it may be running at the beginning of the power-down sequence.
Abstract of the Disclosure A circuit for retention of electrically encoded data is provided that synchronizes the functions of a processor unit generating the data and a memory unit storing the data during a power-down sequence. A voltage comparator provides a signal when power to the circuit drops below a predetermined level, and the signal actuates transfer of data from volatile Random Access Memory to non-volatile Electrically Erasable Programmable Read Only Memory. A logic gate synchronizes the functions of the voltage comparator, processor, and memory units such that data is transferred between volatile and non-volatile memory and the processor is reset only after the processor has completed the servicing of any interrupt routines it may be running at the beginning of the power-down sequence.
Description
~ 7 ~
l D~T~ RETENTION CIRCUIT
B~ck~round o~ the Invention . ~
l. Eield of the In~7~ntion This invention rel~tes to data retention systems, and especially to systems for storing electrically encoded data in the absence of electrical 10 power to the storage unit.
l D~T~ RETENTION CIRCUIT
B~ck~round o~ the Invention . ~
l. Eield of the In~7~ntion This invention rel~tes to data retention systems, and especially to systems for storing electrically encoded data in the absence of electrical 10 power to the storage unit.
2. Descri~tion of the Prior Art It is known in the art to provide inte~ra~ed circuit chips with both Random Access Memory (RAM) -~
and Electrical Erasable Progra~nable Read Only 15 Memory (EEPROM). Non-volatile data can be stored in the EEPROM while at the same time independent data can be accessed in the RAM memory. Data is transferred back and forth between the P~l and ~EPROM by simple store ancl array recall signals.
20 Moreover, the store 9ignal can be generated UpOIl loss of pow~r to the clevice in wllich the RA~I ancl EEPROM are uti.l:ized such that a non-volatile copy of all RAM data can be internally stored within the EEPROM without requiring power when power to 25 the device is lost.
It would be desirable to use a combined R~M
and EEPROM memory unit in conjunction with a micro processor to provide ready access by the processor to data within the RAM during normal operations, and for 30 storage of the data base in EEPROM when power to the memory ~mit is lost. Micro-processor functions, however, include various time sequenced operations, and a transfer of data from ~ I to EEPROM in ~he middle of such a time sequenced operation could creace an .~
l incomplere, inaccurate, and garbled da~a base within the EEPRO`I. For ins,ance, if ?ower were lost to a data ci~cuit ~vnile the micro-processor was servicing an interrupt routine, the transrer of data from R-~M
to EEPRO"I before the incerr~?t routine was finished could ,-esult in an unmeanin~ful data base beinO stored in the EEP~OM. Moreover, it would be desirable to reset the micro-processor registers upon an initial loss of power, but such a resetting while the processor 10 was servicing an interrupt routine could again cause the storage of an inaccurate data base within EEPRO~I.
An electrical circuit including a processor and mer..ory unit that would initiate transfer of data from volatile R~ to non-volatile EEPROM
15 memo~y and that would reset the processor registers during a circuit po~er-down sequence, but would delay the trans-~er of data from RA~I to EEPROiI and the resetting of the registers while the processor was servicing an intcrrupt routine, woukl be a decided aclvantage.
Summa~ f the ~nventlon The problem outlined above is in large measure solved by the data retention circuit in accordance with the presen~ invention. That is to 25 say, the data retention circuit hereor includes a processor and associated memory unit that trans-fers electrically coded data from RA~I to EEPROM memory when po~er to the circuit is lost, but delays the transfer o~ data from R-~I to EEPROM, 30 and also delays resetting of the processor, when the processor is servicing an inter~.^upt routirle.
The data retention circuit hereor broadly includes a processor configured as a co~mter for 35 counting a series of electrical ?u'ses and algebraically 1 adc ng the puls~ cou~t to a pr~viouslv determined count, a data s-orag~ unit for storing the results of che ?rocessor counting function that includes volatile .~ l memory and no..-~rolatile EEPRO~I memory, a voltage comparator for detecting the voltage level of the power applied to the circuit for generating a power-down signal when the voltage level falls below a predeter~ined level! and electrical gating means for transmi,ting the power-down signal to the memorv unit only when ~he processor is not servicing an -nterruDt routine, such that data in the me~ory unit is transferred from the RAM to EEPROM memory only when the processor is not servicing an interrupt function.
Brief Description of the Dr~r~in~r Figure 1 is a block diagram of a data retention circuit in accordance ~itll the prcsen.t inverlt:ioll.
Des(:riotion ol~ mbo(li.~lent Referring to the dra~ing~, a data reren~ion circuit 10 in accordance with the present invention is depicted in block diagram form. The elect-ical signal paths for information flow between functional modules are shown in solid lines, e~panded lateral:Ly when appropriate to indicate multi-conductor, parallel paths, and with arrowed heads to indicate directions of primar~y flow.
The data reten~.ion circuit ].0 broaclly includes processor 12, memory uni~ 14, low po~er detection circuit 16, lo~ power signal gate 18, display driver 20, and display unit 22.
The processor 12 2ay convenien.lv ~e a - 35 model 8748 eight bit micro-computer manufactured 1 by INTEL Corporation. Processor 12 includes an operatin~ power-recei~ing por~ 24, connected to a voltage regulated power source Vcc, a puls~-receiving port 26, and a sign por~ 28. Pulse-receiving por 26 is connected via line 28 to a source of electrical pulses as indicated by numeral 30. Sign port 28 is connected via line 32 to a control switch 3~. Processor 12 also includes a plurality of information ports including data ports 36, 38, ~iO, 42, 44, address ports 46, 48, 50, and data/address ports 52, 54, 56, 58. The processor 12 also includes recall enable ?ort 60, chip select port 62, write enable ports 64, 66, interrupt routine indicating port 68, and reset port 70.
Memory unit 14 may convenientl~ be a ~odel X2210 64X4 ~on-volatile Static RAM manufactured by ~ICOR, Inc. The memory unit 14 includes a control portion 72, Random Access Memory (R~l) por-ti.on 74, ancl Electrically Erasable Programmable Reacl Onl~ Memory portion (F~PRO~I) 76. Memoryunit 14 also incllldes operating po~er-receiving connection point 78 connected to the voltage regulated power source Vcc, recall enabling connection point 80 connected to the processor recall port 60 via line 82, chip select connection point 84 connected to processor chip selection port 62 via line 86, write enable connection point 88 connected to processor write enable por' 64 via line 90, and store enable connectlon point 92. Data connection points 94, 96, 98, lOO are connected ;o processor data ports 36, 38, 40, 42 via lines 102, 104, 106, 108 respectively. Address connection points 110, 112, 114, 116 are connected to processor address/data ports 52, 54, 56, 58 via lines 118, 120. 122, 124.
1 The low power detection circuit 16 includes voltage comparator 126 which may conveniently be a model LM339 comparator manufactured by National Semi-Conductor Corporation. The low power detection circuit includes voltage dividing resistors 128, 130, 132, 134, biasing resistor 136, and feed back resistor 138. Circuit point 140 common to resistors 130 and 136 is connected to the voltage regulated power supply Vcc. Reslstor 132 is connected to an unregulated po~er source V at circuit point 142.
Power source V also supplies power to a voltage regulator (not shown) which provides the volta~e regulated operating power Vcc to the circuit 10.
The operational ampli~ier 126 includes input circuit points 144, 146, and output circuit point 148.
Gate 18 cornprises a logic "AND" gate having a first input termlnal 150 connect:ed to voltage co~nparator O-ltpUt circ~li.t pOi~lt 1.48 via inverter 152. Gate 18 may conveniently be a model SN74LSll and inverter 152 may conveniently be model SN74LS04, both manufactured by Texas Instruments, Inc.
Gate 18 also includes a second input terminal 154 connected to processor interrupt indicating port 68 via line 156, and an output terminal 158 operably coupled to memory unit store enable connection point 92 and processor reset port 70, via inverter 160 and line 162. Inverter 160 rnay again conveniently be a model SN74LS04 manu.Eact~lred by Texas Instruments, Inc.
Display driver 20 may conveniently be.a model IC~1721~C Universal Eight Digit LED Driver ~ System manu~actured by Intersil Corporation. The display driver includes in~ormation ports 164, 166, 168, 170, 172, 174, 176 and 178 comlected via lines 118, 120, 122, 124 and 180 to processor data and 7~
address/da~a por.a 44, 52, 54, 56, 58 and to ?rocessor address ports 46, 4&, 50 via lines 1&2, 184, 1&6. ~rite enable port 188 of driver 20 is connected to processor write enable port 66 via line 190.
Displav 22 advantageouslv comDrises âi.;, seven-segment LED displays. The display 22 is connected to display driver 20 by LED select bus 192, and segment select bus 1~4. As ~ill be appreciated, the ICM7218 Uni.versal LED Driver System includes onboard memory such that the six LED's of the display 22 may simultaneously display numerical information.
In operation, processor 12 is programmed to count the series of pulses 30 received at port 26, and the pulse count is algebraicallv added to the previously determined count as stored in memory unit 14, to main~ain the latter ancl the clisp:lay' 22 Ln regularly up-dated conditi.on. Tlle pulse count .Eor the pulse train 30 :is trea~:ed as e~ her an adclerlcl or a s~lbtrahetld depending on the disposition oE s~itch 34 and the corresponding input at sign po-t 8. Data representing the result of the processor function is tr~nsrerred to the memory unit 14 via lines 102, 104, 106, and 108, and is addressed within the memory unit 14 via lines 118, 120, 122, and 124. At the same time, data is transferred to display driver 20 and di.splay 22 so that the results o~ the count are visually displayed. Data is transferred to the display driver 20 over lines 118, 120, 122, 124 and 180 and is addressed via line 182, 184, 186..
As will be appreciated, the information travelling over lines 11&, 120, 122 and 124 must ~e mul~iplexed ~3l2~
.
1 as between memory unit 14 and displa" ~~-ver 20.
Informa~ion transfe~red bet~een .he ?rocessor 12, and memory unit 14 and displav driver 20, is contrclled in the conventional manner by chip select line 86 and write enable lines 90 and 190.
Under normal operating conditions, da a is s~ored ~ithin RAII portion 74 of memory unit 14.
When the unregulated po~er source V drops below a predetermined voltage level, as measured against the voltage of the regulated power source Vcc by voltage comparator 16, ho~ever, an output from voltage comparator 16 is generated and presented at circuit point 148. The lo~ po~er output is illustrativelv assumed to be a logic 0, and is inverted tO a logic 1 by inverter 152 for presentation to the ~irst terminal 150 of loglc gate 18. When the second terminal 154 ol. logic gate 18 is also at logic 1, a l.ogic 1 signal is presentecl at the OUtp-lt termina:L :L58 oE logic gate 13. Inverter 160 ~ inve~rts the logic 1 to a logic 0 and the Logic 0 signal is transmitted to the store enable connection point 92 of memory unit 14 and reset port 70 of processor 12 via line 162. Control portion 172 of memory unit 14 is actua_ed by the logic 0 signal presented at store enable connection point 92 such that the entire data base stored in the RAM portion 74 is transrerred to the EEPROM portion 76 of the memory ~nit.
Data may be stored in the EEPROM portion 76 of memory unit 14 ~ithout po~er indefinitelv.
T.t shou:Ld be unclerstood that the processor 12 will typically be -lso utilized for concur-ently performing functions in addition to those directly . 35 ~ 7 ~
1 related to this invention~ ch are conventionally handled by ~he ~rocess~ ~' on an interr~pt driven basis such th~t .he pr~gram~ed ~ou~ es for such o-ther functions will be ir~oked -o~ ,e to time in response ~o the occurrence of _orresponding interru?t signals.
The reset function of .he processor 12 is actuated when a logic 0 is presented at the reset port 70 of .he micro-processor 12 Due to the 10 function of logic ~ND gate 18, as described above, a logic 0 will not be presented at reset port 70 unless the unregulated power source V drops below the predetermined voltage level, and the mi~ro-processor ls not performing in interrupt function 15 ~Iore specifically, a logic 0 will not be presented to the reset port 70 unless the voltage comparato:
16 indicates a 10W voltage by presentinz a lo~ic 1 at terminal 150 of AND gate 18, ancl the F~rocessor indicates the non-performance of an lnterrupt routine 20 by prescnting a logic 1 at the interrupt rou~ine indicatiIlg port 68, ~hich is conve~ecI to t!~e second inp-lt terminal of ~ND gate l$ via lir~e 15G
A data recall signal will be transmitted to the memory unit recall enabling connection 25 point 80 from the processor 1~ when po~er is restored to circuit 10, and the processor 12 has settled to a steady operating state Data will then be transferred from the EEPROiI portion 76 to the RA*~ portion 74 of memorr unit 14, whe-e the 30 data may be accessed by the processor 12
and Electrical Erasable Progra~nable Read Only 15 Memory (EEPROM). Non-volatile data can be stored in the EEPROM while at the same time independent data can be accessed in the RAM memory. Data is transferred back and forth between the P~l and ~EPROM by simple store ancl array recall signals.
20 Moreover, the store 9ignal can be generated UpOIl loss of pow~r to the clevice in wllich the RA~I ancl EEPROM are uti.l:ized such that a non-volatile copy of all RAM data can be internally stored within the EEPROM without requiring power when power to 25 the device is lost.
It would be desirable to use a combined R~M
and EEPROM memory unit in conjunction with a micro processor to provide ready access by the processor to data within the RAM during normal operations, and for 30 storage of the data base in EEPROM when power to the memory ~mit is lost. Micro-processor functions, however, include various time sequenced operations, and a transfer of data from ~ I to EEPROM in ~he middle of such a time sequenced operation could creace an .~
l incomplere, inaccurate, and garbled da~a base within the EEPRO`I. For ins,ance, if ?ower were lost to a data ci~cuit ~vnile the micro-processor was servicing an interrupt routine, the transrer of data from R-~M
to EEPRO"I before the incerr~?t routine was finished could ,-esult in an unmeanin~ful data base beinO stored in the EEP~OM. Moreover, it would be desirable to reset the micro-processor registers upon an initial loss of power, but such a resetting while the processor 10 was servicing an interrupt routine could again cause the storage of an inaccurate data base within EEPRO~I.
An electrical circuit including a processor and mer..ory unit that would initiate transfer of data from volatile R~ to non-volatile EEPROM
15 memo~y and that would reset the processor registers during a circuit po~er-down sequence, but would delay the trans-~er of data from RA~I to EEPROiI and the resetting of the registers while the processor was servicing an intcrrupt routine, woukl be a decided aclvantage.
Summa~ f the ~nventlon The problem outlined above is in large measure solved by the data retention circuit in accordance with the presen~ invention. That is to 25 say, the data retention circuit hereor includes a processor and associated memory unit that trans-fers electrically coded data from RA~I to EEPROM memory when po~er to the circuit is lost, but delays the transfer o~ data from R-~I to EEPROM, 30 and also delays resetting of the processor, when the processor is servicing an inter~.^upt routirle.
The data retention circuit hereor broadly includes a processor configured as a co~mter for 35 counting a series of electrical ?u'ses and algebraically 1 adc ng the puls~ cou~t to a pr~viouslv determined count, a data s-orag~ unit for storing the results of che ?rocessor counting function that includes volatile .~ l memory and no..-~rolatile EEPRO~I memory, a voltage comparator for detecting the voltage level of the power applied to the circuit for generating a power-down signal when the voltage level falls below a predeter~ined level! and electrical gating means for transmi,ting the power-down signal to the memorv unit only when ~he processor is not servicing an -nterruDt routine, such that data in the me~ory unit is transferred from the RAM to EEPROM memory only when the processor is not servicing an interrupt function.
Brief Description of the Dr~r~in~r Figure 1 is a block diagram of a data retention circuit in accordance ~itll the prcsen.t inverlt:ioll.
Des(:riotion ol~ mbo(li.~lent Referring to the dra~ing~, a data reren~ion circuit 10 in accordance with the present invention is depicted in block diagram form. The elect-ical signal paths for information flow between functional modules are shown in solid lines, e~panded lateral:Ly when appropriate to indicate multi-conductor, parallel paths, and with arrowed heads to indicate directions of primar~y flow.
The data reten~.ion circuit ].0 broaclly includes processor 12, memory uni~ 14, low po~er detection circuit 16, lo~ power signal gate 18, display driver 20, and display unit 22.
The processor 12 2ay convenien.lv ~e a - 35 model 8748 eight bit micro-computer manufactured 1 by INTEL Corporation. Processor 12 includes an operatin~ power-recei~ing por~ 24, connected to a voltage regulated power source Vcc, a puls~-receiving port 26, and a sign por~ 28. Pulse-receiving por 26 is connected via line 28 to a source of electrical pulses as indicated by numeral 30. Sign port 28 is connected via line 32 to a control switch 3~. Processor 12 also includes a plurality of information ports including data ports 36, 38, ~iO, 42, 44, address ports 46, 48, 50, and data/address ports 52, 54, 56, 58. The processor 12 also includes recall enable ?ort 60, chip select port 62, write enable ports 64, 66, interrupt routine indicating port 68, and reset port 70.
Memory unit 14 may convenientl~ be a ~odel X2210 64X4 ~on-volatile Static RAM manufactured by ~ICOR, Inc. The memory unit 14 includes a control portion 72, Random Access Memory (R~l) por-ti.on 74, ancl Electrically Erasable Programmable Reacl Onl~ Memory portion (F~PRO~I) 76. Memoryunit 14 also incllldes operating po~er-receiving connection point 78 connected to the voltage regulated power source Vcc, recall enabling connection point 80 connected to the processor recall port 60 via line 82, chip select connection point 84 connected to processor chip selection port 62 via line 86, write enable connection point 88 connected to processor write enable por' 64 via line 90, and store enable connectlon point 92. Data connection points 94, 96, 98, lOO are connected ;o processor data ports 36, 38, 40, 42 via lines 102, 104, 106, 108 respectively. Address connection points 110, 112, 114, 116 are connected to processor address/data ports 52, 54, 56, 58 via lines 118, 120. 122, 124.
1 The low power detection circuit 16 includes voltage comparator 126 which may conveniently be a model LM339 comparator manufactured by National Semi-Conductor Corporation. The low power detection circuit includes voltage dividing resistors 128, 130, 132, 134, biasing resistor 136, and feed back resistor 138. Circuit point 140 common to resistors 130 and 136 is connected to the voltage regulated power supply Vcc. Reslstor 132 is connected to an unregulated po~er source V at circuit point 142.
Power source V also supplies power to a voltage regulator (not shown) which provides the volta~e regulated operating power Vcc to the circuit 10.
The operational ampli~ier 126 includes input circuit points 144, 146, and output circuit point 148.
Gate 18 cornprises a logic "AND" gate having a first input termlnal 150 connect:ed to voltage co~nparator O-ltpUt circ~li.t pOi~lt 1.48 via inverter 152. Gate 18 may conveniently be a model SN74LSll and inverter 152 may conveniently be model SN74LS04, both manufactured by Texas Instruments, Inc.
Gate 18 also includes a second input terminal 154 connected to processor interrupt indicating port 68 via line 156, and an output terminal 158 operably coupled to memory unit store enable connection point 92 and processor reset port 70, via inverter 160 and line 162. Inverter 160 rnay again conveniently be a model SN74LS04 manu.Eact~lred by Texas Instruments, Inc.
Display driver 20 may conveniently be.a model IC~1721~C Universal Eight Digit LED Driver ~ System manu~actured by Intersil Corporation. The display driver includes in~ormation ports 164, 166, 168, 170, 172, 174, 176 and 178 comlected via lines 118, 120, 122, 124 and 180 to processor data and 7~
address/da~a por.a 44, 52, 54, 56, 58 and to ?rocessor address ports 46, 4&, 50 via lines 1&2, 184, 1&6. ~rite enable port 188 of driver 20 is connected to processor write enable port 66 via line 190.
Displav 22 advantageouslv comDrises âi.;, seven-segment LED displays. The display 22 is connected to display driver 20 by LED select bus 192, and segment select bus 1~4. As ~ill be appreciated, the ICM7218 Uni.versal LED Driver System includes onboard memory such that the six LED's of the display 22 may simultaneously display numerical information.
In operation, processor 12 is programmed to count the series of pulses 30 received at port 26, and the pulse count is algebraicallv added to the previously determined count as stored in memory unit 14, to main~ain the latter ancl the clisp:lay' 22 Ln regularly up-dated conditi.on. Tlle pulse count .Eor the pulse train 30 :is trea~:ed as e~ her an adclerlcl or a s~lbtrahetld depending on the disposition oE s~itch 34 and the corresponding input at sign po-t 8. Data representing the result of the processor function is tr~nsrerred to the memory unit 14 via lines 102, 104, 106, and 108, and is addressed within the memory unit 14 via lines 118, 120, 122, and 124. At the same time, data is transferred to display driver 20 and di.splay 22 so that the results o~ the count are visually displayed. Data is transferred to the display driver 20 over lines 118, 120, 122, 124 and 180 and is addressed via line 182, 184, 186..
As will be appreciated, the information travelling over lines 11&, 120, 122 and 124 must ~e mul~iplexed ~3l2~
.
1 as between memory unit 14 and displa" ~~-ver 20.
Informa~ion transfe~red bet~een .he ?rocessor 12, and memory unit 14 and displav driver 20, is contrclled in the conventional manner by chip select line 86 and write enable lines 90 and 190.
Under normal operating conditions, da a is s~ored ~ithin RAII portion 74 of memory unit 14.
When the unregulated po~er source V drops below a predetermined voltage level, as measured against the voltage of the regulated power source Vcc by voltage comparator 16, ho~ever, an output from voltage comparator 16 is generated and presented at circuit point 148. The lo~ po~er output is illustrativelv assumed to be a logic 0, and is inverted tO a logic 1 by inverter 152 for presentation to the ~irst terminal 150 of loglc gate 18. When the second terminal 154 ol. logic gate 18 is also at logic 1, a l.ogic 1 signal is presentecl at the OUtp-lt termina:L :L58 oE logic gate 13. Inverter 160 ~ inve~rts the logic 1 to a logic 0 and the Logic 0 signal is transmitted to the store enable connection point 92 of memory unit 14 and reset port 70 of processor 12 via line 162. Control portion 172 of memory unit 14 is actua_ed by the logic 0 signal presented at store enable connection point 92 such that the entire data base stored in the RAM portion 74 is transrerred to the EEPROM portion 76 of the memory ~nit.
Data may be stored in the EEPROM portion 76 of memory unit 14 ~ithout po~er indefinitelv.
T.t shou:Ld be unclerstood that the processor 12 will typically be -lso utilized for concur-ently performing functions in addition to those directly . 35 ~ 7 ~
1 related to this invention~ ch are conventionally handled by ~he ~rocess~ ~' on an interr~pt driven basis such th~t .he pr~gram~ed ~ou~ es for such o-ther functions will be ir~oked -o~ ,e to time in response ~o the occurrence of _orresponding interru?t signals.
The reset function of .he processor 12 is actuated when a logic 0 is presented at the reset port 70 of .he micro-processor 12 Due to the 10 function of logic ~ND gate 18, as described above, a logic 0 will not be presented at reset port 70 unless the unregulated power source V drops below the predetermined voltage level, and the mi~ro-processor ls not performing in interrupt function 15 ~Iore specifically, a logic 0 will not be presented to the reset port 70 unless the voltage comparato:
16 indicates a 10W voltage by presentinz a lo~ic 1 at terminal 150 of AND gate 18, ancl the F~rocessor indicates the non-performance of an lnterrupt routine 20 by prescnting a logic 1 at the interrupt rou~ine indicatiIlg port 68, ~hich is conve~ecI to t!~e second inp-lt terminal of ~ND gate l$ via lir~e 15G
A data recall signal will be transmitted to the memory unit recall enabling connection 25 point 80 from the processor 1~ when po~er is restored to circuit 10, and the processor 12 has settled to a steady operating state Data will then be transferred from the EEPROiI portion 76 to the RA*~ portion 74 of memorr unit 14, whe-e the 30 data may be accessed by the processor 12
Claims (6)
1. In an apparatus for performing a counting function and retaining data representing the results thereof;
means for counting a series of electrical pulses and for algebraically adding said pulse count to a previously determined count, said counting means including an operating power-receiving port adapted for coupling to a source of electrical power, a pulse-receiving port adapted for coupling to a source of said pulses to be counted, a sign port adapted for coupling to a control source for determining whether said pulse count represents an addend or a subtrahend, a plurality or information ports, and an indicating port adapted for presentation of a first signal when said counting means is servicing an interrupt routine and for presentation of a second signal when said counting means is not servicing an interrupt routine;
data storage means for storing said data representing said results of said counting function including volatile memory means, non-volatile memory means, means for controlling the storage of said data within said volatile and non-volatile memory means, a plurality of information connection points, an operating power-receiving connection point adapted for coupling to said power source, and an enabling connection point adapted for receiving an enabling signal for actuating the transfer of said data between said volatile memory means and said non-volatile memory means;
means for operably coupling said information ports and said information connection points;
means for detecting the operational level of the electrical power available to said apparatus from said power source including means for generating a firs t output when said power level is above a predetermined level and a second output when said power level is below said predetermined level, and a circuit point at which said outputs are alternatively presented;
gating means including a first terminal operably coupled with said circuit point, a second terminal operably coupled with said indicating port, and a third terminal operably coupled with said enable connection point, said gating means being responsive to said first and second signals and said first and second outputs for generating said enable signal and presenting said enable signal at said third terminal and hereby to said enable port when, and only when, said second output is presented at said first terminal and said second signal is presented at said second terminal, whereby said controlling means is enabled for transferring data from said volatile memory means to said non-volatile memory means when said power level drops below said predetermined level and said counting means are not performing an interrupt routine.
means for counting a series of electrical pulses and for algebraically adding said pulse count to a previously determined count, said counting means including an operating power-receiving port adapted for coupling to a source of electrical power, a pulse-receiving port adapted for coupling to a source of said pulses to be counted, a sign port adapted for coupling to a control source for determining whether said pulse count represents an addend or a subtrahend, a plurality or information ports, and an indicating port adapted for presentation of a first signal when said counting means is servicing an interrupt routine and for presentation of a second signal when said counting means is not servicing an interrupt routine;
data storage means for storing said data representing said results of said counting function including volatile memory means, non-volatile memory means, means for controlling the storage of said data within said volatile and non-volatile memory means, a plurality of information connection points, an operating power-receiving connection point adapted for coupling to said power source, and an enabling connection point adapted for receiving an enabling signal for actuating the transfer of said data between said volatile memory means and said non-volatile memory means;
means for operably coupling said information ports and said information connection points;
means for detecting the operational level of the electrical power available to said apparatus from said power source including means for generating a firs t output when said power level is above a predetermined level and a second output when said power level is below said predetermined level, and a circuit point at which said outputs are alternatively presented;
gating means including a first terminal operably coupled with said circuit point, a second terminal operably coupled with said indicating port, and a third terminal operably coupled with said enable connection point, said gating means being responsive to said first and second signals and said first and second outputs for generating said enable signal and presenting said enable signal at said third terminal and hereby to said enable port when, and only when, said second output is presented at said first terminal and said second signal is presented at said second terminal, whereby said controlling means is enabled for transferring data from said volatile memory means to said non-volatile memory means when said power level drops below said predetermined level and said counting means are not performing an interrupt routine.
2. In apparatus as set forth in Claim 1, wherein:
said counting means includes a reset port for resetting said counting means when an appropriate control signal is applied to said reset port, and there are provided means for operably coupling said third terminal with said reset port, whereby said enable signal is also applied to said reset port for resetting said counting means when said power level drops below said predetermined level and said counting means are not performing an interrupt routine.
said counting means includes a reset port for resetting said counting means when an appropriate control signal is applied to said reset port, and there are provided means for operably coupling said third terminal with said reset port, whereby said enable signal is also applied to said reset port for resetting said counting means when said power level drops below said predetermined level and said counting means are not performing an interrupt routine.
3. The apparatus as set forth in Claim 1, said counting means including a second indicating port adapted for presentation of a third signal when said counting means attains a steady operating state after power is applied to said apparatus from said power source, said data storage means including a second enabling connection point operably coupled to said second indicating port for receiving said third signal, said control means being responsive to said third signal for transferring data from said non-volatile memory means to said volatile memory means whereby said data is so transferred when said counting means attains said steady state.
4. The apparatus as set forth in Claim 1, said data storage means comprising a non-volatile static random access memory integrated circuit.
5. The apparatus as set forth in Claim 1, said detecting means comprising a voltage comparator.
6. The apparatus as set forth in Claim 1, including means operably coupled to said counting means for visually displaying said data.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US46404783A | 1983-02-04 | 1983-02-04 | |
| US06/464,047 | 1983-02-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1191278A true CA1191278A (en) | 1985-07-30 |
Family
ID=23842325
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000436808A Expired CA1191278A (en) | 1983-02-04 | 1983-09-15 | Data retention circuit |
Country Status (3)
| Country | Link |
|---|---|
| CA (1) | CA1191278A (en) |
| DE (1) | DE3400788A1 (en) |
| FR (1) | FR2540652A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110888605A (en) * | 2019-12-11 | 2020-03-17 | 重庆超力高科技股份有限公司 | EEPROM data writing method and device and electronic equipment |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4234920A (en) * | 1978-11-24 | 1980-11-18 | Engineered Systems, Inc. | Power failure detection and restart system |
| US4296338A (en) * | 1979-05-01 | 1981-10-20 | Motorola, Inc. | Power on and low voltage reset circuit |
| JPS56137209A (en) * | 1980-03-31 | 1981-10-27 | Nissan Motor Co Ltd | Electronic odometer for vehicle |
-
1983
- 1983-09-15 CA CA000436808A patent/CA1191278A/en not_active Expired
- 1983-11-22 FR FR8318595A patent/FR2540652A1/en not_active Withdrawn
-
1984
- 1984-01-12 DE DE19843400788 patent/DE3400788A1/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110888605A (en) * | 2019-12-11 | 2020-03-17 | 重庆超力高科技股份有限公司 | EEPROM data writing method and device and electronic equipment |
| CN110888605B (en) * | 2019-12-11 | 2023-10-20 | 重庆超力高科技股份有限公司 | EEPROM data writing method and device and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2540652A1 (en) | 1984-08-10 |
| DE3400788A1 (en) | 1984-08-09 |
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| MKEC | Expiry (correction) | ||
| MKEX | Expiry |