CA1161969A - Method of fabricating semiconductor devices using laser annealing - Google Patents
Method of fabricating semiconductor devices using laser annealingInfo
- Publication number
- CA1161969A CA1161969A CA000402487A CA402487A CA1161969A CA 1161969 A CA1161969 A CA 1161969A CA 000402487 A CA000402487 A CA 000402487A CA 402487 A CA402487 A CA 402487A CA 1161969 A CA1161969 A CA 1161969A
- Authority
- CA
- Canada
- Prior art keywords
- polysilicon
- layer
- antireflective coating
- laser
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000004065 semiconductor Substances 0.000 title claims abstract description 6
- 238000005224 laser annealing Methods 0.000 title abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 69
- 229920005591 polysilicon Polymers 0.000 claims abstract description 69
- 238000000034 method Methods 0.000 claims abstract description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 239000006117 anti-reflective coating Substances 0.000 claims abstract description 13
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 230000005855 radiation Effects 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 claims description 9
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 229910052786 argon Inorganic materials 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 3
- 229910017604 nitric acid Inorganic materials 0.000 claims description 3
- 230000008859 change Effects 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims 1
- 229910052731 fluorine Inorganic materials 0.000 claims 1
- 239000011737 fluorine Substances 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 6
- 239000002019 doping agent Substances 0.000 abstract description 2
- 239000000155 melt Substances 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 11
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 10
- 229910052698 phosphorus Inorganic materials 0.000 description 10
- 239000011574 phosphorus Substances 0.000 description 10
- 150000004767 nitrides Chemical class 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H01L29/66575—
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical & Material Sciences (AREA)
- High Energy & Nuclear Physics (AREA)
- Plasma & Fusion (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Recrystallisation Techniques (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
METHOD OF FABRICATING SEMICONDUCTOR DEVICES USING LASER ANNEALING
Abstract of the Disclosure In the manufacture of VLSI (very large scale integrated) MOS (metal-oxide-semiconductor) circuits, a polysilicon gate is deposited on an oxide layer overlaying a silicon substrate. Ideally, the polysilicon gate is made extremely small and with sharply defined vertical boundaries. The invention proposes depositing a polysilicon layer, covering a region of the layer with an antireflective coating, and laser annealing the layer. Laser radiation is absorbed to a higher level by the coated region than elsewhere and consequently the polysilicon layer in this region melts and recrystallizes into large grains. The polysilicon layer is then etched using etch conditions ensuring preferential etching of unrecrystallized polysilicon in comparison with recrystallized polysilicon. Consequently, except at the coated region, the polysilicon is etched quickly and there is very little undercutting of the gate region. Preferential etching methods based on differing dopant levels in polysilicon are known but do not produce the sharp edge definition enabled using the present process.
- i -
Abstract of the Disclosure In the manufacture of VLSI (very large scale integrated) MOS (metal-oxide-semiconductor) circuits, a polysilicon gate is deposited on an oxide layer overlaying a silicon substrate. Ideally, the polysilicon gate is made extremely small and with sharply defined vertical boundaries. The invention proposes depositing a polysilicon layer, covering a region of the layer with an antireflective coating, and laser annealing the layer. Laser radiation is absorbed to a higher level by the coated region than elsewhere and consequently the polysilicon layer in this region melts and recrystallizes into large grains. The polysilicon layer is then etched using etch conditions ensuring preferential etching of unrecrystallized polysilicon in comparison with recrystallized polysilicon. Consequently, except at the coated region, the polysilicon is etched quickly and there is very little undercutting of the gate region. Preferential etching methods based on differing dopant levels in polysilicon are known but do not produce the sharp edge definition enabled using the present process.
- i -
Description
1 1¢1~
This invention relates ko a comhined selective laser annealing and preferential etching process for producing polvsilicon gates and interconnections for VLSI (very 1arge scale integrated) circuits.
VLSI MOS (metal-oxide-semiconductor) circuits are characterized by high speed and packing density. These properties are achieved by processing the semiconductor wafer to produce devices which occupy a small area and have shallow junctions. VLSI MOS devices are typified by the MOS FET (field effect transistor), which consists of relatively high conductivity source and drain regions formed within a silicon substrate. A channel extends between the source and drain at the junction of the substrate with an overlying oxide layer. A highly conducting gate overlies the oxide layer above the channel region and conduction in the channel region is controlled by applying a voltage to the gate.
In a well-known fabrication process, an oxide layer is first grown on a silicon substrate and then a polysilicon layer is deposited over the oxide layer. The polysilicon layer is etched to leave the required small gate region and then is doped by phosphorus diffusion to render it more conducting. These steps are performed using conventional photolithographic techniques.
A problem with this fabrication process is that the junction formation in the source and drain regions of the device and the phosphorus diffusion into the polysilicon are normally carried out in one process. In that case, the diffusion may not be sufficient to decrease the polysilicon resistance because extensive impurity diffusion must be avoided in the formation of a shallow junction at the ;
$~
-' l .t ~
source and drain. Since the same polysilicon is used for gate electrodes and for interconnections in integrated circuits, its resistance must be lowered to fabricate high speed devices.
One way to decrease the polysilicon resistance is to carry on the phosphorus doping after or during the deposition of the film. In this case, however, it is difficult to pattern the polysilicon precisely and uniformly. Such high quality patterning is necessary, since threshold voltages of small geometry devices are highly sensitive to channel dimensions, (length and/or width)~ of less than 3~m. Therefore, doping during deposition is not practical for small goemetry devices since a uniform threshold voltage cannot be obtained.
Yamanaka et al, Journal of the Electrochemical Society, Volume 12~, (1979), page 1415, describe an alternative method for decreasing polysilicon resistance. This technique is based on the use of two individual diffusion processes; one is for achieving low resistivity polysilicon interconnects and the other is for obtaining shallow junctions in the source and drain regions. In addition, improved patterning of the polysilicon is achieved by a third diffusion step and the use of a 1:5 etch rate difference between phosphorus doped and undoped polysilicon. However, the disadvantage of this technique is the significant amount of undercut (as large as 70%) due to phosphorus diffusion into the undoped gate thereby limiting the minimum channel length required for the fabrication of small geometry devices.
According to the present invention, there is provided in a process of making silicon integrated circuits, the steps of depositing a layer of polysilicon on an insulating layer, covering a ~ I lLB~9~
region of the polysilicon with an antireflective coating, directing laser radiation at the polysilicon layer to recrystallize only an area of the polysilicon under the antireflective coating, and etching the polysilicon layer using etch conditions polysiliconed ensuring preferential etching of recrystallized polysilicon in comparison to unrecrystallized polysilicon.
Preferably the antireflective coating is a layer of silicon nitride (Si3N4). The insulating layer is -typically a layer of silicon dioxide (SiO2) produced by oxidation of the silicon substrate.
The laser radiation can be the output radiation from a continuous wave argon laser.
The etching is preferably carried out using plasma etching in an atmosphere of carbon tetrafluoride and oxygen at low pressure. Alternatively, wet etching can be performed using a rnixture of hydrofluoric acid~ nitric acid and acetic acid, In the case of plasma etching, the etch rate of unannealed polysilicon is ahout 11 times higher than that of laser annealed polysilicon. In the case of wet etching, the etch rate ratio of laser annealed and unannealed polysilicon is about 1:15.
The laser annealing can produce a grain size increase from about 500 R in initially deposited polysilicon to large crystals greater than 2~m x 20~m in the gate region.
Other process steps in the fabrication of VLSI MOS
devices which are well known in the art are used before laser annealing and after etching the polysilicon layer. These additional conventional steps will be described in the following specific description.
g - An embodiment of khe invention will now he ~scribed b~
way of example with reference to the accompanying drawinys in which:-Figures 1(a) to (e) are sectional views of a part of a silicon wafer showing stages in the fabrication of a VLSI MOS device using a method according to the invention;
Figure 2 is a graph showing the variation in reflectivity as a function of the thickness of a Si3N4coating used in the method;
and Figure 3 is a graph comparing the etch rates of unannealed and laser annealed polysilicon.
Referring to Figure 1 in detail, in the fabrication of a VLSI MOS device incorporating the n-channel, polysilicon gate MOS
transistor shown in Figure 1, a thick field oxide layer 10 is formed and a channel ~egion 12 is defined on a silicon substrate 11 by a standard localized thermal oxidation technique.
After growing a 500 A layer of gate oxide 14, a low pressure chemical vapour deposited (LPCVD) layer 16 of undoped polysilicon havinq a thickness of 0.5~m is deposited at 650C on the oxide layers 10 and 14. Subsequently a 600 A layer 18 of silicon nitride (Si3N4), is LPCVD deposited at 670C on the undoped polysilicon film. The nitride layer 18 is then patterned by standard photolithographic and etching techniques to limit it to a narrow 1-2~m strip 19 at the intended site of a transistor gate electrode or interconnection. A polysilicon region 21 under the nitride film 19 is then annealed using a continuous wave argon laser set to produce a beam diameter of 50~m, an output power of 11 watts, and a scanning speed of 100 cm/s. The temperature of the substrate 11 is maintained at 500C
9 ~ 9 during the laser annealing stage. IJncler the annealing conditions, the silicon nitride layer 19 functions as an antireflective coating which ensures selective laser recrystallization of the polysilicon region 21.
The polysilicon in region 21 is melted by the laser beam and rapidly recrystallizes into large grains as shown in Figure 1(a). An uncoated part 20 of the polysilicon layer is only slightly annealed and undergoes neither melting nor a ma~jor change in grain morphology.
The advantages o~ using silicon ni-tride as an antireflective coating in the selective laser annealing step are that it is compatible with silicon processing technology in terms of deposition, pattern definition, and etching selectivity with respect to polysilicon. Thus the nitride layer adheres well to the polysilicon and neither chemically affects nor is chemically affected by other materials used in the ~OS structure. In addition silicon nitride is transparent at the argon laser wavelength (500 nm) and its refractive index, nAR = 1.95, is less than that of polysilicon, nsi = 4~2, and very close to -the ideal value of n2~R= nSi~ for minimum reflection.
These optical properties of silicon nitride ensure maximum absorption of laser energy which is required in order to melt the underlying poly-2n silicon film~
The amount of radiation energy absorbed by thepolysilicon beneath the nitride layer is also critically dependent on the thickness of the nitride layer as shown in Figure 2. Therefore, the choice of a 600 A thick antireflective layer is crucial for successful selective laser annealing.
As a result of the selective laser annealing step, the resistivity of the polysilicon region 21 is halved and its grain size increases from around 600 A to greater than 2~m by 2n~m.
~ l~I9~
Referring to Figure 1(b), once the annealing step is completed, unmasked slightly annealed polysilicon 20 is etched away using either a plasma or wet etching technique. Plasma etching is carried out in an atmosphere of carbon tetrafluoride and 5% oxygen at a pressure of .4 torr. The etch rate is dependent upon applied radio frequency power which is typically between 400 and 600 watts. As shown in the Figure 3 graph, the etch rate of the unannealed polysilicon is about 11 times higher than that of the annealed polysilicon. Wet etching is carried out in a mixture of hydrofluoric acid, nitric acid and acetic acid, In this case, the etch rate difference between annealed and unannealed polysilicon areas is about 1:15. Using either wet or dry plasma etching techniques, precise and uniform patterning can be accomplished with less than 10% undercutting of the polysilicon gate reqion.
After the removal of the unannealed polysilicon layer 20, thermal oxidation is carried out to grow an additional 1nOOA oxide layer 22 on the oxide layer 10 and the exposed part of oxide layer 14.
As shown in Figure 1(c), the silicon nitride region 19 is then removed using hot phosphoric acid, Phosphorus is then diffused into the laser annealed polysilicon 21 at 1000C for 12 to 16 minutes in a predeposition diffusion step. The diffusion of phosphorus into the polysilicon region 21 significantly reduces the resistance of the region 21 to a value of 0.5 mQ- cm. The oxide layer 22 prevents phosphorus dopant from penetrating into source and drain reglons 24 and 26 in the substrate 11. If phosphorus penetration did occur, it would render the source and drain too heavily doped and their junction with the substrate 11 too deep for efficient operation.
Using standard photolithoyraphic techniques, the oxide over the source and drain regions 24 and 26 is etched away as shown in Figure 1(b). The source and drain regions 24 and 26 are then doped using standard phosphorus predeposition and drivr-in diffusion techniques to a required shallow junction depth of 0.2 to 0.~ m. This latter step can alternatively be accomplished by ion implantation and post implantation thermal annealing cycles as described by Colcaser in "Micro Electronics Processing and Device Design", John Wiley and Sons, N.Y. (1981), chapter 7. The diffusion and annealing steps cause further reduction in the resistivity of the polysilicon so improving the properties of this for the fabrication of high speed integrated circuits. After the doping of the source and drain regions 24 and 26, silicon dioxide is deposited using a well known technique to cover the exposed part of the channel 12 and the gate 21. Contact windows, (not shown) are then opened in the oxide and aluminum contacts are evaporated through the windows to contact the source and drain regions 24 and 26 to complete the fabrication of the n-channel, silicon gate ~OS transistor.
As described previously, the VLSI devices obtained have gates or other polysilicon interconnections which can be made extremely small, of the order of 1-2~m, and which have well-defined vertical edges. Although silicon nitride has properties which ideally suit it for use as an antireflective coating, other materials such as silicon dioxide can also be used. Although the embodiment of the invention clescribed is an n-~lOS FET, the invention can be used to make any silicon based integrated circuit device which has conductors formed from polysilicon.
This invention relates ko a comhined selective laser annealing and preferential etching process for producing polvsilicon gates and interconnections for VLSI (very 1arge scale integrated) circuits.
VLSI MOS (metal-oxide-semiconductor) circuits are characterized by high speed and packing density. These properties are achieved by processing the semiconductor wafer to produce devices which occupy a small area and have shallow junctions. VLSI MOS devices are typified by the MOS FET (field effect transistor), which consists of relatively high conductivity source and drain regions formed within a silicon substrate. A channel extends between the source and drain at the junction of the substrate with an overlying oxide layer. A highly conducting gate overlies the oxide layer above the channel region and conduction in the channel region is controlled by applying a voltage to the gate.
In a well-known fabrication process, an oxide layer is first grown on a silicon substrate and then a polysilicon layer is deposited over the oxide layer. The polysilicon layer is etched to leave the required small gate region and then is doped by phosphorus diffusion to render it more conducting. These steps are performed using conventional photolithographic techniques.
A problem with this fabrication process is that the junction formation in the source and drain regions of the device and the phosphorus diffusion into the polysilicon are normally carried out in one process. In that case, the diffusion may not be sufficient to decrease the polysilicon resistance because extensive impurity diffusion must be avoided in the formation of a shallow junction at the ;
$~
-' l .t ~
source and drain. Since the same polysilicon is used for gate electrodes and for interconnections in integrated circuits, its resistance must be lowered to fabricate high speed devices.
One way to decrease the polysilicon resistance is to carry on the phosphorus doping after or during the deposition of the film. In this case, however, it is difficult to pattern the polysilicon precisely and uniformly. Such high quality patterning is necessary, since threshold voltages of small geometry devices are highly sensitive to channel dimensions, (length and/or width)~ of less than 3~m. Therefore, doping during deposition is not practical for small goemetry devices since a uniform threshold voltage cannot be obtained.
Yamanaka et al, Journal of the Electrochemical Society, Volume 12~, (1979), page 1415, describe an alternative method for decreasing polysilicon resistance. This technique is based on the use of two individual diffusion processes; one is for achieving low resistivity polysilicon interconnects and the other is for obtaining shallow junctions in the source and drain regions. In addition, improved patterning of the polysilicon is achieved by a third diffusion step and the use of a 1:5 etch rate difference between phosphorus doped and undoped polysilicon. However, the disadvantage of this technique is the significant amount of undercut (as large as 70%) due to phosphorus diffusion into the undoped gate thereby limiting the minimum channel length required for the fabrication of small geometry devices.
According to the present invention, there is provided in a process of making silicon integrated circuits, the steps of depositing a layer of polysilicon on an insulating layer, covering a ~ I lLB~9~
region of the polysilicon with an antireflective coating, directing laser radiation at the polysilicon layer to recrystallize only an area of the polysilicon under the antireflective coating, and etching the polysilicon layer using etch conditions polysiliconed ensuring preferential etching of recrystallized polysilicon in comparison to unrecrystallized polysilicon.
Preferably the antireflective coating is a layer of silicon nitride (Si3N4). The insulating layer is -typically a layer of silicon dioxide (SiO2) produced by oxidation of the silicon substrate.
The laser radiation can be the output radiation from a continuous wave argon laser.
The etching is preferably carried out using plasma etching in an atmosphere of carbon tetrafluoride and oxygen at low pressure. Alternatively, wet etching can be performed using a rnixture of hydrofluoric acid~ nitric acid and acetic acid, In the case of plasma etching, the etch rate of unannealed polysilicon is ahout 11 times higher than that of laser annealed polysilicon. In the case of wet etching, the etch rate ratio of laser annealed and unannealed polysilicon is about 1:15.
The laser annealing can produce a grain size increase from about 500 R in initially deposited polysilicon to large crystals greater than 2~m x 20~m in the gate region.
Other process steps in the fabrication of VLSI MOS
devices which are well known in the art are used before laser annealing and after etching the polysilicon layer. These additional conventional steps will be described in the following specific description.
g - An embodiment of khe invention will now he ~scribed b~
way of example with reference to the accompanying drawinys in which:-Figures 1(a) to (e) are sectional views of a part of a silicon wafer showing stages in the fabrication of a VLSI MOS device using a method according to the invention;
Figure 2 is a graph showing the variation in reflectivity as a function of the thickness of a Si3N4coating used in the method;
and Figure 3 is a graph comparing the etch rates of unannealed and laser annealed polysilicon.
Referring to Figure 1 in detail, in the fabrication of a VLSI MOS device incorporating the n-channel, polysilicon gate MOS
transistor shown in Figure 1, a thick field oxide layer 10 is formed and a channel ~egion 12 is defined on a silicon substrate 11 by a standard localized thermal oxidation technique.
After growing a 500 A layer of gate oxide 14, a low pressure chemical vapour deposited (LPCVD) layer 16 of undoped polysilicon havinq a thickness of 0.5~m is deposited at 650C on the oxide layers 10 and 14. Subsequently a 600 A layer 18 of silicon nitride (Si3N4), is LPCVD deposited at 670C on the undoped polysilicon film. The nitride layer 18 is then patterned by standard photolithographic and etching techniques to limit it to a narrow 1-2~m strip 19 at the intended site of a transistor gate electrode or interconnection. A polysilicon region 21 under the nitride film 19 is then annealed using a continuous wave argon laser set to produce a beam diameter of 50~m, an output power of 11 watts, and a scanning speed of 100 cm/s. The temperature of the substrate 11 is maintained at 500C
9 ~ 9 during the laser annealing stage. IJncler the annealing conditions, the silicon nitride layer 19 functions as an antireflective coating which ensures selective laser recrystallization of the polysilicon region 21.
The polysilicon in region 21 is melted by the laser beam and rapidly recrystallizes into large grains as shown in Figure 1(a). An uncoated part 20 of the polysilicon layer is only slightly annealed and undergoes neither melting nor a ma~jor change in grain morphology.
The advantages o~ using silicon ni-tride as an antireflective coating in the selective laser annealing step are that it is compatible with silicon processing technology in terms of deposition, pattern definition, and etching selectivity with respect to polysilicon. Thus the nitride layer adheres well to the polysilicon and neither chemically affects nor is chemically affected by other materials used in the ~OS structure. In addition silicon nitride is transparent at the argon laser wavelength (500 nm) and its refractive index, nAR = 1.95, is less than that of polysilicon, nsi = 4~2, and very close to -the ideal value of n2~R= nSi~ for minimum reflection.
These optical properties of silicon nitride ensure maximum absorption of laser energy which is required in order to melt the underlying poly-2n silicon film~
The amount of radiation energy absorbed by thepolysilicon beneath the nitride layer is also critically dependent on the thickness of the nitride layer as shown in Figure 2. Therefore, the choice of a 600 A thick antireflective layer is crucial for successful selective laser annealing.
As a result of the selective laser annealing step, the resistivity of the polysilicon region 21 is halved and its grain size increases from around 600 A to greater than 2~m by 2n~m.
~ l~I9~
Referring to Figure 1(b), once the annealing step is completed, unmasked slightly annealed polysilicon 20 is etched away using either a plasma or wet etching technique. Plasma etching is carried out in an atmosphere of carbon tetrafluoride and 5% oxygen at a pressure of .4 torr. The etch rate is dependent upon applied radio frequency power which is typically between 400 and 600 watts. As shown in the Figure 3 graph, the etch rate of the unannealed polysilicon is about 11 times higher than that of the annealed polysilicon. Wet etching is carried out in a mixture of hydrofluoric acid, nitric acid and acetic acid, In this case, the etch rate difference between annealed and unannealed polysilicon areas is about 1:15. Using either wet or dry plasma etching techniques, precise and uniform patterning can be accomplished with less than 10% undercutting of the polysilicon gate reqion.
After the removal of the unannealed polysilicon layer 20, thermal oxidation is carried out to grow an additional 1nOOA oxide layer 22 on the oxide layer 10 and the exposed part of oxide layer 14.
As shown in Figure 1(c), the silicon nitride region 19 is then removed using hot phosphoric acid, Phosphorus is then diffused into the laser annealed polysilicon 21 at 1000C for 12 to 16 minutes in a predeposition diffusion step. The diffusion of phosphorus into the polysilicon region 21 significantly reduces the resistance of the region 21 to a value of 0.5 mQ- cm. The oxide layer 22 prevents phosphorus dopant from penetrating into source and drain reglons 24 and 26 in the substrate 11. If phosphorus penetration did occur, it would render the source and drain too heavily doped and their junction with the substrate 11 too deep for efficient operation.
Using standard photolithoyraphic techniques, the oxide over the source and drain regions 24 and 26 is etched away as shown in Figure 1(b). The source and drain regions 24 and 26 are then doped using standard phosphorus predeposition and drivr-in diffusion techniques to a required shallow junction depth of 0.2 to 0.~ m. This latter step can alternatively be accomplished by ion implantation and post implantation thermal annealing cycles as described by Colcaser in "Micro Electronics Processing and Device Design", John Wiley and Sons, N.Y. (1981), chapter 7. The diffusion and annealing steps cause further reduction in the resistivity of the polysilicon so improving the properties of this for the fabrication of high speed integrated circuits. After the doping of the source and drain regions 24 and 26, silicon dioxide is deposited using a well known technique to cover the exposed part of the channel 12 and the gate 21. Contact windows, (not shown) are then opened in the oxide and aluminum contacts are evaporated through the windows to contact the source and drain regions 24 and 26 to complete the fabrication of the n-channel, silicon gate ~OS transistor.
As described previously, the VLSI devices obtained have gates or other polysilicon interconnections which can be made extremely small, of the order of 1-2~m, and which have well-defined vertical edges. Although silicon nitride has properties which ideally suit it for use as an antireflective coating, other materials such as silicon dioxide can also be used. Although the embodiment of the invention clescribed is an n-~lOS FET, the invention can be used to make any silicon based integrated circuit device which has conductors formed from polysilicon.
Claims (11)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. In a method of making silicon integrated circuits, the steps of depositing a layer of polysilicon on an insulating layer, covering a region of the polysilicon with an antireflective coating, directing laser radiation at the polysilicon layer to recrystallize only an area under the antireflective coating, and etching the polysilicon layer using etch conditions ensuring preferential etching of unrecrystallized polysilicon in comparison to recrystallized polysilicon.
2. A method as claimed in claim 1, in which the antireflective coating is silicon nitride (Si3N4).
3. A method as claimed in claim 1, in which the insulating layer is silicon dioxide.
4. A method as claimed in claim 1, in which laser radiation is provided from a continuous wave argon laser.
5. A method as claimed in claim 1, in which the polysilicon layer is etched using a wet etchant comprising a mixture of hydrofluoric acid, nitric acid and acetic acid.
6. A method as claimed in claim 1, in which the polysilicon is plasma etched in a fluorine-based plasma.
7. A method as claimed in claim 1, in which the laser radiation produces in the polysilicon underlying the antireflective coating a change in grain size from approximately 500 .ANG. to a crystal size of at least 2µm x 20µm.
8. A method as claimed in claim 1, in which the polysilicon under the antireflective coating is laser annealed sufficiently to produce at least a halving of resistivity in comparison with the unannealed polysilicon.
9. A method as claimed in claim 1, in which the ratio of etch rates of unannealed and laser annealed polysilicon is from 11:1 to 15:1.
10. A method as claimed in claim 1, comprising the further steps subsequent to the preferential etch step, of removing the antireflective coating and diffusing material into the exposed annealed polysilicon to significantly increase the conductivity thereof.
11. A method as claimed in claim 10, specifically for fabricating metal-oxide-semiconductor (MOS) transistors, the method further comprising exposing areas of the substrate at spaced locations adjacent respective ends of the laser annealed polysilicon and diffusing material into the substrate to a shallow depth to provide transistor source and drain regions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000402487A CA1161969A (en) | 1982-05-07 | 1982-05-07 | Method of fabricating semiconductor devices using laser annealing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000402487A CA1161969A (en) | 1982-05-07 | 1982-05-07 | Method of fabricating semiconductor devices using laser annealing |
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| Publication Number | Publication Date |
|---|---|
| CA1161969A true CA1161969A (en) | 1984-02-07 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000402487A Expired CA1161969A (en) | 1982-05-07 | 1982-05-07 | Method of fabricating semiconductor devices using laser annealing |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1994027326A1 (en) * | 1993-05-12 | 1994-11-24 | Max-Planck-Gesellschaft zur Förderung der Wissenschaften e.V., Berlin | Electronic device with electrodes having microfeatures, and method of producing such a device |
-
1982
- 1982-05-07 CA CA000402487A patent/CA1161969A/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1994027326A1 (en) * | 1993-05-12 | 1994-11-24 | Max-Planck-Gesellschaft zur Förderung der Wissenschaften e.V., Berlin | Electronic device with electrodes having microfeatures, and method of producing such a device |
| US5810945A (en) * | 1993-05-12 | 1998-09-22 | Max-Planck-Gesellschaft Zur Forderung Der Wissenschaften E.V. | Method of fabricating an electronic micropatterned electrode device |
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