CA1159143A - Write control apparatus - Google Patents

Abstract

SPECIFICATION OF
STANLEY I. FRIEDMAN, CHARLES P. COBEEN AND HERBERT K. JACOBSTHAL
FOR
WRITE CONTROL APPARATUS
ABSTRACT OF THE DISCLOSURE

This relates to an apparatus for controlling the recording of data on magnetic tape in any one of the plurality of known formats; e.g. NRZI, PE or GCR each of which is comprised of special markers, characters and data records written at a pre-scribed sequence and for a predetermined length of time. A
plurality of mini-programs each consisting of an ordered series of instructions are stored in a first programmable read only memory (PROM). A special marker or space is written by accessing the appropriate mini-program in this first PROM. A second programmable read only memory is likewise accessed and contains information indicative of the length of time which the corresponding instruction accessed from the first PROM is to be carried out. After each instruction is carried out for a pre-scribed period of time, an address counter is incremented to access the next instruction in the mini-program.

Description

~ 1 5 ~ 3 WRITE CONTROL APPARATUS
by ST~NLEY I. FR~ N, C~ES P. COBEEN AND ~E~T K. J~DOB~E~L
BACRGROUND OF THE INVENTION
oS Field of the Invention This invention relates generally to the writing of data on magnetic mass storage media and, more particularly, to a tape controller write apparatus employing at least one programmable read only memory (PROM).
Modern data processing ~ystems may require information to be written on magnetic tape in Qne or more of several known formats; e.g. non-return to zero-change on ones (NRZI), phase encoded (PE), or group code recorded (GCR). Each of these for-mats will be briefly described below; however, detailed descriptions can be found in specifications available from the American National Standards Institute, specifically ANSI x 3.24-1973, ANSI x 3.39-1973 and ANSI x 3.54-1976.
Since each of these formats is comprised of special markers, characters and data records written in a prescribed sequence, it has, in the past, been necessary to provide a tremendous amount of logic circuitry to produce the required formatting.
This is not only costly, but adds to the overall complexi~y of the system.
~UMMARY OF THE I~rVENTION
It is an object of the present invention to provide an apparatus for writing data on magnetic tape in NRZI and PE
formats.
It is a further object of the invention that the write apparatus employ instructions stored in at least one PROM to 0 accomplish the required formatting thus eliminating a sub-1 1~9~3 stantial amount of logic circuitry.
According to a broad aspect of the invention there is pro-vided a write control apparatus for use in a data processing system wherein data must be recorded on magnetic tape in any one of a plurality of known formats, comprising: first memory means for storing a plurality of programs each consisting of an ordered series of instructions, each of said plurality of programs corresponding to a preselected one of said plurality of formats, the first instru-ction of each program having a starting address and the remainder of instructions in each program having sequentially higher address-es; address generating means coupled to said first memory means for accessing said first memory means; loading means coupled to said generating means for loading a desired starting address corres-ponding to a predetermined one of said plurality of formats into said address generating means; space generating means for deter-mining the length of time an accessed instruction is carried out;
and means for incrementing said address generating means.
The above and other objects of the invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:
BRIEF DESCRIPTION OF THE DRAWINGS
Figures lA, 1~ and lC illustrate formats for NRZI, PE and GCR data recording;
Figures lD and lE illustrate the data record format for PE and NRZI recording;
Figure 2 is a block diagram illustrating a tape handler control apparatus employing the inventive write control apparatus Figure 3 is a data flow charti Figure 4 is a block diagram of the write control apparatus according to the present in~ention; and Figure 5 is a logic diagram of the PROM control logic shown in Figure 4.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Figures lA, lB and lC illustrate the formats for NRZI, PE and GCR data recording. Referring to Figure lA, the NRZI

. q,~
~ - 2a -,~L ,,~

~ l~g~43 format ~egins with a beginning of tape (BOT) marker. This is followed by a plurality of data records each separated by 0.6 inches for a 9 track tape and by 0.75 inches for a 7 track tape.
After the last NRZI data record, a special character i.e. end 05 of-file (EOF) indicates the end of recording. The EOF
character is separated from the last data record by 3.75 inches for 7 track tape and the character itself is an octal 17. fQr-9 track tape, the EOF character trails the last data record by 0.6 inches and is an octal 23. Seven blank bits after the EOF
character there is written a longitudinal check character (LCC).
As shown in Figure lB, the phase encoded format begins with a BOT marker and a PE identification burst on track 4 consisting _ o all l's. The data records follow separated by 0.6 inches. ~~
After the last data record, there appears an end-of-file (EOF) character consisting of two hundred and fifty-l's on tracks 1, ~~~~~ ~

2, 4, 5, 7 and 8.
Finally, the GCR format as shown in Figure lC and begins with a BOT marker and GCR identification burst on track 6 consisting of all 1's. This is immediately followed by an auto-matic read amplification (ARA) burst consisting of all l's onall tracks. The ARA burst is then immediately followed by an AR~ identification character on tracks 2, 3, 5, 6, 8 and 9.
After a 0.3 inch gap, there is a plurality of data records which are terminated by an EOF character consisting of two hundred and fifty l's on tracks 1, 2, 4, 5, 7 and 8.
Figures lD and lE illustrate the data record format for PE
and NRZI recording respectively. Referring to Figure lD, the data is shown preceded by a preamble consisting of forty 0's and one 1 and is followed by a postamble consisting of one 1 and forty 0's.
Referring to Figure lE, which illustrates the NRZI data record format, the data record is shown as being followed by a longitudinal check character (LCC) when recording at 560 bits per inch (BPI) on 7 or 9 track tape or when recording at 800 35 BPI on 7 track tape. When recording at 800 BPI on 9 track tape, the data record is followed by a cyclic redundancy character (CRC) which is then followed by an LCC character.

~ ~ j, 9 ~
Addltiondl details of t~le various recording formats and data record formats can he found in the above cited ANSI specifications.
Fiqure 2 is a block diagram illustratinq in general form a tape handler control apparatus. The block representinq the inventive write 05 apparatus is shown in block 14. Microprogramnlable controller logic 2is shown as having an input from buffer 4 and from buffer 6. Buffer 6 is in turn coupled to a peripheral systems interface. Buffer 4 receives GCR information from GCR option apparatus which has an input coupled to the output of unit 10. Multiplexor 18 selects which of the tape handlers 20, 22, 24, and 26 is to be coupled into the remainder of the system for both reading and writinq purposes. In a read mode, an outPut of multiplexor 18 is coupled to the input of deskew unit 10.
In a write mode, an output of buffer 6 is coupled to the write general logic 14 which has an output coupled to multiplexor 18. Write logic 14 is coupled to the GCR logic 16 which provides the required GCR codinq. The details of GCR logic 16 is the subject of U.S. Patent 4,201,980, issued 6 May 1980 by Stanley I. Friedman, Charles P. Cobeen, and Herbert K.
Jacobsthal.
Figure 3 is a data flowchart illustrating how the various data formats described above are produced. Data in the form of 9 bit bytPs is first applied to switch 28. If the system is operating in a write mode~ switch 28 is enabled and passes the data through to packing apparatus 30. If for example, a 7 track tape handler is being employed, the packinq apparatus converts the 9 bit bytes to 7 bit bytes. However, in general, a 9 track handler is employed, and the 9 bit bytes are passed through unchanged.
The output of packing apparatus 30 is coupled into a first buffer 32 (Ro) which is in turn coupled to buffer 34 (R1) which is likewise in turn coupled to a third buffer 36 (R2). The use of the three buffers provides a certain amount of storage since the data to be written on the tape may be received randomly. The shifting of data from Ro to R1 to R2 assures that there is data in R2 buffer 36 when the time comes to pass data on to the appropriate tape handler.

As can be seen from Figure 3, t:he output of buffer 36 is coupled into switch 42. If the NRZI format is being constructed, CRC generator ~4 and LCC generator 46 produce the CRC and LCC characters described above. These are coupl~d o5 into switch 42 and therein join the data from R2 buffer 36.
Look ahead apparatus 40 is shown as having inputs coupled to the lnput and output of R2 buffer 36 respectively and having an output coupled to switch 42. ~rhis apparatus is provided if the PE format is being constructed and determines whether the last bit was a 1 or a 0. Thus, if the input and output of R2 buffer 36 are different, a phase bit is not included in the format. If, however, they are the same, a phase bit is included.
The output of switch 42 is coupled to an input of gate 48 which delivers the data to an appropriate tape handler. Several other control signals are shown as coupled to inputs of gate 48.
These control signals will be described in more detail below.
If the GCR format is being constructed, the output of R0 buffer 32 is coupled to the input of GCR data record write logic 50 which is described in detail in the a~ove cited application. It should be noted at this point that while Figure

3 represents the data flow required to produce the necessary formatting, it is the programmable read only memory which controls the data flow to produce the required characters and bits for the required periods of time, as will be described below.
Figure 4 is a block diagram of the write general logic 14 shown in Figure 2. A PROM instruction address counter has a first input coupled to an instruction address line and a second input coupled to a PROM command signal. When a PROM
command signal occurs, the instruction address is stored in the PROM address register 82. The output of register 82 is coupled into a PROM address counter 84 having an output which represents the address of an instruction stored in instruction PROM 86. The address output of counter 84 is also coupled into a repeat address PROM 92 whose output is applied to repeat counter 94. Repeat counter 94 is a binary down counter which generates a signal FREPT when the contents of the counter have been decremented to 0. This output is applied to one input of gate 96. The other input of gate 96 receives a terminate signal from the remainder of the system which indicates that the last i ~ 65? 3 ~1 ~

byte of information ls being recei~ed from the system. This terminate signal is denoted FWTRM.
The output of gate 96 (RSTDLISEQ~ is coupled to PROM control logic 90. Two signals FWI'C and DTAC~I are coupled to first and 05 second inputs respectively of a gate 98. The signal DTACH
represents tach pulses, a predetermined number of which are generated per inch of tape movement. The signal FWTC is a clock signal. The frequency of the clock signal and tach pulses may vary depending on the particular tape handlers being used. The output of gate 98 (D~CREPT) rep-resents a clock signal to achieve proper timing in repeat counter 94.
Instruction PROM 86 contains a plurality of stored instruc-tions in the form of mini-programs designed to accomplish various functions in producing the NRZI, PE and GCR formats.
These mini-programs are as follows:
NRZI:
A) 556 (7T ~ 9T) at BOT~ Erase Tape B) 800 (7T ~ 9T~ at BOT ~Erase Tape C) 556 (7T & 9T) /800 (7T) BOT - Data + LCC
D) 800 (9T) BOT - Data + CRC ~ LCC
E) 800 (9T) EOF ~ EOF + 7 Blanks + LCC
PE:
F) 1600 at BOT~ PE ID Burst G) 1600 GAP- Erase Tape H) 1600 BOT~ Preamble + Data + Postamble I) 1600 EOF ~ EOF BOT
GCR:
J) 6250 at BOT~ GCR ID Burst K) 6250 ~ ARA No. 1 Burst L) 6250 ~ ARA No. 2/ID CHAR + DATA
M) 6250 BOT ~ Data N) 6250 EOF ~- EOF BOT
Program A erases both 7 track and 9 track tape at the BOT
marker shown in Figure lA when the system is operating at 556 bits per inch (BPI). Program B performs the same function while operating at 800 BPI. Program C enables the writing of data , and the longitudinal check character on 7 and 9 track tape when operating at 556 BPI and on 7 track tape when operating at 800 ~' BPI as lon~ as no BOT mar~er appears. Program D enables the writing of data, the cyclic redundancy character and the longitudinal check character on 9 track tape when operating at 800 BPI as long as no BOT marker appears. Results of programs 05 C and D are shown in Figure lE. Program E enables the writing of the end of file character followed by seven blanks followed by a longitudinal check character ,~s shown in the right-hand portion of Figure lA.
Program F produces the PE identification burst shown in the right-hand portion of Figure lB. Program G erases the tape fox a distance of 0.6 inches between data records also shown in Figure lB. Program ~ enables the writing of data preceeded by a preamble and followed by a postamble such as is shown in Figure lD. Program I produces the end of file character shown in the right~hand portion of Figure lB.
Program J. produces the GCR identification burst shown in the left-most portion of Figure lC. Program K produces the first ARA burst and Program L produces the ARA identification character and initiates recording of the first GCR data record. Program M initiates recording of additional data records, and Program N produces the end of file character.
A total of fourteen instructions are required to construct the mini-programs described above. These are as follows:
251) LDRPTSTP - Load repeat counter and step.
2) ALZROS - Write all zeros 3) INTPT & JMP - interrupt and jump

4) WRTDTA - write data

5) WRTNLCC - write NRZI LCC
306) WRTCRC - write CRC
7) PEIDBRST - write PE identification burst 8) ALONES - write all ones 9) GCRIDBRST - write GCR identification burst 10) WRTGCRIDCHAR - write GCR identification 3511) WRTGDTA - write GCR data 12) PE/GCREOF - write PE and GCR end-of-file character 13) BLNX - blank 14) STALL - initialize PROM

Each of ~hese instructions stored in instruction PROM
86 are decoded in instruction PROM decode logic 88. Further, instructions 1 and 3 are applied to inputs of PROM control logic 90 along with the PROM command signal and RSTDLISEQ.
05 Upon receipt of instruction 1, PROM control logic 90 generates an increment signal (INCROMCT) which is applied to PROM address coun~er 84 and causes it to increment. A signal LDREPTCT is likewise generated and coupled into repeat counter 94 and serves as an enabling signal allowing the counter to count down. When either the interrupt and jump instruction of the RSTDLISEQ signal is received by PROM control logic 90, a load address counter signal tLDRADCNT) is applied to PROM
address counter 84 causing it to be loaded with the contents of PROM instruction address register 82.
To best illustrate the Gperation of the apparatus shown in Figure 4, reference is made to Appendix A and Programs C and J, for example. Referring to Program C which is em-ployed to write a data record followed by an LCC character as is shown in the left-hand portion of Figure lE, the operation begins by applying a PROM command signal to PROM instruction address register 82 and to PROM control logic 90 while instruc-tion 07 (write data) is applied to the seccnd input of PROM
instruction address register 82. PROM control logic 90 gen-erates the load address counter signal which causes the instruction address, now stored in PROM address register 82, to be loaded into PROM address counter 84. The instruction PROM 86 is accessed and decoded in decode logic 88. Thus, the decoded instruction is forwarded to the write logic caus-ing the data record to be written on tape. The PROM address counter is then incremented by an F~JTAM signal via gate 96 and PROM control logic 90 and a load repeat counter and step instruction address is applied to instruction PROM 86 and repeat address PROM 92. This address accesses a location in PROM 92 causing the contents of that location, in this case "3" to be loaded in the repeat counter 94. The,load repeat counter and step instruction after decoding in,idecode logic 88 is applied to the PROM control logic which causes the 52~2803 g L '~L t~

9_ qeneration o~ an LDREP~CT signal which enables repeat counter 94 to count down ln accordance with clock signals supplied by the output of gate 98. The PROM address counter 84 is again incremented by PROM control logic 90 to an address 09 which 05 corresponds to an instruction to write all 0'~. This instru-tion i5 accessed in PP~OM 85 and decoded in logic 88. Thus, while repeat counter 94 is being decremented, 0's are being written in the gap between the data record and the LCC char-acter shown in Figure lE. When the repeat counter reaches 0, an FREPT signal is generated causing an output from gate 96 to be applied to PROM control logic 90 which in turn again increments the PROM address counter to the 10 address.
This location in PROM a6 corresponds to a second load repeat counter and step instruction. The contents of this address in repeat address PROM 93 corresponds to a "1" which is loaded as before into repeat counter 94. The instruction is likewise accessed in PROM 86 and decoded in logic 88 and applied to PROM control logic 90. The application of the decoded instruction to control logic 90 again causes the PROM
address counter to increment to address 11 corresponding to a write NRZI LCC character. Also, the enabling line (LDREPTCT) is applied to repeat counter 94. When repeat counter 94 again reaches the 0 state, an output from gate 96 is applied to control logic 90 which in turn increments PROM address counter to the 12 address. This address corresponds to an interrupt and jump instruction which places the apparatus in a condition ready to accept a new instruction from PROM addrPss reqister 82. It should be clear that the combination of the repeat address PROM 92 and the repeat counter 94 functions as a space or distance gnerator and controls the length of time a par-ticular instruction is carried out.
Referring, in the Appendix, to Program J, which corres-ponds to the steps necessary to produce the GCR identification burst. The address 55 is placed on the instruction address input to PROM instruction address register 82~ This address is strobed into register 82 at the occurrence of a PROM com--mand signal applied to register 82 and to PROM control logic 90.

, 9 ~ ~ 3 PROM control logic 90 then generates a load address counter signal which permits the contents of address register 82 corresponding to a load repeat counter and step instruction to be loaded into PROM address counter 84. The instruction 05 is accessed in PROM 86 and decoded by logic 88. At the same time, the load repeat counter and step address is applied to repeat address PROM 92. The contents of that address in PROM 92 corresponds to a number "319". This number is for-warded to repeat counter 94. After decoding the instruction in instruction PROM decode logic 88, the instruction is applied to PROM control logic 90 which causes PROM address counter 84 to increment to the 56 state. This instruction corresponds to writing the GCR identification burst. As before, the load repeat and step instruction enables repeat counter 94 to count down in accordance with the clock signals supplied by gate 98. The length of time it takes for repeat counter 94 to decremeht to 0 corresponds to the three inch gap which appears in the left-hand portion of Figure lC. When the 0 state is reached, an FREPT signal is applied to gate 96 which forwards an RSTDLISEQ signal to PROM control logic 90.
This results in an increment signal being applied to PROM
address counter 84. Thus, PROM address counter is now in state 57. This state corresponds to an interrupt and jump instruction which places the apparatus in a condition for receiving the next command from PROM instruction address register 82. It should be clear that the next address to be loaded into PROM instruction address register 82 could be that which is necessary to produce the automatic read amp-lification (ARA) burst consisting of all l's on all tracks.
This is accomplished using mini-program X.
All the blocks shown in Figure 4 with the exception of PROM control logic 90 are commercially available units. For example, PROM instruction address register 82 may be a hex D
flip-flop of the type manufactured by Texas Instrument and having a part number SN 74174. The PROM address counter 84 and repeat counter 94 can b;é constructed from 4 bit up-down counters of the type also manufactured by Texas Instruments I~5~ 13 ~11--and bearing part number SN 74193. Instruction PROM 86 and repeat address PROM 92 are 256X~ PROMS of the type manu-factured by Monolithic Memories and having a part number 6300.
Finally, the instruction PROM decode logic 88 may be a binary oS one of 10 decode manufactured by Texas Instruments and bear-ing part number SN 7442.
Figure 5 is a logic diagram of the PROM control logic 90 shown in Figure 4. The PROM command signal is applied to the J input of flip-flop 100. After the next clock signal, the Q output of flip-flop 100 becomes high causing a logical l to appear at the input of NAND gate 110. Since flip-flop 104 is in the reset state, a logical 1 is presented to the input of the inverter. As a result, the output of N~ND gate 114 is a 1, and this output is presented to the second input of NAND
gate 110. Both inputs to NAND gate 110 are at a logical 1, and the output which is a logical 0 is applied to inverter 106 and thereafter to the J input of flip-flop 102. The next clock pulse will cause flip-flop 102 to become set resulting in a logical 1 being applied to an input of NAND gate 108.
During the next clock pulse, both of the inputs to NAND gate 108 will have a logical 1 thereon for a duration of one clock period thus producing an 0 output from NAND gate 108 corres-ponding to the load address counter signal previously described.
The Q output of flip-flop 102 is applied back into the K input of flip-flop 100, the K input of flip-flop 102 and the J input of flip-flop 10~. Thus, on the next clock pulse, flip-flops 100 a~d 102 will be reset and flip-flop 104 will be set. As a result, the output of inverter 112 will now become a logical 1.
When flip-flop 102 was set, a logical 0 was applied to one input of NAND gate 126 thus producing a logical 1 on the J input of flip-flop 134 and the K input of flip-flop 136.
During the next clock pulse, flip-flop 134 is set and flip-flop 136 is reset. The Q output of flip-flop 134 is appliel back to its K input and to the J input of flip-flop 136.
Thus, one clock period later, flip-flop 134 is reset and flip-flop 136 is set. The Q output of flip-flop 136 is applied 3 l, 4 3 to one input of NAND gate 120 and one input of NAND gate 116.
With a logical l on this inpu-t of NAND gate 116, an inter-rupt a~d jump signal on the second input of NAND gate 116 will cause an 0 to be applied to the second input of NAND
05 gate 114 and therefore a l on the second input of NAN3 gate 110. Thus, the occurrence of another PROM command signal would cause another LDRADCNT signal to be generated.
If a load interrupt and a step signal (LDREPT/STP) should occur, a zero will now appear at the output of NAND
gate 120. After inversion in inverter 130, a logical 1 will be applied to a first input of NAND gate 132. Thus, the next clock period will cause a load repeat counter (LDREPTCT) signal to be generated having a duration of one clock signal.
In the absence of a load repeat counter and step signal, a logical 1 appears at the output of NAND gate 12Q and at a first input of NAND gate 122. ~owever, the occurrence of a RSTDLISEQ signal after inversion in inverter 118 will cause a logical Q to be applied to the second input of NAND gate 122 resulting in a logical l at the input of inverter 124 and at the second input of NAND gate 128. Thus, during the next clock siganl, an increment signal (INCROMCT) will be generated and have a duration equal to one clock pulse. The resulting logical 0 at the output of inverter 124 will again cause flip-flop 134 to be set on the next clock.

t j L ~ 3 APPENDI X A
A. NRZI 556 (7T & 9T) AT BOT
.
ROM INSTRUCTION REPEAT PROM
ADDRS PROM DECODE _ CONTENT

01 LDRPT&STP ADR 1 SET 1668 INTO RPT
ADR (3" of tape) oS 02 ALZROS 2 03 INTPT&JMP 3 B. NRZI 800 (7T & 9T)AT BOT
.

(3" of tape) C. NRZI 556 ~7T &_T) /800 (7T) BOT NOT

08 LDRPT&STP ADR 1 SET "3" INTO RPT ADR

10 LDRPT& STP ADR 1 SET "1" INTO RPT ADR

12 INTRPT&JMP 3 D. NRZI 800 _ 9T ) BOT NOT

14 LDRPT~ STP ADR 1 SET "3" INTO RPT ADR

16 LDRPT&STP ADR 1 SET "1" INTO RPT ADR

. 18 LDRPT&STP ADR 1 SET "3" INTO RPT ADR

20 LDRPT&STP ADR 1 SET "1" INTO RPT ADR

22 INTRPT&JMP 3 E. NRZI 800 (9T) EOF
ROM INSTRUCTION REPEAT PROM
ADDRS PROM _ DECODE CQ~N~

05 24 LDRPT&STP ADR 1 SET "7" INTO RPT ADR

26 LDRPT&STP ADR 1 SET "l" INTO RPT ADR

28 INTRPT~JMP 3 F. PE 1600 BOT
31 LDRPT~STP CLK 1 SET 3200 INTO RPT ADR

33 INTRPT&JMP 3 G. 1600 GAP
34 LDRPT&STP ADR l SET 3200 INTO RPT ADR
35 BLNK l5 36 INTRPT&JMP 3 H. 37 LDRPT&STP ADR 1 SET 80 INTO RPT ADR

39 LDRPT&STP ADR 1 SET 2 INTO RPT ADR

42 LDRPT&STP ADR 1 SET 2 INTO ~PT ADR

44 LDRPT&STP ADR 1 SET 80 INTO RPT ADR

46 INTERCEPT&JMP 3 I. PE 1600 BOT NOT (EOF) 47 LDRPT&STP ADR 1 SET 500 INTO RPT ADR
i~ 48 PE/GCR EOF 12 49 INTRPT&JMP 3 J. GCR 6250 BOT
ROM INSTRUCTION REPEAT PROM
ADDRS ~ROMD!ECODE CONTENT
LDRPT&STP ADR l SET 319 INTO RPT ADR

57 INTRPT&JMP 00 3 - _ .

K. GCR 6250 ARA No. l BURST
61 LDRPT&STP ADR 1 SET 266 P.PT ADR

63 INTRPT&JMP 3 L. GCR 6250 ARA No.2/ID_CHAR + DATA
64 LDRPT&STP ADR 1 SET 851 RPT ADR

66 LDRPT&STP ADR l SET 212 RPT ADR
67 WRT GCR ID CH~R 10 68 LDRPT&STP ADR 1 SET 32 RPT ADR

INTRPT&JMP

M. GCR 6250 ~OT DATA

72 INTRPT&JMP 3 N. GCR 6250 BOT NOT (EOF) 80 LDRPT&STP ADR 1 SET 3 INTO RPT ADR

82 INTRPT&JMP 3

Claims (8)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A write control apparatus for use in a data processing system wherein data must be recorded on magnetic tape in any one of a plurality of known formats, comprising:
first memory means for storing a plurality of programs each consisting of an ordered series of instructions, each of said plurality of programs corresponding to a preselected one of said plurality of formats, the first instruction of each program having a starting address and the remainder of instructions in each program having sequentially higher addresses;
address generating means coupled to said first memory means for accessing said first memory means;
loading means coupled to said generating means for loading a desired starting address corresponding to a predetermined one of said plurality of formats into said address generating means;
space generating means for determining the length of time an accessed instruction is carried out; and means for incrementing said address generating means.

2. An apparatus according to claim 1 wherein said space generating means comprises:
second memory mean coupled to the output of said address generating means and accessed thereby; and first counting means coupled to the output of said second memory means; and means for loading said first counting means with the contents of an addressed location in said second memory means.

3. An apparatus according to claim 2 further including decoding means coupled to said first memory means for decoding instructions accessed from said first memory means.

4. An apparatus according to claim 3 wherein said address generating means comprises a binary counter.

Claim 5. An apparatus according to claim 4 wherein said loading means includes a register for storing a start-ing address.

Claim 6. An apparatus according to claim 5 wherein said first counting means comprises a binary down counter.

Claim 7. An apparatus according to claim 6 wherein said first memory means is a programmable read only memory.

Claim 8. An apparatus according to claim 7 wherein said second memory means is a programmable read only memory.