BR112013006661A2 - método e aparelho para operações de lógica universal - Google Patents
método e aparelho para operações de lógica universalInfo
- Publication number
- BR112013006661A2 BR112013006661A2 BR112013006661A BR112013006661A BR112013006661A2 BR 112013006661 A2 BR112013006661 A2 BR 112013006661A2 BR 112013006661 A BR112013006661 A BR 112013006661A BR 112013006661 A BR112013006661 A BR 112013006661A BR 112013006661 A2 BR112013006661 A2 BR 112013006661A2
- Authority
- BR
- Brazil
- Prior art keywords
- logic operations
- bits
- immediate value
- generate
- universal logic
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/3016—Decoding the operand specifier, e.g. specifier format
- G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30029—Logical and Boolean instructions, e.g. XOR, NOT
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
- G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Executing Machine-Instructions (AREA)
- Advance Control (AREA)
Abstract
método e aparelho para operações de lógica universal. a presente invenção refere-se a um aparelho e um método para a realização de operações de lógicas arbitrárias especificadas por uma tabela. por exemplo, uma modalidade de um método para realizar uma operação de lógica em um processador de computador compreende: a leitura de dados a partir de cada um de dois ou mais operandos da fonte; a combinação dos dados lidos a partir dos operandos da fonte para gerar um valor de índice, o valor de índice identificando um subconjunto de bits dentro de um valor imediato transmitido com uma instrução; a leitura dos bits a partir do valor imediato, e o armazenamento dos bits lidos a partir do valor imediato dentro de um registrador de destino para gerar um resultado da instrução.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/890,571 US8539206B2 (en) | 2010-09-24 | 2010-09-24 | Method and apparatus for universal logical operations utilizing value indexing |
| PCT/US2011/052913 WO2012040552A2 (en) | 2010-09-24 | 2011-09-23 | Method and apparatus for universal logical operations |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| BR112013006661A2 true BR112013006661A2 (pt) | 2016-06-07 |
Family
ID=45871870
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| BR112013006661A BR112013006661A2 (pt) | 2010-09-24 | 2011-09-23 | método e aparelho para operações de lógica universal |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US8539206B2 (pt) |
| JP (1) | JP5607832B2 (pt) |
| KR (1) | KR101524450B1 (pt) |
| CN (1) | CN103109261B (pt) |
| BR (1) | BR112013006661A2 (pt) |
| DE (1) | DE112011103197T5 (pt) |
| GB (1) | GB2499532B (pt) |
| TW (2) | TWI435266B (pt) |
| WO (1) | WO2012040552A2 (pt) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120124341A1 (en) * | 2010-11-17 | 2012-05-17 | Goodrich Allen B | Methods and Apparatus for Performing Multiple Operand Logical Operations in a Single Instruction |
| US20140095845A1 (en) | 2012-09-28 | 2014-04-03 | Vinodh Gopal | Apparatus and method for efficiently executing boolean functions |
| US9128698B2 (en) * | 2012-09-28 | 2015-09-08 | Intel Corporation | Systems, apparatuses, and methods for performing rotate and XOR in response to a single instruction |
| US9471310B2 (en) * | 2012-11-26 | 2016-10-18 | Nvidia Corporation | Method, computer program product, and system for a multi-input bitwise logical operation |
| GB2523823B (en) * | 2014-03-07 | 2021-06-16 | Advanced Risc Mach Ltd | Data processing apparatus and method for processing vector operands |
| US20160283242A1 (en) * | 2014-12-23 | 2016-09-29 | Intel Corporation | Apparatus and method for vector horizontal logical instruction |
| US20160179521A1 (en) * | 2014-12-23 | 2016-06-23 | Intel Corporation | Method and apparatus for expanding a mask to a vector of mask values |
| US10296489B2 (en) * | 2014-12-27 | 2019-05-21 | Intel Corporation | Method and apparatus for performing a vector bit shuffle |
| US10296334B2 (en) * | 2014-12-27 | 2019-05-21 | Intel Corporation | Method and apparatus for performing a vector bit gather |
| EP3782088B1 (en) * | 2018-04-20 | 2024-06-05 | Google LLC | Performing unitary iteration and indexed operations |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4237532A (en) * | 1977-09-02 | 1980-12-02 | Sperry Corporation | Table driven decision and control logic for digital computers |
| EP0349124B1 (en) * | 1988-06-27 | 1996-10-09 | Digital Equipment Corporation | Operand specifier processing |
| US5493687A (en) * | 1991-07-08 | 1996-02-20 | Seiko Epson Corporation | RISC microprocessor architecture implementing multiple typed register sets |
| US5881307A (en) | 1997-02-24 | 1999-03-09 | Samsung Electronics Co., Ltd. | Deferred store data read with simple anti-dependency pipeline inter-lock control in superscalar processor |
| JPH1185507A (ja) * | 1997-09-05 | 1999-03-30 | Mitsubishi Electric Corp | 中央処理装置およびマイクロコンピュータシステム |
| TW498275B (en) * | 1999-05-24 | 2002-08-11 | Toshiba Corp | Processor unit |
| US6792589B2 (en) * | 2001-06-15 | 2004-09-14 | Science & Technology Corporation @ Unm | Digital design using selection operations |
| US6721866B2 (en) | 2001-12-21 | 2004-04-13 | Intel Corporation | Unaligned memory operands |
| US7014122B2 (en) * | 2003-12-24 | 2006-03-21 | International Business Machines Corporation | Method and apparatus for performing bit-aligned permute |
| US7464255B1 (en) | 2005-07-28 | 2008-12-09 | Advanced Micro Devices, Inc. | Using a shuffle unit to implement shift operations in a processor |
| US8732686B2 (en) * | 2006-06-30 | 2014-05-20 | Intel Corporation | Generating optimal instruction sequences for bitwise logical expressions |
| US20080021942A1 (en) * | 2006-07-20 | 2008-01-24 | On Demand Microelectronics | Arrangements for evaluating boolean functions |
| US20080100628A1 (en) * | 2006-10-31 | 2008-05-01 | International Business Machines Corporation | Single Precision Vector Permute Immediate with "Word" Vector Write Mask |
| CN101178644B (zh) * | 2006-11-10 | 2012-01-25 | 上海海尔集成电路有限公司 | 一种基于复杂指令集计算机结构的微处理器架构 |
| US7941641B1 (en) | 2007-10-01 | 2011-05-10 | Yong-Kyu Jung | Retargetable instruction decoder for a computer processor |
-
2010
- 2010-09-24 US US12/890,571 patent/US8539206B2/en active Active
-
2011
- 2011-09-23 CN CN201180046100.2A patent/CN103109261B/zh active Active
- 2011-09-23 BR BR112013006661A patent/BR112013006661A2/pt not_active IP Right Cessation
- 2011-09-23 TW TW100134372A patent/TWI435266B/zh not_active IP Right Cessation
- 2011-09-23 DE DE112011103197T patent/DE112011103197T5/de not_active Withdrawn
- 2011-09-23 JP JP2013530347A patent/JP5607832B2/ja active Active
- 2011-09-23 TW TW103104892A patent/TWI512618B/zh not_active IP Right Cessation
- 2011-09-23 WO PCT/US2011/052913 patent/WO2012040552A2/en active Application Filing
- 2011-09-23 GB GB1306690.7A patent/GB2499532B/en active Active
- 2011-09-23 KR KR1020137008232A patent/KR101524450B1/ko active IP Right Grant
Also Published As
| Publication number | Publication date |
|---|---|
| JP5607832B2 (ja) | 2014-10-15 |
| KR20130064797A (ko) | 2013-06-18 |
| DE112011103197T5 (de) | 2013-07-04 |
| TWI512618B (zh) | 2015-12-11 |
| GB2499532B (en) | 2020-04-01 |
| CN103109261A (zh) | 2013-05-15 |
| TW201432564A (zh) | 2014-08-16 |
| TW201232392A (en) | 2012-08-01 |
| GB201306690D0 (en) | 2013-05-29 |
| GB2499532A (en) | 2013-08-21 |
| TWI435266B (zh) | 2014-04-21 |
| WO2012040552A2 (en) | 2012-03-29 |
| KR101524450B1 (ko) | 2015-06-02 |
| JP2013543175A (ja) | 2013-11-28 |
| US20120079244A1 (en) | 2012-03-29 |
| US8539206B2 (en) | 2013-09-17 |
| CN103109261B (zh) | 2016-03-09 |
| WO2012040552A3 (en) | 2012-05-18 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| B08F | Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette] | ||
| B08K | Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette] |