AU8736782A - Computer with expanded addressing capability - Google Patents

Description

PATENT APPLICATION OF ALEXANDER S. LUSHTAK AND JOHN S. FORKER FOR

COMPUTER WITH EXPANDED ADDRESSING CAPABILITY

BACKGROUND — Field of Invention

This invention relates to a computer, particularly to a computer having an expanded addressing capability.

BACKGROUND — Description of Prior Art

Digital computers generally have a limited addressing capability, i.e. the capabil ity to generate , write information to, and read information from , only up to a given number of memory addresses or locations. For example , in a computer operating on a binary radix ( i.e. a radix of two ) , and having sixteen addres s lines , the computer can generate up to 65536 addresses on its address lines ; these addresses can have any value from 0 to 65535. Each address may be a location in a memory or an input-output (I/O) port which connects the computer to addressable peripheral equipment, such as a keyboard , a printer , or a video display terminal. Each memory location usually consists of eight binary cells which can store a byte ( information word) consisting of ei ght bits ( ONES and ZEROES ) of binary information, and each I/O address can pass eight-bit bytes to and from the computer .

While the capability of addressing 65536 locations, which can contain 65536 x 8 = 524,288 binary cells , may seem like a relatively large capability, in actuality this amount of storage capability is considered relatively limited, even for a small computer, and severely limits the program and data handling and storage capability of the computer and the number of items of peripheral equipment which can be connected to the computer .

It is possible to increase the addressing capability of computer by providing additional address lines and making corresponding expansions in its program counter, instruction register, decoder, etc. However, it is difficult to do so since most small computers are now formed within a monolithic integrated circuit (usually termed a microprocessor) and the number of leads or input terminals of the microprocessor or "chip" are limited by package size. Also, many microprocessors have become standardized for mass .production and therefore have relatively low cost, so that increasing addressing capability requires redesign and commercial implementation of new and non-standard microprocessors at extremely great expense. Therefore it would be desirable to provide a means of expanding the addressing capability of a computer without increasing the number of its address lines or making other concomitant changes therein.

Heretofore, one method of increasing the address capability has been to provide a memory bank switching capability in which, in a given address range, two different banks of memory ar.e provided. Either bank was selectable in a separate bank-select cycle prior to the regular fetch/execute cycle. While the use of the bank selection or bank switching concept has been able to expand the addressing capability of a computer beyond its stated capacity, the degree of expansion possible was extremely limited and merely increased memory capacity slightly, such that a slightly longer program or some additional data could be stored. Host of the aforementioned limitations were still extant and the peripheral equipment capacity of the computer was not increased.

In prior bank switching or bank selection techniques, a non- selected memory bank was enabled or switched into an address range by supplying an enabling signal to latch in the memory bank- prior to the normal memory read or write operation. Host banks of read-only memories (ROHs) were provided in form of a monolithic integrated circuit (IC) or chip which was packaged in a standard or custom integrated circuit package having a plurality of terminals or leads, one of which was the "chip select" or "chip enable" terminal. When this terminal was supplied with an active signal, the chip was "selected" so that it would supply output data in response to an address input;

This method of chip selection was disadvantageous in that it required a separate terminal on the IC where, as stated, the number of available terminals was limited due to size configurations. Also, the IC consumed power whether it was selected or not. While such power consumption was not excessive, any power consumption, especially for unused circuitry, is wasteful and is especially undesirable in portable devices which are operated from an energy cell where the energy supply capability is relatively limited.

Accordingly, several obj ects of the invention are to expand the addressing capability of a computer, to expand the peripheral equipment handling capability of a computer, to provide a computer which can employ more- economical, less-complicated, and much more efficient memory- banks, to provide a computer which is extremely versatile in handling and addressing many areas of memory on peripheral equipment, and to provide such a computer with simpler, more economical, and more efficient ROM chips. Further obj ects and advantages will become apparent from a consideration of the ensuing description thereof.

DRAWINGS

Fig. 1 is a memory map for a computer system in accordance with the invention .

Fig. 2 i s a block diagram of a computer system with an expanded addressing capability according to the invention .

Fig. 3 is a diagram of a ROH chip in accordance with the invention.

Fig. 4 is a diagram of RAH bank selection circuitry in accordance with the invention.

FIG. 1— MEMORY MAP

Fig. 1 is a map of the memory banks and addressable peripherals of a computer in accordance with the invention. As indicated at the bottom of the figure, the computer can generate addresses in a spectrum from 0 to 65535 (decimal or radix 10 designation). Many users designate memory addresses in hexadecimal form (radix 16), in which case the first and last addresses would be 0000 and FFFF. However addresses will be designated herein in a decimal radix.

The memory spectrum shown in Fig. 1 is divided in five address ranges designated from Address Range I to Address Range V, as follows :

Address Range I includes the 8192 addresses from 0 to 8191 and is used for system RAM (Read And write Memory—often referred to as random access memory) , i.e., the temporary storage of variable data and programs which are worked with and manipulated by the computer. Each address comprises a location which can store one byte (eight bits) of binary data. The RAM usually is provided in the form of several integrated circuit chips which are indicated by the rectangular box. The box is heavily outlined to indicate that the system RAM is located within the housing of the computer.

Address Range II includes the 8 192 addresses from 8192 to 16383. Range II contains Control ROM, i.e. Read Only Memory or firmware which is programmed to control the communication between various items of peripheral equipment (e.g., keyboards , video display terminals , modems, printers, etc.) and the computer. The Control ROM is an expanded memory, i.e. instead of one block or bank of memory, up to 256 individual ROM banks, numbered from 0 to 255 as indicated, are provided. Any one of these banks may be made active, such that addresses generated by the computer within Range II will be effective at the active or enabled bank only and all other banks will be inactive and not addressable by the computer. Each of the 256 banks contains its own 8192 locations, so that Range II can have up to 2,097, 152 locations. Although the computer can select any of 256 banks as indicated, only several banks were actually implemented in one presently commercialized portable or hand-held computer, with provision being made so that additional banks could be connected as and if the need arose. The Control ROM banks were also provided in the form of integrated circuits, and these were physically outside the computer housing (indicated by their all being drawn in relatively light rectangles) and within peripheral devices, connected to the computer's busses. Address Range III covers the 16384 addresses from 16384 to 32767. Two types of addressable hardware are provided in Range III: ( 1 ) Program and Data ROM for storing fixed data and programs for various applications or tasks which may be performed by the computer, and (2 ) I/O Ports for communication with peripherals and system control hardware. Typical peripherals are a printer, a video display adapter, and a modem ; typical system control hardware items are a built-in keyboard, liquid crystal display, a low battery sensor, an internal timer, a beeper, etc. The Program and Data ROM is provided in the form of up to 256 banks numbered from 0 to 255 as indicated, and the peripherals and system control hardware are provided as a separate addressable bank, as will be described later. The first three Program a nd Data ROM banks, as indicated by "their heavy outlining (Banks 0 , 1 , and 2 ) , are provided within the main computer housing and are actually provided in the form of "capsules" or integrated circuits which can be plugged into three respective receptacle recesses in the bottom of the computer. These capsules hold fixed data or programs, such as a word-processing program, an appointment calendar program , a salesman's data log and computation program, etc. As with the banks in Range II, any of the Program and Data ROM banks physically internal or external to the computer housing in Range III can be selected to be responsive to addresses generated by the computer. Thus Range III can have up to 257 x 16,384 = 4, 194,560 locations.

Address Range IV covers the 16384 addresses from 32768 to 49151 and comprises banks of RAM which are numbered from 0 to 255, as indicated. These RAM banks hold variable information for use by the system , such as commercially-sold programs which can be loaded into one or more banks, variable data files which can be stored and manipulated by the computer, such as prose in a word-processing application, accounting figures, etc. The number of locations in, or bytes storable by, each RAM Bank is 16, 384, but files longer than this figure can be stored in several adjacent banks. As with Ranges II and III, any bank in Address Range IV can be selected to be responsive to addresses generated within this range by the computer. The RAM Banks are external to the computer housing, as indicated by the absence of heavy outlining.

Lastly, the highest range of addresses, Range V, from address 49152 to address 65535 ( 1 6384 addresses) , is provided for System ROM, i.e. programmed memory or firmware which controls the internal operation of the computer. As indicated by the heavy outline, the System ROM is located within the computer housing and only one bank is provided, so that no bank selection or switching is possible in Range V .

Through the use of plural address ranges, each having plural banks of memory or peripheral equipment which can be selected, the addressing capability of the computer is multiplied many times beyond its nominal range of 65536 addresses and its versatility is greatly enhanced. For example, the computer can use several banks in several different address areas in any combination to perform tasks , such as working with a. peripheral controlled by a ROM in Range II using an application program in Range III and working with data in a RAM in Range IV. Also, the computer can work with many peripherals having the I/O ports in Range III , each controlled by a different ROM in Range II .

FIG 2 — DESCRIPTION OF COMPUTER SYSTEM WITH EXPANDED ADDRESSING CAPABILITY

A computer system in accordance with the invention is shown in block diagram form in Fig. 2. All standard or conventional components are shown without detail, while Circuitry relative to the invention is shown in more detail and details of certain areas of particular interest are expanded in Figs . 3 and 4.

At the heart of the system is a one-chip Microprocessor 1 0 , type designation MCS6502, and manufactured by Synertek, Mostek, or Rockwell. Details of the 6502 microprocessor are given in various publications, such as the Synertek Hardware Manual, published by Synertek, 3050 Coronado Drive , Santa Clara, CA 9505 1. Briefly, the 6502 is a forty-pin device which contains an internal oscillator and clock drivers , a sixteen-bit address bus an eight bit bidirectional data bus , two interrupts , a read/ write (R/W) line , a two-phase clock (outputs on lines Phi 1 and Phi 2 ) , other control terminals , and bias voltage terminals. Clock line Phi 2 is the logical inversion of clock line Phi 1.

As indicated by the five output lines shown, only the read/write, address , data, and clock output terminals of microprocessor 1 0 will be discussed. The address output bus contains sixteen conductors or lines, as indicated, and the data bus conta ins eight lines, but each of these busses is shown as a single heavy line for facilitation of illustration. During the first half of the memory cycle , when clock line Phi 1 is high or active, the address and read/write signals are supplied, and when clock line Phi 2 is high , data transfer takes place .

The System RAM (Address Range I of Fig. 1) is shown at 12 and receives read/write, address , and data inputs , and supplies a data output, as indicated by the two arrows on the data line. Also, RAM 12 receives three further address sub-range select signals A and B, as indicated; these leads come from the outputs of Decoders II and III elsewhere in the diagram and are not joined to their inputs of RAM 1 2 for purposes of facilitation of illustration.

The Control Banks in Address Range II of Fig. 1 are shown at 14 in Fig. 2 and, as indicated in both figures, consist of 254 banks designated 0 to 255. The Control Banks have bank selection Latches 16. Banks 14 contain ROM (for peripheral control software) and some banks also contain RAM (for peripheral . buff ers and variable data). Banks 14 receive address and read/ write inputs and supply data output. Also, Banks 14 receive a control bank select input from Decoder II elsewhere in Fig 2. When one of Banks 14 is preselected as discussed below, it can be read from and written to by Microprocessor 10 when the control bank select input from Decoder II goes active and an address and a read signal are supplied thereto.

Address Range III, conta'ins program and data ROM banks which are implemented in two areas of Fig. 2. Application Capsules 0 to 2, which can be plugged into recesses in the computer housing, are shown at 17 and the rest of the ROM banks (3 to 255) are shown at 18. Each ROM bank or Capsule 0 to 2 receives an address input, supplies a data output, and is enabled by a separate ROM capsule select input from a Decoder VT in Fig. 2. The rest of the ROM banks , 3 to 155 , are provided in a housing separate from the computer and have their own bank select Latches 20 which are connected to the address, data, and read/write lines, and are also connected to an external ROM bank select line from Decoder VT .

Also, in Range III, the I/O ports are provided. The computer has a plug (not shown) onto which either a single item of Peripheral Equipment 30 ( such as a printer) , or a bus expander (not shown) can be connected whereafter up to five items of Peripheral Equipment 34 (such as printer, a RAM, a serial communications interface (industry designation RS232) a TV- driver adapter, or a modem) can be plugged into five slots on the bus expander. When Single Peripheral 30 is connected to the computer, its I/O ports are addressed in an address range from 16384 to 18431. The peripheral is also connected to the address, data, and read/ write lines, in addition to a single peripheral select line from Decoder IV. When the bus expander is connected to. the computer, it and its Peripherals 34 are addressed in an address range from 18432 to 20479 and inputs are supplied by a multi-peripheral select line from Decoder IV and the usual address, data, and read/ write lines. Peripheral 30 is enabled by selecting one of its memory banks through Latch 32. Communication with multiple Peripherals 34 is done via the multi-peripheral I/O adapter or bus expander (not shown) , which contains a multi-peripheral Decoder 36. (The system control hardware, also addressed in Range III, is not indicated.)

In Address Range IV, the RAM Banks are Shown at 22 and are similar to ROM Banks 18 in operation in that they have their own bank select Latches 24 which are connected to the address, data, and read/write lines, and an external RAM bank select line from Decoder I .

In Address Range V, the System ROM is shown at 27. ROM 26 is provided within the computer housing, receives address inputs , provides a data output, and also receives two further address sub— range select inputs D and E which come from a- Decoder II elsewhere in the diagram.

In addition to Microprocessor 10, Memories 12, 14, 16, 18, 22, and 27, and Peripherals 30 and 34, the system of the invention also contains address range decoders, and memory bank select latches ; these comprise the rest of the components in Fig. 2 as follows :

An AND Gate 26 receives eight address inputs (A 0 to A7) from the address bus and also receives an enabling (EN) input from output 3 of Decoder IV- AND gate 26 supplies an output when all of its inputs are ONES and its enabling input terminal is active. Its input from address line A0 is inverted, as indicated by the small circle between the AND gate and the A0 address line. Its output line (designated X ) goes to the strobe (ST) input terminal of a Latch 28. The three least-significant Data Lines, D2, D1 and DO, of the data bus from Microprocessor 10 go to a three-bit latch 28 which receives logic values (ONES OR ZEROES) at its three data input terminals, D2, D1, DO, and supplies and holds these logic values at its three corresponding data output terminals, LD2, I_D 1, and LD0, when latched by an input to its strobe terminal from the output line (X) of AND Gate 26. For example, if the data word 101 should be supplied to input terminals D2, D1, and DO respectively, of Latch 28 while its strobe terminal receives an active input, output terminals LD2, LD 1 and LD0 will supply and hold the same data word, 10 1 , even after inputs D2, D2, and DO change. To change the outputs of Latch 28, a new strobe input and a new set of data inputs must be supplied thereto .

Many of the inputs and outputs of the logic components in the diagram of Fig. 2 are inverted, but the inverters and the individual inversion functions will not be detailed since the locations and functions of all inverters will be readily apparent from the circle symbols provided.

The system also contains six Decoders, designated from I to VT. Each Decoder has two logic input terminals , B and A, and four logic output terminals , 0, 1 , 2, and 3. Decoders I, II, V, and VI have one enabling input terminals , while Decoders III and IV each have two enabling input terminals. When a Decoder is enabled by applying an active signal to its enabling input terminal( s) , one of its four output terminals will be active , depending on the state of its two input terminals, in accordance with the Decoder Truth Table shown in Fig. 2. For example,, if input terminals B and A of Decoder III are both logical ONES, and both enabling input terminals receive active inputs, output terminal 3 will be active, as indicated in the bottom row of the Truth Table.

The connections between the Decoders and the address lines will not all be detailed since they are readily apparent. Note that Address Lines A1 1 to A15 are connected to Decoders I to IV; the three outputs of Latch 28 are supplied to Decoders V and VI, the read/write signal is supplied to. the A input terminal of Decoder V, clock signals Phi 1 and Phi 2 are supplied to the enabling input terminals of Decoders I, II, and IV, the output terminals of certain Decoders axe supplied to the enabling input terminals of other Decoders and to the input terminals of two OR Gates I and II, output terminal 3 of Decoder TV is supplied to the enabling input terminal of AND Gate 26, output terminals 1 and 2 of Decoder IV go to the I/O port (Latches 32 and 36) and the other Decoder output terminals are supplied to the selection latches of the addressable memories.

OR Gates I and II have two and three input terminals, respectively. The output terminal of OR -Sate I is supplied to the enabling input terminal of Decoder II and the output terminal of OR Gate II is supplied to enabling input terminal 2 of Decoder- IV. Each OR Gate supplies an output if either one or more of its inputs axe active.

FIG. 2 — OPERATION

The system of Fig. 2 operates to implement the memory bank selection scheme shown and discussed in Fig. 1 as follows :

Microprocessor 10 operates conventionally with respect to System RAM 12 and System ROM 27. An address supplied on the address bus during Phi 1 (i.e., the first half of the memory cycle (when clock line Phi 1 is active) , will enable data to be read into or out of the corresponding address location during Phi 2 (the second half of the memory cycle, when clock line Phi 2 is active). The read/ write line is made high to read and low to write. Data information can be written into and read from RAM 12, but only read from ROM 27 (it already contains fixed data). To read the data at any location in ROM 27, the address of such location is supplied on the address bus and the computer supplies a high (read) signal on the read/write line.

For example, to read the byte (eight bits) of data stored in location 62387 of ROM 27, the address bus of Microprocessor 10 would be supplied with the binary code on the sixteen lines thereof for decimal number 62387, i.e., binary 1 1 1 1001 1 101 1001 1. Since address lines A 15 and A 13 would be high (logic ONES) , input terminals A and B of Decoder II will be active, whereupon output terminal 3 of Decoder II will be active, thereby enabling the D input terminal of RDM 27. This will, as indicated at output terminal 3 of Decoder II, enable address locations 57344 and 65535 of ROM 27. Address 62387, which is within this range, will be selected by lower order address lines which are supplied directly to ROM 27, in conventional fashion. ROM 27 is addressed during the first half of the memory cycle, when clock line Phi 1 is active. Thereafter, in the second half of the cycle, when clock line Phi 2 is active, the data in location 62387 (eight bits) will be supplied by ROM 27 on the data bus to Microprocessor 10 where it will be used in conventional fashion.

Initial bank selection in accordance with the invention is implemented in an operation requiring two separate memory cycles as follows: During the first or selection cycle, the desired bank is selected and latched, and during a later or address cycle, an address is supplied on the address lines to cause the data to be read from or into the address location of the selected bank. For example, assume that, in accordance with the program, a particular address, say location 17425 of capsule 0 in ROM 16, must be read so that the data therein can be used by Microprocessor 10. The reading of the data in this location requires two steps or cycles as follows:

In the selection cycle, output 0 of Decoder VI is made and held active to select capsule 0. At a later time, when the address cycle occurs, address 17425 is supplied on the address bus in conventional fashion. This address will be effective only at selected ROM capsule 0 , whereupon the data in such location of capsule 0 will be read out on the data bus. Once capsule 0 is selected, it will continue to respond to addresses in Range III until it is "deselected".

More particularly, to access ROM capsule 0 , the following outputs are supplied by Microprocessor 1 0 under program control, in the selection cycle:

Address lines A14, A12, A11 and A7 to A1 supply ONES and all the rest of the address lines supply ZEROES, so as to provide the address ( 22782 ) (58FE in hexadecimal) of the latch.

The Read/Write line is held low to supply a WRITE signal.

These inputs will cause AND Gate 26 to receive an active signal enabling its inp*ut terminal and ONES at all of its logic input terminals, whereupon its output (X) will be active, thereby to strobe latch 28.

During the second half (Phi 2) of the selection cycle, address lines A14, A12, A1 1 and A7 to A1 continue to supply ONES and the read/write continues to remain in the WRITE state. Data lines D2, D1, and DO will now. supply the binary word 100 to select capsule 0 , and the Phi 2 line is of course active. This will cause output terminal 0 of Decoder VT to supply an active signal to capsule 0 of ROM 16. Thus , ROM capsule 0 will be selected.

During the address cycle, the desired address 17425 is supplied by the microprocessor ( again under program control) and the read/write line supplies a READ signal. The address will be effective at ROM Capsule 0 , whereupon the data in this location of Capsule 0 will be supplied on the data bus.

ROM capsules 1 or 2 can each be selected in similar fashion by writing 101 or 110 , respectively, to Latch 28 during the selection cycle .

In order to address the I/O port to select the peripherals and system control hardware in Address Range III (Fig. 1 ) , a similar process is employed. For example, assume that a single peripheral unit, say a printer, is plugged into the computer and the address of one of its ports is 18428. If it is desired to write to this port, no bank selection need be employed since it is not possible to write to a ROM so that any writing automatically must go to I/O ports. Thus, the program should generate the address 18428 and supply the necessary data on the data bus, whereupon the data will automatically proceed to this port.

Specifically, address 18428 is generated by supplying ONES on address lines A14 and A10 to A2 and also supplying a WRITE signal (i.e., a ZERO) on the read/ write line. Address line A14 will supply a ONE to input terminal A of Decoder I, whereupon output terminal 1 thereof will be active, enabling Decoder V. The read/write line will also supply a ZERO or WRITE input to the A input terminal of Decoder V, and this will cause the output terminal of OR Gate II to go active, enabling input terminal 2 of Decoder IV, regardless of whether input B of Decoder V is high or low. Enabling input terminal 1 of Decoder IV will be made active when the Phi 1 line is low. When output terminal 0 of Decoder IV is active, it supplies a "single peripheral select" signal to memory bank select Latch 32. The "single peripheral signal" will also become active for any other address from 1 6384 to 1843 1. Any addres s location within this range is selected, by the power-ordered address inputs A10 to A0 inclusive. None of the capsules in ROMs 17 or 1 8 will be sel ected nor will respond to these addresses , since none of the banks of ROMs 17 or 1 8 are enabled by any output of Decoder VI.

To read any data stored at this address ( 18428 ) in Peripheral 30, it is merely necessary to supply a read signal on the read/ write line along with this address on the address lines while supplying ZEROES (from Latch 28) on lines LD2, LD 1, LDO. The read/ write line will supply a ONE to input terminal A of Decoder V, whereupon output terminal 1 of Decoder V will be active , so that OR Gate I I will activate enabl ing input terminal 2 of Decoder IV. Again, output terminal 0 of Decoder IV will go active in the same manner as before and Peripheral 30 will be selected in similar fashion and the data will be read from the selected location therein.

Even though ROMs 16 and .18 are mapped in the same area as the I/O ports of Peripheral 3 0 , their data will not be read since they were not selected by any output of Decoder VT .

To sel ect any set of μp to ei ght physically-associated banks of external ROM 14, ROM 18, or RAM 22, a respective decoder for each such set of eight banks is provided in every peripheral. The data line numbered the same as the bank to be selected is made high, as will be described in connection with Fig. 4, infra. The selection of higher- numbered banks in these external memories is also described infra in connection with Fig. 4.

FIG. 3— ROM CHIP WITH POWER-ON SELECT

As stated, ROM capsule 0 of Fig. 2 is preferably formed in monolithic integrated circuit form and is selected in the manner indicated in Fig. 3.The integrated circuit or chip constituting ROM capsule 0 is shown at 40. Chip 40 has fourteen address inputs , A 0 to A 1 3 , eight data outputs, DO to D7, and two bias source connections, ground and Vcc, as indicated. ROM 40 has 16k locations (k= 1 024 ) and hence can store 16k ei ght-bit bytes. It thus has 16k x 8 = 128k binary cells which can store 128 bits. Any of the 16k bytes in ROM 40 will be read out on its data lines if the binary address of the byte' s location is supplied and if ROM 40 is selected by supplying an appropriate voltage, usually 5 volts, at its Vcc terminal with respect to its ground terminal.

The Vcc terminal of ROM 0 is energized by the latch and decoder system of Fig. 2, which causes the "ROM capsule 0 select" line at the 0 output of Decoder VI to go active in the manner af oredescribed. This causes a single-pole double-throw Electronic Switch 44 — preferably a combination PNP and NPN transistor circuit which normally connects the Vcc terminal of ROM 40 to ground as indicated--to connect the Vcc terminal to a positive Vcc Source 46, thereby simultaneously to energize and select the ROM chip.

Since the ROM chip is hot connected to any bias source when it is not selected, - it does not consume standby power, thereby making the computer more energy efficient and highly suitable for portable, battery-po wered operations. Since a separate chip select terminal is not required, one more address line may be used. Therefore, a 16k byte ROM can be provided in a twenty-four (rather than twenty-eight) pin package. This allows compatability yith other ROMs ( 1k, 2k, 4k and 8k bytes) packages for use in the computer' s sockets .

All of the ROM banks in the system of Fig. 2 are preferably enabled in this fashion: {RAMs cannot be enabled by a power-on select circuit since RAMs are volatile, i.e. if they are not constantly energized, the information stored therein will be lost.)

Fig. 4 — RAM BANK SELECTION

The system of Fig. 4 shows a multi-bit latch which is one of bank select Latches 24 which can select any one of a set of up to eight RAM banks housed in one RAM peripheral. As stated, Latches 16, of control ROM 14 and Latches 20 of ROM 18 are similar to Latches 24.

The circuit of Fig. 4 receives the external RAM bank select signal from output 2 of Decoder I. This signal is supplied in parallel to the upper input terminal of each of a plurality of AND gates 0 , 1, etc., one for each RAM bank. The other, lower input terminals to the AND gates come from a multi-bit latch consisting of a plurality of correspondingly numbered data flip-flops ; the inverted output of each flip-flop is connected to the lower input terminal of its correspondingly-numbered AND gate. Thus the lower input terminal of AND Gate 0 is connected to the output terminal of Flip-flop 0, the lower input of AND Gate 1 is connected to the output terminal of Flip-flop 1, etc.

The output terminal of each AND gate is connected to a chip enable terminal of a corresponding RAM bank. Thus, the output of AND Gate 0 is connected to the chip enable input of RAM Bank 0, the output of AND Gate 1 is connected to the chip enable input of RAM Bank 1, etc Also, each RAM bank receives a read/ write signal, and is also connected to the chip enable input of RAM Bank 1, etc. Also, each RAM bank received a read/write signal, and is also connected to the data bus a nd the address bus, as indicated. (Each RAM bank may comprise a plurality of separate RAM chips, each of which is mapped in its own address range and which is selected in well-know fashion . )

Each data flip-flop of the multi-bit latch has a D (data) input which is connected to the correspondingly-numbered one of the data lines. Thus the input of. Flip-flop 0 is connected to DO (line 0 of the data bus), etc.

The strobe (ST) or clock input terminal or each flip-flop is supplied with a decoder output signal, Y-bar, similar to the X signal at the output of AND Gate 26 of Fig. 2. This signal is generated by the local address decoder when Microprocessor 10 is writing to this latch, which is regarded as an- output port .

Assume for example that it is desired to supply data to or read data from a particular address in RAM Bank 1. Only input D 1 to the latch circuit of Fig. 4 is made high in the select cycle in order to select RAM Bank 1 ; all the rest of the data lines will be held low. The Y-bar signal will reset all of the flip-flops of Fig. 4 except for Flip-flop 1. The high input on the D1 line will set Flip-flop 1 so that its output (Q-bar) will supply an active (low) input to the lower terminal of AND Gate 1, thus selecting this RAM bank.

In the address cycle, which can either be a read or a write, the address bus supplies the address of any location in RAM Bank 1, causing the external RAM bank select to the top input terminal of the AND gate to go active (low). Appropriate data can then be stored into or read from such location of RAM Bank 1 in conventional fashion.

Using this method, any of the eight banks in one peripheral can be selected and accessed.

Any of the other banks of any of Memories 14, 18, or 22 can also be selected in similar fashion, except that, again, a separate decoder, similar to that of Fig. 2, but with a different address, would be provided to enable each subsequent set of eight banks with their own enabling signal. Thus , a "Z" signal would be provided for the ninth to sixteenth banks, etc.

While the above description contains many specificities, these should not be considered as limitations upon the scope of the invention since many other embodiments and ramifications are possible. For example, the memory map of Fig. 1 can be rearranged in various ways, different logic components can be used in Fig. 2 in lieu of those shown, different components can be supplied within the computer housing and outside thereof than those indicated, different arrangements of the peripheral equipment can be used, etc. Accordingly, the scope of the invention should be determined only by the appended claims and their legal equivalents.

Claims (10)

1. A computer with an expanded addressing capability comprising:

(a) a processor capable of generating and supplying addresses, a clock signal, and a read/write signal, and also capable of supplying, receiving, and processing data, said processor having an address bus with a plurality of address lines capable of supplying addresses throughout an address spectrum,

(b) a plurality of distinct address ranges within said spectrum, each range covering a continuous series of sequential addresses different from the addresses of any other range, a plurality of addressable banks of hardware for each of said ranges, the banks of each range having at least some common addresses within said range, and

(c) means for preselecting any bank of any address range such that if any address within said range is subsequently supplied on said address bus, it will be effective only at the preselected bank of such range.

2. The computer of claim 1 wherein one of said address ranges contain a plurality of banks of read-only memory, each of said banks having sequential addresses within said range, each bank being implemented in the form of at least one monolithic integrated circuit, said integrated circuit having a plurality of address terminals, a plurality of data terminals, and at least one bias supply terminal, said means for preselecting any bank being arranged to cause said bias supply terminal of the integrated circuit of said bank to be connected to a bias supply source terminal when said bank is selected.

3. The computer of claim 2 wherein said monolithic integrated circuit has two bias supply terminals , one designed to be connected to a reference potential and the other being said bias supply terminal and designed to be connected to a biasing potential, said means for preselecting any bank being arranged to cause said supply terminal to be connected to a point at said reference potential whenever said bank is not selected.

4. The computer of claim 1 wherein one of said address ranges contains at least one bank of read-only m emory, said memory having sequential addresses within said range, and an addressable bank comprising a hardware item other than a read-only memory having at least one address within said range identical to one of said sequential addresses of said read-only memory, said means for preselecting any bank of said address range being capable of preselecting said bank of read-only memory when a predetermined data code and address is supplied thereto from said processor.

5. The computer of claim 1 wherein said plurality of addressable banks of hardware comprises a plurality of banks of read-only memory within one of said address ranges , and a plurality of banks of read and write memory within another of said address ranges.

6. The computer of claim 5 wherein said one of said address ranges , in addition to having a plurality of banks of read-only memory, has a bank of addressable hardware other than memory.

7. The computer of claim 1 wherein said plurality of addressable banks of hardware comprises a plurality of banks of read only memory within one of said address ranges, said banks storing respective programs for controlling respective items of peripheral equipment operatively associated with said computer, ano.tner plurality of banks of read only memory within another of said address ranges , said banks storing respective programs and/or data for respective applications which can be perform ed by said computer, and a plurality of banks of read and write memory within yet another of said ranges, said banks storing information selected from the class consisting of data and application programs which can be manipulated and performed by said computer .

8. The computer of claim 7 wherein said other of said address ranges, in addition to having a plurality of banks of read-only memory for storing programs, also has a bank of addressable hardware comprising at least one item of peripheral equipment which is controlled by one of said banks of read-only memory within said one address range.

9. For use in a computer, a read only memory comprising a monolithic integrated circuit having a plurality of address input terminals , a plurality of data output terminals,, and at least one bias supply terminal, said integrated circuit having no other electronically-functional terminal except address input, data output, and bias supply terminals.

10. The read only memory of claim 9 further including means for selecting said read only memory, said means comprising means for connecting said bias supply terminal to a terminal of a bias supply source for energizing said memory.