AU679831B2 - Contrast enhancement for a flat panel display device - Google Patents
Contrast enhancement for a flat panel display device Download PDFInfo
- Publication number
- AU679831B2 AU679831B2 AU14768/95A AU1476895A AU679831B2 AU 679831 B2 AU679831 B2 AU 679831B2 AU 14768/95 A AU14768/95 A AU 14768/95A AU 1476895 A AU1476895 A AU 1476895A AU 679831 B2 AU679831 B2 AU 679831B2
- Authority
- AU
- Australia
- Prior art keywords
- display device
- pixel
- layer
- substrate
- contrast enhancement
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Landscapes
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Description
Contrast Enhancement for a Flat Panel Display Device The present invention relates to the display of images on colour display devices such as computer displays or televisions, used to display computer or other video images and in particular, relates to methods for improvement in the contrast for such displays.
The background art of the present invention will now be described with reference to the accompanying drawings in which: Fig. 1 illustrates the basic operation of a liquid crystal display; Fig. 2 is a plan vL w, shown partly in section, of a liquid crystal device; Fig. 3 is a cross sectional view taken along the line A-A in Fig. 2; Referring now to Fig. 1, there is illustrated the basic operation of a ferroelectric liquid crystal device 2 which comprise a pair of electrode plates (normally consisting of glass substrates coated with transparent form of electrodes) 3 and 4 and a layer of ferroelectric liquid crystal having molecular layers 5 disposed between, and perpendicular to, the electrode plates. The ferroelectric liquid crystal assumes a chiral smectic C phase or an H phase and is disposed in a thickness 0.5 5 microns) thin enough to release the helical structure inherent to the chiral smectic phase.
When an electric field E (or 6 exceeding a certain threshold is applied between the upper and lower substrates 3, 4, liquid crystal molecules 5 become oriented :0 oin accordance with the electric field. A liquid crystal molecule has an elongate shape and 00.
20 shows a refractive anisotropy between its long axis and the short axis. Therefore if the ferroelectric liquid crystal device 2 is sandwiched between a pair of crossed polarisers (not shown), there will be provided a liquid crystal light modulation device.
When an electric field 6 exceeding a certain threshold, is applied the liquid crystal molecules 5 are oriented to a first polarisation orientation state 7. Further, when a reverse electric field is applied, the liquid crystal molecules 5 are oriented to a second polarisation orientation state 8. These orientation states are further retained as long as the electric field E or which is applied, does not exceed a certain threshold in the reverse direction.
•00• When displaying an image on a display, it is desirable to maximise the brightness with which the image is displayed. In flat panel displays, this luminosity is often achieved by means of a back light and hence it is desirable to maximise that •So• •portion of the light able to transfer through the display from the backlighting. However, Sto ensure a high contrast ratio, it is often necessary to ensure that 100% of the light is controlled as it passes through the panel device. In liquid crystal type devices, this can be ensured by either using areas that are opaque to the transfer of light or, as will be further described hereinafter, are controlled by portions of the display that allow the light to pass depending on the state of certain control signals.
Referring now to Fig. 2 and Fig. 3, there is illustrated, in more detail, the fB principles of construction of a liquid crystal display 10. Fig. 2 illustrates a plan view of 288446 CFP0281AU MACRO 05 O:\CISRA\MACRO\COMPLETE\MACROO51AUSPECI:IAD r l~dI the display 10 with part of the interior illustrated and Fig. 3 illustrates a cross-sectional view of a single pixel of the display 10 through the line A-A of Fig. 1. The display structure 10 takes the form of a pair of substrates made up of a bottom substrate 11 and a top substrate 12 made of glass plates, which are held apart with a predetermined gap by distrNbuted spacers 13, located between the substrates. The substrates 11, 12 are kept together by distributed drops of adhesive 14, again placed between the substrates, to form an overall cell structure. Where it is desired to form a full colour display, various colour filters 28, 29, 30 can be formed on the bottom of the top substrate 12 in a known manner.
The next structure to be created on the bottom surface of the top substrate 12 is an electrode structure which is formed to create a drive layer, for applying data voltages for setting up electric fields within the display. The drive layer comprises a large number of transparent electrodes 15, 69, 70 comprising In 2 0 2 SnO 2 or ITO (Indium-Tin Oxide) connected to corresponding metal drive lines 16, 71, 33, 32, 24, 72 in a predetermined pattern, with the metal drive lines encircling each portion of transparent electrode. The metal drive lines are provided to lower the resistance of the electrodes so as to minimise the voltage drop from one part of an electrode to another part.
On the other substrate 11 is formed another electrode group comprising the common layer which includes a plurality of common metal strips 17, to which are 20 connected a plurality of transparent common electrodes 19. The transparent common oo••• Selectrodes 19 are shaped to underlie and to extend substantially perpendicular to corresponding transparent drive layer electrodes 15. An electric driving means (not "shown) is normally provided to setup an electric field between each corresponding drive layer transparent electrode 15 and its underlying common transparent electrode 19.
Between the two glass substrates 11,12 is placed a liquid crystal material (not shown) having a bistable polarisation state with respect to an electric field. An example of the liquid crystal is a chiral smectic liquid crystal, and more particularly a chiral smectic C-phase (SmC*) or H-phase(SmI*).
A light source 27 behind the display device is used in conjunction with polarising sheets 21, 22 so that when the liquid crystal is in a first polarisation state, light is blocked from passing through the display 10 and when the liquid crystal is in a second polarisation state, light is able to traverse the display device through the transparent electrodes e.g. 15, 19.
When constructing a display device of the type discussed, certain minimum design rules must be used. For example, due to inaccuracies of alignments and processes of construction of the various layers, certain minimum separations between adjacent metal drive lines 32, 24 must be kept. Additionally, a certain degree of inaccuracy in alignment of the common electrodes on the bottom substrate and corresponding IN\LIBEIMACRODS:rhk L I -1 1- -L M electrodes on the top substrate, in addition to relative movements of the top substrate 12 and bottom substrate 11 can occur.
Relative movement of the top substrate with respect to the bottom substrate is a significant problem if it results in an alteration of the illumination area of each pixel as alteratidis in illumination area will cause consequential alterations in displayed images.
The separation and alignment problems can be dealt with simply by using certain overall predetermined minimum design rules or manufacturing tolerances.
For the purposes of explanation, it will be assumed that the design rules used are such that the minimum thickness of any metal lines is to be 10am. The minimum distance that any two electrically isolated areas must be separated without a risk of them shorting out is also assumed to be 10m. Similarly, the minimum alignment or movement tolerance of the two overlying substrates is in the order of 5Aim. The actual design rules that must be adhered to in practice will vary according to the type of equipment and manufacturing processes used.
The need to properly align the two substrates is important, particularly as the size of each individual pixel is reduced. As mentioned above, fluctuations in the alignment of a display can result in alterations in display pixel sizes which result in an inability to accurately reproduce images.
The display of Fig. 3 has been designed to take into account the effects of 20 minisalignment or movement 35 in either the row or column direction of the top substrate ooole 12 with respect to the bottom substrate 11. As noted previously, each transparent electrode 15 which defines a pixel on the data level or top substrate 12 is surrounded by a metallic border 32. These metallic borders are designed to overhang a corresponding metallic portion of the lower substrate common metal wires 31. The width of the overhang 34 is such that is able to accommodate the relevant design rules, being in this case 5[m on each side of the common metal layer 31. Additionally, the width of the common metal layer 31 must be such as to allow a 51m movement with respect to the data layer 36. Hence, a 5izm overlay 36 is also required.
oooee Hence the total portion of each pixel devoted to opaque, light blocking metal lines 37 is in the order of 30[tm. If each pixel is of the order of 6011m wide, this represents a substantial reduction in'the effective aperture area and, hence the brightness of eaclh pixel. A display designed according to the above principles does, however, tolerate a movement of one substrate relative to another of up to 5[m in either the row or column direction without a corresponding change in pixel size.
The reduction in the transparent area of a pixel element results in a corresponding reduction in the luminance of a particular display, and in turn, can result in the need to substantially increase the amount of backlighting required. This is particularly disadvantageous when incorporating a display into portable systems such as portable computers or televisions having their own battery power supply.
I b ~L I II In accordance with one aspect of the preferred embodiment, there is provided a display device comprising a bottom substrate, and a top substrate having a plurality of contiguous planar pixel electrode structures defined thereon, said pixel electrode structures each including a substantially opaque electrode portion, a substantially transparent electrode portion and a substantially transparent insulated portion, and said top substrate further comprising a plurality of substantially opaque blocking portions arranged to block a substantial amount of light passing through said substantially transparent insulated portion except at predetermined locations defining pixel apertures on said substrate.
A preferred embodiment of the present invention will now be described with reference to the accompanying drawings in which: Fig. 4 is a cross-sectional view of a portion of a display const cted in accordance with the preferred embodiment; Fig. 5 is a plan view of the data metal layer and data transparent layer of a portion of a display constructed in accordance with the preferred embodiment; Fig. 6 is a plan view of the contrast enhancement layer of a portion of a display constructed in accordance with the preferred embodiment; •Fig. 7 is a plan view of the common metal layer of a portion of a display Soconstructed in accordance with the preferred embodiment; Fig. 8 illustrates a view of the common level transparent electrode layer of a portion of a display constructed in accordance with the preferred embodiment; •V89: Referring now to Fig. 4, the aper.ture ratio or illuminosity of the display 43 is increased through the use of a contrast enhancement layer 46, 47, 74 which allows for an increase in the possible transparent electrode area and hence the panel brightness, while still allowing alignment movement of the bottom substrate 45 and top substrate 44.
This layer 46, 47, 74 provides an opaque mask in the shape of the subpixels which are to 0 be illuminated and is formed as an integral part of the top substrate 44 and hence is not subject to the alignment problems associated with previous designs of movement of the top substrate with respect to the bottom substrate. This contrast enhancement layer 46, 47, 74 is used in place of those portions of the previously used common metal layer e.g.
31 (Fig. 3) and can be deposited after the deposit of the required colour filters 48.
000 Referring now to Figs. 5-8 there is shown various portions of layers of a display incorporating a contrast enhancement layer.
Fig. 5 shows the data level drive lines 49 and the data level transparent layer 50. In this particular embodiment, designed for colour reproduction, the display consists of a large number of pixels, with a pixel being defined by broken line 62. Each pixel is created by the intersection of the data and common level layers. Each pixel 62 includes data electrode areas to define red 63, green 64 and blue 65 electrode areas. Each 1288446 CFP0281AU MACRO 05 electrode area is able to display four levels of luminosity. For example, using the red area transparent electrodes 50, 51 and 52, it is possible to create four red levels of illuminosity for each pixel, being zero level where each transparent electrode is in a nonilluminating state, a first illumination state where only the transparent electrode 51 is set to an illinination state, a second illumination state where transparent electrodes 50 and 52 (which are both connected to the same drive line 66) are illuminated, and a third illumination state whereby all the transparent electrodes 50, 51 and 52 are illuminated.
Of course, if more levels are required for each colour, further transparent electrode areas and drive lines can be provided.
Fig. 6 shows a portion of the contrast enhancement layer 53 of the top substrate 44 (Fig. 4) corresponding to the portion of the data level layer as shown in Fig. 5. This layer includes opaque portions which have a number of apertures e.g. 54 defined therein.
These apertures are used to let through light, the polarisation of which will be under control of the corresponding data level transparent electrodes e.g. 50 (Fig. By using a contrast enhancement layer 53, and removing the need to encircle each transparent electrode of the common level layer, and the data level layer, with metal drive lines which have a substantial overlap, the spacing, as determined by the above mentioned design rules, between transparent portions of subpixels, can be reduced 2 to 20 To ensure that the contrast enhancement layer 53 is sufficiently planar to permit operation of the display, the contrast enhancement 53 layer is preferably very thin (1[tm or less). Due to these constraints the material used is likely to have a high electron mobility and, as such, the contrast enhancement layer 53 can be appreciably conductive.
S°A suitable material, for use as the contrast enhancement layer 53, is molybdenum, as it is easy to apply, has good adhesion to glass, and is easily patterned to high resolution.
Referring again to Fig. 4, the conductivity of the contrast enhancement layer 53 requires that it be insulated from the underlying data drive lines 49 or the underlying transparent data electrodes 50. One method of insulating a conductive contrast enhancement layer 53 from the data level 49, 50 is to deposit a layer of planarised CVD SiO 2 55 after the deposit of the contrast enhancement layer 46, 47, 74.
Unfortunately, imperfections may occur in practice with the deposition of the SiO 2 layer 55 such that possible shorts 56 can occur between the contrast enhancement layer and the data level layer 49, 50. If a multiplicity of these shorts occur, then the display can be rendered unusable. Referring now to Fig. 6, in order to reduce the effects of shorts between the two layers, the contrast enhancement layer is preferably electrically isolated 57 on a pixel by pixel basis by not depositing any of the contrast enhancement layer 53 in a border region around each pixel. As a result of this electrical isolation, all single pixel shorts between data level layer and contrast enhancement layer will have no. effect on the operation of the display, with a column of pixels being Moft~ -6rendered non-operational only when two shorts occur between the contrast enhancement layer 53 and two electrically isolated data level layer electrodes 49 in the same pixel.
"erring now to Fig. 7 and Fig. 8 there is shown those portions forming the common .yer of the bottom substrate. These include the common metal layer 59 (Fig.
7) and thq common level transparent layer 60 (Fig. It can be seen from a comparison of Fig. 7 and Fig. 8 with Fig. 1 that the area of the transparent portions of the common layer has been substantially increased, and the opaque portions 67 of the common layer have been substantially reduced, thereby further increasing the amount of light that can pass through the display. Further one portion of the common layer 67 (Fig. 7) and one of the metal drive lines 49 (Fig. 5) has been designed to overlap the transparent portion 57 (Fig. 6) of the contrast enhancement layer so as to ensure all light is controlled in passing through the display.
In order to incorporate the contrast enhancement layer 53 and planarised SiO 2 layer 55 into the display, a number of extra manufacturing steps are required. These steps are taken before the data transparent layer 50 and data metal layer 49 are added and preferably, after the colour filter layer 58 has been added. The process of creation of the contrast enhancement layer includes, firstly, the deposit of a O. 5gm layer of 9* molybdenum and the etching of the molybdenum using the mask for the contrast iV900. enhancement layer 53 in Fig. 6. This is followed by the deposit of 2/tm of SiO 2 20 followed by a planarisation of the SiO 2 One form of creation of the contrast enhancement layer 53 will now be described. This process assumes that the new layers utilised in creating the contrast enhancement layer are added directly after the deposition of colour filters, but before the filter layer has been made planar. Preferably, the contrast enhancement layer 53 is created from molybdenum. However, other materials, such as aluminium, known to "those skilled in the art of fabrication of semiconductor devices, can be used.
As is customary in the creation of semiconductor devices the following major steps are used in the creation of a metal layer of molybdenum. Firstly a 60 nm thick layer of titanium is sputter deposited on the substrate 44 (Fig. This is followed by the sputtering deposit of a 0,5 btm layer of molybdenum. The contrast enhancement layer 53 can then be created by the spin-coating of a resist, which can be prebaked, exposed and developed using a mask pattern determined by the required layout as shown in Fig, 6.
The resist, molybdenum and titanium are then etched according to the mask pattern, down to the colour filter layer using a mixture of SF 6 and 02 gases. Finally the resist can be stripped and the molybdenum annealed.
An insulating dielectric layer of SiO 2 55 is subsequently added to insulate the molybdenum contrast enhancement layer 53 from the data electrode layer. The insulating layer can also be used to make planar the surface of the substrate 44. The insulating INA\LIBEIMACROOS:rhk ~s~r I r P 9 11 I layer can be created by the chemical vapour deposition (CVD) of 2/mn of SiO 2 on the surface of the substrate 44.
Subsequently, the data level metal layer of Fig. 5 can be created by the deposit of a 0.5 /m layer of molybdenum. This can be followed by the deposit of the data level transparent layer through the deposit of a 0.7 /m layer of ITO.
The construction of the bottom substrate proceeds in accordance with the prior art devices with the alteration of the common level masks in accordance with Fig. 7 and Fig. 8.
The foregoing describes only one embodiment of the present invention.
Modifications, obvious to those skilled in the art, can be made thereto without departing from the scope of the invention.
SS o oe
Claims (12)
1. A display device comprising: a bottom substrate, and a top substrate having a plurality of contiguous planar pixel electrode structures defined thereon, said pixel electrode structures each including a substantially opaque electrode portion, a substantially transparent electrode portion and a substantially transparent insulated portion, and said top substrate further comprising a plurality of substantially opaque blocking portions arranged to block a substantial amount of light passing through said substantially transparent insulated portion except at predetermined locations defining pixel apertures on said substrate.
2. A display device as claimed in claim 1 whereupon small misalignment between said bottom substrate and said top substrate does not substantially alter the amount of light passing through said pixel apertures of said top substrate from said bottom substrate.
3. A display device as claimed in claim 1 or 2 wherein each of said o° substantially opaque blocking portions is electrically isolated from an adjacent 2 substantially opaque blocking portion at predetermined intervals.
4. A display device as claimed in claim 3 wherein said substantially opaque blocking portions are isolated on a pixel electrode by pixel electrode basis. 6
5. A display device as claimed in any of claims 1 to 4 wherein said top substrate further includes a transparent electrically insulating layer between said pixel electrodes and said opaque blocking portions.
6 A display device as claimed in any of claims 1 to 6 wherein said opaque blocking portion comprises a metal.
7. A display device as claimed in claim 7 wherein said metal is selected from the group consisting of aluminium and molybdenum. •00
8. A display device as claimed in any of claims 1 to 7 wherein said display device further comprises a colour filter layer adapted to filter light passing through said transparent electrode portion.
9. A display device as claimed in claim 8 wherein said opaque blocking S, portions are intermediate of said colour filter layer and said pixel electrode structures.
A display device as claimed in any of claims 1 to 9 wherein said bottom substrate includes a plurality of common electrodes comprising a plurality of metallic strips with each metal strip connected to corresponding transparent electrode strip laid out parallel to said metallic strip.
11. A display device as claimed in claim 10 wherein said pixel electrodes .3 are laid out on a subsL.,tially parallel column by column basis and said common 288446 CFP02FIAU MACRO 05 2:\CSRA\MACRO\COMPLETE\MACR0O51AUSPECI:IAD -9- electrodes are laid out on a substantially row by row bases, said rows and columns being substantially mutually perpendicular to said pixel electrode columns.
12. A display device substantially as hereinbefore described with reference to Figs. 4 to 8. DATED this SIXTH day of MARCH 1995 (<qbu&'dV 66 Ko~q C-Apon In-formation Syctms Rseaic Ast i y iLtd Patent Attorneys for the Applicant TR SPRUSON FERGUSON ~A113 s ee 6 *00 S sees ~J Abstract Contrast Enhancement for a Flat Panel Display Device In order to accurately reproduce images on a display, it is desirable to maintain each pixel at a fixed size. In a flat panel display type of device made up of a number of substrates, account must be taken of movement of one substrate relative to another. The present invention discloses the utilisation of a contrast enhancement layer to allow substantial movement of one substrate (44) with respect to another (45) while still maintaining an operational flat panel display device having correctly sized pixels. Additionally, ele rical isolation (57) of the contrast enhancement layer, on a pixel by pixel basis, is also disclosed. S o I ~C=l
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU14768/95A AU679831B2 (en) | 1994-03-11 | 1995-03-10 | Contrast enhancement for a flat panel display device |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AUPM4412A AUPM441294A0 (en) | 1994-03-11 | 1994-03-11 | Contrast enhancement for a flat panel display device |
AUPM4412 | 1994-03-11 | ||
AU14768/95A AU679831B2 (en) | 1994-03-11 | 1995-03-10 | Contrast enhancement for a flat panel display device |
Publications (2)
Publication Number | Publication Date |
---|---|
AU1476895A AU1476895A (en) | 1995-10-05 |
AU679831B2 true AU679831B2 (en) | 1997-07-10 |
Family
ID=25615573
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU14768/95A Ceased AU679831B2 (en) | 1994-03-11 | 1995-03-10 | Contrast enhancement for a flat panel display device |
Country Status (1)
Country | Link |
---|---|
AU (1) | AU679831B2 (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2217088A (en) * | 1988-04-05 | 1989-10-18 | English Electric Valve Co Ltd | Optical display panel |
EP0361981A2 (en) * | 1988-09-30 | 1990-04-04 | Sharp Kabushiki Kaisha | Liquid crystal display device for display with grey levels |
US5124695A (en) * | 1986-09-20 | 1992-06-23 | Thorn Emi Plc | Display device |
-
1995
- 1995-03-10 AU AU14768/95A patent/AU679831B2/en not_active Ceased
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5124695A (en) * | 1986-09-20 | 1992-06-23 | Thorn Emi Plc | Display device |
GB2217088A (en) * | 1988-04-05 | 1989-10-18 | English Electric Valve Co Ltd | Optical display panel |
EP0361981A2 (en) * | 1988-09-30 | 1990-04-04 | Sharp Kabushiki Kaisha | Liquid crystal display device for display with grey levels |
Also Published As
Publication number | Publication date |
---|---|
AU1476895A (en) | 1995-10-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100271037B1 (en) | Structure and fabrication method of lcd | |
CN105159001B (en) | Array substrate and its manufacturing method, display panel and display device | |
CN103163703B (en) | Liquid crystal display and manufacture method thereof | |
CN100397224C (en) | Liquid crystal display device and fabricating method thereof | |
CN102540604B (en) | Array substrate for FFS mode liquid crystal display device and method for fabricating same | |
CN100593752C (en) | Liquid crystal display panel, pixel structure and method of manufacture | |
CN100451782C (en) | Liquid crystal display, thin film diode panel, and manufacturing method of the same | |
CN100362414C (en) | Plane switching mode liquid crystal display device and fabrication method thereof | |
JPH0467127A (en) | Liquid crystal display panel | |
JP2003195330A (en) | Liquid crystal display device | |
JPS6265017A (en) | Thin film fet driven type liquid crystal display unit havingredundant conductor structure | |
CN102200665A (en) | High light transmittance in-plane switching liquid crystal display device and method for manufacturing the same | |
KR100254870B1 (en) | Color filter structure and its manufacturing method of lcd device | |
CN101387806A (en) | LCD panel and method for manufacturing same | |
CN114185211B (en) | Array substrate and liquid crystal display panel | |
CN101868757A (en) | Active matrix substrate, liquid-crystal display device having the substrate, and manufacturing method for the active matrix substrate | |
WO2020088279A1 (en) | Display substrate and display device | |
CN103576358B (en) | The liquid crystal panel of low colour cast and display | |
US5734448A (en) | LCD having a capacitor with two lower capacitor electrodes and a reflective pixel electrode serving as an upper electrode | |
TW200305759A (en) | IPS-LCD device with a color filter formed on an array substrate | |
CN110196521A (en) | Array substrate and preparation method thereof, display device | |
US5432625A (en) | Display screen having opaque conductive optical mask and TFT of semiconductive, insulating, and conductive layers on first transparent conductive film | |
CN105655349A (en) | Array substrate, manufacturing method of array substrate, display panel and display device | |
US5227899A (en) | Liquid crystal display device with low resistance film separated from one of two adjacent electrodes by an insulating film | |
KR100482167B1 (en) | LCD and its manufacturing method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MK14 | Patent ceased section 143(a) (annual fees not paid) or expired |