AU616653B2 - Method and apparatus for determining available memory size - Google Patents

Description

COMMONWEALTH OF AUSTRALIA PATENT ACT 1952 COMPLETE SPECIFICATION 616653

(ORIGINAL)

FOR OFFICE USE CLASS INT. CLASS Application Number: Lodged: Complete Specification Lodged: Accepted: Priority: Related Art-: NAME OF APPL ADDRESS OF AJ

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NAME(S) OF II Published:

ICANT:

PPLICANT:

NVENTOR(S)

APPLE COMPUTER, INC.

20525 Mariani Avenue, Cupertino, California 95014 United States of America Michael J. DHUEY ADDRESS FOR SERVICE: DAVIES COLLISON, Patent Attorneys 1 Little Collins Street, Melbourne, 3000.

COMPLETE SPECIFICATION FOR THE INVENTION ENTITLED:- "METHOD AND APPARATUS FOR DETERMINING AVAILABLE MEMORY SIZE" The following statement is a full description of this invention, including the best method of performing it known to us -1-

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1. Field of the Invention- The present invention relates to apparatus and methods for determining the size of available memory in a computer system. More particularly, the present invention 0 relates to a method for automatically determining memory size in a computer system in which a user may selectively remove and add memory devices.

2. Prior Art: In the computing industry, it is quite common for a central processing unit (CPU) S"I to be coupled to memory devices, such as for example, dynamic random access memory (DRAM). The DRAM memory (like ail semi-conductor memory devices) identifies specific storage locations of data with a unique address. The more memory which is available to the CPU, the higher the addresses available to access data within the memory devices. In many computer systems, such as personal computers (PCs), a *20 user may increase the amount of available memory by adding discrete memory devices, such as,256K bit, 1 M bit, etc. memory chips.

In those computer systems which permit a user to increase the amount of Savailable memory, it is necessary to identify the total available memory address space In order to permit the CPU to access all of the data locations in the now expanded memory.

Historically, the memory size of the system was identified to the CPU through the use of jumper wires on the main printed circuit board, or dual in-line package (DIP) switches located adjacent to the memory on the printed circuit board. If a user incorrectly sets the available memory size in the computer system higher than it actually is, the CPU will overwrite data stored at these non-existant higher addresses into the highest real

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address which exists in the memory system. This feature is commonly referred to as memory "wrap around". Accordingly, errors may result, data loss, and overall system efficiency sacrificed through improper setting of the DIP switches or jumper wires on the printed circuit board, since the CPU will operate under conditions of improper memory address space allocation.

As will be described more fully below, the present invention provides a method and apparatus which permits the CPU to determine the true memory size available to it without the necessity of the user flipping switches, jumpers, or other hardware to set the available memory size in the system.

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SUMMARY OF THE INVENTION In accordance with the present invention there is provided a method for use in a computer system having a central processing unit (CPU) coupled to at least one memory bank having a plurality of possible contiguous addresses (#Mo-M for storing data, said memory bank configured to receive a plurality of memory devices, each of said devices having a plurality of possible storage locations, said plurality of storage locations being identified by one of said possible contiguous addresses, said method, for determining the range of real memory addresses which exist in said memory bank, comprising the steps of: said CPU sequentially storing the addresses of each of said plurality of possible storage locations at said respective addresses, from the highest possible address to the lowest possible address, such that when said CPU stores the value of an address which does not physically exist in said memory bank, said CPU stores said address at the highcst real address of said memory bank; said CPU seque-ltially reading the address of each of said plurality of possible storage locations from the lowest possible address to the highest possible address, and comparing the data stored at each of said possible addresses with the respective address, such that said address is considered to be real if said address and said stored data are equivalent, said highest real address being the highest address in which said stored value is equivalent to said address value; whereby the highest real address available in said memory bank is determined by said CPU, The present invention also provides a method for use in a computer system 25 having a central processing unit (CPU) coupled to a memory bank A having a plurality of possible contiguous addresses (#MO-MN) and a memory bank B having a plurality of possible contiguous addresses (#MN+l-MMA) for storing data, said memory banks configured to receive a plurality of memory devices, each of said devices having a plurality of storage locations said plurality of storage locations being identified by one of said possible contiguous addresses, said CPU accessing data by providing a multi-bit address of a desired storage location, said method, for determining the range of real memory addresses which exist in said memory 91080,dbwspe.033,applc2.spe,3 *t o 3a banks and accessing said desired storage location, comprising the steps of: dividing said memory banks into N binary increments separated by a predetermined number of contiguous possible addresses; said CPU sequentially storing the addresses of each of said N increments at said respective increment addresses, from the highest possible increment address to the lowest possible increment address, such that when said CPU stores the value of an address which does not physically exist in a memory bank, said CPU stores said address at the highest real increment address of said respective memory bank; said CPU, for each of said memory banks, sequentially reading the address of each of said possible increment addresses from the lowest possible increment address to the highest possible increment address, and comparing the data stored in each of said possible increment addresses with the respective address, such that said increment address is considered to be read if said address and said stored data are equivalent, said highest real increment address being the highest increment address for each of said memory banks in which said stored value is equivalent to said address value; said CPU providing a bit value corresponding to the total memory size in Bank A to control logic coupled between said CPU and said memory banks; said control logic enabling one of said memory banks based on the logical state of a predefined one address bit of said multi-bit address provided by said CPU, said ii" predefined one address bit identified by said bit value; said control logic providing control signals to said storage location identified by said multi-bit address provided by said CPU, thereby accessing said •.it desired storage location in said enabled memory bank.

i The present invention further provides an apparatus for use in a computer it •system having a central processing unit (CPU) coupled to a memory bank A having a plurality of possible contiguous addresses (Mo-MN) and a memory bank B having a plurality of possible contiguous addresses (MN+l-MAX) for storing data, said memory banks configured to receive of a plurality of memory devices, each of *said devices having a plurality of possible storage locations said plurality of possible storage locations being identified by one of said possible contiguous 910808,dbwspe.033,appe2.sp,4 3b addresses, said CPU accessing data by providing a multi-bit address of a desired storage location, said apparatus, for determining the range of real memory addresses which exist in said memory banks, and accessing said desired storage location, comprising: means coupled to said CPU for dividing said memory banks into N binary increments separated by a predetermined number of contiguous possible addresses, said means sequentially storing the addresses of each of said N increments at said respective addresses, from the highest possible address to the lowest possible address, such that when said CPU stores the value of an address which does not physically exist in a memory bank, said CPU stores said address at the highest real address of said respective memory bank; reading means coupled to said CPU for reading the address of each of said possible storage locations for each of said memory banks, from the lowest possible address to the highest possible address, and comparing the data stored in each of said possible addresses with the respective address, such that said address is considered to be real if said address and said stored data are equivalent, said highest real address for each of said memory banks being the highest address in which said stored value is equivalent to said address value; storage means coupled to control logic means coupled between said CPU 20 and said memory banks, said storage means for receiving and storing a bit value corresponding to the total memory size in memory Bank A, said control logic means enabling one of said memory banks based on the logical state of a predefined one of said address bits provided by said CPU, said predefined address bit identified by said bit value; 25 said control logic means providing control signals to said memory bank in which storage location is disposed, thereby accessing said desired storage location in said enabled memory bank.

a a S: -BRIEF DESCRIPTION OF THE DRAWINGS S. A preferred embodiment of the present invention is hereinafter described, by way of example only, with reference to the accompanying drawings, wherein: 910808,dbwspe.033,appIc2spc,5 1~ i r tf t f 1 171' FIGURE 1 illustrates a block diagram of a computer system incorporating the teachings of the present invention.

FIGURE 2 illustrates, in conceptual form, the operation of the present invention to determine available memory size in a computer system.

FIGURE 3 symbolically illustrates the overall sequence of operations of the 1.0 present invention as executed by the CPU.

9 FIGURE 4 is a more detailed flow chart illustrating the sequence of operations of the present invention described herein.

J5 FIGURE 5 illustrates a more detailed block diagram of a system incorporating the teachings of the present invention.

FIGURE 6 symbolically illustrates the operation of the multiplexor shown in FIGURE FIGURE 7 illustrates the present invention's use of RAMSIZE bits to represent the size of available memory in bank A of the memory in the system of FIGURE NOTATION AND NOMENCLATUARE The detailed description which follows is presented largely in terms of algorithms and symbolic representations of operations on data bits within a computer memory.

These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art.

An algorithm is here, and generally, conceived to be a self consistent sequence o steps leading to a desired result. These steps are those requiring physical i manipulations of physical quantities. Usually, though not necessarily, these. quantities Stake the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It proves convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers or the like. It should be kept in mind, however, that all of these and similar terms are to be associated with the appropriate *physical quantities and are merely convenient labels applied to these quantities.

Further, the manipulations performed are also referred to in terms, such as adding or comparing, which are commonly associated with mental operations performed by a human operator. No such capability of a human operator is necessary, or desirable in most cases, in any of the operations described herein which form part of the present invention; the operations are machiloe operations. Useful machines for performing the operations of the present invention include general purpose digital computers or other similar devices. In all cases, the distinction between the method operations and i operating a computer and the method of computation itself should be noted. The present invention relates to method steps for operating the computer and processing electrical or other mechanical, chemical) physical signals to generate other desired physical signals.

1 J -^i The present invention also relates to apparatus for performing these operations.

This apparatus may be specially constructed for the required purposes or it may comprise a general computer as selectively activated or reconfigured by a computer program stored in the computer. The algorithms presented herein are not inherently related to any particular computer or other apparatus. In particular, various general purpose machines may be used with the teachings herein, or it may prove more convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these machines will appear from the description given below.

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6* 0 1 oo••o* 1 o*g oo* i i DETAILED DESCRIPTION OF THE INVENTION The present invention provides apparatus and methods for use in a computer system employing memory devices having discrete capacity, such as random access memory (RAM), to automatically determine the amount of available memory in the system. In the following description for purposes of explanation, specific architectures, block diagram layouts, memory devices, memory device capacities, etc. are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without i0 these specific details. In other instances, well known circuits and devices are shown in block diagram form in order not to obscure the present invention unnecessarily.

Referring now to Figure 1, one possible configuration of hardware which may utilize the teachings of the present invention is disclosed. As illustrated, a CPU 10 is S coupled to a bus 12 for communication with a variety of data processing devices, including a Read-Only-Memory (ROM) 14. As is well known, ROM 14 contains S0 *o preprogrammed operations, data, etc. which is available for execution and access by CPU 10. CPU 10 may also utilize Random-Access-Memory (RAM) situated in one or more memory banks, such as for example Bank A and Bank B of Figure 1. Each bank of see.

memory is comprised of a plurality of memory devices having a specific memory capacity. For example, Bank A may be comprised of RAM chips having 256K bit or one megabit of memory, which are currently on the market. In practice, a user inserts the memory devices into sockets on a printed circuit board comprising memory Bank A.

Similarly, Bank B is comprised of a plurality of memory devices having a particular capacity. In prior art systems, it was necessary for a user to set hardware or software switches, or physical jumper wires, in the computer system to notify the CPU of the RAN memory size which is available in the system. In the event a user replaced, for example, 256K memory devices with one megabit devices, the system would be unable to utilize this enhanced memory capacity without hardware modifications to the physical structure of the circuit. The requirement that a user set switches for modified jumpers proves inconvenient, and, if done improperly, may result in data loss, inefficiency, or possible system failure. As will be described below, the present invention permits a user to add or substract memory devices from the system without the necessity of physically i~ I I reconfiguring the hardware to notify CPU 10 of the amount of memory available.

As illustrated in Figure 1, CPU 10 is coupled through bus 12 to RAM Bank A (18) and RAM Bank B RAM Bank A is comprised of a plurality of RAM memory devices, wherein each possible storage location for the memory bank is defined by a unique address from M 0 through MN. The address locations MO through MN are contiguous and sequential. Similarly, RAM Bank B is comprised of a plurality of memory devices with possible addresses MN+1 through MMax, and therefore, it is possible in the system of the present invention for the available memory addresses to run contiguously from M 0 m through MMax. However, in the event that maximum memory is not utilized RAM Bank B 10 may be only partially filled, such that the highest address is less than MMax, but greater io.o. than MN+1. Similarly, it is conceivable that RAM Bank A may only be partially tilled and RAM Bank B completely empty. Due to the limitation that the memory addresses be •contiguous, the presently preferred embodiment would not permit a partially filled Bank A and partially filled Bank B, although the methods and apparatus of the present invention could, with modification, accomodate such a memory scheme. In addition, the I present invention, as illustrated in Figure 1, has the attribute, as do most computer systems, that any attempt to store data at a address which does not physically relate to a real storage location will result in the data being stored in the highest real physical address. This "wrap around" occurs since a system error would result through any 20 attempt to store data at a non-existant address.

06 Currently, dynamic RAM memory devices are available commercially in certain 0 fixed memory capacities. For example, devices are available in 256K or 1 Megabit capacities for most personal computer systems on the market. It is anticipated that by the year 1990, 4Megabit RAM density devices will be available, and possibly by the year 1993, 16Megabit devices will be provided in commercial quantities. As will be described more fully below, the present invention's methods and operations may be optimized by the fact that RAM densities are provided in increments of 256K, 1 Megabit, 4Megabit and 16Megabit, as opposed to odd densities. lih. addition, for purposes of the presently preferred embodiment, the present invention is designed to accept 16Megabit memory devices as the largest devices which may be utilized, under the assumption that these devices will be available in the future. However, it will be appreciated that although the presently preferred embodiment is designed to accept a maximum of 16 8 1: Mbit devices, that the present invention may be utilized using a variety of devices of various capacities.

Referring to Figure 2, the conceptual operation of the present invention will be disclosed. The variable is defined as the total number of "binary increments" comprising boundary points within each memory bank. For example, if 256K memory devices are used in the system, then the boundary points defining the beginning and end of the total possible memory available fall on 256K increments. It will be appreciated by one skilled in the art, that to determine whether or not a particular memory device is coupled to RAM Bank A or B of Figure 1, it is only necessary to test at these binary boundary increments 256K), and not each storage location within all othe memory devices. In Figure 2, for purposes of illustration, the binary boundary increments for Bank A are identified as M 0

M

1

M

3 and MN. Upon power up, CPU attempts to store, beginning at the highest possible address increment for the Bank (MN) through to the lowest address increment (MO) the address of each binary increment for storage at that location. In other words, CPU 10 attempts to sequentially store the address of the particular memory location at that memory location, and begins from the highest address to the lowest incremental address. It wil! be apparent to one skilled in the art, that although the present invention has optimized and increased the efficiency of the system through the use of testing only at the binary increments (M 0

M

1 etc.), that the methods, apparatus and operations of the present invention are equally applicable to those computer systems in which each storage location within the memory, or other predefined increments, are used in place of increments M 0 through MN as disclosed.

With reference to Figures 2 and 3, once CPU 10 has sequentially stored the addresses of the memory boundary points, the CPU then begins to sequentially read the addresses at the increment boundary points from low (MO) to high address (MN At each address read, CPU 10 compares the contents of the storage location at the address with the address it has read. If the stored contents are equivalent to the address read, it will be appreciated that this indicates that the memory address constitutes a real phy,.ical storage location within the computer system. CPU 10 continues to sequentially read and compare the contents of the stored values for each binary increment and compares each value to the respective address. In the event that the stored value of each binary increment equals the address throughout the memory bank (for example i i i- _L Bank A) this indicates that the memory is filled to its maximum capacity and that continguous available memory locations exist from address MO through address MN.

In the event that a stored value does not equal the address value at a particular binary increment, it will be appreciated that the RAM memory is less than the maximum capacity, and in fact, the highest real address is equal to the memory address at the previous binary increment. It will be recalled, that due to the memory "wrali around" feature of the present invention (a feature present in virtually all computer systems) any attempt to write data to a non-existent address results in the data being stored at the last (highest) real physical address location of the system. For example, assume that the 10 contents of M 2 (see Figure 2) are compared with the address and are found to be equivalent. If CPU 10 sequentially increments to memory address location M 3 and I determines that the contents of M 3 are equal to the contents of M 2 they are not equal to S the address of M 3 Due to memory wrap around, an attempt to read a non-existent address (such as M 3 results in the retrieval of data at the last highest real address existence (M 2 Since CPU 10 had written the address locations as data, for each address location from the highest address to the lowest, address location M 2 would contain the value of the address M 2 as opposed to the value of M 3 The reading of a non-existent address such as M 3 results in retrieval of the value stored at M 2 Since memory devices are commercially manufactured having finite known .'.nacities 256K bit, 1M bit, etc.) CPU'10 may then set the maximum contiguous real address at M 2 at the last real binary increment detected.

Once the memory capacity of Bank A is determined using the above-described method, CPU 10 follows a similar procedure with respect to determining the amount of memory'in RAM Bank B. In the c ,a of RAM Bank B, the lowest address value is MN+1, with the highest address being MMax, with a total number of binary increments for the bank.

Figure 4 illustrates, in a more detailed fashion, the sequence of operations executed by CPU 10 in determining the size of memory banks coupled to bus 12. As illustrated, upon power up of the system CPU 10 determines the size of the available memory in the first bank (Bank and sets a variable as the total number of binary increments in the first bank As previously described, althoug the present invention will function by sequentially writing and reading each possible address in a memory disposed in one of the memory banks illustrated in Figure 1, it has been found that by using discrete binary increments 256K) the method of the present invention performs faster and more efficiently. Since memory devices are not commercially marketed in odd sizes (for example 300K memory devices), it is known that a user will fill memory banks utilized by the present invention in finite, discrete and known increments.

Once the total number of binary increments is set for the bank as variable N, CPU writes the value of each address, commencing from the higher increment to the lowest increment, of MN/2A-1, CPU 10 then determines if each increment, has been addressed and stored and, if not, continues its writing operation to store the value of 10 each increment address, sequentialiy, from highest to lowest. Once the writing p operation has been completed, CPU 10 then sequentially reads the address of each increment, from the lowest increment MN+1 for Bank B) to the highest increment MMax). For each increment address read by CPU 10, the CPU determines whether or not the address value is equal to stored data at that address. As previously discussed, if an address is real and physically present in the system, the stored value at the address will equal the address value. In the event that an address increment does not physically exist in the system, the increment address will not equal the stored address, and the stored address will (as a result of "wrap around") be the value of the highest physical address actually found within the memory bank. CPU 10 thereby determines the highest memory value physically coupled to the memory bank, and then Sdetermines if more memory banks are coupled to bus 12 of the system.

•It will be appreciated by one skilled in the art, that although a memory Bank A and a memory Bank B are shown in Figure 1, that numerous additional memory banks may be coupled to bus 12 using the teachings of the present invention. As illustrated in Figure 4, the operations illustrated are repeated for subsequent memory banks until the total size of the available memory coupled to the system illustrated in Fig'ure 1 is determined.

Referring now to Figure 5, a more detailed discussion of the operation of the present invention using the methods discussed above will be described. As illustrated, a CPU 30 is coupled to a multiplexor 32 and a register 35. Multiplexor 32 is in turn coupled to a bus 36 for communication with a RAM memory situated in one or more memory banks, such as for example, memory Bank A (40) and Bank B Memory Bank A (40) and Bank B (42) correspond to memory Banks A and B in Figure 1. As previously described, these memory banks are comprised of RAM chips having discrete memory devices of specific size 256K bit or 1 Megabit). As in the case of the system illustrated in Figure 1, the computer system of Figure 5 delineates each possible storage location for the memory bank by a unique address which, in the case of Bank A, runs from Mg through MN. Similarly, RAM Bank B is comprised of a plurality of memory devices with possible address MN+1 through MMAX. For purposes of the discussion relative to Figure 5, the reader is referred to the description of Figures 1-4, above, with respect to the sequence of operations which the CPU 30 (or in the case of Figure 1, CPU 10) execute in order to determine the range of available memory addresses in memory Banks A and B.

Initially, CPU 30 executes the sequence of operations illustrated in Figure 4 and previously described with respect to Figure 1, to determine the range of available memory in the computer system. In the presently preferred embodiment, CPU 15 comprises a 32 bit processor which accesses RAM memory locations based on a 32 bit Sf address (#A0 A31). As is common, the address of a memory location is comprised of the row address and column address of the particular storage location in the RAM e.a memory which is to be accessed. Multiplexor 32 first applies the row address to the RAM which is then followed by a column address in order to complete the memory 20 access cycle (see Figure Multiplexor 32 is controlled by control logic 45, and is coupled to multiplexor 32 by line 46.

Once CPU has executed a sequence of operations illustrated in Figure 4, above, a two-bit RAMSIZE variable is set to a binary number between 0 and 4. As illustrated 1 in Figure 7, the value of the RAMSIZE bits corresponds to the-memory capacity of Bank A (possible addresses MO through MN) as determined by CPU 30 through execution of the sequence of operations illustrated in Figure 4. The CPU 30 stores.the RAMSIZE value in register 35 which, as illustrated, is coupled to control logic 45. Control logic includes a memory having a look-up table (not shown) whch maps the RAMSIZE number to a particular address bit provided in the address (A0 through A31) by CPU for accessing a RAM location. In the presently preferred embodiment, address bit number 20 (A20) corresponds to a 1 Megabyte memory in Bank A. As illustrated in Figure 7, a 1 Megabit memory size is denoted by a RAMSIZE value of 0. Similarly, a 12 RAMSIZE value of 01 refers to a four megabite RAM Bank A memory size, and corresponds to address bit A22. As illustrated in Figure 7, in address bit 24 corresponds to a 16 Megabyte memory, and address bit 26 corresponds to a 64 Megabyte memory size.

In operation, the logical state of the address bit identified by the RAMSIZE variable determines which memory bank is selected by control logic 45. For example, if the RAMSIZE variable is equal to 4, then control logic 45 checks the value of address bit A22. In the present embodiment, if the' value of A22 is a logical 0 then Bank A is selected, whereas if the value of A22 is a logical 1 then Bank B is selected by control 10 logic 45. Control logic 45 then issues appropriate row address strobe (RAS) and column address strobe (CAS) signals, as is well known, to access a particular memory location in the bank of RAM identified by the logical state of the address bit. It will be appreciated by one skilled in the art that if the RAMSIZE variable is equal to 1, then in accordance with the above discussion, control logic 45 will check the value of address

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bit A22 from CPU 30. Control logic 45 then selects the appropriate memory bank based on the logical state of add'ess bit A22.

S °Accordingly, the present invention, as described above, provides apparatus and methods for use by computer system to determine and allocate the size of the available memory currently in the system. The present invention permits a user tc insert or remove memory devices from memory banks without the need of setting switches, providing jumper wires or the like to reconfigure the memory system size. Although the present invention has been described with reference to Figures 1-7, and with emphasis on a computer system employing two banks of memory devices, it should be understood that the figures.are for illustration only and should not be taken as limitations upon the invention. It is contemplated that many changes and modifications may be made, by one of ordinary skill in the art, to the materials and arrangements of the elements in the invention without departing from the spirit and scope of the invention as disclosed above.

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Claims (8)

14- THE CLAIMS DEFINING THE INVENTION ARE AS FOLLOWS: 1. A method for use in a computer system having a central processing unit (CPU) coupled to at least one memory bank having a plurality of possible contiguous addresses (#MO-MN) for storing data, said memory bank configured to receive a plurality of memory devices, each of said devices having a plurality of possible storage locations, said plurality of storage locations being identified by one of said possible contiguous addresses, said method, for determining the range of real memory addresses which exist in said memory bank, comprising the steps of: said CPU sequentially storing the addresses of each of said plurality of possible storage locations at said respective addresses, from the highest possible address to the lowest possible address, such that when said CPU stores the value of an address which does not physically exist in said memory bank, said CPU stores said address at the highest real address of said memory bank; said CPU sequentially reading the address of each of said plurality of possible storage locations from the lowest possible address to the highest possible address, and comparing the data stored at each of said possible addresses with the respective address, such that said address is considered to be real if said address and said stored data are equivalent, said highest real address being the highest address in which said stored value is equivalent to said address value; whereby the highest real address available in said memory bank is determined by said CPU, 25 2. A method for use in a computer system having a central processing unit: (CPU) coupled to a memory bank A having a plurality of possible contiguous addresses (#Mo-MN) and a memory bank B having a plurality of possible :1 contiguous addresses (#MN -Mmt) for storing data, said memory banks configured to receive a plurality of memory devices, each of said devices having a plurality of storage locations, said plurality of storage locations being identified by of said possible contiguous addresses, said CPU accessing data by providing a multi-bit address of a desired storage location, said method, for determining the 910808,dbwspe.33,apple2.spe,14 range of real memory addresses which exist in said memory banks and accessing said desired storage location, comprising the steps of: dividing said memory banks into N binary increments separated by a predetermined number of contiguous possible addresses; said CPU sequentially storing the addresses of each of said N increments at said respective increment addresses, from the highest possible increment address to the lowest possible increment address, such that when said CPU stores the value of an address which does not physically exist in a memory bank, said CPU stores said address at the highest real increment address of said respective memory bank; said CPU, for each of said memory banks, sequentially reading the address of each of said possible increment addresses from the lowest possible increment address to the highest possible increment address, and comparing the data stored in each of said possible increment addresses with the respective address, such that said increment address is considered to be read if said address and said stored data are equivalent, said highest real increment address being the highest increment address for each of said memory banks in which said stored value is equivalent to said address value; said CPU providing a bit value corresponding to the total memory size in Bank A to control logic coupled between said CPU and said memory banks; said control logic enabling one of said memory banks based on the logical state of a predefined one address bit of said multi-bit address provided by said CPU, said predefined one address bit being identified by said bit value; said control logic providing control signals to said storage location identified by said multi-bit address provided by said CPU, thereby accessing said 25 desired storage location in said enabled memory bank. Ii i I ft 9 r SS S S 55 S S 5 S S 9108W8,dbwspeM 3,appc2.pe, 3. The method as defined by claim 2, further including a register coupled between said CPU and said control logic, such that said bit value is stored in said register prior to being provided to said control logic. 4. The method as defined by claim 3, wherein said multi-bit address includes row addrss bits and column address bits identifying said desired storage location. 5. The method as defined by claim 4, further including a multiplexor coupled between said CPU and said memory banks, said multiplexor being coupled to said control logic. 6, The method as defined by claim 5, wherein said multiplexor alternately couples said row address bits and said column address bits to said memory banks. 7. The method as defined by claim 6, wherein said control logic enables one of said memory banks by coupling a row address strobe (RAS) signal to said selected S bank. foes 1 0o9 I.0 *fee 0.0. 0000 S S.. 8. The method as defined by claim 7, wherein said multi-bit address comprises 32 bits numbered AO through A31. 9. The method as defined by claim 8, wherein said one predefined address bit is address bit number A20 if the memory size of Bank A is 1 megabyte. The method as defined by claim 8, wherein said one predefined address bit is address bit number A22 if the memory size of Bank A is 4 megabytes. 11. The method as defined by claim 8, wherein said one predefined address bit is address bit number A24 if the memory size of Bank A is 16 megabytes. 12. The method as defined by claim 8, wherein said one predefined address bit is address bit number A26 if the memory size of Bank A is 64 megabytes. S r 18 13. An apparatus for use in a computer system having a central processing unit (CPU) coupled to a memory bank A having a plurality of possible contiguous addresses (Mo-MN) and a memory bank B having a plurality of possible contiguous addresses (MNI-MMAX) for storing data, said memory banks configured to receive of a plurality of memory devices, each of said devices having a plurality of possible storage locations said plurality of possible storage locations being identified by one of said possible contiguous addresses, said CPU accessing data by providing a multi-bit address of a desired storage location, said apparatus, for determining the range of nrai memory addresses which exist in said memory banks, and accessing said dsired storage location, comprising: means coupled to said CPU for dividing said memory banks into N binary increments separated by a predetermined number of contiguous possible addresses, said means sequentially storing the addresses of each of said N increments at said respective addresses, from the highest possible address to the lowest possible address, such that when said CPU stores the value of an address which does not physically exist in a memory bank, said CPU stores said address at the highest real address of said respective memory bank; reading means coupled to said CPU for reading the address of each of said possible storage locations for each of said memory banks, from the lowest possible address to the highest possible address, and comparing the data stored in each of said possible addresses with the respective address, such that said address is considered to be real if said address and said stored data are equivalent, said highest real address for each of said memory banks being the highest address in. which said stored value is equivalent to said address value; storage means coupled to control logic means coupled between said CPU and said memory banks, said storage means for receiving and storing a bit value corresponding to the total memory size in memory Bank A, said control logic means enabling one of said memory banks based on the logical state of a predefined one of said address bits provided by said CPU, said predefined address bit identified by said bit value; said control logic means providing control signals to said memory bank in which storage location is disposed, thereby accessing said desired storage location 0* CC C.i C. *i C C C 910808,dbwspe.033,appIc2.p, 18 I S 19 in said enabled memory bank. 14. The apparatus as defined by claim 13, wherein said storage means comprises a register. The apparatus as defined by claim 14, wherein said multi-bit address includes row address bits and column address bits identifying said desired storage location.

16. The apparatus as defined by claim 15, further including a multiplexor coupled between said CPU and said memory banks, said multiplexor being coupled to said control logic.

17. The apparatus as defined by claim 16, wherein said multiplexor alternately couples said row address bits and said column address bits to said memory banks.

18. The apparatus as defined by claim 17, wherein said control logic enables one of said memory banks by coupling a row address strobe (RAS) signal to said selected bank.

19. The apparatus as defined by claim 18, wherein said multi-bit address comprises 32 bits numbered AO through A 3 1 r r c '4 FJ 0 910808,dbwspe.033,ppe2.spe 19 4- 11 The apparatus as defined by claim 18, wherein said one predefined address bit is address bit number A20 if the memory size of Bank A is 1 megabyte.

21. The apparatus as defined by claim 18, wherein said one predefined address bit is address bit number A22 if the memory size of Bank A is 4 megabytes.

22. The apparatus as defined by claim 18, wherein said one predefined address bit is address bit number A24 if the memory size of Bank A is 16 megabytes. 4 S 23. The apparatus as defined by claim 18, wherein said one predefined address bit is address bit number A26 if the memory size of Bank A is 64 megabytes.

24. A method for determining the range of real memory S addresses substantially as hereinbefore described with reference to the drawings. An apparatus for determining the range of real memory addresses substantially as hereinbefore described with reference to the drawings. 4 nti heof- DATED this 18th day of April, 1988. APPLE COMPUTER, INC. By Its Patent Attorneys DAVIES COLLISON S/ 7