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AU589982B2 - Circuitry for complementing binary numbers - Google Patents

Circuitry for complementing binary numbers

Info

Publication number
AU589982B2
AU589982B2 AU59831/86A AU5983186A AU589982B2 AU 589982 B2 AU589982 B2 AU 589982B2 AU 59831/86 A AU59831/86 A AU 59831/86A AU 5983186 A AU5983186 A AU 5983186A AU 589982 B2 AU589982 B2 AU 589982B2
Authority
AU
Australia
Prior art keywords
circuitry
stage
input
bit
exclusive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
AU59831/86A
Other versions
AU5983186A (en
Inventor
Lauren Ann Christopher
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RCA Licensing Corp
Original Assignee
RCA Licensing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RCA Licensing Corp filed Critical RCA Licensing Corp
Publication of AU5983186A publication Critical patent/AU5983186A/en
Application granted granted Critical
Publication of AU589982B2 publication Critical patent/AU589982B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3832—Less usual number representations
    • G06F2207/3836—One's complement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4816—Pass transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Logic Circuits (AREA)
  • Ultra Sonic Daignosis Equipment (AREA)
  • Electrophonic Musical Instruments (AREA)
  • Details Of Television Scanning (AREA)
  • Amplifiers (AREA)
  • Organic Low-Molecular-Weight Compounds And Preparation Thereof (AREA)
  • Developing Agents For Electrophotography (AREA)
  • Analogue/Digital Conversion (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Manipulation Of Pulses (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Radar Systems Or Details Thereof (AREA)

Abstract

Circuitry for forming the twos complement or ones complement of N-bit binary numbers is described. The circuitry includes N stages each of which contains an exclusive NOR gate (300, 310, 320, 330, 340, 350). A first input terminal (B) of the exclusive NOR gate is coupled to receive one bit of the input value and a second input terminal (C) is coupled to receive the carry output signal from the previous stage. A logic one or logic zero is applied to the second input terminal (C) of the exclusive NOR gate (300) of the stage which processes the least significant bit of the binary word if the circuitry is to provide a twos complement or ones complement value respectively. The carry output signal for each stage is generated by ANDing (302, 312, 322, 334, 342) a logically inverted version of the input bit signal with the carry input signal applied to the stage. An application of the complementing circuitry in an absolute value circuit is also described. In this application, the carry input signal to each stage is ORed (612, 622, 632, 642, 652) with a logically inverted version of the sign bit of the input value and the result is applied to the second input terminal (C) of the exclusive NOR gate. This circuitry complements only negative values, passing positive values unchanged.
AU59831/86A 1985-07-15 1986-07-08 Circuitry for complementing binary numbers Ceased AU589982B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/755,011 US4709226A (en) 1985-07-15 1985-07-15 Circuitry for complementing binary numbers
US755011 1985-07-15

Publications (2)

Publication Number Publication Date
AU5983186A AU5983186A (en) 1987-01-22
AU589982B2 true AU589982B2 (en) 1989-10-26

Family

ID=25037332

Family Applications (1)

Application Number Title Priority Date Filing Date
AU59831/86A Ceased AU589982B2 (en) 1985-07-15 1986-07-08 Circuitry for complementing binary numbers

Country Status (10)

Country Link
US (1) US4709226A (en)
EP (1) EP0209308B1 (en)
JP (1) JPH0785221B2 (en)
KR (1) KR940008612B1 (en)
AT (1) ATE68275T1 (en)
AU (1) AU589982B2 (en)
CA (1) CA1246234A (en)
DE (1) DE3681840D1 (en)
ES (1) ES2000270A6 (en)
FI (1) FI862883A (en)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6478029A (en) * 1987-09-18 1989-03-23 Mitsubishi Electric Corp Semiconductor integrated circuit
JP2558739B2 (en) * 1987-09-28 1996-11-27 株式会社東芝 Absolute value circuit
US5307474A (en) * 1987-09-30 1994-04-26 Mitsubishi Denki Kabushiki Kaisha Apparatus and method for processing literal operand computer instructions
JPH0774989B2 (en) * 1988-01-18 1995-08-09 株式会社東芝 Code conversion circuit
US5018094A (en) * 1988-08-30 1991-05-21 Siemens Aktiengesellschaft Dual incrementer
US5237513A (en) * 1989-11-20 1993-08-17 Massachusetts Institute Of Technology Optimal integrated circuit generation
US5162796A (en) * 1990-07-31 1992-11-10 Inmos Limited Digital signal inversion employing cross-over switch
US5268858A (en) * 1991-08-30 1993-12-07 Cyrix Corporation Method and apparatus for negating an operand
JPH0580982A (en) * 1991-09-19 1993-04-02 Nec Corp Absolute value circuit
US5548542A (en) * 1992-08-14 1996-08-20 Harris Corporation Half-band filter and method
KR950009682B1 (en) * 1993-04-30 1995-08-26 현대전자산업주식회사 Two's complementer using parallel aokler
US5563813A (en) * 1994-06-01 1996-10-08 Industrial Technology Research Institute Area/time-efficient motion estimation micro core
US5831886A (en) * 1996-09-24 1998-11-03 Samsung Electronics Co., Ltd. Calculating a + sign(A) in a single instruction cycle
US5835394A (en) * 1996-09-24 1998-11-10 Samsung Electronics Co., Ltd. Calculating selected sign 3 expression in a single instruction cycle
US5850347A (en) * 1996-09-24 1998-12-15 Samsung Semiconductor, Inc. Calculating 2A+ sign(A) in a single instruction cycle
US5831887A (en) * 1996-09-24 1998-11-03 Samsung Electronics Co., Ltd. Calculating 2A-sign(A) in a single instruction cycle
US5856936A (en) * 1996-09-24 1999-01-05 Samsung Semiconductor, Inc. Calculating A - sign(A) in a single instruction cycle
KR100345413B1 (en) * 1999-11-05 2002-07-26 한국타이어 주식회사 Rubber Rolling Apparatus
AU3082701A (en) * 1999-12-23 2001-07-03 Intel Corporation Method and apparatus for performing single-cycle addition or subtraction and comparison in redundant form arithmetic
US6813628B2 (en) 1999-12-23 2004-11-02 Intel Corporation Method and apparatus for performing equality comparison in redundant form arithmetic
US6826588B2 (en) 1999-12-23 2004-11-30 Intel Corporation Method and apparatus for a fast comparison in redundant form arithmetic
US20040015534A1 (en) * 2002-07-17 2004-01-22 Sun Microsystems, Inc. Method for adding one to a binary number
CN103929430A (en) * 2014-05-03 2014-07-16 郑卫兵 Mobile-terminal-based feedback method for sent multimedia information

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4520347A (en) * 1982-11-22 1985-05-28 Motorola, Inc. Code conversion circuit

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3949299A (en) * 1974-11-05 1976-04-06 North Electric Company Signal coding for telephone communication system
JPS5320833A (en) * 1976-08-11 1978-02-25 Seiko Epson Corp Absolute value arithmetic circuit
US4357675A (en) * 1980-08-04 1982-11-02 Bell Telephone Laboratories, Incorporated Ripple-carry generating circuit with carry regeneration
US4369500A (en) * 1980-10-20 1983-01-18 Motorola Inc. High speed NXM bit digital, repeated addition type multiplying circuit
DE3069310D1 (en) * 1980-11-03 1984-10-31 Itt Ind Gmbh Deutsche Binary mos ripple carry parallel adder/subtractor and appropriate adding/subtracting stage
US4422143A (en) * 1980-11-24 1983-12-20 Texas Instruments Incorporated Microprocessor ALU with absolute value function
US4417315A (en) * 1981-07-14 1983-11-22 Rockwell International Corporation Method and apparatus for incrementing a digital word
US4486851A (en) * 1982-07-01 1984-12-04 Rca Corporation Incrementing/decrementing circuit as for a FIR filter

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4520347A (en) * 1982-11-22 1985-05-28 Motorola, Inc. Code conversion circuit

Also Published As

Publication number Publication date
KR870001516A (en) 1987-03-14
ATE68275T1 (en) 1991-10-15
US4709226A (en) 1987-11-24
KR940008612B1 (en) 1994-09-24
DE3681840D1 (en) 1991-11-14
EP0209308A3 (en) 1988-07-13
EP0209308A2 (en) 1987-01-21
JPS6220028A (en) 1987-01-28
ES2000270A6 (en) 1988-02-01
EP0209308B1 (en) 1991-10-09
CA1246234A (en) 1988-12-06
AU5983186A (en) 1987-01-22
FI862883A0 (en) 1986-07-08
JPH0785221B2 (en) 1995-09-13
FI862883A (en) 1987-01-16

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