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AU5335699A - Viterbi decoder with reduced size path metric memory - Google Patents

Viterbi decoder with reduced size path metric memory

Info

Publication number
AU5335699A
AU5335699A AU53356/99A AU5335699A AU5335699A AU 5335699 A AU5335699 A AU 5335699A AU 53356/99 A AU53356/99 A AU 53356/99A AU 5335699 A AU5335699 A AU 5335699A AU 5335699 A AU5335699 A AU 5335699A
Authority
AU
Australia
Prior art keywords
reduced size
viterbi decoder
path metric
metric memory
size path
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU53356/99A
Inventor
David Hansquine
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of AU5335699A publication Critical patent/AU5335699A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0262—Arrangements for detecting the data rate of an incoming signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4107—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing add, compare, select [ACS] operations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
    • H04L1/201—Frame classification, e.g. bad, good or erased
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
    • H04L1/208—Arrangements for detecting or preventing errors in the information received using signal quality detector involving signal re-encoding

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Artificial Intelligence (AREA)
  • Quality & Reliability (AREA)
  • Power Engineering (AREA)
  • Error Detection And Correction (AREA)
AU53356/99A 1998-08-04 1999-08-04 Viterbi decoder with reduced size path metric memory Abandoned AU5335699A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12902198A 1998-08-04 1998-08-04
US09129021 1998-08-04
PCT/US1999/017658 WO2000008768A1 (en) 1998-08-04 1999-08-04 Viterbi decoder with reduced size path metric memory

Publications (1)

Publication Number Publication Date
AU5335699A true AU5335699A (en) 2000-02-28

Family

ID=22438107

Family Applications (1)

Application Number Title Priority Date Filing Date
AU53356/99A Abandoned AU5335699A (en) 1998-08-04 1999-08-04 Viterbi decoder with reduced size path metric memory

Country Status (2)

Country Link
AU (1) AU5335699A (en)
WO (1) WO2000008768A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10010238C2 (en) * 2000-03-02 2003-12-18 Infineon Technologies Ag Method for storing path metrics in a Viterbi decoder
US6757864B1 (en) 2000-04-06 2004-06-29 Qualcomm, Incorporated Method and apparatus for efficiently reading and storing state metrics in memory for high-speed ACS viterbi decoder implementations
CN100428636C (en) * 2004-09-27 2008-10-22 普天信息技术研究院 Add-compare-select device and method for computing progressive path metric value
US8943392B2 (en) * 2012-11-06 2015-01-27 Texas Instruments Incorporated Viterbi butterfly operations

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4979175A (en) * 1988-07-05 1990-12-18 Motorola, Inc. State metric memory arrangement for a viterbi decoder
US5416787A (en) * 1991-07-30 1995-05-16 Kabushiki Kaisha Toshiba Method and apparatus for encoding and decoding convolutional codes
JPH07336239A (en) * 1994-06-07 1995-12-22 Japan Radio Co Ltd Viterbi decoder
US5619514A (en) * 1994-12-29 1997-04-08 Lucent Technologies Inc. In-place present state/next state registers

Also Published As

Publication number Publication date
WO2000008768A1 (en) 2000-02-17

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase