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AU4326699A - Low-power parallel processor and imager integrated circuit - Google Patents

Low-power parallel processor and imager integrated circuit

Info

Publication number
AU4326699A
AU4326699A AU43266/99A AU4326699A AU4326699A AU 4326699 A AU4326699 A AU 4326699A AU 43266/99 A AU43266/99 A AU 43266/99A AU 4326699 A AU4326699 A AU 4326699A AU 4326699 A AU4326699 A AU 4326699A
Authority
AU
Australia
Prior art keywords
low
integrated circuit
parallel processor
power parallel
imager integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU43266/99A
Inventor
Jeff Y. F. Hsieh
Teresa H. Y. Meng
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Leland Stanford Junior University
Original Assignee
Leland Stanford Junior University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Leland Stanford Junior University filed Critical Leland Stanford Junior University
Publication of AU4326699A publication Critical patent/AU4326699A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/43—Hardware specially adapted for motion estimation or compensation
    • H04N19/433—Hardware specially adapted for motion estimation or compensation characterised by techniques for memory access
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/436—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Computing Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Image Processing (AREA)
AU43266/99A 1998-05-30 1999-05-28 Low-power parallel processor and imager integrated circuit Abandoned AU4326699A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US8738798P 1998-05-30 1998-05-30
US60087387 1998-05-30
PCT/US1999/012172 WO1999063751A1 (en) 1998-05-30 1999-05-28 Low-power parallel processor and imager integrated circuit

Publications (1)

Publication Number Publication Date
AU4326699A true AU4326699A (en) 1999-12-20

Family

ID=22204887

Family Applications (1)

Application Number Title Priority Date Filing Date
AU43266/99A Abandoned AU4326699A (en) 1998-05-30 1999-05-28 Low-power parallel processor and imager integrated circuit

Country Status (2)

Country Link
AU (1) AU4326699A (en)
WO (1) WO1999063751A1 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6757019B1 (en) * 1999-03-13 2004-06-29 The Board Of Trustees Of The Leland Stanford Junior University Low-power parallel processor and imager having peripheral control circuitry
JP2001318745A (en) * 2000-05-11 2001-11-16 Sony Corp Data processor, data processing method and recording medium
AU2007200566B2 (en) * 2003-02-17 2007-05-31 Silverbrook Research Pty Ltd Synchronisation protocol
FR2854754B1 (en) 2003-05-06 2005-12-16 METHOD AND APPARATUS FOR IMAGE ENCODING OR DECODING WITH PARALLELIZATION OF PROCESSING ON A PLURALITY OF PROCESSORS, COMPUTER PROGRAM AND CORRESPONDING SYNCHRONIZATION SIGNAL
FR2913784A1 (en) * 2007-03-14 2008-09-19 St Microelectronics Sa DATA MANAGEMENT FOR IMAGE PROCESSING
US8200992B2 (en) 2007-09-24 2012-06-12 Cognitive Electronics, Inc. Parallel processing computer systems with reduced power consumption and methods for providing the same
US8209597B2 (en) 2009-03-23 2012-06-26 Cognitive Electronics, Inc. System and method for achieving improved accuracy from efficient computer architectures
US9141131B2 (en) 2011-08-26 2015-09-22 Cognitive Electronics, Inc. Methods and systems for performing exponentiation in a parallel processing environment
US9063754B2 (en) 2013-03-15 2015-06-23 Cognitive Electronics, Inc. Profiling and optimization of program code/application
CN103237225B (en) * 2013-05-10 2016-04-20 上海国茂数字技术有限公司 YUV is utilized to combine the method revising coding and decoding video error with rgb space
US9146747B2 (en) 2013-08-08 2015-09-29 Linear Algebra Technologies Limited Apparatus, systems, and methods for providing configurable computational imaging pipeline
US11768689B2 (en) 2013-08-08 2023-09-26 Movidius Limited Apparatus, systems, and methods for low power computational imaging

Also Published As

Publication number Publication date
WO1999063751A1 (en) 1999-12-09

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase