AU2013200979B2 - Usb based synchronization and timing system - Google Patents

Abstract

A method for synchronizing the local clock of a USB device, comprising observing a USB data stream, decoding a periodic data structure from the USB 5 data stream, using a free running oscillator clock with multiple outputs, each with a respective phase, upon receipt of the decoded periodic data structure selecting the output that is most in phase with the decoded periodic data structure, and phase adjusting the free running clock based on the selected phase to compensate for the frequency of the free running clock being incorrect 10 or the free running clock being unsynchronized. 4097060_1 (GHMaters) P72070.AU.1 bus interface/1/ connector controller circuitry 88 90 - clock circuitry USB device Figure 3 110 a'-n112 Instruction 1 Instruction Instruction 114 Instruction 16Instruction Instruction 118 Instruction 126 ISR o2 120 sR 130 Instruction Instruction Figure 4

Description

USB BASED SYNCHRONIZATION AND TIMING SYSTEM RELATED APPLICATION This application is divided from and claims the benefit of the priority and filing 5 dates of Australian patent application no. 2008251024 filed 12 May 2008, which was based on and claimed the benefit of the filing date of US application no. 60/938,148 filed 15 May 2007, the content of both of which as filed is incorporated herein by reference in its entirety. 10 FIELD OF THE INVENTION The present invention relates to a method and apparatus for providing a USB based synchronization and timing system, of particular but by no means exclusive use in providing clocks, data acquisition and automation and control of test and measurement equipment, instrumentation interfaces and process 15 control equipment, synchronized to an essentially arbitrary degree in either a local environment or in a distributed scheme. BACKGROUND OF THE INVENTION The USB specification is intended to facilitate the interoperation of devices from 20 different vendors in an open architecture. USB data is encoded using differential signalling (viz. two wires transfer the information) in the form of the difference between the signal levels of those two wires. The USB specification is intended as an enhancement to the PC architecture, spanning portable, desktop and home environments. 25 The USB specification assumes that devices differ. This is true for the intended environments in which devices from a multiplicity of manufacturers are connected, but there exist other environments (such as certain common industrial or laboratory environments) that require a specification for operating 30 multiple devices of a similar nature in a synchronized manner. The specification does not sufficiently address this issue. Such environments are typically those where testing, measuring or monitoring is performed, and which require the devices to be synchronized to a more accurate degree than is specified. The USB specification allows limited inter-device synchronization by 35 providing a 1 kHz clock signal to all devices. However, many laboratory and industrial environments require synchronization at megahertz frequencies and higher. 4097060_1 (GHMaters) P72070.AU.1 -2 USB employs a tiered star topology, where hubs provide attachment points for USB devices. The USB host controller which is located on the user's personal computer (PC), laptop or personal digital assistant (PDA) contains the root hub, 5 which is the origin of all USB ports in the system. The root hub provides a number of USB ports to which USB functional devices or additional hubs may be attached. In turn, one can attach more hubs (such as USB composite devices) to any of 10 these ports, which then provide additional attachment points via ports for further USB devices. In this way, USB allows a maximum of 127 devices (including hubs) to be connected, with the restriction that any device may be at most five levels deep. 15 The root hub in the host transmits a Start of Frame (SOF) signal packet every 1 ms to every device, the time between two SOF packets being termed a frame. Each module receives this SOF packet at a different time, owing to electrical delays inherent in the USB topology, which means that there may be a significant time delay (specified as < 380 ns) between the receipt of a signal at 20 a device connected directly to the host controller and at a device that is five levels down. This is a severe restriction when it is desired to synchronize devices at megahertz levels and above. Furthermore the USB specification allows the host controller to fail to transmit up to five consecutive SOF tokens. 25 Current synchronization between a USB host and a USB device is possible by two types of USB transfers, Interrupt and Isochronous. Interrupt transfers allow guaranteed polling frequencies of devices with minimum periods of 125 ps, whereas isochronous transfers guarantee a constant transfer rate. Both methods require there to be traffic between the device and host for 30 synchronization to take place and therefore reserve more bandwidth for higher degrees of synchronization. This unfortunately means that the available USB bandwidth can be used up before the maximum number of devices has been connected. This approach also places on the host the great computational burden of keeping 127 devices synchronized to the host by means of software, 35 yet still fails to address maintaining synchrony between the devices as to the host the individual devices represent separate processes. 4097060_1 (GHMaters) P72070.AU.1 -3 Devices that contain a physical transducer of some kind, such as a laser diode or a photodetector, may require clock and trigger information. A device such as a laser diode with a modulated light output at 1 MHz may use a clock signal to perform transducer functions at regular intervals or at a constant frequency. A 5 trigger signal is usually used to start or end an operation at a set time. In the laser diode example, a trigger signal could be used to turn the modulated light output on or off. These clock and trigger signals can be used to synchronize a multiplicity of 10 devices to each other (and hence constitute what is referred to below as "synchronization information"), provided that the signals are common and simultaneous to all devices. 'Common' and 'simultaneous' here mean that the variation in time of these signals between the devices is less than a specified quantity, 6t. In the laser diode example, this would enable a multiplicity of laser 15 diodes to modulate their light output at one frequency. The modulation frequency of all devices would be the same, and their waveforms would be in phase. The current USB specification (viz. 2.0) allows for a 6t of up to 0.35 ps. For a signal with a frequency of 1 MHz and a period of 1.0 ts, this delay represents almost half of the period. It is thus unusable as synchronization 20 information for routine use. Devices such as hubs and USB controller chips commonly use some amount of phase locking in order to decode the USB protocol. It is the purpose of the SYNC pattern in the USB protocol to provide a synchronization pattern for 25 another electronic circuit to lock to. However, this is intended to synchronize the device to the USB bit streams to an accuracy sufficient to interpret MHz bit streams. It is not intended to synchronize two separate devices to each other to the level required by many test and measurement instruments. The USB specification-to the extent that it deals with inter-device synchronization-is 30 mainly concerned with synchronizing a USB-CD audio stream sufficiently for output on a USB-speaker pair. The requirements of such an arrangement are in the kHz range and, for this application, the USB specification is satisfactory. However, the specification does not address the potential problems of synchronizing, for example, 100 USB-speaker pairs. 35 As discussed above, USB communication transfers data during regular 1 ms frames (or, in the case of the High-Speed USB specification, in eight micro 4097060_1 (GHMaters) P72070.AU.1 -4 frames per 1 ms frame). A Start of Frame (SOF) packet is transmitted to all but Low-Speed devices at the beginning of each frame and to all High-Speed devices at the beginning of each micro-frame. The SOF packet therefore represents a periodic low resolution signal broadcast to all but Low-Speed 5 devices connected to a given Host Controller. This SOF packet broadcast occurs at a nominal frequency of 1 kHz (in the case of the High-Speed USB specification, 8 kHz). However the USB specification allows a very large frequency tolerance (by instrumentation standards) of some 10 500 parts per million. The background art utilises this low resolution frequency signal that is broadcast to each of the devices to provide clock synchronization, but only to the somewhat ambiguous frequency provided by the USB Host Controller. 15 US Patent No. 6,343,364 (Leydier et al.) discloses an example of frequency locking to USB traffic, which is directed toward a smart card reader. This document teaches a local, free-running clock that is compared to USB SYNC and packet ID streams; its period is updated to match this frequency, resulting in a local clock with a nominal frequency of 1.5 MHz. This provides a degree of 20 synchronization sufficient to read smart card information into a host PC but, as this approach is directed to a smart card reader, inter-device synchronization is not addressed. US Patent No. 6,012,115 and subsequent continuation US Patent No. 25 6,226,701 (Chambers et al.) address the USB SOF periodicity and numbering for timing. These documents disclose a computer system that can perform an accurate determination of the moment in time a predetermined event occurred within a real-time peripheral device by using the start of frame pulse transmitted from a USB host controller to peripheral devices connected to it. 30 However the methods taught by these documents do not involve the measurement of the frequency of a periodic data structure contained within the USB data traffic for determination of the absolute frequency of the master clock in the USB Host Controller, and in some cases rely on the provision of an 35 additional counter in the host. US Patent No. 6,092,210 (Larky et al.) discloses a method for connecting two 4097060_1 (GHMaters) P72070.AU.1 -5 USB hosts for the purpose of data transfer, by employing a USB-to-USB connecting device for synchronizing local device clocks to the data streams of both USB hosts. Phase locked loops are used to synchronize local clocks and over-sampling is used to ensure that data loss does not occur. This document, 5 however, relates to the synchronization of the data streams of two USB hosts with each other (and with limited accuracy) such that transfer of information is then possible between said Hosts. This document does not teach any method for synchronizing a plurality of USB devices to a single USB Host or to a plurality of USB hosts. 10 The USB specification was written with audio applications in mind, and US Patent No. 5,761,537 (Sturges et al.) describes how to synchronize two or more pairs of speakers with individual clocks, where one pair operates off a stereo audio circuit in the PC and the other pair is controlled by the USB. Both 15 speaker pairs use their own clocks, so they need to be synchronized so this document teaches one technique for maintaining synchronization of the audio signals despite possible clock skew between the asynchronous clocks. US Patent Application No. 10/620,769 (Foster et al.) discloses a synchronized 20 version of the USB, in which the local clock of each device is synchronized on a given USB to an arbitrary degree. This document also discloses a method and apparatus for providing a trigger signal to each device within the USB such that an event may be synchronously initiated on multiple devices by the trigger signal. 25 Figure 1 is a schematic diagram of an exemplary background art synchronized USB device 10, connected to a digital USB 12, via a USB bus connector 14. USB device 10 contains an integrated USB interface and microcontroller 16, USB device function circuitry (such as a digitally controlled transducer) 18, bus 30 sampling circuitry 20, digital 1/O bus decoding circuitry 22, synchronization phase comparator 24 and synchronised clock 26. USB device 10 is connected by bus connector 14 to digital USB 12. Digital USB 12 contains USB data and control signals for the USB device 10; bus 35 sampling circuitry 20 observes the internal USB traffic 30 and generates a replica 32 thereof. Digital 1/O bus decoding circuitry 22 decodes clock carrier signal 34 from signal 32. Synchronization phase comparator 24 compares 4097060_1 (GHMaters) P72070.AU.1 -6 decoded clock carrier 34 with divided clock signal 36 from synchronized clock 26 such that the output local clock signal 28 (at a substantially higher frequency than carrier signal 34) is locked to carrier signal 34 in frequency and phase. 5 In this arrangement, synchronization is achieved by detecting and extracting information from USB 12 as USB signal traffic enters USB device 10 and by generating local clock signal 28. This architecture for synchronization of the local clock on each of a plurality of 10 USB devices employs periodic data structures present in the USB traffic. An embodiment disclosed in US Application No. 10/620,769 essentially locks the local clock in frequency and phase to the detection of a SOF packet token at the USB device. Circuitry is employed to observe traffic through the USB and decode a clock carrier signal from bus traffic (in one embodiment, SOF 15 packets), which results in a nominal carrier signal frequency of 1 kHz (or 8 kHz for USB High Speed). The local clock signal from a controlled oscillator clock is locked to the reception of the USB SOF packet in both phase and frequency. This ensures that all devices attached to the root hub are locked in frequency to the point at which they receive the SOF packet token. However, the approach 20 described in US Application No. 10/620,769 is limited in its ability to provide a precisely known clock frequency to each device. Further, although this disclosure teaches the highly accurate clock synchronization of devices attached to a USB, the disclosed approach employs 25 a precision controlled oscillator, typically in the form of a voltage controlled voltage oscillator, and particular care must be taken to provide stable supply voltages. A closed loop control circuit is then applied to the precision oscillator. This adds both cost and complexity to the design of a synchronized USB device. 30 Another synchronized USB device, disclosed in International Patent Application No. PCT/AU2007/000155 filed 15 February 2007 (Foster et al.), is shown schematically in figure 2. The technique of this disclosure allows the generation of accurate clock frequencies on board the USB device regardless of the 35 accuracy of the clock in the Host PC. Referring to figure 2, USB device 40 includes a bus connector 44, bus interface circuitry 46, a microcontroller 48, USB device function circuitry (such as a digitally controlled transducer) 50 and 4097060_1 (GHMaters) P72070.AU.1 -7 synchronization circuitry in the form of synchronizer 52 (comparable to digital 1/O bus decoding circuitry 22, synchronization phase comparator 24 and synchronised clock 26 of figure 1). Bus interface circuitry 46 acts as a transceiver for USB data detected at bus connector 44, passing the USB data 5 to microcontroller 48. USB device 40 also includes circuitry 54 that observes the internal bus link and passes a replica 56 of USB traffic 58 to synchronizer 52. Microcontroller 48 provides information 60 to synchronizer 52 for accurate frequency synthesis of clock signal 62. Microcontroller 48 communicates with device function circuitry 50 through communication bus 64. 10 The carrier signal, once decoded from the USB traffic, is combined with a scaling factor to generate synchronization information and hence to synthesize a local clock signal with precise control of the clock frequency. In this way, the frequency of the local clock signal can be more accurate than the somewhat 15 ambiguous frequency of the carrier signal by the use of additional information signal 60 from microcontroller 48. This arrangement is said to be able to produce a local clock signal to arbitrarily high frequencies, such as a clock frequency of tens of megahertz, and thus to 20 ensure that the local clock of each device connected to a given USB is synchronized in frequency. US Application No. 10/620,769 also teaches a method and apparatus to further synchronize multiple local clocks in phase by measurement of signal propagation time from the host to each device and provision of clock phase compensation on each of the USB devices. 25 While such synchronous USB systems can perform accurate clock synchronisation between USB devices with accurate clock frequency generation, they require special hardware components to decode data present on the USB and precision determination of the moment in time of carrier signal 30 reception. These components are required in addition to the normal USB bus interface circuitry and microcontroller (46 and 48 respectively of figure 2) so these approaches are not compatible with a generic implementation of USB using off the shelf USB interface microcontrollers. 35 Additionally, the USB specification constraints the level of capacitance that the USB device can present to the bus. The effective capacitance of USB each data line to ground in the presence of the parallel effective resistance to ground 4097060_1 (GHMaters) P72070.AU.1 -8 is very tightly controlled. There is generally only a small capacitance margin with compliant USB devices. Addition of a parallel data pathway circuit (comparable to that of bus sampling circuitry 20 of figure 1) to a conventional USB device would typically exceed the capacitance limits. 5 SUMMARY OF THE INVENTION In a first broad aspect, the present invention provides a method for synchronizing the local clock of a USB device, comprising; observing a USB data stream; 10 decoding periodic signal structure packets in the USB data stream; using a free running oscillator clock with multiple outputs, each with a respective phase; upon receipt of the decoded periodic signal structure packets, 15 selecting from the phases of the outputs a phase that is most in phase with the decoded periodic signal structure packets; and phase adjusting the free running clock based on the selected phase to compensate for the frequency of the free running clock being incorrect or the free running clock being unsynchronized. 20 The method may comprise selecting from the phases of the outputs a phase that is most in phase with the decoded periodic signal structure and phase adjusting the free running clock based on the selected phase. 25 The method may comprise using a free running oscillator with multiple phase delayed outputs. The method may comprise using a free running oscillator with multi-tap delay. 30 The periodic data structure packets may comprise, for example, any of the USB packet signal structures defined in the USB specification, command sequences sent to the USB device, data sequences sent to the USB device, OUT tokens, IN tokens, ACK tokens, NAK tokens, STALL tokens, PRE tokens, SOF tokens, SETUP tokens, DATAO tokens, DATA1 tokens, or predefined bit pattern 35 sequences in the USB data packets. According to a second broad aspect, the invention provides a synchronized 4097060_1 (GHMaters) P72070.AU.1 -9 USB comprising a plurality of USB devices synchronized according to the method described above. According to a second broad aspect, the invention provides a method for 5 synchronising the free running local clock of a device with a plurality of selectable phase shifted outputs, the method comprising: (i) the device receiving a periodic reference signal; (ii) on receipt of each of the periodic reference signal, the device detecting which of the plurality of selectable phase shifted outputs is most in 10 phase with the periodic reference signal; and (ii) employing the most in phase of the phase shifted outputs as the local clock signal. The method may include periodically adjusting the local clock signal in phase 15 by repeating steps (i) to (iii). The method may include selecting the phase shifted output that is most in phase with the periodic reference signal when assessed over a plurality of clock cycles. 20 The method may further comprise: determining the cumulative phase error of the free running oscillator outputs experienced during the period between successive cycles of the periodic reference signal; and 25 periodically selecting the next most appropriate of the plurality of phase shifted outputs, within the period between successive cycles of the periodic reference signals, in order to continually minimise the absolute phase error of the local clock signal. 30 It should be noted that the various features of each of the above aspects of the invention can be combined as desired and appropriate. In addition, apparatuses according to the invention can be embodied in various ways. For example, such devices could be constructed in the form of multiple 35 components on a printed circuit or printed wiring board, on a ceramic substrate or at the semiconductor level, that is, as a single silicon (or other semiconductor material) chip. 4097060_1 (GHMaters) P72070.AU.1 -10 BRIEF DESCRIPTION OF THE DRAWING In order that the present invention may be more clearly ascertained, embodiments will now be described, by way of example, with reference to the 5 accompanying drawing, in which: Figure 1 is a schematic diagram of a background art synchronized USB device; Figure 2 is a schematic diagram of another background art synchronized USB device; 10 Figure 3 is a schematic diagram of a synchronized USB device according to a first embodiment of the present invention; Figure 4 is a schematic diagram of the command execution stack of two USB interface/microcontrollers according to the embodiment of figure 3, showing software interrupt latency and uncertainty; 15 Figure 5 is a timing diagram of the command execution stack of figure 4; Figure 6 is a schematic diagram of a synchronized USB device according to a second embodiment of the present invention; Figure 7 is a schematic diagram of the synchronizer circuitry of the 20 USB device of figure 6; and Figure 8 is a schematic timing diagram of the internal circuitry of the synchronizer circuitry of figure 7. DETAILED DESCRIPTION OF THE INVENTION 25 A USB device according to a first embodiment of the present invention is shown schematically at 80 in figure 3, with a digital USB 82. USB device 80 includes a bus connector 84, for connection to USB 82, USB interface/microcontroller 86, digital input/output circuitry 88 (in the form, for example, of a digital transducer such as an analogue to digital converter, pressure transducer or strain gauge) 30 and synchronized clock circuitry 90. Clock synchronization information in the form of a repetitive carrier signal is extracted from USB 82 by USB interface/microcontroller 86. Conventional USB microcontrollers (such as the Cypress EZUSB-FX brand series of USB 35 microcontrollers) can be configured to execute a software interrupt on reception of the Start of Frame (SOF) packet in the USB data stream, and this is so in this embodiment; the interrupt service routine that executes in response to 4097060_1 (GHMaters) P72070.AU.1 - 11 reception of the SOF packet is programmed to generate a reference timing signal 92 (at either 1 kHz for USB Full Speed or 8 kHz for USB High Speed), which is passed to synchronized clock circuitry 90. Synchronized clock circuitry 90 contains a phase locked loop architecture to lock a high frequency local 5 crystal oscillator clock in phase and frequency using low frequency reference signal 92. Synchronized output clock signal 94 is configured to synchronously control the operation of digital input/output circuitry 88 according to data and commands 96 10 provided from USB interface/microcontroller 86. This architecture allows decoding of carrier signals for use by synchronizing circuitry without using dedicated additional hardware components to observe the USB data stream in parallel to the USB interface/microcontroller 86. 15 Figure 4 is a schematic diagram of, respectively, first and second command execution stacks 110, 112 of two examples of USB interface/microcontrollers 86 according to the embodiment of figure 3. Command stacks 110, 112 execute from top to bottom; execution time 114 increases from top to bottom in this view. Microcontroller instructions are integer multiples of a single 20 instruction cycle time and are represented as blocks of time. At some point in first command stack 110, microcontroller 86 receives a physical interrupt stimulus in the form of a SOF interrupt signal 116 corresponding to an internal hardware register receiving a valid SOF packet in 25 the data stream. This occurs at some point during, in this example, instruction 118 (shown arbitrarily as a three cycle instruction in this example). After completion of instruction 118, microcontroller 86 pushes instructions onto the stack and executes an Interrupt Service Routine (ISR) 120. ISR 120 is generally a series of instructions, but is represented as one instruction here for 30 simplicity. ISR 120 responds to interrupt signal 116 at the next available time and is programmed to generate a software interrupt output signal 122 (which is comparable to reference timing signal 92 of figure 3). There is a time delay t 1 between reception of physical interrupt signal 116 and software interrupt output signal 122. 35 Time delay t 1 is variable and depends on both the length of an instruction cycle and the position within an instruction cycle that physical interrupt signal 116 is 4097060_1 (GHMaters) P72070.AU.1 -12 received. This is demonstrated by reference to second exemplary command stack 112. In this example, the microcontroller receives a physical SOF interrupt signal 126 at some point during instruction 128 (which is shown in this figure as a single cycle instruction). After completion of instruction 128, 5 microcontroller 86 executes ISR 130. ISR 130 is generally a series of instructions but has been represented as one instruction here for simplicity. ISR 130 responds to interrupt signal 126 and generates software interrupt output signal 132. There is a time delay t 2 between reception of the physical interrupt signal 126 and the outputting of software interrupt output signal 132. 10 Hence, there is uncertainty-corresponding in magnitude to these time delays t1 and delay t 2 -in determining the exact reception time of a SOF packet. This uncertainty depends on the duration of the currently executing instruction and the position within that instruction at which a physical SOF interrupt signal is 15 received by the hardware interrupt generator. This is typically given by the period of the longest instruction on a given microcontroller. The best case (i.e. minimum) uncertainty is therefore given by the single cycle instruction cycle, of length At. 20 Figure 5 is a schematic timing diagram 150 for the exemplary command execution stacks 110, 112 of figure 4. Figure 5 includes the reception 152 of a SOF packet and timing diagrams 154 and 156 corresponding to command stacks 110 and 112 of figure 4 respectively. Reception 152 of the SOF packet results in a hardware interrupt signal 158 occurring during instruction 160. At 25 the completion of instruction 160, interrupt service routine 162 generates local reference signal 164 which is used as the repetitive synchronization reference signal. Similarly hardware interrupt signal 158 occurs during instruction 166 (corresponding to instruction 128 in command stack 112 of figure 4). Interrupt service routine 168 then generates local reference signal 170. 30 Some microcontrollers have instruction cycle times that range from single instruction cycles to ten or more instruction cycles for complex operations. There is thus significant variability in the uncertainty of any given determination of SOF reception time. If the structure of the software is known, the limits can 35 be determined by the longest instruction execution time and structure of the code. Given the asynchronous nature of the SOF rate and microcontroller code execution there is a random distribution of accurate and inaccurate 4097060_1 (GHMaters) P72070.AU.1 -13 determinations of SOF reception time. However it is possible to determine the accuracy of any given determination of SOF reception time, as it is possible to determine which instruction was 5 executing during reception of the SOF and therefore the length of the instruction and of the resulting uncertainty of measurement. This allows any measurements of SOF reception time that are highly uncertain to be identified and hence discarded. Alternatively some form of statistical weighting can be applied to determinations of SOF reception time based on the length of 10 instruction that was executing during its reception, to reduce reliance on measurements that rely on lengthy instructions. The statistical weighting can determine how each measurement is used in controlling the phase locked loop synthesized clock of a synchronized USB device, and only the most reliable determinations of SOF reception time used in controlling the synchronized clock 15 circuitry 90. Furthermore the use of filtering, averaging or other statistical means can be used to improve the accuracy and stability of the synchronized clock. There is a fixed latency 172 associated with each measurement of SOF 20 reception time. This is the time taken to execute interrupt service routine 162 or 168 respectively. This is constant for each class of microcontroller (assuming identical constant clock frequency and zero batch to batch inconsistencies). In this way, the present invention provides a means of synchronizing the local 25 clock of a USB device in both frequency and phase, to a repetitive reference carrier signal contained in the USB data stream without using special hardware components that might, for example, add additional parallel capacitive loading to the bus. Additionally, the present invention provides a means of decoding data from the bus and generating a software interrupt based synchronizing 30 reference signal. Such interrupt based reference signals do not require the highly accurate temporal resolution of prior art hardware based synchronization disclosures. Furthermore the present invention provides a method for estimating the 35 uncertainty of timing accuracy of any given interrupt based synchronizing reference signal and utilizes filtering or statistical means to improve the accuracy and stability of said synchronized clock. 4097060_1 (GHMaters) P72070.AU.1 -14 A USB device according to a second embodiment of the present invention is shown schematically at 200 in figure 6, with a USB 202. USB device 200 includes a bus connector 204, with which USB device 200 is attached to USB 5 202. USB device 200 has a bus interface/microcontroller 206, USB device function circuitry (such as a digitally controlled transducer) 208, bus sampling circuitry 210 (comparable to bus sampling circuitry 20 of figure 1) and synchronization circuitry 212. 10 Bus interface circuitry 206 observes the USB data stream present at bus connector 204 and passes a replica 214 of the USB traffic 216 to synchronization circuitry 212. Synchronization circuitry 212 generates synchronous local clock signal 218 which is passed to USB device function circuitry 208, which uses it to synchronously execute commands 220 from bus 15 interface/microcontroller 206. Synchronization circuitry 212 decodes periodic clock carrier signal from USB traffic 216. Figure 7 is a schematic diagram of synchronization circuitry 212 of the USB device 200 of figure 6. Synchronization circuitry 212 has an input port 232 for 20 receiving replica 214 of the USB data traffic, a synchronous clock output port 234, a matched filter 236, a multi-tap free running oscillator clock 238 and a clock selector 240. Matched filter 236 receives a USB data stream 242 from input port 232. 25 Matched filter 236 decodes the periodic carrier signals (in the form, in this embodiment, of SOF packet tokens) from USB data stream 242 and generates clock synchronizing signal 244. Multi-tap free running oscillator 238 (which may be in the form of free running oscillator coupled to a multi-tap phase delay generator) generates a plurality of phase delayed clock signals 246. Clock 30 selector 240 uses clock synchronizing signal 244 to select output clock signal 248, being a selected one of plurality of phase delayed clock signals 246. It will be appreciated by those skilled in the art that there are many ways of utilizing an inexpensive free running oscillator to generate a plurality of phase delayed cock signals. 35 In this way synchronization circuitry 230 uses an inexpensive free running oscillator and clock selector circuitry to control the output clock signal phase in 4097060_1 (GHMaters) P72070.AU.1 -15 a digital control loop to maintain course synchronization. Such a system will generally be less stable and less accurate than a conventional analogue phase locked loop architecture (which provides precision phase and frequency control), but this method provides a relatively inexpensive alternative 5 synchronization system because it employs a series of steps (embodied as software or firmware operating in a field programmable gate array) that determines the most appropriate of a plurality of free running clocks to be used at any given time. 10 In order to more fully explain the operation of synchronization circuitry 230, figure 8 provides a schematic diagram 260 of the clock and control signals within synchronization circuitry 212 of figure 7. Decoded Start of Frame signal 262 (comparable to 244 of figure 7) provides the 15 reference signal to which a local synchronized clock must be synchronized. A perfectly synchronized ideal clock 264 is shown for reference along with two phases, first clock phase 266 and second clock phase 268 of local free running oscillator (comparable to two of the plurality of clock phases 246 of figure 7). Output clock 270 (comparable to output clock signal 248 of figure 7) is the 20 synchronized clock signal (comparable to 218 of figure 6) that is used to control the synchronized USB device. Start of Frame decoded pulse 272 constitutes the beginning and decoded pulse 274 constitutes the end of a synchronization window. The ideal clock 264 is 25 synchronized in frequency and phase such that the leading edge of clock pulse 276 is aligned with decoded pulse 272 and the leading edge of clock pulse 278 is aligned with decoded pulse 274. (The leading edge of the clock pulse may in fact be any repeatable point of the waveform, but the leading edge is chosen for simplicity in this discussion.) 30 The free running oscillator is not operated at a precisely controlled frequency and phase, but rather is allowed to vary in frequency across its entire range. First clock phase 266 represents one phase of multiphase clock 237 of figure 7 35 and is synchronised 280 with decoded pulse 272. It will be apparent from a comparison of first clock phase 266 and ideal clock 264 that the free running clock is running slower than the ideal clock frequency. This is indicated by 4097060_1 (GHMaters) P72070.AU.1 -16 phase lag 282, which first clock phase 266 exhibits with respect to ideal clock 264 after several clock cycles (exaggerated in this view for clarity). Although first clock phase 266 is synchronized with decoded pulse 272, by the time the next decoded pulse 274 is received, first clock phase 266 is out of phase as 5 shown by clock pulse 284. Second clock phase 268 is not synchronized 286 (or in phase) with decoded SOF 272 but, owing to the unsynchronized frequency of local free running oscillator clock 238 of figure 7, second clock phase 268 is in phase 288 with 10 decoded SOF 274. Clock selector 240 of figure 7 acts as a digital switch to route one of the plurality of phase delayed clock signals 246 to output port 234 of figure 7. Clock selector 240 of figure 7 switches synchronously with reception of decoded SOF 15 pulse, selecting the most appropriate one (i.e. most accurately aligned) of the plurality of phase delayed clock signals 246. In the example of figure 8, clock selector circuitry 240 of figure 7 has selected first clock phase 266 at SOF pulse 272 and first clock phase 266 continues to 20 be transmitted as output clock 270 until reception of next decoded SOF pulse 274. Second clock phase 268 is most accurately in phase (viz. clock pulse 288) of the plurality of phase delayed clock signals 246 at the moment clock selector circuitry 240 of figure 7 receives decoded SOF signal 274. Therefore second clock phase 268 continues to be transmitted as output clock 270 until 25 reception of next decoded SOF pulse. The final clock cycle 294 of output clock 270 prior to reception of decoded SOF 274 is of a different duration to the rest of the output clock cycles. Given the rate of reception of decoded SOF packets and a reasonably selected frequency tolerance for the free running oscillator clock, final clock cycle 294 is only in error by a small fraction of a clock cycle. 30 In this way, the free running oscillator clock is phase adjusted in a digital fashion every time a new decoded SOF is received. The typical frequency tolerance of free running oscillators is of the order of 50 parts per million to 100 parts per million. A 50 parts per million tolerance for a 35 typical 10 MHz data acquisition oscillator corresponds to a worst possible frequency error of 500 cycles per second. In a USB High Speed system, SOF packets are received at a rate of 8 kHz (or with a period of 125 ps). This means 4097060_1 (GHMaters) P72070.AU.1 -17 that a maximum of 500 cycles of clock error occur in each 125 ps SOF period, or 1/16 of a cycle. One sixteenth of a cycle at 10 MHz corresponds to a worst case phase error of 6.25 ns. Cumulative phase error of this magnitude in successive SOF periods is unacceptable for data acquisition applications. 5 However according to the second embodiment of the present invention digital correction of this magnitude of phase error in each SOF period provides an acceptable data acquisition clock. In this way, the simple digital phase only control loop is used with an 10 inexpensive free running oscillator clock to maintain an output clock frequency that is synchronized with repetitive incoming clock carrier signal from a USB within some acceptable bounds. Furthermore a plurality of USB devices each disposed with similar circuitry forms a synchronized USB. 15 Modifications within the scope of the invention may be readily effected by those skilled in the art. It is to be understood, therefore, that this invention is not limited to the particular embodiments described by way of example hereinabove and that combinations of the various embodiments described herein are readily apparent to those skilled in the art. 20 In the preceding description of the invention, except where the context requires otherwise owing to express language or necessary implication, the words "Host Controller" are used to refer to a standard USB Host controller, a USB-on-the go Host Controller, a wireless USB Host Controller or any other form of USB 25 Host Controller. In the preceding description of the invention, except where the context requires otherwise owing to express language or necessary implication, the word "comprise" or variations such as "comprises" or "comprising" is used in an 30 inclusive sense, that is, to specify the presence of the stated features but not to preclude the presence or addition of further features in various embodiments of the invention. Further, any reference herein to prior art is not intended to imply that such prior 35 art forms or formed a part of the common general knowledge. 4097060_1 (GHMaters) P72070.AU.1

Claims (16)

1. A method for synchronizing the local clock of a USB device, comprising; observing a USB data stream; 5 decoding a periodic data structure from the USB data stream; using a free running oscillator clock with multiple outputs, each with a respective phase; upon receipt of the decoded periodic data structure selecting the output that is most in phase with the decoded periodic data structure; and 10 phase adjusting the free running clock based on the selected phase to compensate for the frequency of the free running clock being incorrect or the free running clock being unsynchronized.

2. A method as claimed in claim 1, comprising selecting from the phases of the 15 outputs a phase that is most in phase with the decoded periodic data structure, and phase adjusting the free running clock based on the selected phase.

3. A method as claimed in either claim 1 or 2, comprising using a free running oscillator with multiple phase delayed outputs. 20

4. A method as claimed in either claim 1 or 2, comprising using a free running oscillator with multi-tap delay generator to generate the multiple phases.

5. A method as claimed in any one of the preceding claims, wherein said 25 periodic data structure packets comprise any of the USB packet signal structures defined in the USB specification, command sequences sent to said USB device, data sequences sent to the USB device, OUT tokens, IN tokens, ACK tokens, NAK tokens, STALL tokens, PRE tokens, SOF tokens, SETUP tokens, DATAO tokens, DATA1 tokens, or predefined bit pattern sequences in 30 the USB data packets.

6. A synchronized USB comprising a plurality of USB devices synchronized according to the method of any one of the preceding claims. 35

7. A method for synchronising the free running local clock of a device with a plurality of selectable phase shifted outputs, the method comprising: (i) said device receiving a periodic reference signal; 4097060_1 (GHMaters) P72070.AU.1 - 19 (ii) on receipt of each of said periodic reference signal, said device detecting which of said plurality of selectable phase shifted outputs is most in phase with said periodic reference signal; and (iii) employing said most in phase of said phase shifted outputs as said 5 local clock signal.

8. A method as claimed in claim 7, including periodically adjusting said local clock signal to be in phase by repeating steps (i) to (iii). 10

9. A method as claimed in either claim 7 or 8, including selecting the phase shifted output that is most in phase with said periodic reference signal when assessed over a plurality of clock cycles.

10. A method as claimed in any one of claims 7 to 9, further comprising: 15 determining the cumulative phase error of said free running oscillator outputs experienced during the period between successive cycles of said periodic reference signal; and periodically selecting the next most appropriate of said plurality of phase shifted outputs, within the period between successive cycles of said periodic 20 reference signals, in order to continually minimise an absolute phase error of the local clock signal.

11. A method for synchronizing the local clock of a USB device substantially as herein described with reference to figures 6 to 8 of the accompanying drawings. 25

12. A method for synchronizing the local clock of a USB device substantially as herein described with reference to figures 3 to 8 of the accompanying drawings.

13. A method for synchronising the free running local clock of a device with a 30 plurality of selectable phase shifted outputs substantially as herein described with reference to figures 6 to 8 of the accompanying drawings.

14. A method for synchronising the free running local clock of a device with a plurality of selectable phase shifted outputs substantially as herein described 35 with reference to figures 3 to 8 of the accompanying drawings.

15. A synchronized USB substantially as herein described with reference to 46789851 (GHMalers) P72070.AU.1 -20 figures 6 to 8 of the accompanying drawings.

16. A synchronized USB substantially as herein described with reference to figures 3 to 8 of the accompanying drawings. 4678905_1 (GNMaUers) P72070.AU.1