AU2004320526A1 - Method for at least partially compensating for errors in ink dot placement due to erroneous rotational displacement - Google Patents
Method for at least partially compensating for errors in ink dot placement due to erroneous rotational displacement Download PDFInfo
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- AU2004320526A1 AU2004320526A1 AU2004320526A AU2004320526A AU2004320526A1 AU 2004320526 A1 AU2004320526 A1 AU 2004320526A1 AU 2004320526 A AU2004320526 A AU 2004320526A AU 2004320526 A AU2004320526 A AU 2004320526A AU 2004320526 A1 AU2004320526 A1 AU 2004320526A1
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/21—Ink jet for multi-colour printing
- B41J2/2132—Print quality control characterised by dot disposition, e.g. for reducing white stripes or banding
- B41J2/2139—Compensation for malfunctioning nozzles creating dot place or dot size errors
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/015—Ink jet characterised by the jet generation process
- B41J2/04—Ink jet characterised by the jet generation process generating single droplets or particles on demand
- B41J2/045—Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
- B41J2/04501—Control methods or devices therefor, e.g. driver circuits, control circuits
- B41J2/04505—Control methods or devices therefor, e.g. driver circuits, control circuits aiming at correcting alignment
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/015—Ink jet characterised by the jet generation process
- B41J2/04—Ink jet characterised by the jet generation process generating single droplets or particles on demand
- B41J2/045—Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
- B41J2/04501—Control methods or devices therefor, e.g. driver circuits, control circuits
- B41J2/0451—Control methods or devices therefor, e.g. driver circuits, control circuits for detecting failure, e.g. clogging, malfunctioning actuator
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/015—Ink jet characterised by the jet generation process
- B41J2/04—Ink jet characterised by the jet generation process generating single droplets or particles on demand
- B41J2/045—Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
- B41J2/04501—Control methods or devices therefor, e.g. driver circuits, control circuits
- B41J2/04541—Specific driving circuit
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/015—Ink jet characterised by the jet generation process
- B41J2/04—Ink jet characterised by the jet generation process generating single droplets or particles on demand
- B41J2/045—Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
- B41J2/04501—Control methods or devices therefor, e.g. driver circuits, control circuits
- B41J2/04551—Control methods or devices therefor, e.g. driver circuits, control circuits using several operating modes
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/015—Ink jet characterised by the jet generation process
- B41J2/04—Ink jet characterised by the jet generation process generating single droplets or particles on demand
- B41J2/045—Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
- B41J2/04501—Control methods or devices therefor, e.g. driver circuits, control circuits
- B41J2/04563—Control methods or devices therefor, e.g. driver circuits, control circuits detecting head temperature; Ink temperature
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/015—Ink jet characterised by the jet generation process
- B41J2/04—Ink jet characterised by the jet generation process generating single droplets or particles on demand
- B41J2/045—Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
- B41J2/04501—Control methods or devices therefor, e.g. driver circuits, control circuits
- B41J2/04573—Timing; Delays
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/015—Ink jet characterised by the jet generation process
- B41J2/04—Ink jet characterised by the jet generation process generating single droplets or particles on demand
- B41J2/045—Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
- B41J2/04501—Control methods or devices therefor, e.g. driver circuits, control circuits
- B41J2/04586—Control methods or devices therefor, e.g. driver circuits, control circuits controlling heads of a type not covered by groups B41J2/04575 - B41J2/04585, or of an undefined type
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/015—Ink jet characterised by the jet generation process
- B41J2/04—Ink jet characterised by the jet generation process generating single droplets or particles on demand
- B41J2/045—Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
- B41J2/04501—Control methods or devices therefor, e.g. driver circuits, control circuits
- B41J2/04591—Width of the driving signal being adjusted
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/21—Ink jet for multi-colour printing
- B41J2/2132—Print quality control characterised by dot disposition, e.g. for reducing white stripes or banding
- B41J2/2146—Print quality control characterised by dot disposition, e.g. for reducing white stripes or banding for line print heads
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2202/00—Embodiments of or processes related to ink-jet or thermal heads
- B41J2202/01—Embodiments of or processes related to ink-jet heads
- B41J2202/20—Modules
Landscapes
- Engineering & Computer Science (AREA)
- Quality & Reliability (AREA)
- Ink Jet (AREA)
- Record Information Processing For Printing (AREA)
- Particle Formation And Scattering Control In Inkjet Printers (AREA)
- Controls And Circuits For Display Device (AREA)
- Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)
- Printers Characterized By Their Purpose (AREA)
Abstract
A printhead module includes at least one row of printhead nozzles. Each row includes at least one displaced row portion. The displacement of the row portion includes a component in a direction normal to that of a pagewidth to be printed.
Description
WO 2005/120835 PCT/AU2004/000706 1 Method for at least partially compensating for errors in ink dot placement due to erroneous rotational displacement FIELD OF THE INVENTION 5 The present invention relates to a method of compensating for errors in ink dot placement due to erroneous rotational displacement of a printhead or printhead module. The invention has primarily been developed for use in a pagewidth inkjet printer comprising a printer controller and a printhead having one or more printhead modules, and will be described with reference to this example. 10 However, it will be appreciated that the invention is not limited to any particular type of printing technology, and is not limited to use in, for example, pagewidth and inkjet printing. CROSS-REFERENCES Various methods, systems and apparatus relating to the present invention are disclosed in the following co 15 pending applications filed by the applicant or assignee of the present invention. The disclosures of all of these co pending applications are incorporated herein by cross-reference. 10/727,181 10/727,162 10/727,163 10/727,245 PEA05US 10/727,233 10/727,280 10/727,157 10/727,178 10/72,210 20 PEA11US 10/727,238 10/727,251 10/727,159 10/727,180 PEA16US PEA17US PEA18US 10/727,164 10/727,161 10/727,198 10/727,158 10/754,536 10/754,938 10/727,227 10/727,160 09/575,108 10/727,162 09/575,110 09/607,985 6,398,332 6,394,573 6,622,923 10/173,739 10/189,459 25 10/713,083 10/713,091 ZG164US 10/713,077 10/713,081 10/713,080 10/667,342 10/664,941 10/664,939 10/664,938 10/665,069 09/112,763 09/112,762 09/112,737 09/112,761 09/113,223 09/505,951 09/505,147 09/505.952 09/517,539 09/517,384 09/516,869 09/517,608 09/517,380 09/516,874 WO 2005/120835 PCT/AU2004/000706 2 09/517,541 10/636,263 10/636,283 ZE028US ZE029US ZE030US 10/407,212 10/407,207 10/683,064 10/683,041 Some applications have been listed by their docket numbers, these will be replaced when application numbers are 5 known. BACKGROUND When a printhead module is being mounted to a carrier, there is the possibility that the position of the printhead will be rotationally erroneous. Such errors arise due to the tolerances in the assembly process, for example. 10 In cases where the printhead module is short, and particularly where it is the only module in the printhead, minor rotational errors may be acceptable. However, in the case of relatively long printheads, the amount of error introduced to dot positions due to the erroneous rotational position of the printhead module relative to the carrier may reach noticeable, and therefore unacceptable (or at least undesirable) levels. 15 The problem is exacerbated when multiple printhead modules are laid end to end to form a printhead, such as a pagewidth printhead, due to the fact that some forms of rotational error will cause discontinuities between rows of dots printed by adjacent modules. In general, these discontinuities are more visible and objectionable than mere consistent skew across a single printhead module. 20 It would be useful to provide a method and apparatus for at least partially compensating for errors in ink dot placement due to erroneous rotational displacement of a printhead module relative to a carrier. SUMMARY OF THE INVENTION 25 In a first aspect the present invention provides a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: (a) determining the rotational displacement; (b) determining at least one correction factor that at least partially compensates for the ink dot displacement; 30 and WO 2005/120835 PCT/AU2004/000706 3 (c) using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. Optionally, step (c) includes altering a timing of a fire signal to at least one of the nozzles on the basis of the 5 correction factor, thereby to effect the at least partial compensation. Optionally, the nozzles are disposed in a plurality of rows, and step (c) includes reallocating at least one of the ink dots from at least one original print line to at least one alternate print line, thereby to effect the at least partial compensation. 10 Optionally, step (c) further includes the step of altering a timing of fire signals to at least one of the nozzles on the basis of the correction factor, thereby to effect the at least partial compensation. Optionally, the altered fire signals are supplied to both reallocated ink dots and non-reallocated ink dots. 15 Optionally, the correction factor is stored in a memory associated with the printhead. Optionally, the memory is mounted with the printhead, the printhead being mounted on the print engine. 20 Optionally, the rotational displacement is roll. Optionally, the rotational displacement is yaw. Optionally, the printhead module being one of a plurality of printhead modules mounted on a carrier to form a 25 printhead and the error in ink dot placement being an error relative to ink dots output by one or more of the other printhead modules Optionally, the printer is a pagewidth printer.
WO 2005/120835 PCT/AU2004/000706 4 Optionally, the printer is a pagewidth printer. Optionally, the present invention provides a printer controller programmed and configured to implement the method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles 5 due to erroneous rotational displacement of a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: (a) determining the rotational displacement; (b) determining at least one correction factor that at least partially compensates for the ink dot displacement; and 10 (c) using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. Optionally, the method including expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a 15 fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally, the method including expelling ink from a printhead module including at least one row that comprises 20 a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and 25 (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. Optionally, the method including manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of 30 laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed.
WO 2005/120835 PCT/AU2004/000706 5 Optionally, the method being performed in conjunction with a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, 5 wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. Optionally, the method being performed in a printer comprising: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and 10 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. Optionally, the method being performed in a printer comprising: 15 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the 20 printhead modules are configured such that no dot data passes between them. Optionally, the method being performed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is 25 longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. 30 Optionally, the method being performed in a printer comprising: WO 2005/120835 PCT/AU2004/000706 6 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to 5 output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. 10 Optionally, the method being performed in conjunction with a printer controller for supplying dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; 15 determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. 20 Optionally, the method being performed in conjunction with a printer controller for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. 25 Optionally, the method being performed in conjunction with a printer controller for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to 30 sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each WO 2005/120835 PCT/AU2004/000706 7 subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. Optionally, the method being performed in conjunction with a printer controller for outputting to a printhead 5 module: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two 10 inks. Optionally, the method being performed in conjunction with a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 15 Optionally, the method being performed in conjunction with a printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the 20 channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. 25 Optionally, the method being performed in conjunction with a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan.
WO 2005/120835 PCT/AU2004/000706 8 Optionally, the method being used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; 5 (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 10 Optionally, the method being used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle 15 position x is at or adjacent the centre of the set of nozzles. Optionally, the method being performed in conjunction with a printer controller for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a 20 direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. 25 Optionally, the method being performed in conjunction with a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot 30 data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
WO 2005/120835 PCT/AU2004/000706 9 Optionally, the method being performed in conjunction with a printer controller for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead, wherein each of the serial outputs is configured to supply dot data for at least two channels of the at least one printhead. 5 Optionally, the method being performed in conjunction with a printhead module including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved 10 with at least one of the other groups of the nozzles. Optionally, the method being performed in conjunction with a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; 15 and a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. Optionally, the method being performed in conjunction with a printhead comprising a plurality of printhead 20 modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. Optionally, the method being performed in conjunction with a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to 25 a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally, the method being performed in conjunction with a printhead module including at least one row that 30 comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: WO 2005/120835 PCT/AU2004/000706 10 in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. 5 Optionally, the method being performed in conjunction with a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. Optionally, the method being performed in conjunction with a printhead module including at least one row of 10 printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. Optionally, the method being performed in conjunction with a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being 15 grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. 20 Optionally, the method being performed in conjunction with a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least 25 some other dots output to print media are printed to by nozzles from the second pair of rows. Optionally, the method being performed in conjunction with a printer controller for providing data to a printhead module that includes: at least one row of print nozzles; 30 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
WO 2005/120835 PCT/AU2004/000706 11 Optionally, the method being performed in conjunction with a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being 5 configured to modify operation of the nozzles in response to the temperature rising above a first threshold. Optionally, the method being performed in conjunction with a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the 10 event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. In a second aspect the present invention provides a method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being 15 configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), ... , nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the nozzle at each given position within the set is fired simultaneously with the nozzles in the other 20 sets at respective corresponding positions. Optionally the printhead module includes a plurality of the rows of nozzles, the method including sequentially repeating the for each of the rows of nozzles. 25 Optionally the rows are disposed in pairs. Optionally the rows in each pair of rows are offset relative to each other. Optionally each pair of rows is configured to print the same color ink. 30 Optionally each pair of rows is connected to a common ink source.
WO 2005/120835 PCT/AU2004/000706 12 Optionally the sets of nozzles are adjacent each other. Optionally the sets of nozzles are separated by an intermediate nozzle, the intermediate nozzle being fired either 5 prior to the nozzle at position 1 in each set, or following the nozzle at position n. Optionally the method includes the step of providing the fire sequence to the printhead module from a printer controller, the fire signals being based on the fire sequence. 10 Optionally the fire sequence is loaded into a shift register in the printhead module. Optionally the method at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: 15 (a) determining the rotational displacement; (b) determining at least one correction factor that at least partially compensates for the ink dot displacement; and (c) using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. 20 Optionally the method includes expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; 25 (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle.
WO 2005/120835 PCT/AU2004/000706 13 Optionally the method includes manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. 5 Optionally, the method being performed in conjunction with a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 10 Optionally, the method being performed in a printer comprising: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to 15 output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. Optionally, the method being performed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel 20 to each other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 25 Optionally, the method being performed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; 30 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead WO 2005/120835 PCT/AU2004/000706 14 module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. Optionally, the method being performed in a printer comprising: 5 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead 10 module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. Optionally, the method being performed in conjunction with a printer controller for supplying dot data to at least 15 one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one 20 printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. Optionally, the method being performed in conjunction with a printer controller for supplying dot data to a 25 printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. 30 Optionally, the method being performed in conjunction with a printer controller for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles WO 2005/120835 PCT/AU2004/000706 15 in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each 5 subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. Optionally, the method being performed in conjunction with a printer controller for outputting to a printhead module: 10 dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 15 Optionally, the method being performed in conjunction with a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 20 Optionally, the method being performed in conjunction with a printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and 25 a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. Optionally, the method being performed in conjunction with a printer controller for supplying data to a printhead 30 comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan.
WO 2005/120835 PCT/AU2004/000706 16 Optionally, the method being used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: 5 (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 10 Optionally, the method being used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle 15 position 1, nozzle position n, nozzle position 2, nozzle position (n-), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally, the method being performed in conjunction with a printer controller for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at 20 least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for 25 printing. Optionally, the method being performed in conjunction with a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second 30 rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
WO 2005/120835 PCT/AU2004/000706 17 Optionally, the method being performed in conjunction with a printer controller for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead, wherein each of the serial outputs is configured to 5 supply dot data for at least two channels of the at least one printhead. Optionally, the method being performed in conjunction with a printhead module including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each 10 shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. Optionally, the method being performed in conjunction with a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: 15 a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. 20 Optionally, the method being performed in conjunction with a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. Optionally, the method being performed in conjunction with a printhead module including at least one row that 25 comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 30 Optionally, the method being performed in conjunction with a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink WO 2005/120835 PCT/AU2004/000706 18 in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and 5 then to fire the central nozzle. Optionally, the method being performed in conjunction with a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. 10 Optionally, the method being performed in conjunction with a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 15 Optionally, the method being performed in conjunction with a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles 20 are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. Optionally, the method being performed in conjunction with a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the 25 printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. Optionally, the method being performed in conjunction with a printer controller for providing data to a printhead 30 module that includes: at least one row of print nozzles; WO 2005/120835 PCT/AU2004/000706 19 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 5 Optionally, the method being performed in conjunction with a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. 10 Optionally, the method being performed in conjunction with a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 15 Optionally the printhead module includes a plurality of the rows, the method including firing each nozzle in each row simultaneously with the nozzle or nozzles at the same position in the other rows. Optionally the method includes a plurality of pairs of the rows, each pair of rows including an odd row and an 20 even row, the odd and even rows in each pair being offset from each other in both x and y directions relative to an intended direction of print media movement relative to the printhead, the method including causing firing of at least a plurality of the odd rows prior to firing any of the even rows, or vice versa. Optionally all the odd rows are fired before any of the even rows are fired, or vice versa. 25 Optionally the odd rows, or the even rows, or both, are fired in a predetermined order. Optionally the predetermined order is selectable from a plurality of predetermined available orders. 30 Optionally the predetermined order is sequential.
WO 2005/120835 PCT/AU2004/000706 20 Optionally the predetermined order can commence at any of a plurality of the rows. In a third aspect the present invention provides a method of expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel 5 ink in response to a fire signal, the method comprising the steps of: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set 10 have been fired, and then firing the central nozzle. Optionally the printhead module includes a plurality of the rows of nozzles, the method including sequentially repeating steps (a) to (d) for each of the rows of nozzles. 15 Optionally the rows are disposed in pairs. Optionally the rows in each pair of rows are offset relative to each other. Optionally each pair of rows is configured to print the same color ink. 20 Optionally each pair of rows is connected to a common ink source. Optionally the sets of nozzles are adjacent each other. 25 Optionally the sets of nozzles are separated by an intermediate nozzle, the intermediate nozzle being fired either prior to the nozzle at position 1 in each set, or following the nozzle at position n. In a second aspect the present invention provides a method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being WO 2005/120835 PCT/AU2004/000706 21 configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), ... , nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 5 Optionally the nozzle at each given position within the set is fired simultaneously with the nozzles in the other sets at respective corresponding positions. Optionally, the method at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier, the nozzles being 10 disposed on the printhead module, the method comprising the steps of: (a) determining the rotational displacement; (b) determining at least one correction factor that at least partially compensates for the ink dot displacement; and (c) using the correction factor to alter the output of the ink dots to at least partially compensate for the 15 rotational displacement. Optionally, the method including expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the 20 sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally, the method including manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of 25 laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. Optionally, the method being performed in conjunction with a printhead module including: at least one row of print nozzles; 30 at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers.
WO 2005/120835 PCT/AU2004/000706 22 Optionally, the method being performed in a printer comprising: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and 5 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. Optionally, the method being performed in a printer comprising: 10 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the 15 printhead modules are configured such that no dot data passes between them. Optionally, the method being performed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is 20 longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. 25 Optionally, the method being performed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; 30 at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead WO 2005/120835 PCT/AU2004/000706 23 module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. Optionally, the method being performed in conjunction with a printer controller for supplying dot data to at least 5 one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one 10 printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. Optionally, the method being performed in conjunction with a printer controller for supplying dot data to a 15 printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. 20 Optionally, the method being performed in conjunction with a printer controller for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire 25 group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. 30 Optionally, the method being performed in conjunction with a printer controller for outputting to a printhead module: dot data to be printed with at least two different inks; and WO 2005/120835 PCT/AU2004/000706 24 control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 5 Optionally, the method being performed in conjunction with a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 10 Optionally, the method being performed in conjunction with a printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and 15 a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. Optionally, the method being performed in conjunction with a printer controller for supplying data to a printhead 20 comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. Optionally, the method being used in conjunction with a printer controller for supplying one or more control 25 signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and 30 (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle.
WO 2005/120835 PCT/AU2004/000706 25 Optionally, the method being used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, 5 the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally, the method being performed in conjunction with a printer controller for supplying dot data to a 10 printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from 15 the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. Optionally, the method being performed in conjunction with a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows 20 comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 25 Optionally, the method being performed in conjunction with a printer controller for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead, wherein each of the serial outputs is configured to supply dot data for at least two channels of the at least one printhead. 30 Optionally, the method being performed in conjunction with a printhead module including: at least one row of print nozzles; WO 2005/120835 PCT/AU2004/000706 26 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 5 Optionally, the method being performed in conjunction with a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the 10 channels, wherein the first number is greater than the second number. Optionally, the method being performed in conjunction with a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 15 Optionally, the method being performed in conjunction with a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle 20 position x is at or adjacent the centre of the set of nozzles. Optionally, the method being performed in conjunction with a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in 25 each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. 30 Optionally, the method being performed in conjunction with a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data.
WO 2005/120835 PCT/AU2004/000706 27 Optionally, the method being performed in conjunction with a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 5 Optionally, the method being performed in conjunction with a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired 10 simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. Optionally, the method being performed in conjunction with a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned 15 with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. 20 Optionally, the method being performed in conjunction with a printer controller for providing data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved 25 with at least one of the other groups of the nozzles. Optionally, the method being performed in conjunction with a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being 30 configured to modify operation of the nozzles in response to the temperature rising above a first threshold.
WO 2005/120835 PCT/AU2004/000706 28 Optionally, the method being performed in conjunction with a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on 5 print media at or adjacent a position where the faulty nozzle would otherwise have printed it. Optionally the printhead module includes a plurality of the rows, the method including firing each nozzle in each row simultaneously with the nozzle or nozzles at the same position in the other rows. 10 Optionally the printhead module includes a plurality of the rows, the method including firing each nozzle in each row simultaneously with the nozzle or nozzles at the same position in the other rows. Optionally the method including a plurality of pairs of the rows, each pair of rows including an odd row and an even row, the odd and even rows in each pair being offset from each other in both x and y directions relative to an 15 intended direction of print media movement relative to the printhead, the method including causing firing of at least a plurality of the odd rows prior to firing any of the even rows, or vice versa. Optionally all the odd rows are fired before any of the even rows are fired, or vice versa. 20 Optionally the odd rows, or the even rows, or both, are fired in a predetermined order. Optionally the predetermined order is selectable from a plurality of predetermined available orders. Optionally the predetermined order is sequential. 25 Optionally the predetermined order can commence at any of a plurality of the rows. In a fourth aspect the present invention provides method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method 30 comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed.
WO 2005/120835 PCT/AU2004/000706 29 In a second aspect the present invention provides a method of manufacturing a plurality of pagewidth printheads, the method comprising the steps of: manufacturing a plurality of printhead modules in accordance with claim 1; and 5 assembling pairs of at least some of the printhead modules to form pagewidth printheads, wherein each of the printhead modules in each pagewidth printhead is shorter than the pagewidth. Optionally the printhead modules of at least one of the pagewidth printheads are of relatively different lengths. 10 Optionally the printhead modules of at least one of the pagewidth printheads are of the same length. Optionally the printhead modules of at least one of the pagewidth printheads are of relatively different lengths, and the printhead modules of at least another of the pagewidth printheads are of the same length. 15 Optionally at least some of the printhead modules are larger than a reticle step used in laying out those printhead modules. Optionally the method includes the step of laying out a plurality of left-handed and right-handed printhead modules. 20 Optionally the method includes the step of laying out a plurality of different lengths of left-handed and right handed printhead modules. Optionally, the method at least partially compensating for errors in ink dot placement by at least one of a plurality 25 of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: (a) determining the rotational displacement; (b) determining at least one correction factor that at least partially compensates for the ink dot displacement; and WO 2005/120835 PCT/AU2004/000706 30 (c) using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. Optionally, the method including expelling ink from a printhead module including at least one row that comprises 5 a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at.or adjacent the centre of the set of nozzles. 10 Optionally, the method including expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b) providing a fire signal to the next inward pair of nozzles in each set; 15 (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. Optionally, the method being performed in conjunction with a printhead module including: 20 at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. Optionally, the method being performed in a printer comprising: 25 a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. 30 Optionally, the method being performed in a printer comprising: WO 2005/120835 PCT/AU2004/000706 31 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead 5 module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. Optionally, the method being performed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel 10 to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second 15 printhead module. Optionally, the method being performed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is 20 longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least 25 some of the dot data received from the first printer controller. Optionally, the method being performed in conjunction with a printer controller for supplying dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module 30 relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; WO 2005/120835 PCT/AU2004/000706 32 determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. 5 Optionally, the method being performed in conjunction with a printer controller for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in 10 response to the temperature rising above a first threshold. Optionally, the method being performed in conjunction with a printer controller for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles 15 in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the 20 order of firing of the nozzles. Optionally, the method being performed in conjunction with a printer controller for outputting to a printhead module: dot data to be printed with at least two different inks; and 25 control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. Optionally, the method being performed in conjunction with a printhead module including at least one row of 30 printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
WO 2005/120835 PCT/AU2004/000706 33 Optionally, the method being performed in conjunction with a printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the 5 channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. 10 Optionally, the method being performed in conjunction with a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 15 Optionally, the method being used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b) providing a fire signal to the next inward pair of nozzles in each set; 20 (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. Optionally, the method being used in conjunction with a printer controller for supplying one or more control 25 signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 30 Optionally, the method being performed in conjunction with a printer controller for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at WO 2005/120835 PCT/AU2004/000706 34 least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from 5 the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. Optionally, the method being performed in conjunction with a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows 10 comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 15 Optionally, the method being performed in conjunction with a printer controller for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead, wherein each of the serial outputs is configured to supply dot data for at least two channels of the at least one printhead. 20 Optionally, the method being performed in conjunction with a printhead module including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved 25 with at least one of the other groups of the nozzles. Optionally, the method being performed in conjunction with a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; 30 and a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number.
WO 2005/120835 PCT/AU2004/000706 35 Optionally, the method being performed in conjunction with a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 5 Optionally, the method being performed in conjunction with a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle 10 position x is at or adjacent the centre of the set of nozzles. Optionally 1, the method being performed in conjunction with a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in 15 each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. 20 Optionally, the method being performed in conjunction with a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. Optionally, the method being performed in conjunction with a printhead module including at least one row of 25 printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. Optionally, the method being performed in conjunction with a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being 30 grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired WO 2005/120835 PCT/AU2004/000706 36 simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. Optionally, the method being performed in conjunction with a printhead module comprising at least first and 5 second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. 10 Optionally, the method being performed in conjunction with a printer controller for providing data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each 15 shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. Optionally, the method being performed in conjunction with a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being 20 configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. Optionally, the method being performed in conjunction with a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least 25 first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. In a fifth aspect the present invention provides a printhead module including: 30 at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers.
WO 2005/120835 PCT/AU2004/000706 37 Optionally, there is a one to one correspondence between the nozzles and elements of the two shift registers. Optionally, each of the shift registers supplies dot data to about half of the nozzles. 5 Optionally the printhead module includes at least one pair of rows of the nozzles, the rows in each pair being offset with respect to each other by half the intra-row nozzle spacing. Optionally, each of the at least two shift registers supplies dot data to at least some of the nozzles in at least one 10 pair of rows. Optionally the present invention provides a printhead comprising a plurality of printhead modules including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one 15 rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. Optionally, the printhead is a pagewidth printhead. Optionally the printhead module is configured to receive dot data to which a method of at least partially 20 compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier has been applied, the nozzles being disposed on the printhead module, the method comprising the steps of: (a) determining the rotational displacement; (b) determining at least one correction factor that at least partially compensates for the ink dot displacement; 25 and (c) using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. Optionally the printhead module is configured to receive dot data to which a method of expelling ink has been 30 applied, the method being applied to a printhead module including at least one row that comprises a plurality of WO 2005/120835 PCT/AU2004/000706 38 adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 5 Optionally the printhead module is configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: 10 (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 15 Optionally the printhead module having been manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. 20 Optionally the printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 25 Optionally the printhead module installed in a printer comprising: a printhead comprising at least the first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to 30 output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead.
WO 2005/120835 PCT/AU2004/000706 39 Optionally the printhead module installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; 5 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 10 Optionally the printhead module installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to 15 output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. Optionally the printhead module installed in a printer comprising: 20 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead 25 module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. Optionally the printhead module is in communication with a printer controller for supplying dot data to at least 30 one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: WO 2005/120835 PCT/AU2004/000706 40 access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and 5 supply the dot data to the printhead module. Optionally the printhead module is in communication with a printer controller for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least 10 one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. Optionally the printhead module is in communication with a printer controller for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows 15 of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each 20 subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. Optionally the printhead module is in communication with a printer controller for outputting to a printhead module: 25 dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 30 WO 2005/120835 PCT/AU2004/000706 41 Optionally the printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 5 Optionally the printhead module is in communication with a printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and 10 a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. Optionally the printhead module is in communication with a printer controller for supplying data to a printhead 15 comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. Optionally the printhead module is used in conjunction with a printer controller for supplying one or more control 20 signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a) a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b) a fire signal is provided to the next inward pair of nozzles in each set; (c) in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; 25 and (d) in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. Optionally the printhead module is used in conjunction with a printer controller for supplying one or more control 30 signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle WO 2005/120835 PCT/AU2004/000706 42 position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printhead module is in communication with a printer controller for supplying dot data to a 5 printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from 10 the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. Optionally the printhead module is in communication with a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows 15 comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 20 Optionally the printhead module is in communication with a printer controller for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. 25 Optionally the printhead module including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 30 Optionally the printhead module being capable of printing a maximum of n of channels of print data, the printhead being configurable into: WO 2005/120835 PCT/AU2004/000706 43 a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. 5. Optionally a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 10 Optionally the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 15 Optionally the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: 20 in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. Optionally a printhead module for receiving dot data to be printed using at least two different inks and control 25 data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. Optional a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to 30 that of a pagewidth to be printed.
WO 2005/120835 PCT/AU2004/000706 44 Optionally a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in 5 the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. Optionally a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second 10 row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. 15 Optionally a printhead module is in communication with a printer controller for providing data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved 20 with at least one of the other groups of the nozzles. Optionally a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in 25 response to the temperature rising above a first threshold. Optionally a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a 30 corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. In a sixth aspect the present invention provides printer comprising: WO 2005/120835 PCT/AU2004/000706 45 a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input 5 of the printhead. Optionally the printer including at least one synchronization means between the first and second printer controllers for synchronizing the supply of dot by the printer controllers. 10 Optionally the printer configured such that the first and second printer controllers sequentially provide the dot data to the common input. Optionally the printer further including a second printhead module, the printer being configured such that: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the 15 second printer controller outputs dot data only to the second printhead module. Optionally the printhead modules are configured such that no dot data passes between them. Optionally each of the printer controllers is configurable to supply the dot data to printhead modules of a plurality 20 of different lengths. Optionally the printhead is a pagewidth printhead. In a further aspect the present invention provides a print engine comprising: 25 a carrier; a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input 30 of the printhead.
WO 2005/120835 PCT/AU2004/000706 46 Optionally the printer including at least one synchronization means between the first and second printer controllers for synchronizing the supply of dot by the printer controllers. 5 Optionally the printer configured such that the first and second printer controllers alternately provide the dot data to the common input. Optionally the printer further including a second printhead module, the printer being configured such that: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the 10 second printer controller outputs dot data only to the second printhead module. Optionally the printhead modules are configured such that no dot data passes between them. Optionally each of the printer controllers is configurable to supply the dot data to printhead modules of a plurality 15 of different lengths. Optionally the printhead is a pagewidth printhead. In a further aspect the present invention provides a printer comprising: 20 a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least first and second rows of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to the printhead to supply data for the first and second rows of nozzles, respectively. 25 Optionally the printer including at least one synchronization means between the first and second printer controllers for synchronizing the supply of dot by the printer controllers. Optionally the printhead modules are configured such that no dot data passes between them. 30 WO 2005/120835 PCT/AU2004/000706 47 Optionally the printhead is a pagewidth printhead. Optionally the printer is for implementing a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module 5 relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: (a) determining the rotational displacement; (b) determining at least one correction factor that at least partially compensates for the ink dot displacement; and (c) using the correction factor to alter the output of the ink dots to at least partially compensate for the 10 rotational displacement. Optionally the printer is for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in 15 accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1),. nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printer is for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink 20 in response to a fire signal, the method comprising the steps of: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set 25 have been fired, and then firing the central nozzle. Optionally the printer is manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein 30 at least one of the printhead modules is right-handed and at least another is left-handed.
WO 2005/120835 PCT/AU2004/000706 48 Optionally the printer including a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 5 Optionally the printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to 10 output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. Optionally the printer comprising: 15 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead 20 module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. Optionally the printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel 25 to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead 30 module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller.
WO 2005/120835 PCT/AU2004/000706 49 Optionally the printer including at least one printhead module, configured for at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; 5 determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. 10 Optionally the printer including a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. 15 Optionally the printer controls a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding 20 nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. Optionally the printer including a printer controller for sending to a printhead: 25 dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 30 WO 2005/120835 PCT/AU2004/000706 50 Optionally the printer including a printer controller for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 5 Optionally the printer including a printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and 10 a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. Optionally the printer including a printer controller for supplying data to a printhead comprising a plurality of 15 printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape.in plan. Optionally the printer including a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, 20 each of the nozzles being configured to expel ink in response to a fire signal, such that: (a) a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b) a fire signal is provided to the next inward pair of nozzles in each set; (c) in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and 25 (d) in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. Optionally the printer including a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent 30 nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle WO 2005/120835 PCT/AU2004/000706 51 position n, nozzle position 2, nozzle position (n-1),..., nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printer including a printer controller for supplying dot data to a printhead module comprising at 5 least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the 10 printer controller being configurable to supply dot data to the printhead module for printing. Optionally the printer including a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a 15 similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 20 Optionally the printer including a printer controller for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. Optionally the printer including a printer controller for supplying data to a printhead module including: 25 at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 30 Optionally the printer including a printer controller for supplying data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: WO 2005/120835 PCT/AU2004/000706 52 a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. 5 Optionally the printer including a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 10 Optionally the printer including a printer controller for supplying data to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 15 Optionally the printer including a printer controller for supplying data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: 20 in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. Optionally the printer including a printer controller for supplying data to a printhead module for receiving dot data 25 to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. Optionally the printer including a printer controller for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the 30 row portion including a component in a direction normal to that of a pagewidth to be printed.
WO 2005/120835 PCT/AU2004/000706 53 Optionally the printer including a printer controller for supplying data to a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired 5 simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. Optionally the printer including a printer controller for supplying data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being 10 aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. 15 Optionally the printer including a printer controller for providing data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 20 Optionally the printer including a printer controller for supplying data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first 25 threshold. Optionally the printer including a printer controller for supplying data to a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being 30 configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
WO 2005/120835 PCT/AU2004/000706 54 In a seventh aspect the present invention provides a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to 5 output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. Optionally the printer includes at least one synchronization means between the first and second printer controllers 10 for synchronizing the supply of dot by the printer controllers. Optionally each of the printer controllers is configurable to supply the dot data to a printhead module of arbitrary length. 15 Optionally the first and second printhead modules are equal in length. Optionally the first and second printhead modules are unequal in length. Optionally the printhead is a pagewidth printhead. 20 In a further aspect the present invention provides a print engine comprising: a carrier; a printhead comprising first and second elongate printhead modules, the printhead modules being mounted parallel to each other end to end on the carrier on either side of a join region; 25 at least first and second printer controllers mounted on the carrier and being configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them.
WO 2005/120835 PCT/AU2004/000706 55 Optionally the print engine includes at least one synchronization means between the first and second printer controllers for synchronizing the supply of dot by the printer controllers. Optionally each of the printer controllers is configurable to supply the dot data to a printhead module of arbitrary 5 length. Optionally the first and second printhead modules are equal in length. Optionally the first and second printhead modules are unequal in length. 10 Optionally the printhead is a pagewidth printhead. Optionally the printer is for implementing a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module 15 relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: (a) determining the rotational displacement; (b) determining at least one correction factor that at least partially compensates for the ink dot displacement; and (c) using the correction factor to alter the output of the ink dots to at least partially compensate for the 20 rotational displacement. Optionally the printer is for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire. signal in 25 accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1),. nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printer is for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink 30 in response to a fire signal, the method comprising the steps of: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; WO 2005/120835 PCT/AU2004/000706 56 (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 5 Optionally the printer is manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. 10 Optionally the printer includes a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 15 Optionally the printer comprises: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to 20 output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. Optionally the printer comprises: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel 25 to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second 30 printhead module.
WO 2005/120835 PCT/AU2004/000706 57 Optionally the printer comprises: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; 5 at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. 10 Optionally the printer comprises at least one printhead module, configured for at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; 15 determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. 20 Optionally the printer comprises a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. 25 Optionally the printer controls a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding 30 nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles.
WO 2005/120835 PCT/AU2004/000706 58 Optionally the printer includes a printer controller for sending to a printhead: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output 5 being configured to output at least some of the control data and at least some of the dot data for the at least two inks. Optionally the printer includes a printer controller for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the 10 row portion including a component in a direction normal to that of a pagewidth to be printed. Optionally the printer includes a printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: 15 a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. 20 Optionally the printer includes a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 25 Optionally the printer includes a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a) a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b) a fire signal is provided to the next inward pair of nozzles in each set; 30 (c) in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and WO 2005/120835 PCT/AU2004/000706 59 (d) in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. Optionally the printer includes a printer controller for supplying one or more control signals to a printhead 5 module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 10 Optionally the printer includes a printer controller for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows 15 are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. Optionally the printer includes a printer controller for supplying dot data to at least one printhead module, the at 20 least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have 25 printed it. Optionally the printer includes a printer controller for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. 30 Optionally the printer includes a printer controller for supplying data to a printhead module including: at least one row of print nozzles; WO 2005/120835 PCT/AU2004/000706 60 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 5 Optionally the printer includes a printer controller for supplying data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the 10 channels, wherein the first number is greater than the second number. Optionally the printer includes a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 15 Optionally the printer includes a printer controller for supplying data to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], 20 wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printer includes a printer controller for supplying data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth 25 position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. 30 Optionally the printer includes a printer controller for supplying data to a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data.
WO 2005/120835 PCT/AU2004/000706 61 Optionally the printer includes a printer controller for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 5 Optionally the printer includes a printer controller for supplying data to a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired 10 simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. Optionally the printer includes a printer controller for supplying data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being 15 aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. 20 Optionally the printer includes a printer controller for providing data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 25 Optionally the printer includes a printer controller for supplying data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first 30 threshold.
WO 2005/120835 PCT/AU2004/000706 62 Optionally the printer includes a printer controller for supplying data to a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a 5 position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. In an eighth aspect the present invention provides a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is 10 longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. 15 Optionally the printhead modules are configured such that no dot data passes between them. Optionally the printer includes at least one synchronization means between the first and second printer controllers for synchronizing the supply of dot data by the printer controllers. 20 Optionally each of the printer controllers is configurable to supply the dot data to printhead modules of a plurality of different lengths. Optionally the printhead is a pagewidth printhead. 25 In a further aspect the present invention provides a print engine comprising: a carrier; a printhead comprising first and second elongate printhead modules, the printhead modules being mounted parallel to each other end to end on the carrier on either side of a join region, wherein the first printhead 30 module is longer than the second printhead module; WO 2005/120835 PCT/AU2004/000706 63 at least first and second printer controllers mounted on the carrier and being configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. 5 Optionally the printhead modules are configured such that no dot data passes between them. Optionally the print engine includes at least one synchronization means between the first and second printer controllers for synchronizing the supply of dot by the printer controllers. 10 Optionally each of the printer controllers is configurable to supply the dot data to printhead modules of a plurality of different lengths. Optionally the printhead is a pagewidth printhead. 15 Optionally the printer is for implementing a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: (a) determining the rotational displacement; 20 (b) determining at least one correction factor that at least partially compensates for the ink dot displacement; and (c) using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. 25 Optionally the printer is for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1),. nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 30 WO 2005/120835 PCT/AU2004/000706 64 Optionally the printer is for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; 5 (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 10 Optionally the printer is manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. 15 Optionally the printer includes a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 20 Optionally the printer includes: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input 25 of the printhead. Optionally the printer includes: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; 30 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead WO 2005/120835 PCT/AU2004/000706 65 module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. Optionally the printer includes: 5 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead 10 module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. Optionally the printer includes at least one printhead module, configured for at least partially compensating for 15 errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at 20 least partially compensate for the rotational displacement and supply the dot data to the printhead module. Optionally the printer includes a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a 25 temperature at or adjacent at least one of the nozzles, the printer being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. Optionally the printer controls a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a 30 printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding WO 2005/120835 PCT/AU2004/000706 66 nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. 5 Optionally the printer includes a printer controller for sending to a printhead: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two 10 inks. Optionally the printer includes a printer controller for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 15 Optionally the printer includes a printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the 20 channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. 25 Optionally the printer includes a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. Optionally the printer includes a printer controller for supplying one or more control signals to a printhead 30 module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: WO 2005/120835 PCT/AU2004/000706 67 (a) a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b) a fire signal is provided to the next inward pair of nozzles in each set; (c) in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and 5 (d) in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. Optionally the printer includes a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent 10 nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 15 Optionally the printer includes a printer controller for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least 20 some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. Optionally the printer includes a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for 25 ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 30 Optionally the printer includes a printer controller for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead.
WO 2005/120835 PCT/AU2004/000706 68 Optionally the printer includes a printer controller for supplying data to a printhead module including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each 5 shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. Optionally the printer includes a printer controller for supplying data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: 10 a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. 15 Optionally the printer includes a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. Optionally the printer includes a printer controller for supplying data to a printhead module including at least one 20 row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 25 Optionally the printer includes a printer controller for supplying data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and 30 in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle.
WO 2005/120835 PCT/AU2004/000706 69 Optionally the printer includes a printer controller for supplying data to a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. 5 Optionally the printer includes a printer controller for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 10 Optionally the printer includes a printer controller for supplying data to a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles 15 are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. Optionally the printer includes a printer controller for supplying data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to 20 the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. Optionally the printer includes a printer controller for providing data to a printhead module that includes: 25 at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 30 Optionally the printer includes a printer controller for supplying data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead WO 2005/120835 PCT/AU2004/000706 70 module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. Optionally the printer includes a printer controller for supplying data to a printhead module comprising a plurality 5 of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 10 In a ninth aspect the present invention provides a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to 15 output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. 20 Optionally the printhead modules are configured such that no dot data passes between them. Optionally the printer includes at least one synchronization means between the first and second printer controllers for synchronizing the supply of dot data by the printer controllers. 25 Optionally each of the printer controllers is configurable to supply the dot data to printhead modules of a plurality of different lengths. Optionally the printhead is a pagewidth printhead. 30 In a further aspect the present invention provides a print engine comprising: a carrier; WO 2005/120835 PCT/AU2004/000706 71 a printhead comprising first and second elongate printhead modules, the printhead modules being mounted parallel to each other end to end on the carrier on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to 5 output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. 10 Optionally the printhead modules are configured such that no dot data passes between them. Optionally the print engine includes at least one synchronization means between the first and second printer controllers for synchronizing the supply of dot by the printer controllers. 15 Optionally each of the printer controllers is configurable to supply the dot data to printhead modules of a plurality of different lengths. Optionally the printhead is a pagewidth printhead. 20 Optionally the printer controller is for implementing a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: (a) determining the rotational displacement; 25 (b) determining at least one correction factor that at least partially compensates for the ink dot displacement; and (c) using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. 30 Optionally the printer controller is for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being WO 2005/120835 PCT/AU2004/000706 72 configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), ... , nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 5 Optionally the printer controller is for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b) providing a fire signal to the next inward pair of nozzles in each set; 10 (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. Optionally the printer controller is manufactured in accordance with a method of manufacturing a plurality of 15 printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. Optionally the printer controller supplies data to a printhead module including: 20 at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. Optionally the printer controller is installed in a printer comprising: 25 a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. 30 Optionally the printer controller is installed in a printer comprising: WO 2005/120835 PCT/AU2004/000706 73 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead 5 module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. Optionally the printer controller is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel 10 to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second 15 printhead module. Optionally the printer controller supplies dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: 20 access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. 25 Optionally the printer controller supplies dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. 30 Optionally the printer controller controls a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part WO 2005/120835 PCT/AU2004/000706 74 of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of 5 each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. Optionally the printer controller outputs to a printhead module: dot data to be printed with at least two different inks; and 10 control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 15 Optionally the printer controller supplies data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. Optionally the printer controller supplies print data to at least one printhead module capable of printing a 20 maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; 25 wherein the printer controller is selectively configurable to supply dot data for the first and second modes. Optionally the printer controller supplies data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 30 WO 2005/120835 PCT/AU2004/000706 75 Optionally the printer controller supplies one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a) a fire signal is provided to nozzles at a first and nth position in each set of nozzles; 5 (b) a fire signal is provided to the next inward pair of nozzles in each set; (c) in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. 10 Optionally the printer controller supplies one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, 15 nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printer controller supplies dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with 20 respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. 25 Optionally the printer controller supplies dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, 30 in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
WO 2005/120835 PCT/AU2004/000706 76 Optionally the printer controller receives first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. Optionally the printer controller supplies data to a printhead module including: 5 at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 10 Optionally the printer controller supplies data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the 15 channels, wherein the first number is greater than the second number. Optionally the printer controller supplies data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 20 Optionally the printer controller supplies data to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle 25 position x is at or adjacent the centre of the set of nozzles. Optionally the printer controller supplies data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of 30 nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and WO 2005/120835 PCT/AU2004/000706 77 in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. Optionally the printer controller supplies data to a printhead module for receiving dot data to be printed using at 5 least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. Optionally the printer controller supplies data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion 10 including a component in a direction normal to that of a pagewidth to be printed. Optionally the printer controller supplies data to a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, 15 the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. Optionally the printer controller supplies data to a printhead module comprising at least first and second rows 20 configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. 25 Optionally the printer controller supplies data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved 30 with at least one of the other groups of the nozzles.
WO 2005/120835 PCT/AU2004/000706 78 Optionally the printer controller supplies data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. 5 Optionally the printer controller supplies data to a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print 10 media at or adjacent a position where the faulty nozzle would otherwise have printed it. In a tenth aspect the present invention provides printer controller for supplying dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the 15 printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and 20 supply the dot data to the printhead module. Optionally, the nozzles are disposed in a plurality of rows, and the printer controller is configured to reallocate at least one of the ink dots from at least one original print line to at least one alternate print line, thereby to effect the at least partial compensation. 25 Optionally the printer controller is configured to retrieve the correction factor from a memory associated with the printhead. Optionally, the memory is mounted with the printhead, the printhead being mounted on the print engine. 30 Optionally, the rotational displacement is roll.
WO 2005/120835 PCT/AU2004/000706 79 Optionally, the rotational displacement is yaw. Optionally, the printhead module being one of a plurality of printhead modules mounted on a carrier to form a 5 printhead and the error in ink dot placement being an error relative to ink dots output by one or more of the other printhead modules Optionally, the printhead module is part of a printhead comprising a plurality of the modules, the printer controller being configured to determine an order in which at least some of the dot data is supplied to a plurality of the 10 printhead modules, the order being determined at least partly on the basis of one or more of the correction factors, thereby to at least partially compensate for the rotational displacement of the plurality of the printheads. Optionally, the correction factor is at least partially based on a thickness of media being printed on. 15 Optionally the printer controller configured to at least improve first order continuity between ink dots printed by adjacent printhead modules. Optionally a print engine including the print controller according and a plurality of the printhead modules that define a printhead, the print engine being configured to compensate for the rotational displacement of at least one 20 of the printhead modules. Optionally the print engine further including a memory for storing the correction factor in a form accessible to the printer controller. 25 Optionally the print engine is configured to alter a timing of fire signals supplied to at least one of the nozzles on the basis of the correction factor, thereby to further effect the at least partial compensation. Optionally the print engine is configured to supply the altered fire signals are to both reallocated ink dots and non reallocated ink dots. 30 WO 2005/120835 PCT/AU2004/000706 80 Optionally the printhead is a pagewidth printhead. Optional a printer including a printer controller for supplying dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead 5 module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at 10 least partially compensate for the rotational displacement; and supply the dot data to the printhead module. Optionally the printer further including a pagewidth printhead comprising a plurality of the printhead modules. 15 Optionally the printer controller is for implementing a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: (a) determining the rotational displacement; 20 (b) determining at least one correction factor that at least partially compensates for the ink dot displacement; and (c) using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. 25 Optionally the printer controller is for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 30 WO 2005/120835 PCT/AU2004/000706 81 Optionally the printer controller is for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; 5 (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 10 Optionally the printer controller is manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. 15 Optionally the printer controller for supplying data to a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 20 Optionally the printer controller is installed in a printer comprising: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input 25 of the printhead. Optionally the printer controller installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; 30 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead WO 2005/120835 PCT/AU2004/000706 82 module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. Optionally the printer controller installed in a printer comprising: 5 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead 10 module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. Optionally the printer controller installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel 15 to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead 20 module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. Optionally the printer controller supplies dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to 25 respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. Optionally the printer controller controls a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part 30 of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of WO 2005/120835 PCT/AU2004/000706 83 each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. Optionally the printer controller outputs to a printhead module: 5 dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 10 Optionally the printer controller supplies data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 15 Optionally the printer controller supplies data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of 20 the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. Optionally the printer controller supplies data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types 25 of the modules, wherein each type is determined by its geometric shape in plan. Optionally the printer controller supplies one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: 30 (a) a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b) a fire signal is provided to the next inward pair of nozzles in each set; WO 2005/120835 PCT/AU2004/000706 84 (c) in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. 5 Optionally the printer controller supplies one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, 10 nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printer controller supplies dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with 15 respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. 20 Optionally the printer controller supplies dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, 25 in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. Optionally the printer controller receives first data and manipulates the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. 30 Optionally the printer controller supplies data to a printhead module including: at least one row of print nozzles; WO 2005/120835 PCT/AU2004/000706 85 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 5 Optionally the printer controller supplies data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the 10 channels, wherein the first number is greater than the second number. Optionally the printer controller supplies data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 15 Optionally the printer controller supplies data to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle 20 position x is at or adjacent the centre of the set of nozzles. Optionally the printer controller supplies data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of 25 nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. 30 Optionally the printer controller supplies data to a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data.
WO 2005/120835 PCT/AU2004/000706 86 Optionally the printer controller supplies data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 5 Optionally the printer controller supplies data to a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously 10 with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. Optionally the printer controller supplies data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with 15 respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. 20 Optionally the printer controller supplies data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 25 Optionally the printer controller supplies data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. 30 Optionally the printer controller supplies data to a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and WO 2005/120835 PCT/AU2004/000706 87 second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 5 In an eleventh aspect the present invention provides printer controller for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. 10 Optionally the printer controller is configured to modify the operation of the nozzles at or adjacent the at least one thermal sensor, such that operation of nozzles not at or adjacent the at least one thermal sensor is not modified. Optionally each thermal sensor is associated with a predetermined group of the nozzles, the printer controller 15 being configured to modify operation of the nozzles in the predetermined group for which the temperature has risen above the first threshold. Optionally each thermal sensor is associated with a single nozzle. 20 Optionally the modification includes the printer controller preventing operation of the nozzle. Optionally the modification includes the printer controller preventing operation of the nozzle for a predetermined period. 25 Optionally the modification includes the printer controller preventing operation of the nozzle until the temperature drops below a second threshold. Optionally the second threshold is lower than the first threshold. 30 Optionally the second threshold is the same as the first threshold.
WO 2005/120835 PCT/AU2004/000706 88 Optionally the temperature is not determined explicitly by the at least one thermal sensor or the module. Optionally each of the nozzles including a thermal ink ejection mechanism. 5 Optionally the thermal sensor comprises at least part of one of the thermal inkjet mechanisms. Optionally the thermal sensor comprises a heating element. 10 Optionally the thermal sensor determines the temperature by determining a resistance of the heating element. Optionally the printer controller is configured to: receive thermal information from the at least one thermal sensor; determine the modification based on the thermal information; and 15 send control information back to the printhead module, the control information being indicative of the modification to make to the operation of the one or more nozzles. Optionally a print engine including a printer controller configured to: receive thermal information from the at least one thermal sensor; 20 determine the modification based on the thermal information; and send control information back to the printhead module, the control information being indicative of the modification to make to the operation of the one or more nozzles; and a printhead module, wherein the printhead module further includes a plurality of data latches, the data latches being configured to provide dot data to respective ones of the nozzles, at least some of the data 25 latches being configured to receive thermal signals from respective ones of the thermal sensors during an acquisition period. Optionally the data latches are configured to form a shift register, the shift register being configured to: shift the print data in during a print load phase; WO 2005/120835 PCT/AU2004/000706 89 sample the signals from the thermal sensors during a temperature load phase; and shift the thermal signals out to the printer controller during an output phase. Optionally the output phase coincides with a subsequent print load phase. 5 Optionally the print engine further includes logic circuitry configured to perform a bitwise operation on: each thermal signal as it is clocked out of the shift register; and each piece of dot data to be clocked into the shift register, such that when a thermal signal is indicative of a thermal problem with a nozzle, the logic circuitry prevents loading of data that would cause firing of that nozzle. 10 Optionally the logic circuitry includes an AND circuit that receives as inputs the dot data and the thermal signal corresponding to the nozzle for which the dot data is intended, an output of the AND circuit being in communication with an input of the shift register. 15 Optionally each thermal sensor is associated with a pair of the nozzles. Optionally the printer controller is for implementing a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps 20 of: (a) determining the rotational displacement; (b) determining at least one correction factor that at least partially compensates for the ink dot displacement; and (c) using the correction factor to alter the output of the ink dots to at least partially compensate for the 25 rotational displacement. Optionally the printer controller is for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a 30 fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
WO 2005/120835 PCT/AU2004/000706 90 Optionally the printer controller is for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: 5 (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 10 Optionally the printer controller is manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. 15 Optionally the printer controller supplies data to a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 20 Optionally the printer controller is installed in a printer comprising: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to 25 output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. Optionally the printer controller is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel 30 to each other and being disposed end to end on either side of a join region; WO 2005/120835 PCT/AU2004/000706 91 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 5 Optionally the printer controller is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; 10 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. 15 Optionally the printer controller is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to 20 output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. 25 Optionally the printer controller supplies dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one 30 printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module.
WO 2005/120835 PCT/AU2004/000706 92 Optionally the printer controller controls a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire 5 groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. 10 Optionally the printer controller outputs to a printhead module: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output 15 being configured to output at least some of the control data and at least some of the dot data for the at least two inks. Optionally the printer controller supplies data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion 20 including a component in a direction normal to that of a pagewidth to be printed. Optionally the printer controller supplies print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the 25 channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. 30 Optionally the printer controller supplies data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan.
WO 2005/120835 PCT/AU2004/000706 93 Optionally the printer controller supplies one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: 5 (a) a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b) a fire signal is provided to the next inward pair of nozzles in each set; (c) in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each 10 set have been fired, and then the central nozzle is fired. Optionally the printer controller supplies one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of 15 nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printer controller supplies dot data to a printhead module comprising at least first and second rows 20 configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller 25 being configurable to supply dot data to the printhead module for printing. Optionally the printer controller supplies dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or 30 color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
WO 2005/120835 PCT/AU2004/000706 94 Optionally the printer controller receives first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. Optionally the printer controller supplies data to a printhead module including: 5 at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 10 Optionally the printer controller supplies data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the 15 channels, wherein the first number is greater than the second number. Optionally the printer controller supplies data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 20 Optionally the printer controller supplies data to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), nozzle position x], wherein nozzle 25 position x is at or adjacent the centre of the set of nozzles. Optionally the printer controller supplies data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of 30 nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and WO 2005/120835 PCT/AU2004/000706 95 in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. Optionally the printer controller supplies data to a printhead module for receiving dot data to be printed using at 5 least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. Optionally the printer controller supplies data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion 10 including a component in a direction normal to that of a pagewidth to be printed. Optionally the printer controller supplies data to a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, 15 the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. Optionally the printer controller supplies data to a printhead module comprising at least first and second rows 20 configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. 25 Optionally the printer controller supplies data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved 30 with at least one of the other groups of the nozzles.
WO 2005/120835 PCT/AU2004/000706 96 Optionally the printer controller supplies data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. 5 Optionally the printer controller supplies data to a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print 10 media at or adjacent a position where the faulty nozzle would otherwise have printed it. Optionally the printer controller further includes a logic circuit accepting as inputs a masking signal and the thermal signal corresponding to the nozzle for which the dot data is intended, the logic circuit outputting the thermal signal to the input of the AND circuit in reliance on a value of the masking signal. 15 Optionally the value of the masking signal enables masking of the thermal signal for at least one nozzle position, including the nozzle for which the current dot data is intended. Optionally the value of the masking signal enables masking of the thermal signal for a plurality of nozzle positions corresponding to a region of the printhead associated the nozzle for which the current dot data is 20 intended. Optionally the value of the masking signal enables masking of the thermal signal for all of the nozzle positions of the printhead. 25 In a twelfth aspect the present invention provides a printer controller for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired 30 simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles.
WO 2005/120835 PCT/AU2004/000706 97 Optionally the one or more control signals include a fire control sequence indicative of a first fire group to be fired. 5 Optionally, the printhead being configured to shift the fire control sequence through a shift register to cause subsequent firing of the second and any other fire groups, wherein the printer controller is configured to provide the fire control sequence during an initiation phase of the printhead, such that the fire control sequence does not need to be repeatedly provided by the printer controller while printing is taking place. 10 Optionally, the printhead being configured to shift the fire control sequence through a shift register to cause subsequent firing of the second and any other fire groups, wherein the printer controller is configured to provide the fire control sequence periodically during printing. Optionally the printhead being configured to provide the fire control sequence on a per row or per print-line basis. 15 Optionally the printhead being configured to provide a fire enable signal in addition to the one or more fire control signals, such that the combination of the fire enable and fire control signals cause selected ones of the nozzles to fire in the predetermined sequence and in accordance with a predetermined timing. 20 In a further aspect the present invention provides a print engine including a printhead and a printer controller, the printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the 25 sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. 30 Optionally the one or more control signals include a fire control sequence indicative of a first fire group to be fired.
WO 2005/120835 PCT/AU2004/000706 98 Optionally the printhead being configured to shift the fire control sequence through a shift register to cause subsequent firing of the second and any other fire groups, wherein the printer controller is configured to provide the fire control sequence during an initiation phase of the printhead, such that the fire control sequence does not need to be repeatedly provided by the printer controller while printing is taking place. 5 Optionally, the printhead being configured to shift the fire control sequence through a shift register to cause subsequent firing of the second and any other fire groups, wherein the printer controller is configured to provide the fire control sequence periodically during printing. 10 Optionally the print engine being configured to provide the fire control sequence on a per row or per print-line basis. Optionally the print engine being configured to provide a fire enable signal in addition to the one or more fire control signals, such that the combination of the fire enable and fire control signals cause selected ones of the 15 nozzles to fire in the predetermined sequence and in accordance with a predetermined timing. Optionally the printer controller is for implementing a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps 20 of: (a) determining the rotational displacement; (b) determining at least one correction factor that at least partially compensates for the ink dot displacement; and (c) using the correction factor to alter the output of the ink dots to at least partially compensate for the 25 rotational displacement. Optionally the printer controller is for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a 30 fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
WO 2005/120835 PCT/AU2004/000706 99 Optionally the printer controller is for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; 5 (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 10 Optionally the printer controller is manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. 15 Optionally the printer controller supplies data to a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 20 Optionally the printer controller is installed in a printer comprising: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input 25 of the printhead. Optionally the printer controller is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; 30 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead WO 2005/120835 PCT/AU2004/000706 100 module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. Optionally the printer controller is installed in a printer comprising: 5 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead 10 module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. Optionally the printer controller is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel 15 to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead 20 module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. Optionally the printer controller supplies dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due 25 to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and 30 supply the dot data to the printhead module.
WO 2005/120835 PCT/AU2004/000706 101 Optionally the printer controller supplies dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. 5 Optionally the printer controller outputs to a printhead module: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being 10 configured to output at least some of the control data and at least some of the dot data for the at least two inks. Optionally the printer controller supplies data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 15 Optionally the printer controller supplies print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and 20 a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. Optionally the printer controller supplies data to a printhead comprising a plurality of printhead modules, the 25 printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. Optionally the printer controller supplies one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being 30 configured to expel ink in response to a fire signal, such that: (a) a fire signal is provided to nozzles at a first and nth position in each set of nozzles; WO 2005/120835 PCT/AU2004/000706 102 (b) a fire signal is provided to the next inward pair of nozzles in each set; (c) in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each 5 set have been fired, and then the central nozzle is fired. Optionally the printer controller supplies one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of 10 nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printer controller supplies dot data to a printhead module comprising at least first and second rows 15 configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller 20 being configurable to supply dot data to the printhead module for printing. Optionally the printer controller supplies dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or 25 color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. Optionally the printer controller receives first data and manipulating the first data to produce dot data to be 30 printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. Optionally the printer controller supplies data to a printhead module including: WO 2005/120835 PCT/AU2004/000706 103 at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 5 Optionally the printer controller supplies data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and 10 a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. Optionally the printer controller supplies data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types 15 of the modules, wherein each type is determined by its geometric shape in plan. Optionally the printer controller supplies data to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle 20 position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printer controller supplies data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response 25 to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. 30 WO 2005/120835 PCT/AU2004/000706 104 Optionally the printer controller supplies data to a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. 5 Optionally the printer controller supplies data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. Optionally the printer controller supplies data to a printhead module having a plurality of rows of nozzles 10 configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. 15 Optionally the printer controller supplies data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are 20 fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. Optionally the printer controller supplies data to a printhead module that includes: at least one row of print nozzles; 25 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. Optionally the printer controller supplies data to a printhead module having a plurality of nozzles for expelling 30 ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold.
WO 2005/120835 PCT/AU2004/000706 105 Optionally the printer controller supplies data to a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a 5 nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. Optionally the printhead module includes a plurality of pairs of the rows, each pair of rows including an odd row and an even row, the odd and even rows in each pair being offset from each other in both x and y directions 10 relative to an intended direction of print media movement relative to the printhead, the printer controller being configured to control the at least one printhead module to cause firing of at least a plurality of the odd rows prior to firing any of the even rows, or vice versa. Optionally all the odd rows are fired before any of the even rows are fired, or vice versa. 15 Optionally the printer controller configurable to control the printhead module such that the odd rows, or the even rows, or both, are fired in a predetermined order. Optionally the printer controller configurable such that the predetermined order is selectable from a plurality of 20 predetermined available orders. Optionally the predetermined order is sequential. Optionally the printer controller configurable such that the predetermined order can commence at any of a 25 plurality of the rows. In a thirteenth aspect the present invention provides a printer controller for outputting to a printhead module: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; 30 the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks.
WO 2005/120835 PCT/AU2004/000706 106 Optionally the communication output is configured to output the dot data and control data serially. Optionally the printer controller further includes a plurality of the communication outputs. 5 Optionally the printer controller further includes a plurality of the communication outputs. Optionally a print engine comprising a print controller and a plurality of printhead modules, the printhead modules being disposed end to end for printing a width exceeding that of any of the individual printhead modules, 10 the communications input of each of the printhead modules being connected to a common dot data and control data bus, the common dot data and control data bus being in functional communication with the communication output. Optionally each module is configured to respond to dot data and control data on the bus only when it is intended 15 for that module. Optionally a printer incorporating a print engine comprising a print controller and a plurality of printhead modules, the printhead modules being disposed end to end for printing a width exceeding that of any of the individual printhead modules, the communications input of each of the printhead modules being connected to a 20 common dot data and control data bus, the common dot data and control data bus being in functional communication with the communication output. Optionally a printer incorporating a print controller for outputting to a printhead module: dot data to be printed with at least two different inks; and 25 control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. Optionally the printhead modules together form a pagewidth printhead. 30 WO 2005/120835 PCT/AU2004/000706 107 Optionally the printer further including a pagewidth printhead comprising a plurality of the printhead modules. Optionally the printer controller is for implementing a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead 5 module relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: (a) determining the rotational displacement; (b) determining at least one correction factor that at least partially compensates for the ink dot displacement; and 10 (c) using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. Optionally the printer controller is for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being 15 configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), ... , nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printer controller is for implementing a method of expelling ink from a printhead module including 20 at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and 25 (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. Optionally the printer controller is manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth 30 printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed.
WO 2005/120835 PCT/AU2004/000706 108 Optionally the printer controller supplies data to a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, 5 wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. Optionally the printer controller is installed in a printer comprising: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and 10 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. Optionally the printer controller is installed in a printer comprising: 15 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the 20 printhead modules are configured such that no dot data passes between them. Optionally the printer controller is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is 25 longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. 30 Optionally the printer controller is installed in a printer comprising: WO 2005/120835 PCT/AU2004/000706 109 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to 5 output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. 10 Optionally the printer controller supplies dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead 15 modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. Optionally the printer controller supplies dot data to a printhead module having a plurality of nozzles for expelling 20 ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. Optionally the printer controller controls a printhead comprising at least one monolithic printhead module, the at 25 least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of 30 each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles.
WO 2005/120835 PCT/AU2004/000706 110 Optionally the printer controller supplies data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 5 Optionally the printer controller supplies print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the 10 channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. Optionally the printer controller supplies data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types 15 of the modules, wherein each type is determined by its geometric shape in plan. Optionally the printer controller supplies one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: 20 (a) a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b) a fire signal is provided to the next inward pair of nozzles in each set; (c) in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each 25 set have been fired, and then the central nozzle is fired. Optionally the printer controller supplies one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of 30 nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
WO 2005/120835 PCT/AU2004/000706 111 Optionally the printer controller supplies dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the 5 printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. 10 Optionally the printer controller supplies dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a 15 position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. Optionally the printer controller receives first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. 20 Optionally the printer controller supplies data to a printhead module including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 25 Optionally the printer controller supplies data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and 30 a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number.
WO 2005/120835 PCT/AU2004/000706 112 Optionally the printer controller supplies data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 5 Optionally the printer controller supplies data to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 10 Optionally the printer controller supplies data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: 15 in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and.then to fire the central nozzle. Optionally the printer controller supplies data to a printhead module for receiving dot data to be printed using at 20 least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. Optionally the printer controller supplies data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion 25 including a component in a direction normal to that of a pagewidth to be printed. Optionally the printer controller supplies data to a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, 30 the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row.
WO 2005/120835 PCT/AU2004/000706 113 Optionally the printer controller supplies data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the 5 printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. Optionally the printer controller provides data to a printhead module that includes: 10 at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 15 Optionally the printer controller supplies data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. 20 Optionally the printer controller supplies data to a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 25 In a fourteenth aspect the present invention provides a printer controller for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed, 30 the printer controller being configured to control order and timing of the data supplied to the printhead such that the dropped row is compensated for during printing by the printhead module.
WO 2005/120835 PCT/AU2004/000706 114 Optionally the displaced row portion is disposed adjacent one end of the printhead module. Optionally the printhead module includes a plurality of the rows, wherein each of at least a plurality of the rows includes one of the displaced row portions. 5 Optionally the displaced row portions of at least some of the rows are different in length than the displaced row portions of at least some of the other rows. Optionally each of the rows has a displaced row portion, and the sizes of the respective displaced row portions 10 increase from row to row in the direction normal to that of the pagewidth to be printed. Optionally the printer controller supplies the data to a printhead comprising a plurality of the printhead modules. Optionally the printer controller supplies data to a printhead comprising a plurality of the printhead modules, 15 wherein the displaced row portion of at least one of the printhead modules is disposed adjacent another of the printhead modules. Optionally the printhead modules are the same shape and configuration as each other, and are arranged end to end across the intended print width. 20 Optionally, the printhead being a pagewidth printhead. Optionally, the printhead being a pagewidth printhead. 25 Optionally the printer controller is for implementing a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: (a) determining the rotational displacement; WO 2005/120835 PCT/AU2004/000706 115 (b) determining at least one correction factor that at least partially compensates for the ink dot displacement; and (c) using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. 5 Optionally the printer controller is for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle 10 position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printer controller is for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: 15 (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; J (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 20 Optionally the printer controller is manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. 25 Optionally the printer controller supplies data to a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 30 Optionally the printer controller is installed in a printer comprising: WO 2005/120835 PCT/AU2004/000706 116 a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input 5 of the printhead. Optionally the printer controller is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; 10 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 15 Optionally the printer controller is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to 20 output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. Optionally the printer controller is installed in a printer comprising: 25 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead 30 module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller.
WO 2005/120835 PCT/AU2004/000706 117 Optionally the printer controller supplies dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: 5 access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. 10 Optionally the printer controller supplies dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. 15 Optionally the printer controller controls a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, 20 such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. 25 Optionally the printer controller outputs to a printhead module: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 30 Optionally the printer controller supplies print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: WO 2005/120835 PCT/AU2004/000706 118 a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; 5 wherein the printer controller is selectively configurable to supply dot data for the first and second modes. Optionally the printer controller supplies data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 10 Optionally the printer controller supplies one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a) a fire signal is provided to nozzles at a first and nth position in each set of nozzles; 15 (b) a fire signal is provided to the next inward pair of nozzles in each set; (c) in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. 20 Optionally the printer controller supplies one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, 25 nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printer controller supplies dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with 30 respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least WO 2005/120835 PCT/AU2004/000706 119 some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. Optionally the printer controller supplies dot data to at least one printhead module, the at least one printhead 5 module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 10 Optionally the printer controller receives first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. Optionally the printer controller supplies data to a printhead module including: 15 at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 20 Optionally the printer controller supplies data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, 25 wherein the first number is greater than the second number. Optionally the printer controller supplies data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 30 WO 2005/120835 PCT/AU2004/000706 120 Optionally the printer controller supplies data to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle 5 position x is at or adjacent the centre of the set of nozzles. Optionally the printer controller supplies data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of 10 nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. 15 Optionally the printer controller supplies data to a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. Optionally the printer controller supplies data to a printhead module including at least one row of printhead 20 nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. Optionally the printer controller supplies data to a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped 25 into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. 30 Optionally the printer controller supplies data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are WO 2005/120835 PCT/AU2004/000706 121 fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. Optionally the printer controller supplies data to a printhead module that includes: 5 at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 10 Optionally the printer controller supplies data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. 15 Optionally the printer controller supplies data to a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 20 In a fifteenth aspect the present invention provides printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: 25 a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. 30 Optionally the first number is n.
WO 2005/120835 PCT/AU2004/000706 122 Optionally the first number is less than n. Optionally the printhead module is configurable into at least one other mode, in which the at least one printhead 5 module is configured to receive print data for a third number of print channels other than the first and second numbers, the printer controller being selectively configurable to supply the print data for the third number of print channels. Optionally n is 4 and the second number is less than 4. 10 Optionally n is 5 and the second number is less than 5. Optionally n is 6 and the second number is less than 6. 15 Optionally the second number is 3, 4 or 5. Optionally the print engine includes the print controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: 20 a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes; 25 and the at least one printhead module. Optionally the mode is selected based on the contents of a memory associated with the at least one printhead module. 30 Optionally the memory is a register.
WO 2005/120835 PCT/AU2004/000706 123 Optionally the register is on an integrated circuit forming part of the print engine. Optionally the printer includes a printer controller for supplying print data to at least one printhead module 5 capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the 10 channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. Optionally the printer includes a print engine including the print controller for supplying print data to at least one 15 printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the 20 channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes; and the at least one printhead module. Optionally the printer includes a printer controller for supplying print data to at least one printhead module 25 capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the 30 channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes; and WO 2005/120835 PCT/AU2004/000706 124 including a pagewidth printhead comprising a plurality of the printhead modules capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and 5 a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. Optionally the printer controller for implementing a method of at least partially compensating for errors in ink dot 10 placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: (a) determining the rotational displacement; (b) determining at least one correction factor that at least partially compensates for the ink dot displacement; and 15 (c) using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. Optionally the printer controller for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being 20 configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printer controller for implementing a method of expelling ink from a printhead module including at 25 least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and 30 (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle.
WO 2005/120835 PCT/AU2004/000706 125 Optionally the printer controller manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer 5 substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. Optionally the printer controller supplies data to a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, 10 wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. Optionally the printer controller installed in a printer comprising: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and 15 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. Optionally the printer controller installed in a printer comprising: 20 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the 25 printhead modules are configured such that no dot data passes between them. Optionally a printer controller installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is 30 longer than the second printhead module; WO 2005/120835 PCT/AU2004/000706 126 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. 5 Optionally the printer controller installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; 10 at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. 15 Optionally the printer controller supplies dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; 20 determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. 25 Optionally the printer controller supplies dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. 30 Optionally the printer controller controls a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire WO 2005/120835 PCT/AU2004/000706 127 groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to 5 provide one or more control signals that control the order of firing of the nozzles. Optionally the printer controller outputs to a printhead module: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; 10 the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. Optionally the printer controller supplies data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion 15 including a component in a direction normal to that of a pagewidth to be printed. Optionally the printer controller supplies data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 20 Optionally the printer controllers supplies one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a) a fire signal is provided to nozzles at a first and nth position in each set of nozzles; 25 (b) a fire signal is provided to the next inward pair of nozzles in each set; (c) in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. 30 WO 2005/120835 PCT/AU2004/000706 128 Optionally the printer controller supplies one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, 5 nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printer controller supplies dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with 10 respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. 15 Optionally the printer controller supplies dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, 20 in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. Optionally the printer controller receives first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. 25 Optionally the printer controller supplies data to a printhead module including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at 30 least one of the other groups of the nozzles. Optionally the printer controller supplies data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: WO 2005/120835 PCT/AU2004/000706 129 a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. 5 Optionally the printer controller supplies data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 10 Optionally the printer controller supplies data to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 15 Optionally the printer controller supplies data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: 20 in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. Optionally the printer controller supplies data to a printhead module for receiving dot data to be printed using at 25 least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. Optionally the printer controller supplies data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion 30 including a component in a direction normal to that of a pagewidth to be printed.
WO 2005/120835 PCT/AU2004/000706 130 Optionally the printer controller supplies data to a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously 5 with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. Optionally the printer controller supplies data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with 10 respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. 15 Optionally the printer controller supplies data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 20 Optionally the printer controller supplies data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. 25 Optionally the printer controller supplies data to a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print 30 media at or adjacent a position where the faulty nozzle would otherwise have printed it. In a sixteenth aspect the present invention provides a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the WO 2005/120835 PCT/AU2004/000706 131 modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. Optionally the printhead comprises a plurality of at least one of the types of module. 5 Optionally the printhead comprises a plurality of each of at least two of the types of module. Optionally the printhead comprises two types of the module. 10 Optionally the two types of module alternate across a print width of the printhead. Optionally, each of the modules including at least one row of print nozzles, wherein each of the at least one row of print nozzles includes at least a portion that extends at an acute angle to an intended relative direction of movement between the printhead and print media. 15 Optionally the different types of modules are configured, and arranged relative to each other, such that there is substantially no growth in offset of each of the at least one row of print nozzles in a direction across an intended print width of the printhead. 20 Optionally each of the printhead modules is a monolithic integrated circuit. Optionally, each of the modules including at least one row of print nozzles, wherein each of the at least one rows includes at least two sub-rows, each of the sub-rows being parallel to each other and displaced relative to each other in a direction of intended movement of print media relative to the printhead. 25 Optionally at least one row in each of the printhead modules prints an ink corresponding to at least one row on an adjacent printhead module, wherein the corresponding rows of at least two of the different printhead modules are offset from each other in a direction of intended movement of print media relative to the printhead, 30 Optionally the printhead being a pagewidth printhead.
WO 2005/120835 PCT/AU2004/000706 132 Optionally the printhead being a pagewidth printhead. Optionally, the printhead being a pagewidth printhead. 5 Optionally the printer controller is for implementing a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: 10 (a) determining the rotational displacement; (b) determining at least one correction factor that at least partially compensates for the ink dot displacement; and (c) using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. 15 Optionally the printer controller is for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle 20 position (n-1), ... , nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printer controller is for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: 25 (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 30 WO 2005/120835 PCT/AU2004/000706 133 Optionally the printer controller is manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. 5 Optionally the printer controller supplies data to a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 10 Optionally the printer controller is installed in a printer comprising: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to 15 output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. Optionally the printer controller is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel 20 to each other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 25 Optionally the printer controller is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; 30 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead WO 2005/120835 PCT/AU2004/000706 134 module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. Optionally the printer controller is installed in a printer comprising: 5 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead 10 module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. Optionally the printer controller supplies dot data to at least one printhead module and at least partially 15 compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least 20 partially compensate for the rotational displacement; and supply the dot data to the printhead module. Optionally the printer controller supplies dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to 25 respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. Optionally the printer controller controls a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part 30 of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding WO 2005/120835 PCT/AU2004/000706 135 nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. 5 Optionally the printer controller outputs to a printhead module: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 10 Optionally the printer controller supplies data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 15 Optionally the printer controller supplies print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the 20 channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. Optionally the printer controller supplies one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles-being 25 configured to expel ink in response to a fire signal, such that: (a) a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b) a fire signal is provided to the next inward pair of nozzles in each set; (c) in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and 30 (d) in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired.
WO 2005/120835 PCT/AU2004/000706 136 Optionally the printer controller supplies one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of 5 nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printer controller supplies dot data to a printhead module comprising at least first and second rows 10 configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller 15 being configurable to supply dot data to the printhead module for printing. Optionally the printer controller supplies dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or 20 color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. Optionally the printer controller receives first data and manipulating the first data to produce dot data to be 25 printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. Optionally the printer controller supplies data to a printhead module including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift 30 register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
WO 2005/120835 PCT/AU2004/000706 137 Optionally the printer controller supplies data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and 5 a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. Optionally the printer controller supplies data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types 10 of the modules, wherein each type is determined by its geometric shape in plan. Optionally the printer controller supplies data to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle 15 position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printer controller supplies data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response 20 to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. 25 Optionally the printer controller supplies data to a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. 30 Optionally the printer controller supplies data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
WO 2005/120835 PCT/AU2004/000706 138 Optionally the printer controller supplies data to a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, 5 the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. Optionally the printer controller supplies data to a printhead module comprising at least first and second rows 10 configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. 15 Optionally the printer controller supplies data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at 20 least one of the other groups of the nozzles. Optionally the printer controller supplies data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to 25 modify operation of the nozzles in response to the temperature rising above a first threshold. Optionally the printer controller supplies data to a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a 30 nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
WO 2005/120835 PCT/AU2004/000706 139 In a seventeenth aspect the present invention provides printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a) a fire signal is provided to nozzles at a first and nth position in each set of nozzles; 5 (b) a fire signal is provided to the next inward pair of nozzles in each set; (c) in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. 10 Optionally the printhead module includes a plurality of the rows of nozzles, the printer controller being configured to control the printhead module such that steps (a) to (d) are repeated for each of the rows of nozzles. Optionally the rows are disposed in pairs. 15 Optionally the rows in each pair of rows are offset relative to each other. Optionally each pair of rows is configured to print the same color ink. 20 Optionally each pair of rows is connected to a common ink source. Optionally the sets of nozzles are adjacent each other. Optionally the sets of nozzles are separated by an intermediate nozzle, the intermediate nozzle being fired either 25 prior to the nozzle at position 1 in each set, or following the nozzle at position n. Optionally the printhead module is one of a plurality of printhead modules that form a pagewidth printhead, the printer controller being configure to supply the control signals to at least a plurality of the printhead modules.
WO 2005/120835 PCT/AU2004/000706 140 Optionally the printer controller is for implementing a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: 5 (a) determining the rotational displacement; (b) determining at least one correction factor that at least partially compensates for the ink dot displacement; and (c) using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. 10 Optionally the printer controller is for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle 15 position (n-1), ... , nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printer controller is for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: 20 (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 25 Optionally the printer controller is manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. 30 Optionally the printer controller supplies data to a printhead module including: WO 2005/120835 PCT/AU2004/000706 141 at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 5 Optionally the printer controller is installed in a printer comprising: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input 10 of the printhead. Optionally the printer controller is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; 15 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 20 Optionally the printer controller is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to 25 output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. Optionally the printer controller is installed in a printer comprising: WO 2005/120835 PCT/AU2004/000706 142 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to 5 output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. 10 Optionally the printer controller supplies dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead 15 modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. Optionally the printer controller supplies dot data to a printhead module having a plurality of nozzles for expelling 20 ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. Optionally the printer controller controls a printhead comprising at least one monolithic printhead module, the at 25 least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of 30 each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. Optionally the printer controller outputs to a printhead module: WO 2005/120835 PCT/AU2004/000706 143 dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 5 Optionally the printer controller supplies data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 10 Optionally the printer controller supplies print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the 15 channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. Optionally the printer controller supplies data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types 20 of the modules, wherein each type is determined by its geometric shape in plan. Optionally the printer controller supplies one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of 25 nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printer controller supplies dot data to a printhead module comprising at least first and second rows 30 configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are WO 2005/120835 PCT/AU2004/000706 144 fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. 5 Optionally the printer controller supplies dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a 10 position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. Optionally the printer controller receives first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. 15 Optionally the printer controller supplies data to a printhead module including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 20 Optionally the printer controller supplies data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and 25 a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. Optionally the printer controller supplies data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types 30 of the modules, wherein each type is determined by its geometric shape in plan.
WO 2005/120835 PCT/AU2004/000706 145 Optionally the printer controller supplies data to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle 5 position x is at or adjacent the centre of the set of nozzles. Optionally the printer controller supplies data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of 10 nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. 15 Optionally the printer controller supplies data to a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. Optionally the printer controller supplies data to a printhead module including at least one row of printhead 20 nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. Optionally the printer controller supplies data to a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped 25 into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. 30 Optionally the printer controller supplies data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are WO 2005/120835 PCT/AU2004/000706 146 fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. Optionally the printer controller supplies data to a printhead module that includes: 5 at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 10 Optionally the printer controller supplies data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. 15 Optionally the printer controller supplies data to a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 20 Optionally the printhead module includes a plurality of the rows, the printer controller being configured to cause firing of each nozzle in each row simultaneously with the nozzle or nozzles at the same position in the other rows. Optionally the printer controller includes a plurality of pairs of the rows, each pair of rows including an odd row 25 and an even row, the odd and even rows in each pair being offset from each other in both x and y directions relative to an intended direction of print media movement relative to the printhead, the printer controller being configured to control the at least one printhead module to cause firing of at least a plurality of the odd rows prior to firing any of the even rows, or vice versa. 30 Optionally all the odd rows are fired before any of the even rows are fired, or vice versa.
WO 2005/120835 PCT/AU2004/000706 147 Optionally the printer controller is configured to control the printhead such that the odd rows, or the even rows, or both, are fired in a predetermined order. Optionally the printer controller is configurable such that the predetermined order is selectable from a plurality of 5 predetermined available orders. Optionally the predetermined order is sequential. Optionally the printer controller is configurable such that the predetermined order can commence at any of a 10 plurality of the rows. In an eighteenth aspect the present invention provides printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method 15 comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printer controller is configured to cause the nozzle at each given position within the set to be fired 20 simultaneously with the nozzles in the other sets at respective corresponding positions. Optionally the printhead module includes a plurality of the rows of nozzles, the printer controller being configured to control the printhead module such that the steps are repeated for each of the rows of nozzles. 25 Optionally the rows are disposed in pairs. Optionally the rows in each pair of rows are offset relative to each other. Optionally each pair of rows is configured to print the same color ink. 30 WO 2005/120835 PCT/AU2004/000706 148 Optionally each pair of rows is connected to a common ink source. Optionally the sets of nozzles are adjacent each other. 5 Optionally the sets of nozzles are separated by an intermediate nozzle, the intermediate nozzle being fired either prior to the nozzle at position 1 in each set, or following the nozzle at position n. Optionally the printhead module is one of a plurality of printhead modules that form a pagewidth printhead, the printer controller being configure to supply the control signals to at least a plurality of the printhead modules. 10 Optionally the printer controller is for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; 15 (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 20 Optionally the printer controller is manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. 25 Optionally the printer controller supplies data to a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 30 Optionally the printer controller is installed in a printer comprising: WO 2005/120835 PCT/AU2004/000706 149 a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input 5 of the printhead. Optionally the printer controller is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; 10 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 15 Optionally the printer controller is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to 20 output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. Optionally the printer controller is installed in a printer comprising: 25 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead 30 module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller.
WO 2005/120835 PCT/AU2004/000706 150 Optionally the printer controller supplies dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: 5 access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. 10 Optionally the printer controller supplies dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. 15 Optionally the printer controller controls a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, 20 such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. 25 Optionally the printer controller outputs to a printhead module: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 30 WO 2005/120835 PCT/AU2004/000706 151 Optionally the printer controller supplies data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 5 Optionally the printer controller supplies print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the 10 channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. Optionally the printer controller supplies data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types 15 of the modules, wherein each type is determined by its geometric shape in plan. Optionally the printer controller supplies one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of 20 nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printer controller supplies dot data to a printhead module comprising at least first and second rows 25 configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller 30 being configurable to supply dot data to the printhead module for printing.
WO 2005/120835 PCT/AU2004/000706 152 Optionally the printer controller supplies dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, 5 in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. Optionally the printer controller receives first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. 10 Optionally the printer controller supplies data to a printhead module including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at 15 least one of the other groups of the nozzles. Optionally the printer controller supplies data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; 20 and a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. Optionally the printer controller supplies data to a printhead comprising a plurality of printhead modules, the 25 printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. Optionally the printer controller supplies data to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire 30 signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
WO 2005/120835 PCT/AU2004/000706 153 Optionally the printer controller supplies data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of 5 nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. 10 Optionally the printer controller supplies data to a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. Optionally the printer controller supplies data to a printhead module including at least one row of printhead 15 nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. Optionally the printer controller supplies data to a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped 20 into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. 25 Optionally the printer controller supplies data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least 30 some other dots output to print media are printed to by nozzles from the second pair of rows. Optionally the printer controller supplies data to a printhead module that includes: WO 2005/120835 PCT/AU2004/000706 154 at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 5 Optionally the printer controller supplies data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. 10 Optionally the printer controller supplies data to a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print 15 media at or adjacent a position where the faulty nozzle would otherwise have printed it. Optionally the printhead module includes a plurality of the rows, the printer controller being configured to cause firing of each nozzle in each row simultaneously with the nozzle or nozzles at the same position in the other rows. 20 Optionally the printer controller includes a plurality of pairs of the rows, each pair of rows including an odd row and an even row, the odd and even rows in each pair being offset from each other in both x and y directions relative to an intended direction of print media movement relative to the printhead, the printer controller being configured to control the at least one printhead module to cause firing of at least a plurality of the odd rows prior to firing any of the even rows, or vice versa. 25 Optionally all the odd rows are fired before any of the even rows are fired, or vice versa. Optionally the printer controller is configured to control the printhead such that the odd rows, or the even rows, or both, are fired in a predetermined order. 30 Optionally the printer controller is configurable such that the predetermined order is selectable from a plurality of predetermined available orders.
WO 2005/120835 PCT/AU2004/000706 155 Optionally the predetermined order is sequential. Optionally the printer controller is configurable such that the predetermined order can commence at any of a 5 plurality of the rows. In a nineteenth aspect the present invention provides a printer controller for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of 10 intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. 15 Optionally print engine comprising a printer controller for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second 20 pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing; and a printhead module, wherein the printhead module is controllable such that either of the nozzles in each aligned pair of nozzles in the first and second rows can be selected to output ink for a selected dot to be printed on the 25 print media. Optionally in the event a nozzle in the first row is faulty, the corresponding nozzle in the second row is selected to output ink for a dot for which the faulty nozzle would otherwise have output ink. 30 Optionally the print engine includes a plurality of sets of the first and second rows. Optionally each of the sets of the first and second rows is configured to print in a single color or ink type.
WO 2005/120835 PCT/AU2004/000706 156 Optionally the first and second rows in at least one of the sets are separated by one or more rows from the other set or sets. 5 Optionally each of the rows includes an odd sub-row and an even sub-row, the odd and even sub-rows being offset with respect to each other in a direction of intended print media travel relative to the printhead. Optionally the odd and even sub-rows are transversely offset relative to each other. 10 Optionally the print engine is configured such that the first and second rows are fired alternately. Optionally the print engine comprises a plurality of the printhead modules. Optionally a printer including a printer controller for supplying dot data to a printhead module comprising at least 15 first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller 20 being configurable to supply dot data to the printhead module for printing. Optionally a printer including a print engine comprising a printer controller for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of 25 intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing; and 30 a printhead module, wherein the printhead module is controllable such that either of the nozzles in each aligned pair of nozzles in the first and second rows can be selected to output ink for a selected dot to be printed on the print media.
WO 2005/120835 PCT/AU2004/000706 157 Optionally the printer controller is for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: 5 (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 10 Optionally the printer controller is manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. 15 Optionally the printer controller supplies data to a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 20 Optionally the printer controller is installed in a printer comprising: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to 25 output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. Optionally the printer controller is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel 30 to each other and being disposed end to end on either side of a join region; WO 2005/120835 PCT/AU2004/000706 158 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 5 Optionally the printer controller is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; 10 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. 15 Optionally the printer controller is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to 20 output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. 25 Optionally the printer controller supplies dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead 30 modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module.
WO 2005/120835 PCT/AU2004/000706 159 Optionally the printer controller supplies dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to 5 modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. Optionally the printer controller controls a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire 10 groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. 15 Optionally the printer controller outputs to a printhead module: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being 20 configured to output at least some of the control data and at least some of the dot data for the at least two inks. Optionally the printer controller supplies data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 25 Optionally the printer controller supplies print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and 30 a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes.
WO 2005/120835 PCT/AU2004/000706 160 Optionally the printer controller supplies data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 5 Optionally the printer controller supplies one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, 10 nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printer controller supplies dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with 15 respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. 20 Optionally the printer controller supplies dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, 25 in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. Optionally the printer controller receives first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. 30 Optionally the printer controller supplies data to a printhead module including: at least one row of print nozzles; WO 2005/120835 PCT/AU2004/000706 161 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 5 Optionally the printer controller supplies data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, 10 wherein the first number is greater than the second number. Optionally the printer controller supplies data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 15 Optionally the printer controller supplies data to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle 20 position x is at or adjacent the centre of the set of nozzles. Optionally the printer controller supplies data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of 25 nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. 30 Optionally the printer controller supplies data to a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data.
WO 2005/120835 PCT/AU2004/000706 162 Optionally the printer controller supplies data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 5 Optionally the printer controller supplies data to a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously 10 with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. Optionally the printer controller supplies data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with 15 respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. 20 Optionally the printer controller supplies data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 25 Optionally the printer controller supplies data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. 30 Optionally the printer controller supplies data to a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and WO 2005/120835 PCT/AU2004/000706 163 second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 5 In a twentieth aspect the present invention provides a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle 10 in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. Optionally a print engine comprising a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of 15 nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it; and 20 the at least one printhead module, wherein each nozzle in the first row is paired with a nozzle in the second row, such that each pair of nozzles is aligned in an intended direction of print media travel relative to the printhead module. Optionally the print engine includes a plurality of sets of the first and second rows. 25 Optionally each of the sets of the first and second rows is configured to print in a single color or ink type. Optionally each of the rows includes an odd and an even sub-row, the odd and even sub-rows being offset with respect to each other in a direction of print media travel relative to the printhead in use. 30 Optionally the odd and even sub-rows are transversely offset with respect to each other.
WO 2005/120835 PCT/AU2004/000706 164 Optionally a printer including at least one printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one 5 printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. Optionally a printer includes at least one print engine comprising a printer controller for supplying dot data to at 10 least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty 15 nozzle would otherwise have printed it; and the at least one printhead module, wherein each nozzle in the first row is paired with a nozzle in the second row, such that each pair of nozzles is aligned in an intended direction of print media travel relative to the printhead module. 20 Optionally the printer controller is for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b) providing a fire signal to the next inward pair of nozzles in each set; 25 (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. Optionally the printer controller is manufactured in accordance with a method of manufacturing a plurality of 30 printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed.
WO 2005/120835 PCT/AU2004/000706 165 Optionally the printer controller supplies data to a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 5 Optionally the printer controller is installed in a printer comprising: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to 10 output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. Optionally the printer controller is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel 15 to each other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 20 Optionally the printer controller is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; 25 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. 30 Optionally the printer controller is installed in a printer comprising: WO 2005/120835 PCT/AU2004/000706 166 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to 5 output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. 10 Optionally the printer controller supplies dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead 15 modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. Optionally the printer controller supplies dot data to a printhead module having a plurality of nozzles for expelling 20 ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. Optionally the printer controller controls a printhead comprising at least one monolithic printhead module, the at 25 least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of 30 each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. Optionally the printer controller outputs to a printhead module: WO 2005/120835 PCT/AU2004/000706 167 dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 5 Optionally the printer controller supplies data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. .10 Optionally the printer controller supplies print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the 15 channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. Optionally the printer controller supplies data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types 20 of the modules, wherein each type is determined by its geometric shape in plan. Optionally the printer controller supplies one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of 25 nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printer controller supplies dot data to a printhead module comprising at least first and second rows 30 configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are WO 2005/120835 PCT/AU2004/000706 168 fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. 5 Optionally the printer controller supplies dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a 10 position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. Optionally the printer controller receives first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. 15 Optionally the printer controller supplies data to a printhead module including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 20 Optionally the printer controller supplies data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and 25 a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. Optionally the printer controller supplies data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types 30 of the modules, wherein each type is determined by its geometric shape in plan.
WO 2005/120835 PCT/AU2004/000706 169 Optionally the printer controller supplies data to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle 5 position x is at or adjacent the centre of the set of nozzles. Optionally the printer controller supplies data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of 10 nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. 15 Optionally the printer controller supplies data to a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. Optionally the printer controller supplies data to a printhead module including at least one row of printhead 20 nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. Optionally the printer controller supplies data to a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped 25 into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. 30 Optionally the printer controller supplies data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are WO 2005/120835 PCT/AU2004/000706 170 fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. Optionally the printer controller supplies data to a printhead module that includes: 5 at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 10 Optionally the printer controller supplies data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. 15 Optionally the printer controller supplies data to a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 20 In a twenty first aspect the present invention provides a printer controller for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead, wherein each of the serial outputs is configured to supply dot data for at least two channels of the at least one printhead. 25 Optionally the at least two channels include at least two color channels. Optionally the at least two channels include at least one fixative channel. 30 Optionally the at least two channels include at least one infrared ink channel.
WO 2005/120835 PCT/AU2004/000706 171 Optionally the first data includes one or more instructions associated with production of the dot data from the first data, the print controller including processing means for producing the dot data from the first data on the basis of the one or more instructions. 5 Optionally the printhead is a pagewidth printhead. Optionally the printer controller is for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: 10 (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 15 Optionally the printer controller is manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. 20 Optionally the printer controller supplies data to a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 25 Optionally the printer controller is installed in a printer comprising: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to 30 output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead.
WO 2005/120835 PCT/AU2004/000706 172 Optionally the printer controller is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; 5 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 10 Optionally the printer controller is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to 15 output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. Optionally the printer controller is installed in a printer comprising: 20 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead 25 module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. Optionally the printer controller supplies dot data to at least one printhead module and at least partially 30 compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; WO 2005/120835 PCT/AU2004/000706 173 determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. 5 Optionally the printer controller supplies dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. 10 Optionally the printer controller controls a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, 15 such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. 20 Optionally the printer controller outputs to a printhead module: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 25 Optionally the printer controller supplies data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 30 Optionally the printer controller supplies print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: WO 2005/120835 PCT/AU2004/000706 174 a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; 5 wherein the printer controller is selectively configurable to supply dot data for the first and second modes. Optionally the printer controller supplies data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 10 Optionally the printer controller supplies one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, 15 nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printer controller supplies dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with 20 respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. 25 Optionally the printer controller supplies dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, 30 in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
WO 2005/120835 PCT/AU2004/000706 175 Optionally the printer controller receives first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. Optionally the printer controller supplies data to a printhead module including: 5 at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 10 Optionally the printer controller supplies data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, 15 wherein the first number is greater than the second number. Optionally the printer controller supplies data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 20 Optionally the printer controller supplies data to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle 25 position x is at or adjacent the centre of the set of nozzles. Optionally the printer controller supplies data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of 30 nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and WO 2005/120835 PCT/AU2004/000706 176 in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. Optionally the printer controller supplies data to a printhead module for receiving dot data to be printed using at 5 least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. Optionally the printer controller supplies data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion 10 including a component in a direction normal to that of a pagewidth to be printed. Optionally the printer controller supplies data to a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, 15 the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. Optionally the printer controller supplies data to a printhead module comprising at least first and second rows 20 configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. 25 Optionally the printer controller supplies data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at 30 least one of the other groups of the nozzles.
WO 2005/120835 PCT/AU2004/000706 177 Optionally the printer controller supplies data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. 5 Optionally the printer controller supplies data to a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print 10 media at or adjacent a position where the faulty nozzle would otherwise have printed it. In a twenty second aspect the present invention provides a printhead module including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data 15 source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. Optionally there is a one to one correspondence between the nozzles and respective elements of the first and 20 second shift registers. Optionally each of the shift registers supplies dot data to about half of the nozzles in a row. Optionally the printhead module includes at least one pair of rows of the nozzles, the rows in each pair being 25 offset in a direction parallel to the rows by half the intra-row nozzle spacing. Optionally each of the at least two shift registers supplies dot data to at least some of the nozzles in at least the pair of rows.
WO 2005/120835 PCT/AU2004/000706 178 Optionally the printhead module includes a plurality of the rows configured to print using at least two ink channels, the nozzles for each of the ink channels being fed the dot data from at least one pair of first and second registers. 5 Optionally the printhead module is configured to receive dot data to which a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier has been applied, the nozzles being disposed on the printhead module, the method comprising the steps of: (a) determining the rotational displacement; 10 (b) determining at least one correction factor that at least partially compensates for the ink dot displacement; and (c) using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. 15 Optionally the printhead module is configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle 20 position x is at or adjacent the centre of the set of nozzles. Optionally the printhead module is configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the 25 method comprising the steps of: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set 30 have been fired, and then firing the central nozzle.
WO 2005/120835 PCT/AU2004/000706 179 Optionally the printhead module is manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. 5 Optionally the printhead module further including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 10 Optionally the printhead module is installed in a printer comprising: a printhead comprising at least the first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to 15 output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. Optionally the printhead module is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel 20 to each other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 25 Optionally the printhead module is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; 30 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead WO 2005/120835 PCT/AU2004/000706 180 module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. Optionally the printhead module is installed in a printer comprising: 5 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and 10 the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. Optionally the printhead module is in communication with a printer controller for supplying dot data to at least 15 one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead 20 modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. Optionally the printhead module is in communication with a printer controller for supplying dot data to a 25 printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. 30 Optionally the printhead module is in communication with a printer controller for controlling a head comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row WO 2005/120835 PCT/AU2004/000706 181 being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, 5 wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. Optionally the printhead module is, in communication with a printer controller for outputting to a printhead module: 10 dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 15 Optionally the printhead module includes at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. Optionally the printhead module is in communication with a printer controller for supplying print data to at least 20 one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the 25 channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. Optionally the printhead module is in communication with a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the 30 modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan.
WO 2005/120835 PCT/AU2004/000706 182 Optionally the printhead module is used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a) a fire signal is provided to nozzles at a first and nth position in each set of nozzles; 5 (b) a fire signal is provided to the next inward pair of nozzles in each set; (c) in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. 10 Optionally the printhead module is used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle 15 position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printhead module is in communication with a printer controller for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at 20 least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for 25 printing. Optionally the printhead module is in communication with a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second 30 rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
WO 2005/120835 PCT/AU2004/000706 183 Optionally the printhead module is in communication with a printer controller for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. 5 Optionally the printhead module further including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at 10 least one of the other groups of the nozzles. Optionally the printhead module being capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; 15 and a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. Optionally a module further comprising a plurality of printhead modules including: 20 at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles; and the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two 25 types of the modules, wherein each type is determined by its geometric shape in plan. Optionally the printhead module includes at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, 30 nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
WO 2005/120835 PCT/AU2004/000706 184 Optionally the printhead module further includes at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next 5 inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. 10 Optionally a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. Optionally a printhead module further includes at least one row of printhead nozzles, at least one row including at 15 least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. Optionally a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the 20 printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. 25 Optionally a printhead module further comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are 30 printed to by nozzles from the second pair of rows.
WO 2005/120835 PCT/AU2004/000706 185 Optionally a printhead module is in communication with a printer controller for providing data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift 5 register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. Optionally a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or 10 adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. Optionally a printhead module further comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print 15 ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. In a twenty third aspect the present invention provides a printhead module capable of printing a maximum of n of 20 channels of print data, the printhead module being configurable into: a first mode, in which the printhead module is configured to receive print data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. 25 Optionally the first number is n. Optionally the first number is less than n. 30 Optionally the printhead module is configurable into at least one other mode, in which the printhead is configured to receive print data for a number of print channels other than the first and second numbers.
WO 2005/120835 PCT/AU2004/000706 186 Optionally n is 4 and the second number is less than 4. Optionally n is 5 and the second number is less than 5. 5 Optionally n is 6 and the second number is less than 6. Optionally the second number is 3, 4 or 5. 10 Optionally the selected mode is selected based on the contents of a memory associated with the printhead. Optionally the memory is a register. Optionally the register is on an integrated circuit, and wherein the integrated circuit and the printhead are mounted 15 to a print engine. Optionally printhead comprising a plurality of printhead modules capable of printing a maximum of n of channels of print data, the printhead module being configurable into: a first mode, in which the printhead module is configured to receive print data for a first number of the 20 channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. Optionally printhead is a pagewidth printhead. 25 Optionally the printhead module is configured to receive dot data to which a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier has been applied, the nozzles being disposed on the printhead module, the method comprising the steps of: WO 2005/120835 PCT/AU2004/000706 187 (a) determining the rotational displacement; (b) determining at least one correction factor that at least partially compensates for the ink dot displacement; and (c) using the correction factor to alter the output of the ink dots to at least partially compensate for the 5 rotational displacement. Optionally the printhead module is configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, 10 the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printhead module is configured to receive dot data to which a method of expelling ink has been 15 applied, the method being applied to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b) providing a fire signal to the next inward pair of nozzles in each set; 20 (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. Optionally the printhead module is manufactured in accordance with a method of manufacturing a plurality of 25 printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. Optionally the printhead module further including: 30 at least one row of print nozzles; WO 2005/120835 PCT/AU2004/000706 188 at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. Optionally the printhead module is installed in a printer comprising: 5 a printhead comprising at least the first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. 10 Optionally the printhead module is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to 15 output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. Optionally the printhead module is installed in a printer comprising: 20 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead 25 module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. Optionally the printhead module is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel 30 to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; WO 2005/120835 PCT/AU2004/000706 189 at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data 5 received from the first printer controller. Optionally the printhead module is in communication with a printer controller for supplying dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module 10 relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and 15 supply the dot data to the printhead module. Optionally the printhead module is in communication with a printer controller for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least 20 one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. Optionally the printhead module is in communication with a printer controller for controlling a head comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles 25 configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, 30 wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles.
WO 2005/120835 PCT/AU2004/000706 190 Optionally the printhead module is, in communication with a printer controller for outputting to a printhead module: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; 5 the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. Optionally the printhead module includes at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to 10 that of a pagewidth to be printed. Optionally the printhead module is in communication with a printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: 15 a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. 20 Optionally the printhead module is in communication with a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 25 Optionally the printhead module is used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a) a fire signal is provided to nozzles at a first and nth position in each set of nozzles; 30 (b) a fire signal is provided to the next inward pair of nozzles in each set; WO 2005/120835 PCT/AU2004/000706 191 (c) in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. 5 Optionally the printhead module is used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle 10 position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printhead module is in communication with a printer controller for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at 15 least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for 20 printing. Optionally the printhead module is in communication with a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second 25 rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 30 Optionally the printhead module is in communication with a printer controller for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead.
WO 2005/120835 PCT/AU2004/000706 192 Optionally the printhead module further including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at 5 least one of the other groups of the nozzles. Optionally the printhead module being capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; 10 and a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. Optionally a module further comprising a plurality of printhead modules including: 15 at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles; and 20 the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. Optionally the printhead module includes at least one row that comprises a plurality of sets of n adjacent nozzles, 25 each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
WO 2005/120835 PCT/AU2004/000706 193 Optionally the printhead module further includes at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: 5 in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. Optionally a printhead module for receiving dot data to be printed using at least two different inks and control 10 data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. Optionally a printhead module further includes at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal 15 to that of a pagewidth to be printed. Optionally a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that 20 each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. Optionally a printhead module further comprising at least first and second rows configured to print ink of a similar 25 type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. 30 Optionally a printhead module is in communication with a printer controller for providing data to a printhead module that includes: WO 2005/120835 PCT/AU2004/000706 194 at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 5 Optionally a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. 10 Optionally a printhead module further comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position 15 where the faulty nozzle would otherwise have printed it. In a twenty fourth aspect the present invention provides a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two 20 types of the modules, wherein each type is determined by its geometric shape in plan. Optionally the printhead comprising a plurality of at least one of the types of module. Optionally the printhead comprising a plurality of each of at least two of the types of module. 25 Optionally the printhead comprising two types of the module. Optionally the two types of module alternate across a print width of the printhead.
WO 2005/120835 PCT/AU2004/000706 195 Optionally each of the modules including at least one row of print nozzles, wherein each of the at least one row of print nozzles includes at least a portion that extends at an acute angle to an intended relative direction of movement between the printhead and print media. 5 Optionally the different types of modules are configured, and arranged relative to each other, such that there is substantially no growth in offset of each of the at least one row of print nozzles in a direction across an intended print width of the printhead. Optionally each of the printhead modules is a monolithic integrated circuit. 10 Optionally each of the modules including at least one row of print nozzles, wherein each of the at least one rows includes at least two sub-rows, each of the sub-rows being parallel to each other and displaced relative to each other in a direction of intended movement of print media relative to the printhead. 15 Optionally the printhead being a pagewidth printhead. Optionally the printhead being a pagewidth printhead. Optionally the printhead being a pagewidth printhead. 20 Optionally the printhead is configured to receive dot data to which a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier has been applied, the nozzles being disposed on the printhead module, the method comprising the steps of: 25 (a) determining the rotational displacement; (b) determining at least one correction factor that at least partially compensates for the ink dot displacement; and (c) using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. 30 WO 2005/120835 PCT/AU2004/000706 196 Optionally the printhead is configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, 5 nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printhead is configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of sets of n 10 adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and 15 (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. Optionally the printhead is manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the 20 method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. Optionally the printhead further including: at least one row of print nozzles; 25 at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. Optionally the printhead is installed in a printer comprising: a printhead comprising at least the first elongate printhead module, the at least one printhead module 30 including at least one row of print nozzles for expelling ink; and WO 2005/120835 PCT/AU2004/000706 197 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. 5 Optionally the printhead is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead 10 module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. Optionally the printhead is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel 15 to each other and being disposed end to end on either side of ajoin region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second 20 printhead module. Optionally the printhead is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is 25 longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data 30 received from the first printer controller.
WO 2005/120835 PCT/AU2004/000706 198 Optionally the printhead is in communication with a printer controller for supplying dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: 5 access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. 10 Optionally the printhead is in communication with a printer controller for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to 15 the temperature rising above a first threshold. Optionally the printhead is in communication with a printer controller for controlling a head comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row 20 being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing 25 of the nozzles. Optionally the printhead is in communication with a printer controller for outputting to a printhead module: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; 30 the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks.
WO 2005/120835 PCT/AU2004/000706 199 Optionally the printhead further including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 5 Optionally the printhead is in communication with a printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and 10 a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. Optionally the printhead is in communication with a printer controller for supplying data to a printhead 15 comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. Optionally the printhead is used in conjunction with a printer controller for supplying one or more control signals 20 to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a) a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b) a fire signal is provided to the next inward pair of nozzles in each set; (c) in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; 25 and (d) in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. Optionally the printhead is used in conjunction with a printer controller for supplying one or more control signals 30 to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, WO 2005/120835 PCT/AU2004/000706 200 nozzle position n, nozzle position 2, nozzle position (n-1), nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printhead is in communication with a printer controller for supplying dot data to a printhead 5 module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the 10 second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. Optionally the printhead is in communication with a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a 15 plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 20 Optionally the printhead is in communication with a printer controller for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. 25 Optionally the printhead further including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 30 Optionally the printhead being capable of printing a maximum of n of channels of print data, the printhead being configurable into: WO 2005/120835 PCT/AU2004/000706 201 a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. 5 Optionally the printhead further including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of 10 nozzles. Optionally the printhead further including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward 15 pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. 20 Optionally the printhead receives dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. Optionally the printhead further including at least one row of printhead nozzles, at least one row including at least 25 one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. Optionally the printhead having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead 30 being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in WO 2005/120835 PCT/AU2004/000706 202 the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. Optionally the printhead further comprising at least first and second rows configured to print ink of a similar type 5 or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. 10 Optionally the printhead is in communication with a printer controller for providing data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift 15 register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. Optionally the printhead having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least 20 one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. Optionally the printhead further comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a 25 similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 30 In a twenty fifth aspect the present invention provides a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle WO 2005/120835 PCT/AU2004/000706 203 position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the nozzle at each given position within the set is fired simultaneously with the nozzles in the other 5 sets at respective corresponding positions. Optionally the printhead module includes a plurality of the rows of nozzles, the printhead module being configured to fire all the nozzles on each row prior to firing any nozzles from a subsequent row. 10 Optionally the rows are disposed in pairs. Optionally the rows in each pair of rows are offset relative to each other. Optionally each pair of rows is configured to print the same color ink. 15 Optionally each pair of rows is connected to a common ink source. Optionally the sets of nozzles are adjacent each other. 20 Optionally the sets of nozzles are separated by an intermediate nozzle, the intermediate nozzle being fired either prior to the nozzle at position 1 in each set, or following the nozzle at position n. Optionally a printhead comprising a plurality of printhead modules including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire 25 signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printhead is a pagewidth printhead. 30 WO 2005/120835 PCT/AU2004/000706 204 Optionally the printhead module is configured to receive dot data to which a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier has been applied, the nozzles being disposed on the printhead module, the method comprising the steps of: 5 (a) determining the rotational displacement; (b) determining at least one correction factor that at least partially compensates for the ink dot displacement; and (c) using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. 10 Optionally the printhead module is configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle 15 position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printhead module is configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of 20 sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and 25 (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. Optionally the printhead module is manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth 30 printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed.
WO 2005/120835 PCT/AU2004/000706 205 Optionally the printhead module further including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 5 Optionally the printhead module is installed in a printer comprising: a printhead comprising at least the first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to 10 output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. Optionally the printhead module is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel 15 to each other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 20 Optionally the printhead module is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; 25 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. 30 Optionally the printhead module is installed in a printer comprising: WO 2005/120835 PCT/AU2004/000706 206 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot 5 data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. 10 Optionally the printhead module is in communication with a printer controller for supplying dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; 15 determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. 20 Optionally the printhead module is in communication with a printer controller for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. 25 Optionally the printhead module is in communication with a printer controller for controlling a head comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, 30 for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, WO 2005/120835 PCT/AU2004/000706 207 wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. Optionally the printhead module is, in communication with a printer controller for outputting to a printhead 5 module: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 10 Optionally the printhead module includes at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 15 Optionally the printhead module is in communication with a printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and 20 a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. Optionally the printhead module is in communication with a printer controller for supplying data to a printhead 25 comprising a plurality of printhead modules, the printhead being wider than a reticle step used in fonning the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. Optionally the printhead module is used in conjunction with a printer controller for supplying one or more control 30 signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: WO 2005/120835 PCT/AU2004/000706 208 (a) a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b) a fire signal is provided to the next inward pair of nozzles in each set; (c) in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and 5 (d) in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. Optionally the printhead module is used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of 10 adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 15 Optionally the printhead module is in communication with a printer controller for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by 20 nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. Optionally the printhead module is in communication with a printer controller for supplying dot data to at least 25 one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty 30 nozzle would otherwise have printed it.
WO 2005/120835 PCT/AU2004/000706 209 Optionally the printhead module is in communication with a printer controller for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. 5 Optionally the printhead module further including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 10 Optionally the printhead module being capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and 15 a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. Optionally a module further comprising a plurality of printhead modules including: at least one row of print nozzles; 20 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles; and the printhead being wider than a reticle step used in forming the modules, the printhead 25 comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. Optionally the printhead module includes at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a 30 fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, WO 2005/120835 PCT/AU2004/000706 210 nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printhead module further includes at least one row that comprises a plurality of adjacent sets of n 5 adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire 10 the central nozzle. Optionally a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. 15 Optionally a printhead module further includes at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 20 Optionally a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row 25 are all fired before the nozzles of each subsequent row. Optionally a printhead module further comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being 30 configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows.
WO 2005/120835 PCT/AU2004/000706 211 Optionally a printhead module is in communication with a printer controller for providing data to a printhead module that includes: at least one row of print nozzles; 5 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. Optionally a printhead module having a plurality of nozzles for expelling ink, the printhead module including a 10 plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. Optionally a printhead module further comprising a plurality of rows, each of the rows 15 comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 20 Optionally the printhead module further comprising a plurality of the rows, the printhead module being configured to fire each nozzle in each row simultaneously with the nozzle or nozzles at the same position in the other rows. Optionally the printhead module further including a plurality of pairs of the rows, each pair of rows including an 25 odd row and an even row, the odd and even rows in each pair being offset from each other in both x and y directions relative to an intended direction of print media movement relative to the printhead, the printhead module being configured to cause firing of at least a plurality of the odd rows prior to firing any of the even rows, or vice versa. 30 Optionally all the odd rows are fired before any of the even rows are fired, or vice versa.
WO 2005/120835 PCT/AU2004/000706 212 Optionally all the odd rows, or the even rows, or both, are fired in a predetermined order. Optionally the printhead module is configurable such that the predetermined order is selectable from a plurality of predetermined available orders. 5 Optionally the predetermined order is sequential. Optionally the printhead module is configurable such that the predetermined order can commence at any of a plurality of the rows. 10 In a twenty sixth aspect the present invention provides a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the. nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in 15 each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. 20 Optionally the printhead module includes a plurality of the rows of nozzles, the printhead module being configured to fire all the nozzles on each row prior to firing any nozzles from a subsequent row. Optionally the rows are disposed in pairs. 25 Optionally the rows in each pair of rows are offset relative to each other. Optionally each pair of rows is configured to print the same color ink. Optionally each pair of rows is connected to a common ink source.
WO 2005/120835 PCT/AU2004/000706 213 Optionally the sets of nozzles are adjacent each other. Optionally the sets of nozzles are separated by an intermediate nozzle, the intermediate nozzle being fired either 5 prior to the nozzle at position 1 in each set, or following the nozzle at position n. Optionally the printhead module is configured to receive dot data to which a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier has been applied, the nozzles being disposed on the 10 printhead module, the method comprising the steps of: (a) determining the rotational displacement; (b) determining at least one correction factor that at least partially compensates for the ink dot displacement; and (c) using the correction factor to alter the output of the ink dots to at least partially compensate for the 15 rotational displacement. Optionally the printhead module is configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, 20 the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printhead module is configured to receive dot data to which a method of expelling ink has been 25 applied, the method being applied to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b) providing a fire signal to the next inward pair of nozzles in each set; 30 (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and WO 2005/120835 PCT/AU2004/000706 214 (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. Optionally the printhead module is manufactured in accordance with a method of manufacturing a plurality of 5 printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. Optionally the printhead module further including: 10 at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. Optionally the printhead module is installed in a printer comprising: 15 a printhead comprising at least the first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. 20 Optionally the printhead module is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to 25 output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. Optionally the printhead module is installed in a printer comprising: WO 2005/120835 PCT/AU2004/000706 215 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to 5 output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. Optionally the printhead module is installed in a printer comprising: 10 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and 15 the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. Optionally the printhead module is in communication with a printer controller for supplying dot data to at least 20 one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead 25 modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. Optionally the printhead module is in communication with a printer controller for supplying dot data to a 30 printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold.
WO 2005/120835 PCT/AU2004/000706 216 Optionally the printhead module is in communication with a printer controller for controlling a head comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row 5 being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing 10 of the nozzles. Optionally the printhead module is, in communication with a printer controller for outputting to a printhead module: dot data to be printed with at least two different inks; and 15 control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. Optionally the printhead module includes at least one row of printhead nozzles, at least one row including at least 20 one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. Optionally the printhead module is in communication with a printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead 25 module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; 30 wherein the printer controller is selectively configurable to supply dot data for the first and second modes.
WO 2005/120835 PCT/AU2004/000706 217 Optionally the printhead module is in communication with a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 5 Optionally the printhead module is used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a) a fire signal is provided to nozzles at a first and nth position in each set of nozzles; 10 (b) a fire signal is provided to the next inward pair of nozzles in each set; (c) in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. 15 Optionally the printhead module is used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle 20 position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printhead module is in communication with a printer controller for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at 25 least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for 30 printing. Optionally the printhead module is in communication with a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows WO 2005/120835 PCT/AU2004/000706 218 comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty 5 nozzle would otherwise have printed it. Optionally the printhead module is in communication with a printer controller for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. 10 Optionally the printhead module further including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at 15 least one of the other groups of the nozzles. Optionally the printhead module being capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; 20 and a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. Optionally a module further comprising a plurality of printhead modules including: 25 at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles; and WO 2005/120835 PCT/AU2004/000706 219 the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 5 Optionally the printhead module includes at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 10 Optionally the printhead module further includes at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: 15 in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. Optionally a printhead module for receiving dot data to be printed using at least two different inks and control 20 data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. Optionally a printhead module further includes at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal 25 to that of a pagewidth to be printed. Optionally a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that 30 each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row.
WO 2005/120835 PCT/AU2004/000706 220 Optionally a printhead module further comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being 5 configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. Optionally a printhead module is in communication with a printer controller for providing data to a printhead 10 module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 15 Optionally a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. 20 Optionally a printhead module further comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position 25 where the faulty nozzle would otherwise have printed it. Optionally the printhead module further comprising a plurality of the rows, the printhead module being configured to fire each nozzle in each row simultaneously with the nozzle or nozzles at the same position in the other rows. 30 Optionally the printhead module further including a plurality of pairs of the rows, each pair of rows including an odd row and an even row, the odd and even rows in each pair being offset from each other in both x and y directions relative to an intended direction of print media movement relative to the printhead, the printhead WO 2005/120835 PCT/AU2004/000706 221 module being configured to cause firing of at least a plurality of the odd rows prior to firing any of the even rows, or vice versa. Optionally all the odd rows are fired before any of the even rows are fired, or vice versa. 5 Optionally all the odd rows, or the even rows, or both, are fired in a predetermined order. Optionally the printhead module is configurable such that the predetermined order is selectable from a plurality of predetermined available orders. 10 Optionally the predetermined order is sequential. Optionally the printhead module is configurable such that the predetermined order can commence at any of a plurality of the rows. 15 In a twenty seventh aspect the present invention provides a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. 20 Optionally the communication input is configured to receive the dot data and control data serially. Optionally the printhead module further including a plurality of the communication inputs. Optionally the printhead module further including a plurality of the communication inputs. 25 Optionally a printhead comprising a plurality of printhead modules for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data; WO 2005/120835 PCT/AU2004/000706 222 the printhead modules being disposed end to end for printing a width exceeding that of any of the individual printhead modules, the communications input of each of the printhead modules being connected to a common dot data and control data bus. 5 Optionally each module is configured to respond to dot data and control data on the bus only when it is intended for that module. Optionally the printhead module is configured to receive dot data to which a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational 10 displacement of a printhead module relative to a carrier has been applied, the nozzles being disposed on the printhead module, the method comprising the steps of: (a) determining the rotational displacement; (b) determining at least one correction factor that at least partially compensates for the ink dot displacement; and 15 (c) using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. Optionally the printhead module is configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of 20 adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 25 Optionally the printhead module is configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; 30 (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and WO 2005/120835 PCT/AU2004/000706 223 (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. Optionally the printhead module is manufactured in accordance with a method of manufacturing a plurality of 5 printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. Optionally the printhead module further including: 10 at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. Optionally the printhead module is installed in a printer comprising: 15 a printhead comprising at least the first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. 20 Optionally the printhead module is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to 25 output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. Optionally the printhead module is installed in a printer comprising: WO 2005/120835 PCT/AU2004/000706 224 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to 5 output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. Optionally the printhead module is installed in a printer comprising: 10 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and 15 the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. Optionally the printhead module is in communication with a printer controller for supplying dot data to at least 20 one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead 25 modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. Optionally the printhead module is in communication with a printer controller for supplying dot data to a 30 printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold.
WO 2005/120835 PCT/AU2004/000706 225 Optionally the printhead module is in communication with a printer controller for controlling a head comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row 5 being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing 10 of the nozzles. Optionally the printhead module is, in communication with a printer controller for outputting to a printhead module: dot data to be printed with at least two different inks; and 15 control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. Optionally the printhead module includes at least one row of printhead nozzles, at least one row including at least 20 one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. Optionally the printhead module is in communication with a printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead 25 module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; 30 wherein the printer controller is selectively configurable to supply dot data for the first and second modes.
WO 2005/120835 PCT/AU2004/000706 226 Optionally the printhead module is in communication with a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 5 Optionally the printhead module is used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a) a fire signal is provided to nozzles at a first and nth position in each set of nozzles; 10 (b) a fire signal is provided to the next inward pair of nozzles in each set; (c) in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. 15 Optionally the printhead module is used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle 20 position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printhead module is in communication with a printer controller for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at 25 least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for 30 printing. Optionally the printhead module is in communication with a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows WO 2005/120835 PCT/AU2004/000706 227 comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty 5 nozzle would otherwise have printed it. Optionally the printhead module is in communication with a printer controller for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. 10 Optionally the printhead module further including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at 15 least one of the other groups of the nozzles. Optionally the printhead module being capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; 20 and a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. Optionally a module further comprising a plurality of printhead modules including: 25 at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles; and WO 2005/120835 PCT/AU2004/000706 228 the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 5 Optionally the printhead module includes at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 10 Optionally the printhead module further includes at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: 15 in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. Optionally a printhead module for receiving dot data to be printed using at least two different inks and control 20 data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. Optionally a printhead module further includes at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal 25 to that of a pagewidth to be printed. Optionally a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that 30 each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row.
WO 2005/120835 PCT/AU2004/000706 229 Optionally a printhead module further comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being 5 configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. Optionally a printhead module is in communication with a printer controller for providing data to a printhead 10 module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 15 Optionally a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. 20 Optionally a printhead module further comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position 25 where the faulty nozzle would otherwise have printed it. In a twenty eighth aspect the present invention provides a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 30 Optionally the displaced row portion is disposed adjacent one end of the monolithic printhead module.
WO 2005/120835 PCT/AU2004/000706 230 Optionally the printhead module further including a plurality of the rows, wherein each of at least a plurality of the rows includes one of the displaced row portions. Optionally the displaced row portions of at least some of the rows are different in length than the displaced row 5 portions of at least some of the other rows. Optionally each of the rows has a displaced row portion, and the sizes of the respective displaced row portions increase from row to row in the direction normal to that of the pagewidth to be printed. 10 Optionally the dropped rows together comprise a generally trapezoidal shape, in plan. Optionally the dropped rows together comprise a generally triangular shape, in plan. Optionally a printhead comprising a plurality of printhead modules, including at least one of the printhead 15 modules including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. Optionally a printhead comprising a plurality of printhead modules, including at least one the printhead modules 20 according to claim 2, wherein the displaced row portion of at least one of the printhead modules is disposed adjacent another of the printhead modules. Optionally the printhead modules are the same shape and configuration as each other, and are arranged end to end across the intended print width. 25 Optionally the printhead being a pagewidth printhead. Optionally the printhead being a pagewidth printhead.
WO 2005/120835 PCT/AU2004/000706 231 Optionally the printhead module is configured to receive dot data to which a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier has been applied, the nozzles being disposed on the printhead module, the method comprising the steps of: 5 (a) determining the rotational displacement; (b) determining at least one correction factor that at least partially compensates for the ink dot displacement; and (c) using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. 10 Optionally the printhead module is configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle 15 position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printhead module is configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of 20 sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and 25 (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. Optionally the printhead module is manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth 30 printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed.
WO 2005/120835 PCT/AU2004/000706 232 Optionally the printhead module further including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 5 Optionally the printhead module is installed in a printer comprising: a printhead comprising at least the first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to 10 output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. Optionally the printhead module is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel 15 to each other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 20 Optionally the printhead module is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; 25 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. 30 Optionally the printhead module is installed in a printer comprising: WO 2005/120835 PCT/AU2004/000706 233 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot 5 data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. 10 Optionally the printhead module is in communication with a printer controller for supplying dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; 15 determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. 20 Optionally the printhead module is in communication with a printer controller for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. 25 Optionally the printhead module is in communication with a printer controller for controlling a head comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, 30 for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, WO 2005/120835 PCT/AU2004/000706 234 wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. Optionally the printhead module is, in communication with a printer controller for outputting to a printhead 5 module: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 10 Optionally the printhead module includes at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 15 Optionally the printhead module is in communication with a printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and 20 a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. Optionally the printhead module is in communication with a printer controller for supplying data to a printhead 25 comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. Optionally the printhead module is used in conjunction with a printer controller for supplying one or more control 30 signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: WO 2005/120835 PCT/AU2004/000706 235 (a) a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b) a fire signal is provided to the next inward pair of nozzles in each set; (c) in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and 5 (d) in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. Optionally the printhead module is used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of 10 adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 15 Optionally the printhead module is in communication with a printer controller for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by 20 nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. Optionally the printhead module is in communication with a printer controller for supplying dot data to at least 25 one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty 30 nozzle would otherwise have printed it.
WO 2005/120835 PCT/AU2004/000706 236 Optionally the printhead module is in communication with a printer controller for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. 5 Optionally the printhead module further including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 10 Optionally the printhead module being capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and 15 a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. Optionally a module further comprising a plurality of printhead modules including: at least one row of print nozzles; 20 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles; and the printhead being wider than a reticle step used in forming the modules, the printhead 25 comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. Optionally the printhead module includes at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a 30 fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, WO 2005/120835 PCT/AU2004/000706 237 nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printhead module further includes at least one row that comprises a plurality of adjacent sets of n 5 adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire 10 the central nozzle. Optionally a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. 15 Optionally a printhead module further includes at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 20 Optionally a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row 25 are all fired before the nozzles of each subsequent row. Optionally a printhead module further comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being 30 configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows.
WO 2005/120835 PCT/AU2004/000706 238 Optionally a printhead module is in communication with a printer controller for providing data to a printhead module that includes: at least one row of print nozzles; 5 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. Optionally a printhead module having a plurality of nozzles for expelling ink, the printhead module including a 10 plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. Optionally a printhead module further comprising a plurality of rows, each of the rows comprising a plurality of 15 nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 20 In a twenty ninth aspect the present invention provides a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row 25 by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. Optionally the rows are disposed in pairs extending generally transverse to a direction media is to be moved relative to the printhead. 30 Optionally the rows in each pair of rows are configured to print the same color ink as each other. Optionally the rows in each pair of rows share an ink supply.
WO 2005/120835 PCT/AU2004/000706 239 Optionally the rows in each pair of rows are offset with respect to each other. Optionally the printhead module is configured to fire the nozzles such that at least some ink dots from one row 5 land on top of dots previously deposited by one or more of the other rows. Optionally the printhead module is operable in at least two fire modes, wherein at least some of the at least two fire modes define relatively different numbers of nozzles in each of the fire groups. 10 Optionally at least some of the at least two fire groups define relatively different fire group sequences. Optionally a printhead comprising a plurality of printhead modules having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, 15 the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. 20 Optionally the printhead is a pagewidth printhead. Optionally the printhead module is configured to receive dot data to which a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier has been applied, the nozzles being disposed on the 25 printhead module, the method comprising the steps of: (a) determining the rotational displacement; (b) determining at least one correction factor that at least partially compensates for the ink dot displacement; and (c) using the correction factor to alter the output of the ink dots to at least partially compensate for the 30 rotational displacement.
WO 2005/120835 PCT/AU2004/000706 240 Optionally the printhead module is configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle 5 position 1, nozzle position n, nozzle position 2, nozzle position (n-1), nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printhead module is configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of 10 sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and 15 (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. Optionally the printhead module is manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth 20 printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. Optionally the printhead module further including: at least one row of print nozzles; 25 at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. Optionally the printhead module is installed in a printer comprising: a printhead comprising at least the first elongate printhead module, the at least one printhead module 30 including at least one row of print nozzles for expelling ink; and WO 2005/120835 PCT/AU2004/000706 241 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. 5 Optionally the printhead module is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead 10 module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. Optionally the printhead module is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel 15 to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second 20 printhead module. Optionally the printhead module is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is 25 longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data 30 received from the first printer controller.
WO 2005/120835 PCT/AU2004/000706 242 Optionally the printhead module is in communication with a printer controller for supplying dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: 5 access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. 10 Optionally the printhead module is in communication with a printer controller for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in 15 response to the temperature rising above a first threshold. Optionally the printhead module is in communication with a printer controller for controlling a head comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row 20 being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing 25 of the nozzles. Optionally the printhead module is, in communication with a printer controller for outputting to a printhead module: dot data to be printed with at least two different inks; and 30 control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks.
WO 2005/120835 PCT/AU2004/000706 243 Optionally the printhead module includes at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 5 Optionally the printhead module is in communication with a printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the 10 channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. 15 Optionally the printhead module is in communication with a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 20 Optionally the printhead module is used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a) a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b) a fire signal is provided to the next inward pair of nozzles in each set; 25 (c) in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. 30 Optionally the printhead module is used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of WO 2005/120835 PCT/AU2004/000706 244 adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 5 Optionally the printhead module is in communication with a printer controller for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the 10 nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. 15 Optionally the printhead module is in communication with a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding 20 nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. Optionally the printhead module is in communication with a printer controller for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial 25 outputs for supplying the dot data to at least one printhead. Optionally the printhead module further including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift 30 register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
WO 2005/120835 PCT/AU2004/000706 245 Optionally the printhead module being capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and 5 a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. Optionally a module further comprising a plurality of printhead modules including: at least one row of print nozzles; 10 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles; and the printhead being wider than a reticle step used in forming the modules, the printhead 15 comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. Optionally the printhead module includes at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a 20 fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printhead module further includes at least one row that comprises a plurality of adjacent sets of n 25 adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire 30 the central nozzle.
WO 2005/120835 PCT/AU2004/000706 246 Optionally a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. 5 Optionally a printhead module further includes at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. Optionally a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least 10 part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. 15 Optionally a printhead module further comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print 20 media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. Optionally a printhead module is in communication with a printer controller for providing data to a printhead module that includes: 25 at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 30 Optionally a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold.
WO 2005/120835 PCT/AU2004/000706 247 Optionally a printhead module further comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a 5 corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. Optionally the printhead module further comprises a plurality of the rows, the printhead module being configured to fire each nozzle in each row simultaneously with the nozzle or nozzles at the same position in the other rows. 10 Optionally the printhead module further includes a plurality of pairs of the rows, each pair of rows including an odd row and an even row, the odd and even rows in each pair being offset from each other in both x and y directions relative to an intended direction of print media movement relative to the printhead, the printhead module being configured to cause firing of at least a plurality of the odd rows prior to firing any of the even rows, 15 or vice versa. Optionally all the odd rows are fired before any of the even rows are fired, or vice versa. Optionally all the odd rows, or the even rows, or both, are fired in a predetermined order. 20 Optionally the printhead module is configurable such that the predetermined order is selectable from a plurality of predetermined available orders. Optionally the predetermined order is sequential. 25 Optionally the printhead module is configurable such that the predetermined order can commence at any of a plurality of the rows. In a thirtieth aspect the present invention provides a printhead module comprising at least first and second rows 30 configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the WO 2005/120835 PCT/AU2004/000706 248 printhead, the printhead module being configurable such that the nozzles in the first and second rows are fired such that some dots output to print media are printed to by nozzles from the first row and at least some other dots output to print media are printed to by nozzles from the second row. 5 Optionally the printhead module is controllable such that either of the nozzles in each aligned pair of nozzles in the first and second rows can be selected to output ink for a selected dot to be printed on the print media. Optionally in the event a nozzle in the first row is faulty, the corresponding nozzle in the second row is selected to 10 output ink for a dot for which the faulty nozzle would otherwise have output ink. Optionally the printhead module includes a plurality of sets of the first and second rows. Optionally each of the sets of the first and second rows is configured to print in a single color or ink type. 15 Optionally the first and second rows in at least one of the sets are separated by one or more rows from the other set or sets. Optionally each of the rows includes an odd sub-row and an even sub-row, the odd and even sub-rows being 20 offset with respect to each other in a direction of intended print media travel relative to the printhead. Optionally the odd and even sub-rows are transversely offset relative to each other. Optionally the printhead module is configured such that the first and second rows are fired alternately. 25 Optionally a printhead comprising a plurality of printhead modules comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second rows are fired WO 2005/120835 PCT/AU2004/000706 249 such that some dots output to print media are printed to by nozzles from the first row and at least some other dots output to print media are printed to by nozzles from the second row. Optionally the printhead being a pagewidth printhead. 5 Optionally the printhead module is configured to receive dot data to which a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier has been applied, the nozzles being disposed on the printhead module, the method comprising the steps of: 10 (a) determining the rotational displacement; (b) determining at least one correction factor that at least partially compensates for the ink dot displacement; and (c) using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. 15 Optionally the printhead module is configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle 20 position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printhead module is configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of 25 sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and 30 (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle.
WO 2005/120835 PCT/AU2004/000706 250 Optionally the printhead module is manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer 5 substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. Optionally the printhead module further including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, 10 wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. Optionally the printhead module is installed in a printer comprising: a printhead comprising at least the first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and 15 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. Optionally the printhead module is installed in a printer comprising: 20 a printhead comprising first and second elongate printhead modules,,the printhead modules being parallel to each other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the 25 printhead modules are configured such that no dot data passes between them. Optionally the printhead module is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is 30 longer than the second printhead module; WO 2005/120835 PCT/AU2004/000706 251 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. 5 Optionally the printhead module is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; 10 at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. 15 Optionally the printhead module is in communication with a printer controller for supplying dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: 20 access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. 25 Optionally the printhead module is in communication with a printer controller for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in 30 response to the temperature rising above a first threshold.
WO 2005/120835 PCT/AU2004/000706 252 Optionally the printhead module is in communication with a printer controller for controlling a head comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, 5 for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. 10 Optionally the printhead module is, in communication with a printer controller for outputting to a printhead module: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; 15 the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. Optionally the printhead module includes at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to 20 that of a pagewidth to be printed. Optionally the printhead module is in communication with a printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into:, 25 a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. 30 Optionally the printhead module is in communication with a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the WO 2005/120835 PCT/AU2004/000706 253 modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. Optionally the printhead module is used in conjunction with a printer controller for supplying one or more control 5 signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a) a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b) a fire signal is provided to the next inward pair of nozzles in each set; (c) in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; 10 and (d) in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. Optionally the printhead module is used in conjunction with a printer controller for supplying one or more control 15 signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1),.., nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 20 Optionally the printhead module is in communication with a printer controller for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the 25 nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. 30' Optionally the printhead module is in communication with a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot WO 2005/120835 PCT/AU2004/000706 254 data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 5 Optionally the printhead module is in communication with a printer controller for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. Optionally the printhead module further including: 10 at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 15 Optionally the printhead module being capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, 20 wherein the first number is greater than the second number. Optionally a module further comprising a plurality of printhead modules including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data 25 source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles; and the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its 30 geometric shape in plan.
WO 2005/120835 PCT/AU2004/000706 255 Optionally the printhead module includes at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, 5 nozzle position (n-1), ... , nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printhead module further includes at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead 10 being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. 15 Optionally a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. 20 Optionally a printhead module further includes at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. Optionally a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least 25 part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. 30 Optionally a printhead module further comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the WO 2005/120835 PCT/AU2004/000706 256 second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. 5 Optionally a printhead module is in communication with a printer controller for providing data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift 10 register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. Optionally a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or 15 adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. Optionally a printhead module further comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print 20 ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. In a thirty first aspect the present invention provides a printer controller for providing data to a printhead module 25 that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 30 Optionally there is a one to one correspondence between the nozzles and respective elements of the first and second shift registers.
WO 2005/120835 PCT/AU2004/000706 257 Optionally each of the shift registers supplies dot data to about half of the nozzles in a row. Optionally the printer controller includes at least one pair of rows of the nozzles, the rows in each pair being offset 5 in a direction parallel to the rows by half the intra-row nozzle spacing. Optionally each of the at least two shift registers supplies dot data to at least some of the nozzles in at least the pair of rows. 10 Optionally the printer includes a plurality of the rows configured to print using at least two ink channels, the nozzles for each of the ink channels being fed the dot data from at least one pair of first and second registers. Optionally the printhead module forms part of a printhead. 15 Optionally the printhead includes a plurality of the printhead modules and the printer controller is configured to supply data to a plurality of the modules. Optionally the printhead is a pagewidth printhead comprising a plurality of the printhead modules. 20 Optionally the printer controller is for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b) providing a fire signal to the next inward pair of nozzles in each set; 25 (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. Optionally the printer controller is manufactured in accordance with a method of manufacturing a plurality of 30 printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth WO 2005/120835 PCT/AU2004/000706 258 printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. Optionally the printer controller supplies data to a printhead module including: 5 at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. Optionally the printer controller is installed in a printer comprising: 10 a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. 15 Optionally the printer controller is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to 20 output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. Optionally the printer controller is installed in a printer comprising: 25 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead 30 module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module.
WO 2005/120835 PCT/AU2004/000706 259 Optionally the printer controller is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is 5 longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least 10 some of the dot data received from the first printer controller. Optionally the printer controller supplies dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: 15 access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. 20 Optionally the printer controller supplies dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. 25 Optionally the printer controller controls a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, 30 such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles.
WO 2005/120835 PCT/AU2004/000706 260 Optionally the printer controller outputs to a printhead module: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; 5 the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. Optionally the printer controller supplies data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion 10 including a component in a direction normal to that of a pagewidth to be printed. Optionally the printer controller supplies print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the 15 channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. 20 Optionally the printer controller supplies data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. Optionally the printer controller supplies one or more control signals to a printhead module, the printhead module 25 including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 30 WO 2005/120835 PCT/AU2004/000706 261 Optionally the printer controller supplies dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are 5 fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. Optionally the printer controller supplies dot data to at least one printhead module, the at least one printhead 10 module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 15 Optionally the printer controller receives first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. Optionally the printer controller supplies data to a printhead module including: 20 at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 25 Optionally the printer controller supplies data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, 30 wherein the first number is greater than the second number.
WO 2005/120835 PCT/AU2004/000706 262 Optionally the printer controller supplies data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 5 Optionally the printer controller supplies data to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 10 Optionally the printer controller supplies data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: 15 in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. Optionally the printer controller supplies data to a printhead module for receiving dot data to be printed using at 20 least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. Optionally the printer controller supplies data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion 25 including a component in a direction normal to that of a pagewidth to be printed. Optionally the printer controller supplies data to a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, 30 the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row.
WO 2005/120835 PCT/AU2004/000706 263 Optionally the printer controller supplies data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the 5 printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. Optionally the printer controller supplies data to a printhead module that includes: 10 at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 15 Optionally the printer controller supplies data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. 20 Optionally the printer controller supplies data to a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 25 In a thirty second aspect the present invention provides a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. 30 Optionally the printhead module is configured to modify the operation of the nozzles at or adjacent the at least one thermal sensor, such that operation of nozzles not at or adjacent the at least one thermal sensor is not modified.
WO 2005/120835 PCT/AU2004/000706 264 Optionally each thermal sensor is associated with a predetermined group of the nozzles, the nozzles in the predetermined group being those for which the operation is modified. 5 Optionally each thermal sensor is associated with a single nozzle. Optionally the modification includes preventing operation of the nozzle. Optionally the modification includes preventing operation of the nozzle for a predetermined period. 10 Optionally the modification includes preventing operation of the nozzle until the temperature drops below a second threshold. Optionally the second threshold is lower than the first threshold. 15 Optionally the second threshold is the same as the first threshold. Optionally the temperature is not determined explicitly by the at least one thermal sensor or the module. 20 Optionally the printhead module is a thermal inkjet printhead module and each of the nozzles includes a thermal ink ejection mechanism. Optionally the thermal sensor comprises at least part of one of the thermal inkjet mechanisms. 25 Optionally the thermal sensor comprises a heating element. Optionally the thermal sensor determines the temperature by determining a resistance of the heating element.
WO 2005/120835 PCT/AU2004/000706 265 Optionally printhead module according to claim 1, configured to: output thermal information from the at least one thermal sensor to a controller; and receive control information back from the controller, the control information being indicative of the modification to make to the operation of the one or more nozzles. 5 Optionally the printhead module further including a plurality of data latches, the data latches being configured to provide dot data to respective ones of the nozzles, at least some of the data latches being configured to receive thermal signals from respective ones of the thermal sensors during an acquisition period. 10 Optionally the data latches are configured to form a shift register, the shift register being configured to: shift the print data in during a print load phase; sample the signals from the thermal sensors during a temperature load phase; and shift the thermal signals out during an output phase. 15 Optionally the output phase coincides with a subsequent print load phase. Optionally the printhead module further including logic circuitry configured to perform a bitwise operation on: each thermal signal as it is clocked out of the shift register; and each piece of dot data to be clocked into the shift register, such that when a thermal signal is indicative of a thermal problem with a nozzle, the logic circuitry 20 prevents loading of data that would cause firing of that nozzle. Optionally the logic circuitry includes an AND circuit that receives as inputs the dot data and the thermal signal corresponding to the nozzle for which the dot data is intended, an output of the AND circuit being in communication with an input of the shift register. 25 Optionally the printhead module is configured to receive dot data to which a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier has been applied, the nozzles being disposed on the printhead module, the method comprising the steps of: 30 (a) determining the rotational displacement; WO 2005/120835 PCT/AU2004/000706 266 (b) determining at least one correction factor that at least partially compensates for the ink dot displacement; and (c) using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. 5 Optionally the printhead module is configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle 10 position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printhead module is configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of 15 sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and 20 (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. Optionally the printhead module is manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth 25 printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. Optionally the printhead module further including: at least one row of print nozzles; 30 at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers.
WO 2005/120835 PCT/AU2004/000706 267 Optionally the printhead module is installed in a printer comprising: a printhead comprising at least the first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and 5 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. Optionally the printhead module is installed in a printer comprising: 10 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the 15 printhead modules are configured such that no dot data passes between them. Optionally the printhead module is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is 20 longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. 25 Optionally the printhead module is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; 30 at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein WO 2005/120835 PCT/AU2004/000706 268 the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. Optionally the printhead module is in communication with a printer controller for supplying dot data to at least 5 one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead 10 modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. Optionally the printhead module is in communication with a printer controller for supplying dot data to a 15 printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. 20 Optionally the printhead module is in communication with a printer controller for controlling a head comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired 25 simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. 30 Optionally the printhead module is, in communication with a printer controller for outputting to a printhead module: dot data to be printed with at least two different inks; and WO 2005/120835 PCT/AU2004/000706 269 control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 5 Optionally the printhead module includes at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. Optionally the printhead module is in communication with a printer controller for supplying print data to at least 10 one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the 15 channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. Optionally the printhead module is in communication with a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the 20 modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. Optionally the printhead module is used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of 25 n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a) a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b) a fire signal is provided to the next inward pair of nozzles in each set; (c) in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and 30 (d) in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired.
WO 2005/120835 PCT/AU2004/000706 270 Optionally the printhead module is used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, 5 the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printhead module is in communication with a printer controller for supplying dot data to a 10 printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from 15 the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. Optionally the printhead module is in communication with a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows 20 comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 25 Optionally the printhead module is in communication with a printer controller for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. 30 Optionally the printhead module further including: at least one row of print nozzles; WO 2005/120835 PCT/AU2004/000706 271 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 5 Optionally the printhead module being capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, 10 wherein the first number is greater than the second number. Optionally a module further comprising a plurality of printhead modules including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data 15 source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles; and the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its 20 geometric shape in plan. Optionally the printhead module includes at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, 25 nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printhead module further includes at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead 30 being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: WO 2005/120835 PCT/AU2004/000706 272 in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. 5 Optionally a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. Optionally a printhead module further includes at least one row of printhead nozzles, at least one row including at 10 least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. Optionally a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the 15 printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. 20 Optionally a printhead module further comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are 25 printed to by nozzles from the second pair of rows. Optionally a printhead module is in communication with a printer controller for providing data to a printhead module that includes: at least one row of print nozzles; 30 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
WO 2005/120835 PCT/AU2004/000706 273 Optionally a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in 5 response to the temperature rising above a first threshold. Optionally a printhead module further comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a 10 corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. Optionally the printhead module further including a logic circuit accepting as inputs a masking signal and the thermal signal corresponding to the nozzle for which the dot data is intended, the logic circuit outputting the 15 thermal signal to the input of the AND circuit in reliance on a value of the masking signal. Optionally the value of the masking signal enables masking of the thermal signal for at least one nozzle position, including the nozzle for which the current dot data is intended. 20 Optionally the value of the masking signal enables masking of the thermal signal for a plurality of nozzle positions corresponding to a region of the printhead associated the nozzle for which the current dot data is intended. Optionally the value of the masking signal enables masking of the thermal signal for all of the nozzle positions of 25 the printhead. In a thirty third aspect the present invention provides a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a 30 nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
WO 2005/120835 PCT/AU2004/000706 274 Optionally each nozzle in the first row is paired with a nozzle in the second row, such that each pair of nozzles is aligned in an intended direction of print media travel relative to the printhead module. Optionally each printhead module further including a plurality of sets of the first and second rows. 5 Optionally each of the sets of the first and second rows is configured to print in a single color or ink type. Optionally each of the rows includes an odd and an even sub-row, the odd and even sub-rows being offset with respect to each other in a direction of print media travel relative to the printhead in use. 10 Optionally the odd and even sub-rows are transversely offset with respect to each other. Optionally printhead comprising a plurality of printhead modules wherein each nozzle in the first row is paired with a nozzle in the second row, such that each pair of nozzles is aligned in an intended direction of print media 15 travel relative to the printhead module. Optionally printhead comprising a plurality of printhead modules each of the sets of the first and second rows is configured to print in a single color or ink type. 20 Optionally the printhead being a pagewidth printhead. Optionally the printhead module is configured to receive dot data to which a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier has been applied, the nozzles being disposed on the 25 printhead module, the method comprising the steps of: (a) determining the rotational displacement; (b) determining at least one correction factor that at least partially compensates for the ink dot displacement; and (c) using the correction factor to alter the output of the ink dots to at least partially compensate for the 30 rotational displacement.
WO 2005/120835 PCT/AU2004/000706 275 Optionally the printhead module is configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, 5 the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printhead module is configured to receive dot data to which a method of expelling ink has been 10 applied, the method being applied to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b) providing a fire signal to the next inward pair of nozzles in each set; 15 (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. Optionally the printhead module is manufactured in accordance with a method of manufacturing a plurality of 20 printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. Optionally the printhead module further including: 25 at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. Optionally the printhead module is installed in a printer comprising: 30 a printhead comprising at least the first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and WO 2005/120835 PCT/AU2004/000706 276 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. 5 Optionally the printhead module is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead 10 module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. Optionally the printhead module is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel 15 to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second 20 printhead module. Optionally the printhead module is installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is 25 longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data 30 received from the first printer controller.
WO 2005/120835 PCT/AU2004/000706 277 Optionally the printhead module is in communication with a printer controller for supplying dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: 5 access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. 10 Optionally the printhead module is in communication with a printer controller for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in 15 response to the temperature rising above a first threshold. Optionally the printhead module is in communication with a printer controller for controlling a head comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row 20 being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing 25 of the nozzles. Optionally the printhead module is, in communication with a printer controller for outputting to a printhead module: dot data to be printed with at least two different inks; and 30 control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks.
WO 2005/120835 PCT/AU2004/000706 278 Optionally the printhead module includes at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 5 Optionally the printhead module is in communication with a printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the 10 channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. 15 Optionally the printhead module is in communication with a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 20 Optionally the printhead module is used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a) a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b) a fire signal is provided to the next inward pair of nozzles in each set; 25 (c) in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. 30 Optionally the printhead module is used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of WO 2005/120835 PCT/AU2004/000706 279 adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 5 Optionally the printhead module is in communication with a printer controller for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the 10 nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. 15 Optionally the printhead module is in communication with a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding 20 nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. Optionally the printhead module is in communication with a printer controller for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial 25 outputs for supplying the dot data to at least one printhead. Optionally the printhead module further including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift 30 register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
WO 2005/120835 PCT/AU2004/000706 280 Optionally the printhead module being capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and 5 a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. Optionally a module further comprising a plurality of printhead modules including: at least one row of print nozzles; 10 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles; and the printhead being wider than a reticle step used in forming the modules, the printhead 15 comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. Optionally the printhead module includes at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a 20 fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. Optionally the printhead module further includes at least one row that comprises a plurality of adjacent sets of n 25 adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire 30 the central nozzle.
WO 2005/120835 PCT/AU2004/000706 281 Optionally a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. 5 Optionally a printhead module further includes at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. Optionally a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least 10 part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. 15 Optionally a printhead module further comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print 20 media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. Optionally a printhead module is in communication with a printer controller for providing data to a printhead module that includes: 25 at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 30 Optionally a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold.
WO 2005/120835 PCT/AU2004/000706 282 Optionally a printhead module further comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a 5 corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. In a thirty fourth aspect the present invention provides a first entity configured to authenticate a digital signature supplied by a second entity, wherein one of the entities includes a base key and the other of the entities includes a 10 variant key and a bit-pattern, the variant key being based on the result of applying a one way function to the base key and the bit-pattern, the digital signature having been generated by the second entity using its key to digitally signing at least part of data to be authenticated, the first entity being configured to: (a) receive the digital signature from the second entity; (b) receive the data; and 15 (c) authenticate the digital signature based on the received data and the first entity's key. Optionally the first entity includes the base key, the first entity being configured to receive, from the second entity, the bit-pattern, wherein (c) includes: generating the variant key from the bit-pattern and the base key; and 20 authenticating the digital signature using the generated variant key. Optionally, the first entity storing information, wherein the data is indicative of a request to be performed on the information. 25 Optionally the information is a value. Optionally the data is indicative of a read instruction. Optionally the data is indicate of a write instruction, the data being indicative of new information to be written. 30 WO 2005/120835 PCT/AU2004/000706 283 Optionally the data is indicative of a function to be applied to the information. Optionally the function is a decrement or increment function. 5 Optionally the data is indicative of a value stored in the second entity. Optionally the first entity being configured to send a request to the second entity, the data being returned in response to the request. 10 Optionally the data is indicative of a value stored in the second entity. Optionally the first entity being configured to digitally sign at least some of the request with the base key. Optionally the first entity has the base key. 15 Optionally the first entity storing information, wherein the data is indicative of a request to be performed on the information. Optionally the information is a value. 20 Optionally the data is indicative of a read instruction. Optionally the data is indicate of a write instruction, the data being indicative of new information to be written. 25 Optionally the data is indicative of a function to be applied to the information. Optionally the function is a decrement or increment function.
WO 2005/120835 PCT/AU2004/000706 284 Optionally the data is indicative of a value stored in the second entity. Optionally the first entity being configured to send a read request to the second entity, the data being returned in response to the request. 5 Optionally the data is indicative of a value stored in the second entity. Optionally the first entity being configured to digitally sign at least some of the request with the base key. 10 Optionally there is provided a first entity, including: a first bit-pattern a non-volatile memory storing resource data, a first base key for use with at least a first variant key; 15 a second variant key for use with a second base key, the second variant key being the result of a one way function applied to: the second base key; and the first bit-pattern or a modified bit-pattern based on the first bit pattern. Optionally there is provided a first entity configured for use in a method of enabling or disabling a verification 20 process of a first entity in response to a predetermined event, the first entity having at least one associated bit pattern and at least one variant key, each of the variant keys having been generated by applying a one way function to: a base key; and one or more of the at least one bit-patterns, respectively; or one or more alternative bit patterns, each of the alternative bit-patterns being based on one or the at least one bit-patterns, the method including 25 the method including: (a) determining that the predetermined event has happened; and (b) enabling or disabling at least one of the first variant keys in response the predetermined event.
WO 2005/120835 PCT/AU2004/000706 285 Optionally there is provided a first entity for use in a system for enabling authenticated communication between a first entity and at least one other entity, the system including a second entity, wherein: the first entity and the second entity share transport keys; and the second entity includes at least one authentication key configured to be transported from the second entity to 5 the first entity using the transport keys, the authentication key being usable to enable the authenticated communication by the first entity. Optionally there is provided a first entity configured for use in a method of storing a first bit-pattern in non 10 volatile memory of a device, the method comprising: (a) applying a one way function to a second bit-pattern associated with the device, thereby to generate a first result; (b) applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and 15 (c) storing the second result in the memory, thereby indirectly storing the first bit-pattern. Optionally there is provided a first entity configured for use in a method of storing a bit-pattern in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: 20 (a) determining a first memory location; and (b) storing the bit-pattern at the first memory location; wherein the first memory locations are different in at least a plurality of the respective devices. Optionally there is provided a first entity configured for use in a method of storing at least one functionally 25 identical code segment in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: (a) determining a first memory location; and (b) storing a first of the at least one code segments in the memory at the first memory location; wherein the first memory location is different in at least a plurality of the respective devices. 30 WO 2005/120835 PCT/AU2004/000706 286 Optionally there is provided a first entity configured for implementing a method for providing a sequence of nonces (RO, RI, R2, ) commencing with a current seed of a sequence of seeds (xl, x2, x3,...), the method comprising: (a) applying a one-way function to the current seed, thereby to generate a current nonce; (b) outputting the 5 current nonce; (c) using the current seed to generate a next seed in a sequence of seeds, the seed so generated becoming the current seed; and (c) repeating steps (a) to (c) as required to generate further nonces in the sequence of nonces. 10 Optionally there is provided a first entity configured for implementing a method of storing multiple first bit patterns in non-volatile memory of a device, the method comprising, for each of the first bit-patterns to be stored: (a) applying a one way function to a third bit-pattern based on a second bit-pattern associated with the device, thereby to generate a first result; (b) applying a second function to the first result and the first bit-pattern, thereby to generate a second result; 15 and (c) storing the second result in the memory, thereby indirectly storing the first bit-pattern; wherein the third bit-patterns used for the respective first bit-patterns are relatively unique compared to each other. 20 In a thirty fifth aspect the present invention provides a first entity including: a first bit-pattern a non-volatile memory storing resource data, a first base key for use with at least a first variant key; 25 a second variant key for use with a second base key, the second variant key being the result of a one way function applied to: the second base key; and the first bit-pattern or a modified bit-pattern based on the first bit pattern. Optionally the first variant key is stored in a second entity. 30 WO 2005/120835 PCT/AU2004/000706 287 Optionally the second base key is stored in a third entity. Optionally the first entity is configured to receive a request from any of a plurality of second entities, the request being indicative of at least one operation to be performed on the resource data, each of the second entities having 5 an associated bit-pattern and one of the first variant keys, the first variant key in each of second entities being based on the result of applying a one way function to the first base key and the associated bit-pattern of that second entity, the first entity being configured to: (a) receive the request from one of the second entities; (b) perform the at least one operation in the request, thereby to generate a response; 10 (c) use the first base key to digitally sign at least part of the response, thereby to generate a digital signature; and (d) send the response and the digital signature to the second entity from which the request was received, such that the second entity can verify the at least part of the response using its variant key. 15 Optionally the first entity is configured to, prior to (b), receive the associated bit-pattern from the second entity that makes the request in (a), wherein (c) includes: (i) using the first base key and the associated bit-pattern received from the second entity to generate the first variant key of the second entity making the request in (a); and (ii) using the first variant key generated in (i) to perform the signing of at least part of the response the 20 response. Optionally the first entity is configured to receive a request from any of one or more third entities, the request being indicative of at least one operation to be performed on the resource data, each of the one or more third entities having the second base key, the first entity being configured to: 25 (e) receive the request from the one of the third entities; (f) perform the at least one operation in the request, thereby to generate a response; (g) use the second variant key to digitally sign at least part of the response, thereby to generate a digital signature; and (h) send the response and the digital signature to the third entity from which the request was received, such 30 that the third entity can verify the at least part of the response using its base key.
WO 2005/120835 PCT/AU2004/000706 288 Optionally the first entity is configured to send the first bit-pattern to the third entity that makes the request in (e), such that the third entity can: (i) use the second base key and the bit-pattern received from the first entity to generate the second variant key; and 5 (ii) use the second variant key generated in (i) to perform the verification. Optionally the first entity is configured to receive a request from any of one or more third entities, the request being indicative of at least one operation to be performed on the resource data, each of the one or more third entities having the second base key, the first entity being configured to: 10 (a) receive the request from the one of the third entities; (b) perform the at least one operation in the request, thereby to generate a response; (c) use the first variant key to digitally sign at least part of at least the response, thereby to generate a digital signature; and (d) send the response and the digital signature to the third entity from which the request was received, such 15 that the third entity can verify at least part of the response using its base key. Optionally the first entity is configured to send the first bit-pattern the third entity that makes the request in (a), such that the third entity can: (i) use the second base key and the bit-pattern received from the first entity to generate the second variant 20 key; and (ii) use the second variant key generated in (i) to perform the verification. Optionally the second and third entities have different permissions in relation to the operations they can perform on the resource data, the permissions being defined based which of the first and second base key and variant key 25 combinations is used for the verification. Optionally the first base and variant key combination provides a higher permission to perform an operation on the resource data than the second base key and variant key combination.
WO 2005/120835 PCT/AU2004/000706 289 Optionally the second and third entities have different permissions in relation to the operations they can perform on the resource data, the permissions being defined based which of the first and second base key and variant key combinations is used for the verification. 5 Optionally the first base and variant key combination provides a higher permission to perform an operation on the resource data than the second base key and variant key combination. Optionally the first entity is configured to receive a request from any of a plurality of second entities, the request being indicative of at least one operation to be performed on the resource data, each of the second entities having 10 an associated bit-pattern and one of the first variant keys, the first variant key in each of second entities being based on the result of applying a one way function to the first base key and the associated bit-pattern of that second entity, the first entity being configured to: (a) receive the request from one of the second entities; (b) receive the bit-pattern associated with the entity from which the request was received; 15 (c) receive a digital signature from the entity from which the request was received, the digital signature having been generated by digitally signing at least part of the request using the variant key; (d) generate the variant key of the entity from which the request sent, by applying the one way function to the first base key and the received bit pattern; and (e) verify the request by digitally signing at least part of the request using the variant key generated in (d) 20 and comparing the produced signature against the signature received in (d). Optionally the first entity is configured to receive a request from any of one or more third entities, the request being indicative of at least one operation to be performed on the resource data, each of the one or more third entities having the second base key, the first entity being configured to: 25 (f) receive the request from the one of the third entities; (g) receive a digital signature from the third entity from which the request was received, the digital signature having been generated by the third entity signing at least part of the request using the second variant key; (h) verify the at least part of the request by digitally signing at least part of the request using the second variant key and comparing the produced signature against the signature received in (g). 30 WO 2005/120835 PCT/AU2004/000706 290 Optionally the first entity is configured to send the first bit-pattern to the third entity that makes the request in (f), such that the third entity can: (i) use the second base key and the bit-pattern received from the first entity to generate the second variant key; and 5 (ii) use the second variant key generated in (i) to digitally sign at least part of the request; and (iii) send the request for receipt by the first entity in (a). Optionally the first entity is configured to receive a request from any of one or more third entities, the request being indicative of at least one operation to be performed on the resource data, each of the one or more third 10 entities having the second base key, the first entity being configured to: (f) receive the request from the one of the third entities; (g) receive a digital signature from the third entity from which the request was received, the digital signature having been generated by the third entity signing at least part of the request using the second variant key; (h) verify the at least part of the request by digitally signing at least part of the request using the second 15 variant key and comparing the produced signature against the signature received in (g). Optionally the second and third entities have different pennissions in relation to the operations they can perform on the resource data, the permissions being defined based which of the first and second base key and variant key combinations is used for the verification. 20 Optionally the first base and variant key combination provides a higher permission to perform an operation on the resource data than the second base key and variant key combination. Optionally the resource data represents a physical property. 25 Optionally the physical property is a remaining amount of a physical resource. Optionally the resource is a consumable resource.
WO 2005/120835 PCT/AU2004/000706 291 Optionally the resource entity is physically attached to a reservoir or magazine that holds the consumable resource. Optionally the resource is a fluid. 5 Optionally the fluid is ink. Optionally the operation includes a read, in which the resource data is read by the entity making the request. 10 Optionally the operation includes write, in which the resource data is modified by the entity making the request. Optionally the operation includes decrementing, in which the resource is decremented by the entity making the request. 15 Optionally the one way function is a hash function. Optionally the one way function is SHAL. Optionally a second entity configured for use with the first entity including: 20 a first bit-pattern a non-volatile memory storing resource data, a first base key for use with at least a first variant key; a second variant key for use with a second base key, the second variant key being the result of a one way function applied to: the second base key; and the first bit-pattern or a modified bit-pattern based on the first bit 25 pattern. Optionally a second entity configured for use with the first entity configured to receive a request from any of a plurality of second entities, the request being indicative of at least one operation to be performed on the resource data, each of the second entities having an associated bit-pattern and one of the first variant keys, the first variant WO 2005/120835 PCT/AU2004/000706 292 key in each of second entities being based on the result of applying a one way function to the first base key and the associated bit-pattern of that second entity, the first entity being configured to: (a) receive the request from one of the second entities; (b) perform the at least one operation in the request, thereby to generate a response; 5 (c) use the first base key to digitally sign at least part of the response, thereby to generate a digital signature; and (d) send the response and the digital signature to the second entity from which the request was received, such that the second entity can verify the at least part of the response using its variant key. 10 Optionally a second entity configured for use with the first entity configured to receive a request from any of a plurality of second entities, the request being indicative of at least one operation to be performed on the resource data, each of the second entities having an associated bit-pattern and one of the first variant keys, the first variant key in each of second entities being based on the result of applying a one way function to the first base key and 15 the associated bit-pattern of that second entity, the first entity being configured to: (a) receive the request from one of the second entities; (b) receive the bit-pattern associated with the entity from which the request was received; (c) receive a digital signature from the entity from which the request was received, the digital signature having been generated by digitally signing at least part of the request using the variant key; 20 (d) generate the variant key of the entity from which the request sent, by applying the one way function to the first base key and the received bit pattern; and (e) verify the request by digitally signing at least part of the request using the variant key generated in (d) and comparing the produced signature against the signature received in (d). 25 Optionally a third entity configured for use with the first entity configured to receive a request from any of one or more third entities, the request being indicative of at least one operation to be performed on the resource data, each of the one or more third entities having the second base key, the first entity being configured to: (e) receive the request from the one of the third entities; 30 (f) perform the at least one operation in the request, thereby to generate a response; WO 2005/120835 PCT/AU2004/000706 293 (g) use the second variant key to digitally sign at least part of the response, thereby to generate a digital signature; and (h) send the response and the digital signature to the third entity from which the request was received, such that the third entity can verify the at least part of the response using its base key. 5 Optionally a third entity configured for use with the first entity configured to receive a request from any of one or more third entities, the request being indicative of at least one operation to be performed on the resource data, each of the one or more third entities having the second base key, the first entity being configured to: 10 (a) receive the request from the one of the third entities; (b) perform the at least one operation in the request, thereby to generate a response; (c) use the first variant key to digitally sign at least part of at least the response, thereby to generate a digital signature; and (d) send the response and the digital signature to the third entity from which the request was received, such 15 that the third entity can verify at least part of the response using its base key. Optionally a third entity configured for use with the first entity configured to receive a request from any of one or more third entities, the request being indicative of at least one operation to be performed on the resource data, 20 each of the one or more third entities having the second base key, the first entity being configured to: (f) receive the request from the one of the third entities; (g) receive a digital signature from the third entity from which the request was received, the digital signature having been generated by the third entity signing at least part of the request using the second variant key; (h) verify the at least part of the request by digitally signing at least part of the request using the second 25 variant key and comparing the produced signature against the signature received in (g). Optionally there is provided a first entity configured to authenticate a digital signature supplied by a second entity, wherein one of the entities includes a base key and the other of the entities includes a variant key and a bit-pattern, the variant key being based on the result of applying a one way function to the base key and the bit-pattern, the 30 digital signature having been generated by the second entity using its key to digitally signing at least part of data to be authenticated, the first entity being configured to: WO 2005/120835 PCT/AU2004/000706 294 (a) receive the digital signature from the second entity; (b) receive the data; and (c) authenticate the digital signature based on the received data and the first entity's key. 5 Optionally there is provided a first entity configured to implement a method of enabling or disabling a verification process of a first entity in response to a predetermined event, the first entity having at least one associated bit pattern and at least one variant key, each of the variant keys having been generated by applying a one way function to: a base key; and one or more of the at least one bit-patterns, respectively; or one or more alternative bit 10 patterns, each of the alternative bit-patterns being based on one or the at least one bit-patterns, the method including the method including: (a) determining that the predetermined event has happened; and (b) enabling or disabling at least one of the first variant keys in response the predetermined event. 15 Optionally there is provided a first entity configured for usein a system for enabling authenticated communication between a first entity and at least one other entity, the system including a second entity, wherein: the first entity and the second entity share transport keys; and 20 the second entity includes at least one authentication key configured to be transported from the second entity to the first entity using the transport keys, the authentication key being usable to enable the authenticated communication by the first entity. Optionally there is provided a first entity configured to implement a method of storing a first bit-pattern in non 25 volatile memory of a device, the method comprising: (a) applying a one way function to a second bit-pattern associated with the device, thereby to generate a first result; (b) applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and 30 (c) storing the second result in the memory, thereby indirectly storing the first bit-pattern.
WO 2005/120835 PCT/AU2004/000706 295 Optionally there is provided a first entity configured to implement a method of storing a bit-pattern in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: 5 (a) determining a first memory location; and (b) storing the bit-pattern at the first memory location; wherein the first memory locations are different in at least a plurality of the respective devices. 10 Optionally there is provided a first entity configured to implement a method of storing at least one functionally identical code segment in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: (a) determining a first memory location; and (b) storing a first of the at least one code segments in the memory at the first memory location; 15 wherein the first memory location is different in at least a plurality of the respective devices. Optionally there is provided a first entity configured to implement a method for providing a sequence of nonces (RO, RI, R2, ... ) commencing with a current seed of a sequence of seeds (xI, x2, x3,...), the method comprising: 20 (a) applying a one-way function to the current seed, thereby to generate a current nonce; (b) outputting the current nonce; (c) using the current seed to generate a next seed in a sequence of seeds, the seed so generated becoming the current seed; and (c) repeating steps (a) to (c) as required to generate further nonces in the sequence of nonces. 25 Optionally there is provided a first entity configured to implement a method of storing multiple first bit-patterns in non-volatile memory of a device, the method comprising, for each of the first bit-patterns to be stored: (a) applying a one way function to a third bit-pattern based on a second bit-pattern associated with the 30 device, thereby to generate a first result; WO 2005/120835 PCT/AU2004/000706 296 (b) applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and (c) storing the second result in the memory, thereby indirectly storing the first bit-pattern; wherein the third bit-patterns used for the respective first bit-patterns are relatively unique compared to 5 each other. In a thirty sixth aspect the present invention provides a method of enabling or disabling a verification process of a first entity in response to a predetermined event, the first entity having at least one associated bit-pattern and at least one variant key, each of the variant keys having been generated by applying a one way function to: a base 10 key; and one or more of the at least one bit-patterns, respectively; or one or more alternative bit patterns, each of the alternative bit-patterns being based on one or the at least one bit-patterns, the method including the method including: (a) determining that the predetermined event has happened; and (b) enabling or disabling at least one of the first variant keys in response the predetermined event. 15 Optionally step (a) includes disabling at least one of the variant keys, such that the disabled at least one variant key can no longer be used to digitally sign information in that entity. Optionally step (a) includes disabling at least one of the variant keys, such that the disabled at least one variant 20 key can no longer be used to verify information signed by one or more respective base keys related to the disabled at least one variant key in that entity. Optionally the step of disabling the at least one variant key includes modifying a status of a flag associated with that at least one variant key. 25 Optionally the step of disabling the at least one variant key includes deleting that at least one variant key. Optionally the step of disabling the at least one variant key includes modifying that at least one variant key 30 Optionally the event is a predetermined point in time being reached or passed.
WO 2005/120835 PCT/AU2004/000706 297 Optionally the first entity includes a plurality of the variant keys, the plurality of variant keys being based on the result of a one way function applied to: a respective one of a corresponding plurality of base keys; and one of the at least one bit-patterns or one of the at least one alternative bit-patterns, the method including the steps of: 5 determining that a predetermined event related to one of the variant keys has happened; and enabling or disabling at least one of the plurality of variant keys with which the predetermined event is associated. Optionally the plurality of base keys has a corresponding sequence of predetermined events associated with them, the method including the steps of: 10 (a) determining that one of the predetermined event has happened; and (b) enabling or disabling the variant key in the sequence corresponding to predetermined event that is determined to have happened. Optionally the variant keys are disabled in the order of the sequence of predetermined events. 15 Optionally the sequence of events is chronological. Optionally each of the events includes a time being reached. 20 Optionally the step of determining that one of the events has happened includes receiving a time from a trusted source. Optionally the time is a date. 25 Optionally the date is determined with a resolution of a month. Optionally the predetermined event includes detection of compromise of one or more of the keys, the method including disabling the one or more variant keys corresponding to the one or more keys that were compromised.
WO 2005/120835 PCT/AU2004/000706 298 Optionally the predetermined event includes suspect compromise of one or more of the keys, the method including disabling the one or more variant keys corresponding to the one or more keys that were suspected of being compromised. 5 In a further aspect the present invention provides a method of manufacturing second entities for use in the verification process with the first entity of claim 1, each of the first entities including at least first and second variant key, the first variant key having been generated by applying a one way function to a first base key and a first bit-pattern, and the second variant key having been generated by applying a one way function to a second base key and a second bit-pattern, the method comprising the steps of: 10 manufacturing a plurality of second entities for use with the first entities, each of the second entities including at least the first base key; and upon the first variant key being disabled in response to one of the predetermined event, manufacturing a plurality of third entities for use with the first entities, each of the third entities including at least the second base key. 15 Optionally the first variant key is automatically disabled in response to a predetermined event. Optionally the method further includes the step of causing the first variant key to be disabled. Optionally the first variant key is disabled in response to a time being reached. 20 Optionally at least some of the first entities have one or more further variant keys, each of the respective further variant keys having been generated by applying a one way function to respective further base keys and bit patterns, each of the variant keys being enabled or disabled in response to respective predetermined events, the method comprising the step of manufacturing a sequence of sets of second entities, each set of the second entities 25 being manufactured such that the variant key corresponding to its base key is enabled for the verification process during the life of that set. Optionally the predetermined events are selected such that the variant keys corresponding with the base keys of more than one of the sets are enabled at once. 30 WO 2005/120835 PCT/AU2004/000706 299 Optionally there is provided a method using a first entity configured to authenticate a digital signature supplied by a second entity, wherein one of the entities includes a base key and the other of the entities includes a variant key and a bit-pattern, the variant key being based on the result of applying a one way function to the base key and the bit-pattern, the digital signature having been generated by the second entity using its key to digitally signing at 5 least part of data to be authenticated, the first entity being configured to: (a) receive the digital signature from the second entity; (b) receive the data; and (c) authenticate the digital signature based on the received data and the first entity's key. 10 Optionally there is provided a method using a first entity including: a first bit-pattern a non-volatile memory storing resource data, a first base key for use with at least a first variant key; 15 a second variant key for use with a second base key, the second variant key being the result of a one way function applied to: the second base key; and the first bit-pattern or a modified bit-pattern based on the first bit pattern. 20 Optionally there is provided a method using a system for enabling authenticated communication between a first entity and at least one other entity, the system including a second entity, wherein: the first entity and the second entity share transport keys; and the second entity includes at least one authentication key configured to be transported from the second entity to the first entity using the transport keys, the authentication key being usable to enable the authenticated 25 communication by the first entity. Optionally there is provided a method including storing a first bit-pattern in non-volatile memory of a device, the method comprising: (a) applying a one way function to a second bit-pattern associated with the device, thereby to generate a first 30 result; WO 2005/120835 PCT/AU2004/000706 300 (b) applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and (c) storing the second result in the memory, thereby indirectly storing the first bit-pattern. 5 Optionally there is provided a method including storing a bit-pattern in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: (a) determining a first memory location; and (b) storing the bit-pattern at the first memory location; 10 wherein the first memory locations are different in at least a plurality of the respective devices. Optionally there is provided a method including storing at least one functionally identical code segment in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: (a) determining a first memory location; and 15 (b) storing a first of the at least one code segments in the memory at the first memory location; wherein the first memory location is different in at least a plurality of the respective devices. Optionally there is provided a method including providing a sequence of nonces (RO, R1, R2, ... ) commencing with a current seed of a sequence of seeds (xl, x2, x3,...), the method comprising: 20 (a) applying a one-way function to the current seed, thereby to generate a current nonce; (b) outputting the current nonce; (c) using the current seed to generate a next seed in a sequence of seeds, the seed so generated becoming the current seed; and (c) repeating steps (a) to (c) as required to generate further nonces in the sequence of nonces. 25 Optionally there is provided a method including storing multiple first bit-patterns in non-volatile memory of a device, the method comprising, for each of the first bit-patterns to be stored: (a) applying a one way function to a third bit-pattern based on a second bit-pattern associated with the device, thereby to generate a first result; WO 2005/120835 PCT/AU2004/000706 301 (b) applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and (c) storing the second result in the memory, thereby indirectly storing the first bit-pattern; wherein the third bit-patterns used for the respective first bit-patterns are relatively unique compared to 5 each other. In a thirty seventh aspect the present invention provides a system for enabling authenticated communication between a first entity and at least one other entity, the system including a second entity, wherein: the first entity and the second entity share transport keys; and 10 the second entity includes at least one authentication key configured to be transported from the second entity to the first entity using the transport keys, the authentication key being usable to enable the authenticated communication by the first entity. Optionally the transport keys include: 15 a first transport key in the first entity; and a second transport key in the second entity. Optionally the first and second transport keys are the same. 20 Optionally the second transport key is a base key and the first transport key is a variant key, the variant key having been generated by applying a one way function to the base key and a first bit-pattern. Optionally the first bit-pattern is stored in the first entity. 25 Optionally each of the first and second transport keys is a second bit-pattern stored in the first and second entities during manufacture of the system or its components. Optionally the second bit-pattern was determined randomly or pseudo-randomly.
WO 2005/120835 PCT/AU2004/000706 302 Optionally the second bit-pattern was generated using a stochastic process or mechanism. Optionally the authentication key enables authenticated communication between the first and second entities. 5 Optionally the authentication key provides the first entity with permission to request performance of at least one operation on at least one value in the second entity. Optionally the authentication key enables authenticated communication between the first entity and one or more entities other than the second entity. 10 Optionally the authentication key is a variant key. Optionally the one or more entities include the base key corresponding to the authentication key. 15 Optionally the variant key in each system is relatively unique compared to the variant keys in the other systems. Optionally the authentication key is a third bit-pattern that was determined randomly or pseudo-randomly. Optionally the third bit-pattern was generated using a stochastic process or mechanism. 20 In a further aspect the present invention provides a system for enabling authenticated communication between a first entity and at least one other entity, the system including a second entity, wherein: the first entity and the second entity share additional transport keys; the second entity and each of the at least one other entities share transport keys; and 25 the second entity includes at least one authentication key configured to be transported from the second entity to the first entity using the first transport keys and to each of the at least one other entities using the respective additional shared transport keys, such that the authentication keys, once transported to the first and at least one other entities, enable verified communication therebetween.
WO 2005/120835 PCT/AU2004/000706 303 Optinally each pair of transport keys is different from the other pairs of transport keys. Optionally the authentication key is the first transport key. 5 Optionally the authentication key is the additional transport key for one of the at least one other entities. Optionally the authentication key is not the same as any of the transport keys. Optionally the authentication key is a variant key, the variant key having been generated by applying a one way 10 function to a base key and a first bit-pattern. Optionally the first transport key is a bit-pattern stored in the first and second entities during manufacture of the system or its components. 15 Optionally the bit-pattern was determined randomly or pseudo-randomly. Optionally the bit-pattern was generated using a stochastic process or mechanism. In a further aspect the present invention provides a method of manufacturing a system having at least first and 20 second entities, method comprising the steps of: providing the first and second entities with transport keys; and providing the second entity with at least one authentication key; the system being configured to enable transport of the at least one authentication key from the second entity to the first entity using the transport keys, the authentication key being usable to enable the authenticated 25 communication by the first entity. Optionally the transport keys include: a first transport key in the first entity; and a second transport key in the second entity.
WO 2005/120835 PCT/AU2004/000706 304 Optionally the first and second transport keys are the same. Optionally the second transport key is a base key and the first transport key is a variant key, the variant key having 5 been generated by applying a one way function to the base key and a first bit-pattern. Optionally the first bit-pattern is stored in the first entity. Optionally each of the first and second transport keys is a second bit-pattern stored in the first and second entities 10 during manufacture of the system or its components. Optionally the second bit-pattern was determined randomly or pseudo-randomly. Optionally the second bit-pattern was generated using a stochastic process or mechanism. 15 Optionally the authentication key enables authenticated communication between the first and second entities. Optionally the authentication key enables authenticated communication between the first entity and one or more entities other than the second entity. 20 Optionally the authentication key is a third bit-pattern that was determined randomly or pseudo-randomly. Optionally the third bit-pattern was generated using a stochastic process or mechanism. 25 In a further aspect the present invention provides a method for enabling authenticated communication between a first entity and at least one other entity in a system including a second entity, wherein: the first entity and the second entity share first transport keys; the second entity and each of the at least one other entities share additional transport keys; and the second entity includes at least one authentication key; WO 2005/120835 PCT/AU2004/000706 305 the method including the steps of: transporting the authentication key from the second entity to the first entity using the first transport keys, and to each of the at least one other entities using the respective shared additional transport keys, such that the authentication keys, once transported to the first and at least one other entities, enable verified communication 5 therebetween. Optionally each pair of transport keys is different from the other pairs of transport keys. Optionally the authentication key is the first transport key. 10 Optionally the authentication key is one of the additional transport keys. Optionally the authentication key is not the same as any of the transport keys. 15 Optionally the authentication key is a variant key, the variant key having been generated by applying a one way function to a base key and a first bit-pattern. Optionally the first transport key is a bit-pattern stored in the first and second entities during manufacture of the system or its components. 20 Optionally bit-pattern was determined randomly or pseudo-randomly. Optionally the bit-pattern was generated using a stochastic process or mechanism. 25 Optionally there is provided a method including a first entity configured to authenticate a digital signature supplied by a second entity, wherein one of the entities includes a base key and the other of the entities includes a variant key and a bit-pattern, the variant key being based on the result of applying a one way function to the base key and the bit-pattern, the digital signature having been generated by the second entity using its key to digitally signing at least part of data to be authenticated, the first entity being configured to: 30 (a) receive the digital signature from the second entity; WO 2005/120835 PCT/AU2004/000706 306 (b) receive the data; and (c) authenticate the digital signature based on the received data and the first entity's key. 5 Optionally there is provided a system including a first entity including: a first bit-pattern a non-volatile memory storing resource data, a first base key for use with at least a first variant key; a second variant key for use with a second base key, the second variant key being the result of a one way 10 function applied to: the second base key; and the first bit-pattern or a modified bit-pattern based on the first bit pattern. Optionally there is provided a system configured to implement a method of enabling or disabling a verification process of a first entity in response to a predetermined event, the first entity having at least one associated bit 15 pattern and at least one variant key, each of the variant keys having been generated by applying a one way function to: a base key; and one or more of the at least one bit-patterns, respectively; or one or more alternative bit patterns, each of the alternative bit-patterns being based on one or the at least one bit-patterns, the method including the method including: 20 (a) determining that the predetermined event has happened; and (b) enabling or disabling at least one of the first variant keys in response the predetermined event. Optionally there is provided a system configured to implement a method of storing a first bit-pattern in non volatile memory of a device, the method comprising: 25 (a) applying a one way function to a second bit-pattern associated with the device, thereby to generate a first result; (b) applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and (c) storing the second result in the memory, thereby indirectly storing the first bit-pattern. 30 WO 2005/120835 PCT/AU2004/000706 307 Optionally there is provided a system configured to implement a method of storing a bit-pattern in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: (a) determining a first memory location; and (b) storing the bit-pattern at the first memory location; 5 wherein the first memory locations are different in at least a plurality of the respective devices. Optionally there is provided a system configured to implement a method of storing at least one functionally identical code segment in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: 10 (a) determining a first memory location; and (b) storing a first of the at least one code segments in the memory at the first memory location; wherein the first memory location is different in at least a plurality of the respective devices. Optionally there is provided a system configured to implement a method of providing a sequence of nonces (RO, 15 Ri, R2, ... ) commencing with a current seed of a sequence of seeds (x1, x2, x3,...), the method comprising: (a) applying a one-way function to the current seed, thereby to generate a current nonce; (b) outputting the current nonce; (c) using the current seed to generate a next seed in a sequence of seeds, the seed so generated becoming the current seed; and 20 (c) repeating steps (a) to (c) as required to generate further nonces in the sequence of nonces. Optionally there is provided a system configured to implement a method of storing multiple first bit-patterns in non-volatile memory of a device, the method comprising, for each of the first bit-patterns to be stored: (a) applying a one way function to a third bit-pattern based on a second bit-pattern associated with the 25 device, thereby to generate a first result; (b) applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and (c) storing the second result in the memory, thereby indirectly storing the first bit-pattern; wherein the third bit-patterns used for the respective first bit-patterns are relatively unique compared to 30 each other.
WO 2005/120835 PCT/AU2004/000706 308 In a thirty eighth aspect the present invention provides a method of storing a first bit-pattern in non-volatile memory of a device, the method comprising: (a) applying a one way function to a second bit-pattern associated with the device, thereby to generate a first 5 result; (b) applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and (c) storing the second result in the memory, thereby indirectly storing the first bit-pattern. 10 Optionally the one way function is more cryptographically secure than the second function. Optionally the second function is a logical function. Optionally the logical function is an XOR function. 15 Optionally the one way function is a hash function. Optionally the one way function is SHAl. 20 Optionally the first bit-pattern is a key. Optionally the method further includes the step of storing one or more code segments in the memory, the code segments being configured to run on a processor of the device, thereby enabling the device to: apply the one way function to the second bit-pattern, thereby to generate the first result; 25 apply a third function to the first result and the second result, thereby to generate the first bit-pattern; wherein the third function is the inverse of the second function. Optionally the third function and the second function are the same.
WO 2005/120835 PCT/AU2004/000706 309 Optionally the second bit-pattern was generated randomly or pseudo-randomly. Optionally the method further includes the step, performed prior to step (a), of determining the second bit-pattern. 5 Optionally determining the second bit-pattern includes generating the second bit-pattern randomly or pseudo randomly. Optionally determining the second bit-pattern includes generating the second bit-pattern based on a stochastic process or mechanism. 10 Optionally determining the second bit-pattern includes selecting the second-bit pattern from an existing list or sequence of second bit-patterns. In a further aspect the present invention provides method of storing a first bit-pattern in non-volatile memory of 15 each of a plurality of devices, the method comprising, for each of the devices: (a) applying a one way function to a second bit-pattern associated with the device, thereby to generate a first result; (b) applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and 20 (c) storing the second result in the non-volatile memory, thereby indirectly storing the first bit-pattern; wherein the second bit-patterns of the respective devices are relatively unique with respect to each other. Optionally the one way function is more cryptographically secure than the second function. 25 Optionally the second function is a logical function. Optionally the logical function is an XOR function. Optionally the one way function is a hash function.
WO 2005/120835 PCT/AU2004/000706 310 Optionally the one way function is SHAl. Optionally the first bit-pattern is a key. 5 Optionally step (c) comprises, for each device: (d) determining a first memory location; and (e) storing the second result at the first memory location; wherein the first memory locations are different in at least a plurality of the respective devices. 10 Optionally step (d) includes randomly selecting the first memory location. Optionally step (a) includes selecting the first memory location based on a stochastic process or mechanism. 15 Optionally step (a) includes selecting the first memory location from an existing list or sequence of memory locations. Optionally the method further includes the step of storing one or more code segments in the device, the code segments being configured to run on a processor of the device, thereby enabling the device to: 20 apply the one way function to the second bit-pattern, thereby to generate the first result; and apply a third function to the first result and the second result, thereby to generate the first bit-pattern; wherein the third function is the inverse of the second function. Optionally the third function and the second function are the same. 25 Optionally the second bit-patterns have characteristics associated with random numbers. Optionally the second bit-pattern was generated randomly or pseudo-randomly.
WO 2005/120835 PCT/AU2004/000706 311 Optionally the method further includes the step, performed prior to step (a), of determining the second bit-pattern. Optionally determining the second bit-pattern includes generating the second bit-pattern randomly or pseudo 5 randomly. Optionally determining the second bit-pattern includes generating the second bit-pattern based on a stochastic process or mechanism. 10 Optionally there is provided a device manufactured in accordance with the method of storing a first bit-pattern in non-volatile memory of a device, the method comprising: (a) applying a one way function to a second bit-pattern associated with the device, thereby to generate a first result; (b) applying a second function to the first result and the first bit-pattern, thereby to generate a second result; 15 and (c) storing the second result in the memory, thereby indirectly storing the first bit-pattern. Optionally there is provided a device manufactured in accordance with the method including the step of storing one or more code segments in the memory, the code segments being configured to run on a processor of the 20 device, thereby enabling the device to: apply the one way function to the second bit-pattern, thereby to generate the first result; apply a third function to the first result and the second result, thereby to generate the first bit-pattern; wherein the third function is the inverse of the second function. 25 Optionally there is provided a device manufactured in accordance with the method of storing a first bit-pattern in non-volatile memory of each of a plurality of devices, the method comprising, for each of the devices: (a) applying a one way function to a second bit-pattern associated with the device, thereby to generate a first result; (b) applying a second function to the first result and the first bit-pattern, thereby to generate a second result; 30 and WO 2005/120835 PCT/AU2004/000706 312 (c) storing the second result in the non-volatile memory, thereby indirectly storing the first bit-pattern; wherein the second bit-patterns of the respective devices are relatively unique with respect to each other. Optionally there is provided a device manufactured in accordance with the method including the step of storing 5 one or more code segments in the device, the code segments being configured to run on a processor of the device, thereby enabling the device to: apply the one way function to the second bit-pattern, thereby to generate the first result; and apply a third function to the first result and the second result, thereby to generate the first bit-pattern; wherein the third function is the inverse of the second function. 10 Optionally the device having an associated second bit-pattern, and non-volatile memory, the non-volatile memory indirectly storing a first bit-pattern in the form of a second result, the second result being generated by: (a) applying a one way function to the second bit-pattern, thereby to generate a first result; and 15 (b) applying a second function to the first result and the first bit-pattern, thereby to generate the second result. Optionally the device further includes a processor, the processor being configured to run one or more code segments that: 20 (c) apply the one way function to the second bit pattern, thereby to generate the first result; and (d) apply a third function to the first result and the second result, the third function being the inverse of the second function, thereby to generate the first bit-pattern. Optionally the third function and the second function are the same. 25 Optionally the one or more code segments, when run on the processor, use the first bit-pattern in a cryptographic process. Optionally the cryptographic process is digital signing.
WO 2005/120835 PCT/AU2004/000706 313 Optionally the one way function is more cryptographically secure than the second function. Optionally the second function is a logical function. 5 Optionally the logical function is an XOR function. Optionally the one way function is a hash function. 10 Optionally the one way function is SHAl. Optionally the first bit-pattern is a key. Optionally the second bit-pattern was generated randomly or pseudo-randomly. 15 Optionally the second bit-pattern was generated using a stochastic process or mechanism. Optionally there is provided a method implemented in a first entity configured to authenticate a digital signature supplied by a second entity, wherein one of the entities includes a base key and the other of the entities includes a 20 variant key and a bit-pattern, the variant key being based on the result of applying a one way function to the base key and the bit-pattern, the digital signature having been generated by the second entity using its key to digitally signing at least part of data to be authenticated, the first entity being configured to: (a) receive the digital signature from the second entity; (b) receive the data; and 25 (c) authenticate the digital signature based on the received data and the first entity's key. Optionally there is provided a method implemented in a first entity including: a first bit-pattern a non-volatile memory storing resource data, WO 2005/120835 PCT/AU2004/000706 314 a first base key for use with at least a first variant key; a second variant key for use with a second base key, the second variant key being the result of a one way function applied to: the second base key; and the first bit-pattern or a modified bit-pattem based on the first bit pattern. 5 Optionally there is provided a method for enabling or disabling a verification process of a first entity in response to a predetermined event, the first entity having at least one associated bit-pattern and at least one variant key, each of the variant keys having been generated by applying a one way function to: a base key; and one or more of the at least one bit-patterns, respectively; or one or more alternative bit patterns, each of the alternative bit 10 patterns being based on one or the at least one bit-patterns, the method including the method including: (a) determining that the predetermined event has happened; and (b) enabling or disabling at least one of the first variant keys in response the predetermined event. 15 Optionally there is provided a method implemented in a system for enabling authenticated communication between a first entity and at least one other entity, the system including a second entity, wherein: the first entity and the second entity share transport keys; and the second entity includes at least one authentication key configured to be transported from the second 20 entity to the first entity using the transport keys, the authentication key being usable to enable the authenticated communication by the first entity. Optionally there is provided a method for storing a bit-pattern in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: 25 (a) determining a first memory location; and (b) storing the bit-pattern at the first memory location; wherein the first memory locations are different in at least a plurality of the respective devices. Optionally there is provided a method for storing at least one functionally identical code segment in each of a 30 plurality of devices, each of the devices having a memory, the method comprising, for each device: WO 2005/120835 PCT/AU2004/000706 315 (a) determining a first memory location; and (b) storing a first of the at least one code segments in the memory at the first memory location; wherein the first memory location is different in at least a plurality of the respective devices. 5 Optionally there is provided a method for providing a sequence of nonces (RO, RI, R2, ... ) commencing with a current seed of a sequence of seeds (xl, x2, x3,...), the method comprising: (a) applying a one-way function to the current seed, thereby to generate a current nonce; (b) outputting the current nonce; (c) using the current seed to generate a next seed in a sequence of seeds, the seed so generated becoming the 10 current seed; and (c) repeating steps (a) to (c) as required to generate further nonces in the sequence of nonces. Optionally there is provided a method for storing multiple first bit-patterns in non-volatile memory of a device, the method comprising, for each of the first bit-patterns to be stored: 15 (a) applying a one way function to a third bit-pattern based on a second bit-pattern associated with the device, thereby to generate a first result; (b) applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and (c) storing the second result in the memory, thereby indirectly storing the first bit-pattern; 20 wherein the third bit-patterns used for the respective first bit-patterns are relatively unique compared to each other. In a thirty ninth aspect the present invention provides a method of storing a bit-pattern in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: 25 (a) determining a first memory location; and (b) storing the bit-pattern at the first memory location; wherein the first memory locations are different in at least a plurality of the respective devices. Optionally step (a) includes randomly selecting the first memory location. 30 WO 2005/120835 PCT/AU2004/000706 316 Optionally step (a) includes selecting the first memory location based on a stochastic process or mechanism. Optionally step (a) includes selecting the first memory location from an existing list or sequence of memory locations. 5 Optionally the memory is non-volatile memory. Optionally, the method further comprises storing one or more code segments in the memory of each device, the one or more code segments including data indicative of the first memory location at which the bit-pattern is stored 10 on that device. Optionally, wherein the first memory locations of the devices are selected such that, from device to device, there is no overlap of the positions of at least some of the bits, bytes or characters of the devices' respective bit-pattern. 15 Optionally the first memory locations of the devices are selected such that, from device to device, positions of at least some of the bits, bytes or characters of the devices' respective bit-patterns overlap. Optionally the first memory locations of the devices are selected such that, from device to device, bit, byte or character positions of the devices' respective bit-patterns are shuffled, rotated or otherwise ordered differently. 20 Optionally the first memory locations of the devices are selected such that, from device to device, bit, byte or character positions of the devices' respective bit-patterns are shuffled, rotated or otherwise ordered differently. Optionally the method further comprises: 25 applying a function to the first bit pattern and a second bit pattern, thereby to generate a result; and storing the result in the first memory location, thereby indirectly storing the first bit-pattern. Optionally the second bit-pattern is stored with the device.
WO 2005/120835 PCT/AU2004/000706 317 Optionally the second bit-pattern is stored in the device in a non-volatile manner. Optionally the function is a logical function. 5 Optionally the logical function is an XOR function. Optionally the first bit-pattern is a key. Optionally the second bit pattern was generated randomly. 10 Optionally the method further comprises randomly selecting the second bit-pattern. Optionally the method further comprises selecting the second bit-pattern based on a stochastic process or mechanism. 15 Optionally the method further comprises selecting the second bit-pattern from an existing list or sequence of bit patterns. Optionally the first memory locations of the devices are selected such that, from device to device, there is no 20 overlap of the positions of at least some of the bits, bytes or characters of the devices' respective results. Optionally the first memory locations of the devices are selected such that, from device to device, positions of at least some of the bits, bytes or characters of the devices' respective results overlap. 25 Optionally the first memory locations of the devices are selected such that, from device to device, bit, byte or character positions of the devices' respective results are shuffled, rotated or otherwise ordered differently. Optionally the first memory locations of the devices are selected such that, from device to device, bit, byte or character positions of the devices' respective results are shuffled, rotated or otherwise ordered differently.
WO 2005/120835 PCT/AU2004/000706 318 Optionally the respective second bit-patterns are stored at a second memory location of each of the respective devices, wherein the second memory locations are different in at least a plurality of the respective devices. 5 Optionally the second memory locations of the devices are selected such that, from device to device, there is no overlap of the positions of at least some of the bits, bytes or characters of the devices' respective second bit patterns. Optionally the second memory locations of the devices are selected such that, from device to device, positions of 10 at least some of the bits, bytes or characters of the devices' respective second bit-patterns overlap. Optionally the second memory locations of the devices are selected such that, from device to device, bit, byte or character positions of the devices' respective second bit-patterns are shuffled, rotated or otherwise ordered differently. 15 Optionally the second memory locations of the devices are selected such that, from device to device, bit, byte or character positions of the devices' respectives second bit-patterns are shuffled, rotated or otherwise ordered differently. 20 Optionally the method further comprises storing one or more code segments in the memory of each device, the one or more code segments including data indicative of the second memory location at which the second bit pattern is stored on that device. Optionally the method further comprises for each device: 25 determining a second memory location; and storing, at the second memory location, a result of applying a function to the bit-pattern; wherein the second memory locations are different in at least a plurality of the respective devices. Optionally the function is a logical operation. 30 WO 2005/120835 PCT/AU2004/000706 319 Optionally the function is a bit inversion operation. Optionally step (a) includes randomly selecting the second memory location. 5 Optionally step (a) includes selecting the second memory location based on a stochastic process or mechanism. Optionally step (a) includes selecting the second memory location from an existing list or sequence of memory locations. 10 Optionally the memory is non-volatile memory. Optionally the method further comprises storing one or more code segments in the memory of each device, the one or more code segments including data indicative of the second memory location at which the result is stored on that device. 15 Optionally the second memory locations of the devices are selected such that, from device to device, there is no overlap of the positions of at least some of the bits, bytes or characters of the devices' respective results. Optionally the second memory locations of the devices are selected such that, from device to device, positions of 20 at least some of the bits, bytes or characters of the devices' respective results overlap. Optionally the second memory locations of the devices are selected such that, from device to device, bit, byte or character positions of the devices' respective results are shuffled, rotated or otherwise ordered differently. 25 Optionally the second memory locations of the devices are selected such that, from device to device, bit, byte or character positions of the devices' respective results are shuffled, rotated or otherwise ordered differently. Optionally the present invention provides a device having a bit-pattern stored in it in accordance with the method of storing a bit-pattern in each of a plurality of devices, each of the devices having a memory, the method 30 comprising, for each device: WO 2005/120835 PCT/AU2004/000706 320 (a) determining a first memory location; and (b) storing the bit-pattern at the first memory location; wherein the first memory locations are different in at least a plurality of the respective devices. 5 Optionally, in a further embodiment there is provided a device having a bit-pattern and a result stored in it in accordance with the method comprising: applying a function to the first bit pattern and a second bit pattern, thereby to generate a result; and storing the result in the first memory location, thereby indirectly storing the first bit-pattern. 10 Optionally, in a further embodiment there is provided a device having a bit-pattern and a result stored in it in accordance with the method wherein the first memory locations of the devices are selected such that, from device to device, there is no overlap of the positions of at least some of the bits, bytes or characters of the devices' respective results. 15 Optionally there is provided a plurality of devices having respective bit-patterns stored in them in accordance with the method of storing a bit-pattern in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: (a) determining a first memory location; and 20 (b) storing the bit-pattern at the first memory location; wherein the first memory locations are different in at least a plurality of the respective devices. Optionally, in a further embodiment there is provided a plurality of devices having respective bit-patterns and results stored in them in accordance with the method comprising: 25 applying a function to the first bit pattern and a second bit pattern, thereby to generate a result; and storing the result in the first memory location, thereby indirectly storing the first bit-pattern. Optionally there is provided a plurality of devices having respective bit-patterns and results stored in them in accordance with the method wherein the first memory locations of the devices are selected such that, from device WO 2005/120835 PCT/AU2004/000706 321 to device, there is no overlap of the positions of at least some of the bits, bytes or characters of the devices' respective results. Optionally there is provided a device having a bit-pattern stored in it in accordance with the method of storing a 5 bit-pattern in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: (a) determining a first memory location; and (b) storing the bit-pattern at the first memory location; wherein the first memory locations are different in at least a plurality of the respective devices. 10 Optionally there is provided a device having a bit-pattern and a result stored in it in accordance with the method comprising: applying a function to the first bit pattern and a second bit pattern, thereby to generate a result; and storing the result in the first memory location, thereby indirectly storing the first bit-pattern. 15 Optionally there is provided a device having a bit-pattern and a result stored in it in accordance with the method wherein the first memory locations of the devices are selected such that, from device to device, there is no overlap of the positions of at least some of the bits, bytes or characters of the devices' respective results. 20 Optionally there is provided a plurality of devices having respective bit patterns stored in them in accordance with the method of storing a bit-pattern in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: (a) determining a first memory location; and (b) storing the bit-pattern at the first memory location; 25 wherein the first memory locations are different in at least a plurality of the respective devices. Optionally there is provided a plurality of devices having a bit-pattern and a result stored in them in accordance with the method comprising: applying a function to the first bit pattern and a second bit pattern, thereby to generate a result; and 30 storing the result in the first memory location, thereby indirectly storing the first bit-pattern.
WO 2005/120835 PCT/AU2004/000706 322 Optionally there is provided a plurality of devices having a bit-pattern and a result stored in them in accordance with the method wherein the first memory locations of the devices are selected such that, from device to device, there is no overlap of the positions of at least some of the bits, bytes or characters of the devices' respective 5 results. Optionally there is provided a method implemented in a first entity configured to authenticate a digital signature supplied by a second entity, wherein one of the entities includes a base key and the other of the entities includes a variant key and a bit-pattern, the variant key being based on the result of applying a one way function to the base 10 key and the bit-pattern, the digital signature having been generated by the second entity using its key to digitally signing at least part of data to be authenticated, the first entity being configured to: (a) receive the digital signature from the second entity; (b) receive the data; and (c) authenticate the digital signature based on the received data and the first entity's key. 15 Optionally there is provided a method implemented in a first entity including: a first bit-pattern a non-volatile memory storing resource data, a first base key for use with at least a first variant key; 20 a second variant key for use with a second base key, the second variant key being the result of a one way function applied to: the second base key; and the first bit-pattern or a modified bit-pattern based on the first bit pattern. Optionally there is provided a method for enabling or disabling a verification process of a first entity in response 25 to a predetermined event, the first entity having at least one associated bit-pattern and at least one variant key, each of the variant keys having been generated by applying a one way function to: a base key; and one or more of the at least one bit-patterns, respectively; or one or more alternative bit patterns, each of the alternative bit patterns being based on one or the at least one bit-patterns, the method including the method including: 30 (a) determining that the predetermined event has happened; and (b) enabling or disabling at least one of the first variant keys in response the predetermined event.
WO 2005/120835 PCT/AU2004/000706 323 Optionally there is provided a method implemented in a system for enabling authenticated communication between a first entity and at least one other entity, the system including a second entity, wherein: 5 the first entity and the second entity share transport keys; and the second entity includes at least one authentication key configured to be transported from the second entity to the first entity using the transport keys, the authentication key being usable to enable the authenticated communication by the first entity. 10 Optionally there is provided a method for storing a first bit-pattern in non-volatile memory of a device, the method comprising: (a) applying a one way function to a'second bit-pattern associated with the device, thereby to generate a first result; (b) applying a second function to the first result and the first bit-pattern, thereby to generate a second result; 15 and (c) storing the second result in the memory, thereby indirectly storing the first bit-pattern. Optionally there is provided a method for storing at least one functionally identical code segment in each of a 20 plurality of devices, each of the devices having a memory, the method comprising, for each device: (a) determining a first memory location; and (b) storing a first of the at least one code segments in the memory at the first memory location; wherein the first memory location is different in at least a plurality of the respective devices. 25 Optionally there is provided a method for providing a sequence of nonces (RO, RI, R2, ... ) commencing with a current seed of a sequence of seeds (x1, x2, x3,...), the method comprising: (a) applying a one-way function to the current seed, thereby to generate a current nonce; (b) outputting the current nonce; (c) using the current seed to generate a next seed in a sequence of seeds, the seed so generated becoming the 30 current seed; and WO 2005/120835 PCT/AU2004/000706 324 (c) repeating steps (a) to (c) as required to generate further nonces in the sequence of nonces. Optionally there is provided a method for storing multiple first bit-patterns in non-volatile memory of a device, the method comprising, for each of the first bit-patterns to be stored: 5 (a) applying a one way function to a third bit-pattern based on a second bit-pattern associated with the device, thereby to generate a first result; (b) applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and (c) storing the second result in the memory, thereby indirectly storing the first bit-pattern; 10 wherein the third bit-patterns used for the respective first bit-patterns are relatively unique compared to each other. In a fortieth aspect the present invention provides a method of storing at least one functionally identical code segment in each of a plurality of devices, each of the devices having a memory, the method comprising, for each 15 device: (a) determining a first memory location; and (b) storing a first of the at least one code segments in the memory at the first memory location; wherein the first memory location is different in at least a plurality of the respective devices. 20 Optionally at least one of the code segments in each of the devices includes an initial instruction, the initial instruction being located at an initial instruction location, the initial instruction location being the same in all the devices. Optionally the initial instruction in each device is indicative of the first memory location of that device. 25 Optionally the initial instruction is indicative of the first memory location by including an explicit reference to the memory location. Optionally the initial instruction is indicative of the first memory location by including an implicit reference to the 30 memory location.
WO 2005/120835 PCT/AU2004/000706 325 Optionally the implicit reference is a pointer to a location at which the address of the first memory location is stored. 5 Optionally the implicit reference is a pointer to a register that holds the address of the first memory location. Optionally step (a) includes randomly selecting the first memory location. Optionally step (a) includes selecting the first memory location based on a stochastic process or mechanism. 10 Optionally step (a) includes selecting the first memory location from an existing list or sequence of memory locations. Optionally each device including at least one additional memory location, each of the at least one code segments 15 being located at the first memory location or one of the additional memory locations, wherein each of the code segments includes at least one instruction that is indicative of one of the at least one additional memory locations or of the first memory location, and wherein at least one of the additional memory locations corresponding to one of the code segments is different in at least a plurality of the respective devices. 20 Optionally the at least one instruction is indicative of the additional or first memory location by including an explicit reference to the memory location. Optionally the at least one instruction is indicative of the additional or first memory location by including an implicit reference to the memory location. 25 Optionally the implicit reference is a pointer to a location at which the address of the additional or first memory location is stored. Optionally the implicit reference is a pointer to a register that holds the address of the additional or first memory 30 location.
WO 2005/120835 PCT/AU2004/000706 326 Optionally the implicit reference is an index into an address table wherein the address table holds the location of the additional or first memory location. 5 Optionally the memory is non-volatile memory. Optionally the memory is non-volatile memory. Optionally there is provided a method implemented in a first entity configured to authenticate a digital signature 10 supplied by a second entity, wherein one of the entities includes a base key and the other of the entities includes a variant key and a bit-pattern, the variant key being based on the result of applying a one way function to the base key and the bit-pattern, the digital signature having been generated by the second entity using its key to digitally signing at least part of data to be authenticated, the first entity being configured to: (a) receive the digital signature from the second entity; 15 (b) receive the data; and (c) authenticate the digital signature based on the received data and the first entity's key. Optionally there is provided a method implemented in a first entity including: a first bit-pattern 20 a non-volatile memory storing resource data, a first base key for use with at least a first variant key; a second variant key for use with a second base key, the second variant key being the result of a one way function applied to: the second base key; and the first bit-pattern or a modified bit-pattern based on the first bit pattern. 25 Optionally there is provided a method for enabling or disabling a verification process of a first entity in response to a predetermined event, the first entity having at least one associated bit-pattern and at least one variant key, each of the variant keys having been generated by applying a one way function to: a base key; and one or more of WO 2005/120835 PCT/AU2004/000706 327 the at least one bit-patterns, respectively; or one or more alternative bit patterns, each of the alternative bit patterns being based on one or the at least one bit-patterns, the method including the method including: (a) determining that the predetermined event has happened; and 5 (b) enabling or disabling at least one of the first variant keys in response the predetermined event. Optionally there is provided a method implemented in a system for enabling authenticated communication between a first entity and at least one other entity, the system including a second entity, wherein: 10 the first entity and the second entity share transport keys; and the second entity includes at least one authentication key configured to be transported from the second entity to the first entity using the transport keys, the authentication key being usable to enable the authenticated communication by the first entity. 15 Optionally there is provided a method for storing a first bit-pattern in non-volatile memory of a device, the method comprising: (a) applying a one way function to a second bit-pattern associated with the device, thereby to generate a first result; 20 (b) applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and (c) storing the second result in the memory, thereby indirectly storing the first bit-pattern. 25 Optionally there is provided a method for storing a bit-pattern in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: (a) determining a first memory location; and (b) storing the bit-pattern at the first memory location; wherein the first memory locations are different in at least a plurality of the respective devices. 30 WO 2005/120835 PCT/AU2004/000706 328 Optionally there is provided a method for providing a sequence of nonces (RO, RI, R2, ... ) commencing with a current seed of a sequence of seeds (xl, x2, x3,...), the method comprising: (a) applying a one-way function to the current seed, thereby to generate a current nonce; (b) outputting the current nonce; 5 (c) using the current seed to generate a next seed in a sequence of seeds, the seed so generated becoming the current seed; and (c) repeating steps (a) to (c) as required to generate further nonces in the sequence of nonces. Optionally there is provided a method for storing multiple first bit-patterns in non-volatile memory of a device, 10 the method comprising, for each of the first bit-patterns to be stored: (a) applying a one way function to a third bit-pattern based on a second bit-pattern associated with the device, thereby to generate a first result; (b) applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and 15 (c) storing the second result in the memory, thereby indirectly storing the first bit-pattern; wherein the third bit-patterns used for the respective first bit-patterns are relatively unique compared to each other. 20 In a forty first aspect the present invention provides a method for providing a sequence of nonces (RO, RI, R2, ... ) commencing with a current seed of a sequence of seeds (xl, x2, x3,...), the method comprising: (a) applying a one-way function to the current seed, thereby to generate a current nonce; (b) outputting the current nonce; (c) using the current seed to generate a next seed in a sequence of seeds, the seed so generated becoming the 25 current seed; and (c) repeating steps (a) to (c) as required to generate further nonces in the sequence of nonces. Optionally x1 is generated based on an initial seed x0, the initial seed having been generated by a random number generator. 30 WO 2005/120835 PCT/AU2004/000706 329 Optionally, the initial seed x having been generated based on a stochastic process. Optionally the next seed is generated from the current seed on the basis of a second function. 5 Optionally the second function is less cryptographically strong than the one way function. Optionally the second function is additive. Optionally the second function is a linear feedback shift register function. 10 Optionally the one way function is a hash function. Optionally the hash function is SHAL. 15 In a further aspect the present invention provides a device for generating a sequence of nonces (RO, RI, R2,...), the device including: memory for storing a current seed of a sequence of seeds (x1, x2, x3....)' a processor configured to: (a) apply a one way function to the current seed to generate a current nonce; and 20 (b) use the current seed to generate a next seed in the sequence of seeds, the seed so generated becoming the current seed; and (c) storing the current seed in memory. Optionally the device is configured to generate x1 in the seed sequence based on an initial seed x0, the initial seed 25 being stored in a non-volatile manner in the device. Optionally xO was generated by a random number generator.
WO 2005/120835 PCT/AU2004/000706 330 Optionally, the initial seed xO having been generated based on a stochastic process. Optionally the processor is configured to generate the next seed by applying a second function to the current seed. 5 Optionally the second function is less cryptographically strong than the one way function. Optionally the second function is additive. Optionally the second function is a linear feedback shift register function. 10 Optionally the memory is non-volatile. Optionally the memory is flash memory. 15 Optionally the device comprises one or more integrated circuits. Optionally the device comprises a monolithic integrated circuit. Optionally the one way function is a hash function. 20 Optionally the hash function is SHAl. In a further aspect the present invention provides a method of manufacturing a series of devices, each of the devices for generating a sequence of nonces (RO, RI, R2, ... ), the device including: 25 memory for storing a current seed of a sequence of seeds (xl, x2, x3,...)' a processor configured to: (a) apply a one way function to the current seed to generate a current nonce; and WO 2005/120835 PCT/AU2004/000706 331 (b) use the current seed to generate a next seed in the sequence of seeds, the seed so generated becoming the current seed; and (c) storing the current seed in memory. and including a non-volatile memory, the method comprising: 5 generating a bit-pattern on the basis of a random or pseudo random process; storing the bit-pattern in a non-volatile manner in the device; wherein the device is configured to use the bit-pattern as an initial current seed, and to store subsequent generated seeds in the non-volatile memory. 10 Optionally the step of storing the bit-pattern in a non-volatile manner includes storing the value in a place other than in the non-volatile memory. Optionally the bit-pattern is stored in non-erasable form. 15 Optionally the method including the step of storing a program on the device, the program including the one way function for generating the current nonce from the current seed. Optionally the one way function is a hash function. 20 Optionally the one way function is non-compressing. Optionally the hash function is SHAl. Optionally there is provided a method implemented in a first entity configured to authenticate a digital signature 25 supplied by a second entity, wherein one of the entities includes a base key and the other of the entities includes a variant key and a bit-pattern, the variant key being based on the result of applying a one way function to the base key and the bit-pattern, the digital signature having been generated by the second entity using its key to digitally signing at least part of data to be authenticated, the first entity being configured to: (a) receive the digital signature from the second entity; 30 (b) receive the data; and WO 2005/120835 PCT/AU2004/000706 332 (c) authenticate the digital signature based on the received data and the first entity's key. Optionally there is provided a method implemented in a first entity including: 5 a first bit-pattern a non-volatile memory storing resource data, a first base key for use with at least a first variant key; a second variant key for use with a second base key, the second variant key being the result of a one way function applied to: the second base key; and the first bit-pattern or a modified bit-pattern based on the first bit 10 pattern. Optionally there is provided a method for enabling or disabling a verification process of a first entity in response to a predetermined event, the first entity having at least one associated bit-pattern and at least one variant key, 15 each of the variant keys having been generated by applying a one way function to: a base key; and one or more of the at least one bit-patterns, respectively; or one or more alternative bit patterns, each of the alternative bit patterns being based on one or the at least one bit-patterns, the method including the method including: (a) determining that the predetermined event has happened; and 20 (b) enabling or disabling at least one of the first variant keys in response the predetermined event. Optionally there is provided a method implemented in a system for enabling authenticated communication between a first entity and at least one other entity, the system including a second entity, wherein: 25 the first entity and the second entity share transport keys; and the second entity includes at least one authentication key configured to be transported from the second entity to the first entity using the transport keys, the authentication key being usable to enable the authenticated communication by the first entity.
WO 2005/120835 PCT/AU2004/000706 333 Optionally there is provided a method for storing a first bit-pattern in non-volatile memory of a device, the method comprising: (a) applying a one way function to a second bit-pattern associated with the device, thereby to generate a first result; 5 (b) applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and (c) storing the second result in the memory, thereby indirectly storing the first bit-pattern. 10 Optionally there is provided a method for storing a bit-pattern in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: (a) determining a first memory location; and (b) storing the bit-pattern at the first memory location; wherein the first memory locations are different in at least a plurality of the respective devices. 15 Optionally there is provided a method for storing at least one functionally identical code segment in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: (a) determining a first memory location; and 20 (b) storing a first of the at least one code segments in the memory at the first memory location; wherein the first memory location is different in at least a plurality of the respective devices. Optionally there is provided a method for storing multiple first bit-patterns in non-volatile memory of a device, 25 the method comprising, for each of the first bit-patterns to be stored: (a) applying a one way function to a third bit-pattern based on a second bit-pattern associated with the device, thereby to generate a first result; (b) applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and 30 (c) storing the second result in the memory, thereby indirectly storing the first bit-pattern; WO 2005/120835 PCT/AU2004/000706 334 wherein the third bit-patterns used for the respective first bit-patterns are relatively unique compared to each other. 5 In a forty second aspect the present invention provides a method of storing multiple first bit-patterns in non volatile memory of a device, the method comprising, for each of the first bit-patterns to be stored: (a) applying a one way function to a third bit-pattern based on a second bit-pattern associated with the device, thereby to generate a first result; (b) applying a second function to the first result and the first bit-pattern, thereby to generate a second result; 10 and (c) storing the second result in the memory, thereby indirectly storing the first bit-pattern; wherein the third bit-patterns used for the respective first bit-patterns are relatively unique compared to each other. 15 Optionally step (c) comprises: (d) determining a first memory location; and (e) storing the second result at the first memory location. Optionally step (d) includes randomly selecting the first memory location. 20 Optionally step (d) includes selecting the first memory location based on a stochastic process or mechanism. Optionally step (d) includes selecting the first memory location from an existing list or sequence of memory locations. 25 Optionally each third bit-pattern is generated from the second bit-pattern by removing, adding or changing one or more bits, bytes or characters of the second bit-pattern.
WO 2005/120835 PCT/AU2004/000706 335 Optionally each third bit-pattern is generated from the second bit-pattem by adding an index of one or more bits, bytes or characters to the second bit-pattern, the index having been added at any position of the identifier, including being appended before or after the identifier, or being distributed within the identifier. 5 Optionally the index added to the second bit-pattern for the respective second bit-patterns is derived from a series of indices. Optionally the method includes the step of generating the index as required. 10 Optionally the one way function is more cryptographically secure than the second function. Optionally the second function is a logical function. Optionally the logical function is an XOR function. 15 Optionally the one way function is a hash function. Optionally each of the first bit-patterns is a key. 20 Optionally the method further includes the step of storing one or more code segments in the memory, the code segments being configured to run on a processor of the device, thereby enabling the device to, for each of first bit patterns to be retrieved: generate the third-bit pattern corresponding to the first bit pattern to be retrieved; apply the one way function to the third bit-pattern, thereby to generate the first result; and 25 apply a third function to the first result and the second result corresponding to the first bit-pattern to be retrieved, thereby to generate that first bit-pattern; wherein the third function is the inverse of the second function. Optionally the third function and the second function are the same.
WO 2005/120835 PCT/AU2004/000706 336 Optionally the second bit-pattern was generated randomly or pseudo-randomly. Optionally method further including the step, performed prior to step (a), of determining the second bit-pattern. 5 Optionally determining the second bit-pattern includes generating the second bit-pattern randomly or pseudo randomly. Optionally determining the second bit-pattern includes generating the second bit-pattern based on a stochastic 10 process or mechanism. Optionally determining the second bit-pattern includes selecting the second-bit pattern from an existing list or sequence of bit-patterns. 15 In a further aspect the present invention provides a method of storing multiple first bit-patterns in non-volatile memory of each of a plurality of devices, the method comprising, for each of the first bit-patterns to be stored: (a) applying a one way function to a third bit-pattern based on a second bit-pattern associated with the device, thereby to generate a first result; (b) applying a second function to the first result and the first bit-pattern, thereby to generate a second result; 20 and (c) storing the second result in the memory, thereby indirectly storing the first bit-pattern; wherein the third bit-patterns used for the respective first bit-patterns in each device are relatively unique with respect to each other, and the second bit-patterns of the respective devices are relatively unique with respect to each other. 25 Optionally step (c) comprises, for each device: (d) determining a first memory location; and (e) storing the second result at the first memory location. 30 Optionally step (d) includes randomly selecting the first memory location.
WO 2005/120835 PCT/AU2004/000706 337 Optionally step (d) includes selecting the first memory location based on a stochastic process or mechanism. Optionally step (d) includes selecting the first memory location from an existing list or sequence of memory 5 locations. Optionally the first memory locations of the devices are selected such that, from device to device, there is no overlap of the positions of at least some of the bits, bytes or characters of the devices' respective second results. 10 Optionally the first memory locations of the devices are selected such that, from device to device, positions of at least some of the bits, bytes or characters of the devices' respective second results overlap. Optionally the first memory locations of the devices are selected such that, from device to device, bit, byte or character positions of the devices' respective second results are shuffled, rotated or otherwise ordered differently. 15 Optionally the first memory locations of the devices are selected such that, from device to device, bit, byte or character positions of the devices' respective second results are shuffled, rotated or otherwise ordered differently. Optionally for each device, each third bit-pattern is generated from the second bit-pattern by removing, adding or 20 changing one or more bits, bytes or characters of the second bit-pattern. Optionally for each device, each third bit-pattern is generated from the second bit-pattern by adding an index of one or more bits, bytes or characters to the second bit-pattern, the index having been added at any position of the identifier, including being distributed within the identifier. 25 Optionally the index added to the second bit-pattern for the respective second bit-patterns is derived from a series of indices. Optionally the method includes the step, for each device, of generating the index as required. 30 WO 2005/120835 PCT/AU2004/000706 338 Optionally the one way function is more cryptographically secure than the second function. Optionally the second function is a logical function. 5 Optionally the logical function is an XOR function. Optionally the one way function is a hash function. Optionally each of the first bit-patterns is a key. 10 Optionally the method further includes the step of storing one or more code segments in the memory of each device, the code segments being configured to run on a processor of each device, thereby enabling each device to, for each of first bit-patterns to be retrieved: generate the third-bit pattern corresponding to the first bit pattern to be retrieved; 15 apply the one way function to the third bit-pattern, thereby to generate the first result; and apply a third function to the first result and the second result corresponding to the first bit-pattern to be retrieved, thereby to generate that first bit-pattern; wherein the third function is the inverse of the second function. 20 Optionally the third function and the second function are the same. Optionally the second bit-pattern for each device was generated randomly or pseudo-randomly. Optionally the second bit-pattern for each device was generated based on a stochastic process or mechanism. 25 Optionally there is provided a device manufactured in accordance with the method of storing multiple first bit patterns in non-volatile memory of a device, the method comprising, for each of the first bit-patterns to be stored: (a) applying a one way function to a third bit-pattern based on a second bit-pattern associated with the device, thereby to generate a first result; WO 2005/120835 PCT/AU2004/000706 339 (b) applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and (c) storing the second result in the memory, thereby indirectly storing the first bit-pattern; wherein the third bit-patterns used for the respective first bit-patterns are relatively unique compared to 5 each other. Optionally there is provided a device manufactured in accordance with the method of method of storing multiple first bit-patterns in non-volatile memory of a device, the method comprising, for each of the first bit-patterns to be 10 stored: (a) applying a one way function to a third bit-pattern based on a second bit-pattern associated with the device, thereby to generate a first result; (b) applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and 15 (c) storing the second result in the memory, thereby indirectly storing the first bit-pattern; wherein the third bit-patterns used for the respective first bit-patterns are relatively unique compared to each other; andfurther including the step of storing one or more code segments in the memory, the code segments being configured to run on a processor of the device, thereby enabling the device to, for each of first bit-patterns to be retrieved: 20 generate the third-bit pattern corresponding to the first bit pattern to be retrieved; apply the one way function to the third bit-pattern, thereby to generate the first result; and apply a third function to the first result and the second result corresponding to the first bit-pattern to be retrieved, thereby to generate that first bit-pattern; wherein the third function is the inverse of the second function. 25 Optionally there is provided a plurality of devices manufactured in accordance with the method of storing multiple first bit-patterns in non-volatile memory of each of a plurality of devices, the method comprising, for each of the first bit-patterns to be stored: (a) applying a one way function to a third bit-pattern based on a second bit-pattern associated with the 30 device, thereby to generate a first result; WO 2005/120835 PCT/AU2004/000706 340 (b) applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and (c) storing the second result in the memory, thereby indirectly storing the first bit-pattern; wherein the third bit-patterns used for the respective first bit-patterns in each device are relatively unique 5 with respect to each other, and the second bit-patterns of the respective devices are relatively unique with respect to each other. Optionally there is provided a plurality of devices manufactured in accordance with the of method of storing multiple first bit-patterns in non-volatile memory of each of a plurality of devices, the method comprising, for 10 each of the first bit-patterns to be stored: (a) applying a one way function to a third bit-pattern based on a second bit-pattern associated with the device, thereby to generate a first result; (b) applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and 15 (c) storing the second result in the memory, thereby indirectly storing the first bit-pattern; wherein the third bit-patterns used for the respective first bit-patterns in each device are relatively unique with respect to each other, and the second bit-patterns of the respective devices are relatively unique with respect to each other; and further including the step of storing one or more code segments in the memory of each device, the code segments being configured to run on a 20 processor of each device, thereby enabling each device to, for each of first bit-patterns to be retrieved: generate the third-bit pattern corresponding to the first bit pattern to be retrieved; apply the one way function to the third bit-pattern, thereby to generate the first result; and apply a third function to the first result and the second result corresponding to the first bit-pattern to be retrieved, thereby to generate that first bit-pattern; 25 wherein the third function is the inverse of the second function. Optionally there is provided a method implemented in a first entity configured to authenticate a digital signature supplied by a second entity, wherein one of the entities includes a base key and the other of the entities includes a variant key and a bit-pattern, the variant key being based on the result of applying a one way function to the base 30 key and the bit-pattern, the digital signature having been generated by the second entity using its key to digitally signing at least part of data to be authenticated, the first entity being configured to: WO 2005/120835 PCT/AU2004/000706 341 (a) receive the digital signature from the second entity; (b) receive the data; and (c) authenticate the digital signature based on the received data and the first entity's key. 5 Optionally there is provided a method implemented in a first entity including: a first bit-pattern a non-volatile memory storing resource data, a first base key for use with at least a first variant key; 10 a second variant key for use with a second base key, the second variant key being the result of a one way function applied to: the second base key; and the first bit-pattern or a modified bit-pattern based on the first bit pattern. 15 Optionally there is provided a method for enabling or disabling a verification process of a first entity in response to a predetermined event, the first entity having at least one associated bit-pattern and at least one variant key, each of the variant keys having been generated by applying a one way function to: a base key; and one or more of the at least one bit-patterns, respectively; or one or more alternative bit patterns, each of the alternative bit patterns being based on one or the at least one bit-patterns, the method including 20 the method including: (a) determining that the predetermined event has happened; and (b) enabling or disabling at least one of the first variant keys in response the predetermined event. 25 Optionally there is provided a method implemented in a system for enabling authenticated communication between a first entity and at least one other entity, the system including a second entity, wherein: the first entity and the second entity share transport keys; and the second entity includes at least one authentication key configured to be transported from the second entity to the first entity using the transport keys, the authentication key being usable to enable the authenticated 30 communication by the first entity.
WO 2005/120835 PCT/AU2004/000706 342 Optionally there is provided a method for storing a first bit-pattern in non-volatile memory of a device, the method comprising: (a) applying a one way function to a second bit-pattern associated with the device, thereby to generate a first 5 result; (b) applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and (c) storing the second result in the memory, thereby indirectly storing the first bit-pattern. 10 A method according to claim 1, for storing a bit-pattern in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: (a) determining a first memory location; and (b) storing the bit-pattern at the first memory location; 15 wherein the first memory locations are different in at least a plurality of the respective devices. Optionally there is provided a method for storing at least one functionally identical code segment in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: (a) determining a first memory location; and 20 (b) storing a first of the at least one code segments in the memory at the first memory location; wherein the first memory location is different in at least a plurality of the respective devices. Optionally there is provided a method for providing a sequence of nonces (RO, R1, R2, ... ) commencing with a current seed of a sequence of seeds (xl, x2, x3,...), the method comprising: 25 (a) applying a one-way function to the current seed, thereby to generate a current nonce; (b) outputting the current nonce; (c) using the current seed to generate a next seed in a sequence of seeds, the seed so generated becoming the current seed; and (c) repeating steps (a) to (c) as required to generate further nonces in the sequence of nonces.
WO 2005/120835 PCT/AU2004/000706 343 BRIEF DESCRIPTION OF THE DRAWINGS Figure 1. Example State machine notation Figure 2. Single SoPEC A4 Simplex system Figure 3. Dual SoPEC A4 Simplex system 5 Figure 4. Dual SoPEC A4 Duplex system Figure 5. Dual SoPEC A3 simplex system Figure 6. Quad SoPEC A3 duplex system Figure 7. SoPEC A4 Simplex system with extra SoPEC used as DRAM storage Figure 8. SoPEC A4 Simplex system with network connection to Host PC 10 Figure 9. Document data flow Figure 10. Pages containing different numbers of bands Figure 11. Contents of a page band Figure 12. Page data path from host to SoPEC Figure 13. Page structure 15 Figure 14. SoPEC System Top Level partition Figure 15. Proposed SoPEC CPU memory map (not to scale) Figure 16. Possible USB Topologies for Multi-SoPEC systems Figure 17. CPU block diagram Figure 18. CPU bus transactions 20 Figure 19. State machine for a CPU subsystem slave Figure 20. Proposed SoPEC CPU memory map (not to scale) Figure 21. MMU Sub-block partition, exteral signal view Figure 22. MMU Sub-block partition, integral signal view Figure 23. DRAM Write buffer 25 Figure 24. DIU waveforms for multiple transactions Figure 25. SoPEC LEON CPU core Figure 26. Cache Data RAM wrapper Figure 27. Realtime Debug Unit block diagram Figure 28. Interrupt acknowledge cycles for a single and pending interrupts 30 Figure 29. UHU Dataflow Figure 30. UHU Basic Block Diagram Figure 31. ehci ohci Basic Block Diagram. Figure 32. uhu-ctl Figure 33. uhu dma 35 Figure 34. EHCI DIU Buffer Partition Figure 35. UDU Sub-block Partition Figure 36. Local endpoint packet buffer partitioning Figure 37. Circular buffer operation Figure 38. Overview of Control Transfer State Machine 40 Figure 39. Writing a Setup packet at the start of a Control-In transfer WO 2005/120835 PCT/AU2004/000706 344 Figure 40. Reading Control-In data Figure 41. Status stage of Control-In transfer Figure 42. Writing Control-Out data Figure 43. Reading Status In data during a Control-Out transfer 5 Figure 44. Reading bulk/interrupt IN data Figure 45. A bulk OUT transfer Figure 46. VCI slave port bus adapter Figure 47. Duty Cycle Select Figure 48. Low Pass filter structure 10 Figure 49. GPIO partition Figure 50. GPIO Partition (continued) Figure 51. LEON UART block diagram Figure 52. Input de-glitch RTL diagram Figure 53. Motor control RTh diagram 15 Figure 54. BLDC controllers RTL diagram Figure 55. Period Measure RTL diagram Figure 56. Frequency Modifier sub-block partition Figure 57. Fixed point bit allocation Figure 58. Frequency Modifier structure 20 Figure 59. Line sync generator diagram Figure 60. HSI timing diagram Figure 61. Centronic interface timing diagram Figure 62. Parallel Port EPP read and write transfers Figure 63. ECP forward Data and command cycles 25 Figure 64. ECP Reverse Data and command cycles Figure 65. 68K example read and w-rite access Figure 66. Non burst, non pipeline read and write accesses with wait states Figure 67. Generic Flash Read and Write operation Figure 68. Serial flash example 1 byte read and write protocol 30 Figure 69. MMI sub-block partition Figure 70. MMI Engine sub-block diagram Figure 71. Instruction field bit allocation Figure 72. Circular buffer operation Figure 73. ICU partition 35 Figure 74. Interrupt clear state diagram Figure 75. Timers sub-block partition diagram Figure 76. Watchdog timer RTL diagram Figure 77. Generic timer RTL diagram Figure 78. Pulse generator RTL diagram 40 Figure 79. SoPEC clock relationship WO 2005/120835 PCT/AU2004/000706 345 Figure 80. CPR block partition Figure 81. Reset Macro block structure Figure 82. Reset control logic state machine Figure 83. PLL and Clock divider logic 5 Figure 84. PLL control state machine diagram Figure 85. Clock gate logic diagram Figure 86. SoPEC clock distribution diagram Figure 87. Sub-block partition of the ROM block Figure 88. LSS master system-level interface 10 Figure 89. START and STOP conditions Figure 90. LSS transfer of 2 data bytes Figure 91. Example of LSS write to a QA Chip Figure 92. Example of LSS read from QA Chip Figure 93. LSS block diagram 15 Figure 94. Example LSS multi-command transaction Figure 95. Start and stop generation based on previous bus state Figure 96. S master state machine Figure 97. LSS Master timing Figure 98. SoPEC System Top Level partition 20 Figure 99. Shared read bus with 3 cycle random DRAM read accesses Figure 100. Interleaving CPU and non-CPU read accesses Figure 101. Interleaving read and write accesses with 3 cycle random DRAM accesses Figure 102. Interleaving write accesses with 3 cycle random DRAM accesses Figure 103. Read protocol for a SoPEC Unit making a single 256-bit access 25 Figure 104. Read protocol for a CPU making a single 256-bit access Figure 105. Write Protocol shown for a SoPEC Unit making a single 256-bit access Figure 106. Protocol for a posted, masked, 128-bit write by the CPU. Figure 107. Write Protocol shown for CDU making four contiguous 64-bit accesses Figure 108. Timeslot based arbitration 30 Figure 109. Timeslot based arbitration with separate pointers Figure 110. Example (a), separate read and write arbitration Figure 111. Example (b), separate read and write arbitration Figure 112. Example (c), separate read and write arbitration Figure 113. DIU Partition 35 Figure 114. DIU Partition Figure 115. Multiplexing and address translation logic for two memory instances Figure 116. Timing of dau-dcu-valid, dcu-dau_adv and dcu-dau-wadv Figure 117. DCU state machine Figure 118. Random read timing 40 Figure 119. Random write timing WO 2005/120835 PCT/AU2004/000706 346 Figure 120. Refresh timing Figure 121. Page mode write timing Figure 122. Timing of non-CPU DIU read access Figure 123. Timing of CPU DIU read access 5 Figure 124. CPU DIU read access Figure 125. Timing of CPU DIU write access Figure 126. Timing of a non-CDU / non-CPU DIU write access Figure 127. Timing of CDU DIU write access Figure 128. Command multiplexor sub-block partition 10 Figure 129. Command Multiplexor timing at DIU requestors interface Figure 130. Generation of re-arbitrate and re-arbitrate-wadv Figure 131. CPU Interface and Arbitration Logic Figure 132. Arbitration timing Figure 133. Setting RotationSync to enable a new rotation. 15 Figure 134. Timeslot based arbitration Figure 135. Timeslot based arbitration with separate pointers Figure 136. CPU pre-access write lookahead pointer Figure 137. Arbitration hierarchy Figure 138. Hierarchical round-robin priority comparison 20 Figure 139. Read Multiplexor partition. Figure 140. Read Multiplexor timing Figure 141. Read command queue (4 deep buffer) Figure 142. State-machines for shared read bus accesses Figure 143. Read Multiplexor timing for back to back shared read bus transfers 25 Figure 144. Write multiplexor partition Figure 145. Block diagram of PCU Figure 146. PCU accesses to PEP registers Figure 147. Command Arbitration and execution Figure 148. DRAM command access state machine 30 Figure 149. Outline of condone data flow with respect to CDU Figure 150. Block diagram of CDU Figure 151. State machine to read compressed condone data Figure 152. DRAM storage arrangement for a single line of JPEG 8x8 blocks in 4 colors Figure 153. State machine to write decompressed condone data 35 Figure 154. Lead-in and lead-out clipping of condone data in multi-SoPEC environment Figure 155. Block diagram of CFU Figure 156. DRAM storage arrangement for a single line of JPEG blocks in 4 colors Figure 157. State machine to read decompressed condone data from DRAM Figure 158. Block diagram of color space converter 40 Figure 159. High level block diagram of LBD in context WO 2005/120835 PCT/AU2004/000706 347 Figure 160. Schematic outline of the LBD and the SFU Figure 161. Block diagram of lossless bi-level decoder Figure 162. Stream decoder block diagram Figure 163. Command controller block diagram 5 Figure 164. State diagram for the Command Controller (CC) state machine Figure 165. Next Edge Unit block diagram Figure 166. Next edge unit buffer diagram Figure 167. Next edge unit edge detect diagram Figure 168. State diagram for the Next Edge Unit (NEU) state machine 10 Figure 169. Line fill unit block diagram Figure 170. State diagram for the Line Fill Unit (LFU) state machine Figure 171. Bi-level DRAM buffer Figure 172. Interfaces between LBD/SFU/HCU Figure 173. SFU Sub-Block Partition 15 Figure 174. LBDPrevLineFifo Sub-block Figure 175. Timing of signals on the LBDPrevLineFIFO interface to DIU and Address Generator Figure 176. Timing of signals on LBDPrevLineFIFO interface to DIU and Address Generator Figure 177. LBDNextLineFifo Sub-block Figure 178. Timing of signals on LBDNextLineFIFO interface to DIU and Address Generator 20 Figure 179. LBDNextLineFIFO DIU Interface State Diagram Figure 180. LDB to SFU write interface Figure 181. LDB to SFU read interface (within a line) Figure 182. HCUReadLineFifo Sub-block Figure 183. DIU Write Interface 25 Figure 184. DIU Read Interface multiplexing by selecthrfpIf Figure 185. DIU read request arbitration logic Figure 186. Address Generation Figure 187. X scaling control unit Figure 188. Y scaling control unit 30 Figure 189. Overview of X and Y scaling at HCU interface Figure 190. High level block diagram of TE in context Figure 191. Example QR Code developed by Denso of Japan Figure 192. Netpage tag structure Figure 193. Netpage tag with data rendered at 1600 dpi (magnified view) 35 Figure 194. Example of 2x2 dots for each block of QR code Figure 195. Placement of tags for portrait & landscape printing Figure 196. General representation of tag placement Figure 197. Composition of SoPEC's tag format structure Figure 198. Simple 3x3 tag structure 40 Figure 199. 3x3 tag redesigned for 21 x 21 area (not simple replication) WO 2005/120835 PCT/AU2004/000706 348 Figure 200. TE Block Diagram Figure 201. TE Hierarchy Figure 202. Tag Encoder Top-Level FSM Figure 203. Logic to combine dot information and Encoded Data 5 Figure 204. Generation of Lastdotintag Figure 205. Generation of Dot Position Valid Figure 206. Generation of write enable to the TFU Figure 207. Generation of Tag Dot Number Figure 208. TDI Architecture 10 Figure 209. Data Flow Through the TDI Figure 210. Raw tag data interface block diagram Figure 211. RTDI State Flow Diagram Figure 212. Relationship between teendoftagdata, testartofbandstore and teendofbandstore Figure 213. TDi State Flow Diagram 15 Figure 214. Mapping of the tag data to codewords 0-7 for (15,5) encoding. Figure 215. Coding and mapping of uncoded Fixed Tag Data for (15,5) RS encoder Figure 216. Mapping of pre-coded Fixed Tag Data Figure 217. Coding and mapping of Variable Tag Data for (15,7) RS encoder Figure 218. Coding and mapping of uncoded Fixed Tag Data for (15,7) RS encoder 20 Figure 219. Mapping of 2D decoded Variable Tag Data, DataRedun = 0 Figure 220. Simple block diagram for an m=4 Reed Solomon Encoder Figure 221. RS Encoder 1/0 diagram Figure 222. (15,5) & (15,7) RS Encoder block diagram Figure 223. (15,5) RS Encoder timing diagram 25 Figure 224. (15,7) RS Encoder timing diagram Figure 225. Circuit for multiplying by a3 Figure 226. Adding two field elements, (15,5) encoding. Figure 227. RS Encoder Implementation Figure 228. encoded tag data interface 30 Figure 229. Breakdown of the Tag Format Structure Figure 230. TFSI FSM State Flow Diagram Figure 231. TFS Block Diagram Figure 232. Table A address generator Figure 233. Table C interface block diagram 35 Figure 234. Table B interface block diagram Figure 235. Interfaces between TE, TFU and HCU Figure 236. 16-byte FIFO in TFU Figure 237. High level block diagram showing the HCU and its external interfaces Figure 238. Block diagram of the HCU 40 Figure 239. Block diagram of the control unit WO 2005/120835 PCT/AU2004/000706 349 Figure 240. Block diagram of determine advdot unit Figure 241. Page structure Figure 242. Block diagram of margin unit Figure 243. Block diagram of dither matrix table interface 5 Figure 244. Example reading lines of dither matrix from DRAM Figure 245. State machine to read dither matrix table Figure 246. Contone dotgen unit Figure 247. Block diagram of dot reorg unit Figure 248. HCU to DNC interface (also used in DNC to DWU, LLU to PHI) 10 Figure 249. SFU to HCU (all feeders to HCU) Figure 250. Representative logic of the SFU to HCU interface Figure 251. High level block diagram of DNC Figure 252. Dead nozzle table format Figure 253. Set of dots operated on for error diffusion 15 Figure 254. Block diagram of DNC Figure 255. Sub-block diagram of ink replacement unit Figure 256. Dead nozzle table state machine Figure 257. Logic for dead nozzle removal and ink replacement Figure 258. Sub-block diagram of error diffusion unit 20 Figure 259. Maximum length 32-bit LFSR used for random bit generation Figure 260. High level data flow diagram of DWU in context Figure 261. Printhead Nozzle Layout for conceptual 36 Nozzle AB single segment printhead Figure 262. Paper and printhead nozzles relationship (example with Di=D 2 =5) Figure 263. Dot line store logical representation 25 Figure 264. Conceptual view of 2 adjacent printhead segments possible row alignment Figure 265. Conceptual view of 2 adjacent printhead segments row alignment (as seen by the LLU) Figure 266. Even dot order in DRAM (13312 dot wide line) Figure 267. Dotline FIFO data structure in DRAM (LLU specification) Figure 268. DWU partition 30 Figure 269. Sample dot data generation for color 0 even dot Figure 270. Buffer address generator sub-block Figure 271. DIU Interface sub-block Figure 272. Interface controller state diagram Figure 273. High level data flow diagram of LLU in context 35 Figure 274. Paper and printhead nozzles relationship (example with DI=D 2 =5) Figure 275. Conceptual view of vertically misaligned printhead segment rows (external) Figure 276. Conceptual view of vertically misaligned printhead segment rows (internal) Figure 277. Conceptual view of color dependent vertically misaligned printhead segment rows (internal) Figure 278. Conceptual horizontal misalignment between segments 40 Figure 279. Relative positions of dot fired (example cases) WO 2005/120835 PCT/AU2004/000706 350 Figure 280. Example left and right margins Figure 281. Dot data generated and transmitted order Figure 282. Dotline FIFO data structure in DRAM (LLU specification) Figure 283. LLU partition 5 Figure 284. DIU interface Figure 285. Interface controller state diagram Figure 286. Address generator logic Figure 287. Write pointer state machine Figure 288. PHI to linking printhead connection (Single SoPEC) 10 Figure 289. PHI to linking printhead connection (2 SoPECs) Figure 290. CPU command word format Figure 291. Example data and command sequence on a print head channel Figure 292. PHI block partition Figure 293. Data generator state diagram 15 Figure 294. PHI mode Controller Figure 295. Encoder RTL diagram Figure 296. 28-bit scrambler Figure 297. Printing with 1 SoPEC Figure 298. Printing with 2 SoPECs (existing hardware) 20 Figure 299. Each SoPEC generates dot data and writes directly to a single printhead Figure 300. Each SoPEC generates dot data and writes directly to a single printhead Figure 301. Two SoPECs generate dots and transmit directly to the larger printhead Figure 302. Serial Load Figure 303. Parallel Load 25 Figure 304. Two SoPECs generate dot data but only one transmits directly to the larger printhead Figure 305. Odd and Even nozzles on same shift register Figure 306. Odd and Even nozzles on different shift registers Figure 307. Interwoven shift registers Figure 308. Linking Printhead Concept 30 Figure 309. Linking Printhead 30ppm Figure 310. Linking Printhead 60ppm Figure 311. Theoretical 2 tiles assembled as A-chip / A-chip - right angle join Figure 312. Two tiles assembled as A-chip / A-chip Figure 313. Magnification of color n in A-chip / A-chip 35 Figure 314. A-chip / A-chip growing offset Figure 315. A-chip / A-chip aligned nozzles, sloped chip placement Figure 316. Placing multiple segments together Figure 317. Detail of a single segment in a multi-segment configuration Figure 318. Magnification of inter-slope compensation 40 Figure 319. A-chip / B-chip WO 2005/120835 PCT/AU2004/000706 351 Figure 320. A-chip / B-chip multi-segment printhead Figure 321. Two A-B-chips linked together Figure 322. Two A-B-chips with on-chip compensation Figure 323. Frequency modifier block diagram 5 Figure 324. Output frequency error versus input frequency Figure 325. Output frequency error including K Figure 326. Optimised for output jitter <0.2%, F = 48MHzK=25 Figure 327. Direct form 11 biquad Figure 328. Output response and internal nodes 10 Figure 329. Butterworth filter (Fc=O.005) gain error versus input level Figure 330. Step response Figure 331. Output frequency quantisation (K=2^25) Figure 332. Jitter attenuation with a 2nd order Butterworth, F, = 0.05 Figure 333. Period measurement and NCO cumulative error 15 Figure 334. Stepped input frequency and output response Figure 335. Block diagram overview Figure 336. Multiply/divide unit Figure 337. Power-on-reset detection behaviour Figure 338. Brown-out detection behaviour 20 Figure 339. Adapting the IBM POR macro for brown-out detection Figure 340. Deglitching of power-on-reset signal Figure 341. Deglitching of brown-out detector signal Figure 342. Proposed top-level solution Figure 343. First Stage Image Format 25 Figure 344. Second Stage Image Format Figure 345. Overall Logic Flow Figure 346. Initialisation Logic Flow Figure 347. Load & Verify Second Stage Image Logic Flow Figure 348. Load from LSS Logic Flow 30 Figure 349. Load from USB Logic Flow Figure 350. Verify Header and Load to RAM Logic Flow Figure 351. Body Verification Logic Flow Figure 352. Run Application Logic Flow Figure 353. Boot ROM Memory Layout 35 Figure 354. Overview of LSS buses for single SoPEC system Figure 355. Overview of LSS buses for single SoPEC printer Figure 356. Overview of LSS buses for simplest two-SoPEC printer Figure 357. Overview of LSS buses for alternative two-SoPEC printer Figure 358. SoPEC System top level partition 40 Figure 359. Print construction and Nozzle position WO 2005/120835 PCT/AU2004/000706 352 Figure 360. Conceptual horizontal misplacement between segments Figure 361. Printhead row positioning and default row firing order Figure 362. Firing order of fractionally misaligned segment Figure 363. Example of yaw in printhead IC misplacement 5 Figure 364. Vertical nozzle spacing Figure 365. Single printhead chip plus connection to second chip Figure 366. Two printheads connected to form a larger printhead Figure 367. Colour arrangement. Figure 368. Nozzle Offset at Linking Ends 10 Figure 369. Bonding Diagram Figure 370. MEMS Representation. Figure 371. Line Data Load and Firing, properly placed Printhead, Figure 372. Simple Fire order Figure 373. Micro positioning 15 Figure 374. Measurement convention Figure 375. Scrambler implementation Figure 376. Block Diagram Figure 377. Netlist hierarchy Figure 378. Unit cell schematic 20 Figure 379. Unit cell arrangement into chunks Figure 380. Unit Cell Signals Figure 381. Core data shift registers Figure 382. Core Profile logical connection Figure 383. Column SR Placement 25 Figure 384. TDC block diagram Figure 385. TDC waveform Figure 386. TDC construction Figure 387. FPG Outputs positionn 0) Figure 388. DEX block diagram 30 Figure 389. Data sampler Figure 390. Data Eye Figure 391. scrambler/descrambler Figure 392. Aligner state machine Figure 393. Disparity decoder 35 Figure 394. CU command state machine Figure 395. Example transaction Figure 396. c phases Figure 397. Planned tool flow 40 WO 2005/120835 PCT/AU2004/000706 353 DETAILED DESCRIPTION OF PREFERRED EMBODIMENT Various aspects of the preferred and other embodiments will now be described. It will be appreciated that the following description is a highly detailed exposition of the hardware and 5 associated methods that together provide a printing system capable of relatively high resolution, high speed and low cost printing compared to prior art systems. Much of this description is based on technical design documents, so the use of words like "must", "should" and "will", and all others that suggest limitations or positive attributes of the performance of a particular 10 product, should not be interpreted as applying to the invention in general. These comments, unless clearly referring to the invention in general, should be considered as desirable or intended features in a particular design rather than a requirement of the invention. The intended scope of the invention is defined in the claims. 15 Also throughout this description, "printhead module" and "printhead" are used somewhat interchangeably. Technically, a "printhead" comprises one or more "printhead modules", but occasionally the former is used to refer to the latter. It should be clear from the context which meaning should be allocated to any use of the word "printhead". 20 PRINT SYSTEM OVERVIEW 1 INTRODUCTION This document describes the SoPEC ASIC (Small office home office Print Engine Controller) suitable for use in price sensitive SoHo printer products. The SoPEC ASIC is intended to be a relatively low cost solution for linking printhead control, replacing the multichip solutions in larger more professional systems with a single 25 chip. The increased cost competitiveness is achieved by integrating several systems such as a modified PECI printing pipeline, CPU control system, peripherals and memory sub-system onto one SoC ASIC, reducing component count and simplifying board design. SoPEC contains features making it suitable for multifunction or "all-in-one" devices as well as dedicated printing systems. This section will give a general introduction to Memjet printing systems, introduce the components that make 30 a linking printhead system, describe a number of system architectures and show how several SoPECs can be used to achieve faster, wider and/or duplex printing. The section "SoPEC ASIC" describes the SoC SoPEC ASIC, with subsections describing the CPU, DRAM and Print Engine Pipeline subsystems. Each section gives a detailed description of the blocks used and their operation within the overall print system. 35 Basic features of the preferred embodiment of SoPEC include: * Continuous 30ppm operation for 1600dpi output at A4/Letter. " Linearly scalable (multiple SoPECs) for increased print speed and/or page width.
WO 2005/120835 PCT/AU2004/000706 354 * 192MHz internal system clock derived from low-speed crystal input " PEP processing pipeline, supports up to 6 color channels at 1 dot per channel per clock cycle * Hardware color plane decompression, tag rendering, halftoning and compositing " Data formatting for Linking Printhead 5 - Flexible compensation for dead nozzles, printhead misalignment etc. * Integrated 20Mbit (2.5MByte) DRAM for print data and CPU program store e LEON SPARC v8 32-bit RISC CPU e Supervisor and user modes to support multi-threaded software and security * 1kB each of I-cache and D-cache, both direct mapped, with optimized 256-bit fast cache update. 10 - 1 x USB2.0 device port and 3 x USB2.0 host ports (including integrated PHYs) e Support high speed (480Mbit/sec) and full speed (12Mbit/sec) modes of USB2.0 - Provide interface to host PC, other SoPECs, and external devices e.g. digital camera e Enable alternative host PC interfaces e.g. via external USB/ethernet bridge e Glueless high-speed serial LVDS interface to multiple Linking Printhead chips 15 - 64 remappable GPIOs, selectable between combinations of integrated system control components: * 2 x LSS interfaces for QA chip or serial EEPROM * LED drivers, sensor inputs, switch control outputs * Motor controllers for stepper and brushless DC motors * Microprogrammed multi-protocol media interface for scanner, external RAM/Flash, etc. 20 e 112-bit unique ID plus 112-bit random number on each device, combined for security protocol support * IBM Cu-l 1 0.13 micron CMOS process, 1.5V core supply, 3.3V 10. * 208 pin Plastic Quad Flat Pack 25 2 NOMENCLATURE DEFINITIONS The following terms are used throughout this specification: CPU Refers to CPU core, caching system and MMU. 30 Host A PC providing control and print data to a Memjet printer. ISCMaster In a multi-SoPEC system, the ISCMaster (Inter SoPEC Communication Master) is the SoPEC device that initiates communication with other SoPECs in the system. The ISCMaster interfaces with the host.
WO 2005/120835 PCT/AU2004/000706 355 ISCSlave In a multi-SoPEC system, an ISCSlave is a SoPEC device that responds to communication initiated by the ISCMaster. LEON Refers to the LEON CPU core. LineSyncMaster The LineSyncMaster device generates the line synchronisation pulse that all SoPECs 5 in the system must synchronise their line outputs to. Linking Printhead Refers to a page-width printhead constructed from multiple linking printhead ICs Linking Printhead IC A MEMS IC. Multiple ICs link together to form a complete printhead. An A4/Letter page width printhead requires 11 printhead ICs. Multi-SoPEC Refers to SoPEC based print system with multiple SoPEC devices 10 Netpage Refers to page printed with tags (normally in infrared ink). PEC1 Refers to Print Engine Controller version 1, precursor to SoPEC used to control printheads constructed from multiple angled printhead segments. PrintMaster The PrintMaster device is responsible for coordinating all aspects of the print operation. There may only be one PrintMaster in a system. 15 QA Chip Quality Assurance Chip Storage SoPEC A SoPEC used as a DRAM store and which does not print. Tag Refers to pattern which encodes information about its position and orientation which allow it to be optically located and its data contents read. ACRONYM AND ABBREVIATIONS 20 The following acronyms and abbreviations are used in this specification CFU Contone FIF053 Unit CPU Central Processing Unit DIU DRAM Interface Unit DNC Dead Nozzle Compensator 25 DRAM Dynamic Random Access Memory DWU DotLine Writer Unit GPIO General Purpose Input Output HCU Halftoner Compositor Unit ICU Interrupt Controller Unit 30 LDB Lossless Bi-level Decoder LLU Line Loader Unit WO 2005/120835 PCT/AU2004/000706 356 LSS Low Speed Serial interface MEMS Micro Electro Mechanical System MMI Multiple Media Interface MMU Memory Management Unit 5 PCU SoPEC Controller Unit PHI PrintHead Interface PHY USB multi-port Physical Interface PSS Power Save Storage Unit RDU Real-time Debug Unit 10 ROM Read Only Memory SFU Spot FIFO Unit SMG4 Silverbrook Modified Group 4. SoPEC Small office home office Print Engine Controller SRAM Static Random Access Memory 15 TE Tag Encoder TFU Tag FIFO Unit TIM Timers Unit UDU USB Device Unit UHU USB Host Unit 20 USB Universal Serial Bus PSEUDOCODE NOTATION In general the pseudocode examples use C like statements with some exceptions. Symbol and naming convections used for pseudocode. // Comment 25 = Assignment Operator equal, not equal, less than, greater than Operator addition, subtraction, multiply, divide, modulus &,|,^,<<,>>,~ Bitwise AND, bitwise OR, bitwise exclusive OR, left shift, right shift, complement AND,OR,NOT Logical AND, Logical OR, Logical inversion 30 [XX:YY] Array/vector specifier WO 2005/120835 PCT/AU2004/000706 357 {a, b, c} Concatenation operation ++-- Increment and decrement 3 Register and signal naming conventions In general register naming uses the C style conventions with capitalization to denote word delimiters. Signals 5 use RTL style notation where underscore denote word delimiters. There is a direct translation between both conventions. For example the CmdSourceFifo register is equivalent to cmdsource_fifo signal. 4 STATE MACHINE NOTATION State machines are described using the pseudocode notation outlined above. State machine descriptions use the convention of underline to indicate the cause of a transition from one state to another and plain text (no 10 underline) to indicate the effect of the transition i.e. signal transitions which occur when the new state is entered. A sample state machine is shown in Figure 1. 5 PRINT QUALITY CONSIDERATIONS The preferred embodiment linking printhead produces 1600 dpi bi-level dots. On low-diffusion paper, each 15 ejected drop forms a 22.5gm diameter dot. Dots are easily produced in isolation, allowing dispersed-dot dithering to be exploited to its fullest. Since the preferred form of the linking printhead is pagewidth and operates with a constant paper velocity, color planes are printed in good registration, allowing dot-on-dot printing. Dot-on-dot printing minimizes 'muddying' of midtones caused by inter-color bleed. A page layout may contain a mixture of images, graphics and text. Continuous-tone (contone) images and 20 graphics are reproduced using a stochastic dispersed-dot dither. Unlike a clustered-dot (or amplitude modulated) dither, a dispersed-dot (or frequency-modulated) dither reproduces high spatial frequencies (i.e. image detail) almost to the limits of the dot resolution, while simultaneously reproducing lower spatial frequencies to their full color depth, when spatially integrated by the eye. A stochastic dither matrix is carefully designed to be free of objectionable low-frequency patterns when tiled across the image. As such its 25 size typically exceeds the minimum size required to support a particular number of intensity levels (e.g. 16x16x 8 bits for 257 intensity levels). Human contrast sensitivity peaks at a spatial frequency of about 3 cycles per degree of visual field and then falls off logarithmically, decreasing by a factor of 100 beyond about 40 cycles per degree and becoming immeasurable beyond 60 cycles per degree. At a normal viewing distance of 12 inches (about 300mm), this 30 translates roughly to 200-300 cycles per inch (cpi) on the printed page, or 400-600 samples per inch according to Nyquist's theorem. In practice, contone resolution above about 300 ppi is of limited utility outside special applications such as medical imaging. Offset printing of magazines, for example, uses contone resolutions in the range 150 to 300 ppi. Higher resolutions contribute slightly to color error through the dither.
WO 2005/120835 PCT/AU2004/000706 358 Black text and graphics are reproduced directly using bi-level black dots, and are therefore not anti-aliased (i.e. low-pass filtered) before being printed. Text should therefore be supersampled beyond the perceptual limits discussed above, to produce smoother edges when spatially integrated by the eye. Text resolution up to about 1200 dpi continues to contribute to perceived text sharpness (assuming low-diffusion paper). 5 A Netpage printer, for example, may use a contone resolution of 267 ppi (i.e. 1600 dpi / 6), and a black text and graphics resolution of 800 dpi. A high end office or departmental printer may use a contone resolution of 320 ppi (1600 dpi / 5) and a black text and graphics resolution of 1600 dpi. Both formats are capable of exceeding the quality of commercial (offset) printing and photographic reproduction. 10 6 MEMJET PRINTER ARCHITECTURE The SoPEC device can be used in several printer configurations and architectures. In the general sense, every preferred embodiment SoPEC-based printer architecture will contain: * One or more SoPEC devices. - One or more linking printheads. 15 * Two or more LSS busses. * Two or more QA chips. * Connection to host, directly via USB2.0 or indirectly. e Connections between SoPECs (when multiple SoPECs are used). Some example printer configurations as outlined in Section 6.2. The various system components are outlined 20 briefly in Section 6.1. 6.1 SYSTEM COMPONENTS 6.1.1 SoPEC Print Engine Controller The SoPEC device contains several system on a chip (SoC) components, as well as the print engine pipeline control application specific logic. 25 6.1.1.1 Print Engine Pipeline (PEP) Logic The PEP reads compressed page store data from the embedded memory, optionally decompresses the data and formats it for sending to the printhead. The print engine pipeline functionality includes expanding the page image, dithering the contone layer, compositing the black layer over the contone layer, rendering of Netpage tags, compensation for dead nozzles in the printhead, and sending the resultant image to the linking printhead. 30 6.1.1.2 Embedded CPU SoPEC contains an embedded CPU for general-purpose system configuration and management. The CPU performs page and band header processing, motor control and sensor monitoring (via the GPIO) and other WO 2005/120835 PCT/AU2004/000706 359 system control functions. The CPU can perform buffer management or report buffer status to the host. The CPU can optionally run vendor application specific code for general print control such as paper ready monitoring and LED status update. 6.1.1.3 Embedded Memory Buffer 5 A 2.5Mbyte embedded memory buffer is integrated onto the SoPEC device, of which approximately 2Mbytes are available for compressed page store data. A compressed page is divided into one or more bands, with a number of bands stored in memory. As a band of the page is consumed by the PEP for printing a new band can be downloaded. The new band may be for the current page or the next page. Using banding it is possible to begin printing a page before the complete compressed page is downloaded, but 10 care must be taken to ensure that data is always available for printing or a buffer underrun may occur. A Storage SoPEC acting as a memory buffer (Section 6.2.6) could be used to provide guaranteed data delivery. 6.1.1.4 Embedded USB2.0 Device Controller The embedded single-port USB2.0 device controller can be used either for interface to the host PC, or for 15 communication with another SoPEC as an ISCSlave. It accepts compressed page data and control commands from the host PC or ISCMaster SoPEC, and transfers the data to the embedded memory for printing or downstream distribution. 6.1.1.5 Embedded USB2.0 Host Controller The embedded three-port USB2.0 host controller enables communication with other SoPEC devices as a 20 ISCMaster, as well as interfacing with external chips (e.g. for Ethernet connection) and external USB devices, such as digital cameras. 6.1.1.6 Embedded Device/Motor Controllers SoPEC contains embedded controllers for a variety of printer system components such as motors, LEDs etc, which are controlled via SoPEC's GPIOs. This minimizes the need for circuits external to SoPEC to build a 25 complete printer system. 6.1.2 Linking Printhead The printhead is constructed by abutting a number of printhead ICs together. Each SoPEC can drive up to 12 printhead ICs at data rates up to 30ppm or 6 printhead ICs at data rates up to 60ppm. For higher data rates, or wider printheads, multiple SoPECs must be used.
WO 2005/120835 PCT/AU2004/000706 360 6.1.3 LSS interface bus Each SoPEC device has 2 LSS system buses for communication with QA devices for system authentication and ink usage accounting. The number of QA devices per bus and their position in the system is unrestricted with the exception that PRINTERQA and INKQA devices should be on separate LSS busses. 5 6.1.4 QA devices Each SoPEC system can have several QA devices. Normally each printing SoPEC will have an associated PRINTERQA. Ink cartridges will contain an INK QA chip. PRINTERQA and INKQA devices should be on separate LSS busses. All QA chips in the system are physically identical with flash memory contents defining PRINTER_QA from INKQA chip. 10 6.1.5 Connections between SoPECs In a multi-SoPEC system, the primary communication channel is from a USB2.0 Host port on one SoPEC (the ISCMaster), to the USB2.0 Device port of each of the other SoPECs (ISCSlaves). If there are more ISCSlave SoPECs than available USB Host ports on the ISCMaster, additional connections could be via a USB Hub chip, or daisy-chained SoPEC chips. Typically one or more of SoPEC's GPIO signals would also 15 be used to communicate specific events between multiple SoPECs. 6.1.6 Non-USB Host PC Communication The communication between the host PC and the ISCMaster SoPEC may involve an external chip or subsystem, to provide a non-USB host interface, such as ethernet or WiFi. This subsystem may also contain memory to provide an additional buffered band/page store, which could provide guaranteed bandwidth data 20 deliver to SoPEC during complex page prints. 6.2 POSSIBLE SoPEC SYSTEMS Several possible SoPEC based system architectures exist. The following sections outline some possible architectures. It is possible to have extra SoPEC devices in the system used for DRAM storage. The QA chip configurations shown are indicative of the flexibility of LSS bus architecture, but not limited to those 25 configurations. 6.2.1 A4 Simplex at 30 ppm with I SoPEC device In Figure 2, a single SoPEC device is used to control a linking printhead with 11 printhead ICs. The SoPEC receives compressed data from the host through its USB device port. The compressed data is processed and WO 2005/120835 PCT/AU2004/000706 361 transferred to the printhead. This arrangement is limited to a speed of 30ppm. The single SoPEC also controls all printer components such as motors, LEDs, buttons etc, either directly or indirectly. 6.2.2 A4 Simplex at 60 ppm with 2 SoPEC devices In Figure 3, two SoPECs control a single linking printhead, to provide 60ppm A4 printing. Each SoPEC 5 drives 5 or 6 of the printheads ICs that make up the complete printhead. SoPEC #0 is the ISCMaster, SoPEC #1 is an ISCSlave. The ISCMaster receives all the compressed page data for both SoPECs and re-distributes the compressed data for the ISCSlave over a local USB bus. There is a total of 4MBytes of page store memory available if required. Note that, if each page has 2MBytes of compressed data, the USB2.0 interface to the host needs to run in high speed (not full speed) mode to sustain 60ppm printing. (In practice, many 10 compressed pages will be much smaller than 2MBytes). The control of printer components such as motors, LEDs, buttons etc, is shared between the 2 SoPECs in this configuration. 6.2.3 A4 Duplex with 2 SoPEC devices In Figure 4, two SoPEC devices are used to control two printheads. Each printhead prints to opposite sides of the same page to achieve duplex printing. SoPEC #0 is the ISCMaster, SoPEC #1 is an ISCSlave. The 15 ISCMaster receives all the compressed page data for both SoPECs and re-distributes the compressed data for the ISCSlave over a local USB bus. This configuration could print 30 double-sided pages per minute. 6.2.4 A3 Simplex with 2 SoPEC devices In Figure 5, two SoPEC devices are used to control one A3 linking printhead, constructed from 16 printhead ICs. Each SoPEC controls 8 printhead ICs. This system operates in a similar manner to the 60ppm A4 system 20 in Figure 3, although the speed is limited to 30ppm at A3, since each SoPEC can only drive 6 printhead ICs at 60ppm speeds. A total of 4Mbyte of page store is available, this allows the system to use compression rates as in a single SoPEC A4 architecture, but with the increased page size of A3. 6.2.5 A3 Duplex with 4 SoPEC devices In Figure 6 a four SoPEC system is shown. It contains 2 A3 linking printheads, one for each side of an A3 25 page. Each printhead contain 16 printhead ICs, each SoPEC controls 8 printhead ICs. SoPEC #0 is the ISCMaster with the other SoPECs as ISCSlaves. Note that all 3 USB Host ports on SoPEC #0 are used to communicate with the 3 ISCSlave SoPECs. In total, the system contains 8Mbytes of compressed page store (2Mbytes per SoPEC), so the increased page size does not degrade the system print quality, from that of an A4 simplex printer. The ISCMaster receives all the compressed page data for all SoPECs and re-distributes WO 2005/120835 PCT/AU2004/000706 362 the compressed data over the local USB bus to the ISCSlaves. This configuration could print 30 double-sided A3 sheets per minute. 6.2.6 SoPEC DRAM storage solution: A4 Simplex with I printing SoPEC and I memory SoPEC 5 Extra SoPECs can be used for DRAM storage e.g. in Figure 7 an A4 simplex printer can be built with a single extra SoPEC used for DRAM storage. The DRAM SoPEC can provide guaranteed bandwidth delivery of data to the printing SoPEC. SoPEC configurations can have multiple extra SoPECs used for DRAM storage. 6.2.7 Non-USB connection to Host PC Figure 8 shows a configuration in which the connection from the host PC to the printer is an ethernet network, 10 rather than USB. In this case, one of the USB Host ports on SoPEC interfaces to a external device that provide ethernet-to-USB bridging. Note that some networking software support in the bridging device might be required in this configuration. A Flash RAM will be required in such a system, to provide SoPEC with driver software for the Ethernet bridging function. 7 DOCUMENT DATA FLOW 15 7.1 OVERALL FLOW FOR PC-BASED PRINTING Because of the page-width nature of the linking printhead, each page must be printed at a constant speed to avoid creating visible artifacts. This means that the printing speed can't be varied to match the input data rate. Document rasterization and document printing are therefore decoupled to ensure the printhead has a constant supply of data. A page is never printed until it is fully rasterized. This can be achieved by storing a 20 compressed version of each rasterized page image in memory. This decoupling also allows the RIP(s) to run ahead of the printer when rasterizing simple pages, buying time to rasterize more complex pages. Because contone color images are reproduced by stochastic dithering, but black text and line graphics are reproduced directly using dots, the compressed page image format contains a separate foreground bi-level 25 black layer and background contone color layer. The black layer is composited over the contone layer after the contone layer is dithered (although the contone layer has an optional black component). A final layer of Netpage tags (in infrared, yellow or black ink) is optionally added to the page for printout. Figure 9 shows the flow of a document from computer system to printed page. 7.2 MULTI-LAYER COMPRESSION 30 At 267 ppi for example, an A4 page (8.26 inches x 11.7 inches) of contone CMYK data has a size of 26.3MB. At 320 ppi, an A4 page of contone data has a size of 37.8MB. Using lossy contone compression algorithms WO 2005/120835 PCT/AU2004/000706 363 such as JPEG, contone images compress with a ratio up to 10:1 without noticeable loss of quality, giving compressed page sizes of 2.63MB at 267 ppi and 3.78 MB at 320 ppi. At 800 dpi, an A4 page of bi-level data has a size of 7.4MB. At 1600 dpi, a Letter page of bi-level data has a size of 29.5 MB. Coherent data such as text compresses very well. Using lossless bi-level compression 5 algorithms such as SMG4 fax as discussed in Section 8.1.2.3.1, ten-point plain text compresses with a ratio of about 50:1. Lossless bi-level compression across an average page is about 20:1 with 10:1 possible for pages which compress poorly. The requirement for SoPEC is to be able to print text at 10:1 compression. Assuming 10:1 compression gives compressed page sizes of 0.74 MB at 800 dpi, and 2.95 MB at 1600 dpi. Once dithered, a page of CMYK contone image data consists of 116MB of bi-level data. Using lossless bi 10 level compression algorithms on this data is pointless precisely because the optimal dither is stochastic - i.e. since it introduces hard-to-compress disorder. Netpage tag data is optionally supplied with the page image. Rather than storing a compressed bi-level data layer for the Netpage tags, the tag data is stored in its raw form. Each tag is supplied up to 120 bits of raw variable data (combined with up to 56 bits of raw fixed data) and covers up to a 6mm x 6mm area (at 1600 15 dpi). The absolute maximum number of tags on a A4 page is 15,540 when the tag is only 2mm x 2mm (each tag is 126 dots x 126 dots, for a total coverage of 148 tags x 105 tags). 15,540 tags of 128 bits per tag gives a compressed tag page size of 0.24 MB. The multi-layer compressed page image format therefore exploits the relative strengths of lossy JPEG contone image compression, lossless bi-level text compression, and tag encoding. The format is compact enough to be 20 storage-efficient, and simple enough to allow straightforward real-time expansion during printing. Since text and images normally don't overlap, the normal worst-case page image size is image only, while the normal best-case page image size is text only. The addition of worst case Netpage tags adds 0.24MB to the page image size. The worst-case page image size is text over image plus tags. The average page size assumes a quarter of an average page contains images. Table 1 shows data sizes for a compressed A4 page for these 25 different options. Table 1. Data sizes for A4 page (8.26 Inches x 11.7 inches) -I v Image only (contone), 10:1 2.63 MB 3.78 MB compression Text only (bi-level), 10:1 0.74 MB 2.95 MB compression Netpage tags, 1600 dpi 0.24 MB 0.24 MB Worst case (text + image + tags) 3.61 MB 6.67 MB Average (text + 25% image + tags) 1.64 MB 4.25 MB WO 2005/120835 PCT/AU2004/000706 364 7.3 DOCUMENT PROCESSING STEPS The Host PC rasterizes and compresses the incoming document on a page by page basis. The page is restructured into bands with one or more bands used to construct a page. The compressed data is then transferred to the SoPEC device directly via a USB link, or via an external bridge e.g. from ethernet to USB. 5 A complete band is stored in SoPEC embedded memory. Once the band transfer is complete the SoPEC device reads the compressed data, expands the band, normalizes contone, bi-level and tag data to 1600 dpi and transfers the resultant calculated dots to the linking printhead. The document data flow is e The RIP software rasterizes each page description and compress the rasterized page image. 10 - The infrared layer of the printed page optionally contains encoded Netpage tags at a programmable density. e The compressed page image is transferred to the SoPEC device via the USB (or ethernet), normally on a band by band basis. e The print engine takes the compressed page image and starts the page expansion. 15 e The first stage page expansion consists of 3 operations performed in parallel e expansion of the JPEG-compressed contone layer e expansion of the SMG4 fax compressed bi-level layer * encoding and rendering of the bi-level tag data. e The second stage dithers the contone layer using a programmable dither matrix, producing up to 20 four bi-level layers at full-resolution. e The third stage then composites the bi-level tag data layer, the bi-level SMG4 fax de-compressed layer and up to four bi-level JPEG de-compressed layers into the full-resolution page image. * A fixative layer is also generated as required. * The last stage formats and prints the bi-level data through the linking printhead via the printhead 25 interface. The SoPEC device can print a full resolution page with 6 color planes. Each of the color planes can be generated from compressed data through any channel (either JPEG compressed, bi-level SMG4 fax compressed, tag data generated, or fixative channel created) with a maximum number of 6 data channels from page RIP to linking printhead color planes. 30 The mapping of data channels to color planes is programmable. This allows for multiple color planes in the printhead to map to the same data channel to provide for redundancy in the printhead to assist dead nozzle compensation. Also a data channel could be used to gate data from another data channel. For example in stencil mode, data from the bilevel data channel at 1600 dpi can be used to filter the contone data channel at 320 dpi, giving the 35 effect of 1600 dpi edged contone images, such as 1600dpi color text.
WO 2005/120835 PCT/AU2004/000706 365 7.4 PAGE SIZE AND COMPLEXITY IN SOPEC The SoPEC device typically stores a complete page of document data on chip. The amount of storage available for compressed pages is limited to 2Mbytes, imposing a fixed maximum on compressed page size. A comparison of the compressed image sizes in Table 1 indicates that SoPEC would not be capable of printing 5 worst case pages unless they are split into bands and printing commences before all the bands for the page have been downloaded. The page sizes in the table are shown for comparison purposes and would be considered reasonable for a professional level printing system. The SoPEC device is aimed at the consumer level and would not be required to print pages of that complexity. Target document types for the SoPEC device are shown Table 2. Table 2. Page content targets for SoPEC P~~~ ~ ~ ~ ~ e netDsV o u Best Case picture Image, 267ppi with 3 colors, A4 size 8.26x11.7x267x267x3 1.97 @10:1 Full page text, 800dpi A4 size 8.26x1 1.7x800x800 @ 0.74 10:1 Mixed Graphics and Text 6x4x267x267x3 @ 5:1 1.55 - Image of 6 inches x 4 inches @ 267 ppi and 3 colors 800x800x73 @ 10:1 - Remaining area text -73 inches 2 , 800 dpi Best Case Photo, 3 Colors, 6.6 MegaPixel Image 6.6 Mpixel @ 10:1 2.00 10 If a document with more complex pages is required, the page RIP software in the host PC can determine that there is insufficient memory storage in the SoPEC for that document. In such cases the RIP software can take two courses of action: * It can increase the compression ratio until the compressed page size will fit in the SoPEC device, at 15 the expense of print quality, or * It can divide the page into bands and allow SoPEC to begin printing a page band before all bands for that page are downloaded. Once SoPEC starts printing a page it cannot stop; if SoPEC consumes compressed data faster than the bands can be downloaded a buffer underrun error could occur causing the print to fail. A buffer underrun occurs if a 20 line synchronisation pulse is received before a line of data has been transferred to the printhead. Other options which can be considered if the page does not fit completely into the compressed page store are to slow the printing or to use multiple SoPECs to print parts of the page. Alternatively, a number of methods are available to provide additional local page data storage with guaranteed bandwidth to SoPEC, for example a Storage SoPEC (Section 6.2.6).
WO 2005/120835 PCT/AU2004/000706 366 7.5 OTHER PRINTING SOURCES The preceding sections have described the document flow for printing from a host PC in which the RIP on the host PC does much of the management work for SoPEC. SoPEC also supports printing of images directly from other sources, such as a digital camera or scanner, without the intervention of a host PC. 5 In such cases, SoPEC receives image data (and associated metadata) into its DRAM via a USB host or other local media interface. Software running on SoPEC's CPU determines the image format (e.g. compressed or non-compressed, RGB or CMY, etc.), and optionally applies image processing algorithms such as color space conversion. The CPU then makes the data to be printed available to the PEP pipeline. SoPEC allows various PEP pipeline stages to be bypassed, for example JPEG decompression. Depending on the format of the data to 10 be printed, PEP hardware modules interact directly with the CPU to manage DRAM buffers, to allow streaming of data from an image source (e.g. scanner) to the printhead interface without overflowing the limited on-chip DRAM. 8 PAGE FORMAT 15 When rendering a page, the RIP produces a page header and a number of bands (a non-blank page requires at least one band) for a page. The page header contains high level rendering parameters, and each band contains compressed page data. The size of the band will depend on the memory available to the RIP, the speed of the RIP, and the amount of memory remaining in SoPEC while printing the previous band(s). Figure 10 shows the high level data structure of a number of pages with different numbers of bands in the page. 20 Each compressed band contains a mandatory band header, an optional bi-level plane, optional sets of interleaved contone planes, and an optional tag data plane (for Netpage enabled applications). Since each of these planes is optional, the band header specifies which planes are included with the band. Figure 11 gives a high-level breakdown of the contents of a page band. A single SoPEC has maximum rendering restrictions as follows: 25 - 1 bi-level plane * 1 contone interleaved plane set containing a maximum of 4 contone planes e 1 tag data plane e a linking printhead with a maximum of 12 printhead ICs The requirement for single-sided A4 single SoPEC printing at 30ppm is 30 - average contone JPEG compression ratio of 10:1, with a local minimum compression ratio of 5:1 for a single line of interleaved JPEG blocks. e average bi-level compression ratio of 10:1, with a local minimum compression ratio of 1:1 for a single line. If the page contains rendering parameters that exceed these specifications, then the RIP or the Host PC must 35 split the page into a format that can be handled by a single SoPEC.
WO 2005/120835 PCT/AU2004/000706 367 In the general case, the SoPEC CPU must analyze the page and band headers and generate an appropriate set of register write commands to configure the units in SoPEC for that page. The various bands are passed to the destination SoPEC(s) to locations in DRAM determined by the host. The host keeps a memory map for the DRAM, and ensures that as a band is passed to a SoPEC, it is stored in 5 a suitable free area in DRAM. Each SoPEC receives its band data via its USB device interface. Band usage information from the individual SoPECs is passed back to the host. Figure 12 shows an example data flow for a page destined to be printed by a single SoPEC. SoPEC has an addressing mechanism that permits circular band memory allocation, thus facilitating easy memory management. However it is not strictly necessary that all bands be stored together. As long as the 10 appropriate registers in SoPEC are set up for each band, and a given band is contiguous, the memory can be allocated in any way. 8.1 PRINT ENGINE EXAMPLE PAGE FORMAT Note: This example is illustrative of the types of data a compressed page format may need to contain. The actual implementation details of page formats are a matter for software design (including embedded software 15 on the SoPEC CPU); the SoPEC hardware does not assume any particular format. This section describes a possible format of compressed pages expected by the embedded CPU in SoPEC. The format is generated by software in the host PC and interpreted by embedded software in SoPEC. This section indicates the type of information in a page format structure, but implementations need not be limited to this format. The host PC can optionally perform the majority of the header processing. 20 The compressed format and the print engines are designed to allow real-time page expansion during printing, to ensure that printing is never interrupted in the middle of a page due to data underrun. The page format described here is for a single black bi-level layer, a contone layer, and a Netpage tag layer. The black bi-level layer is defined to composite over the contone layer. The black bi-level layer consists of a bitmap containing a 1-bit opacity for each pixel. This black layer matte 25 has a resolution which is an integer or non-integer factor of the printer's dot resolution. The highest supported resolution is 1600 dpi, i.e. the printer's full dot resolution. The contone layer, optionally passed in as YCrCb, consists of a 24-bit CMY or 32-bit CMYK color for each pixel. This contone image has a resolution which is an integer or non-integer factor of the printer's dot resolution. The requirement for a single SoPEC is to support 1 side per 2 seconds A4/Letter printing at a 30 resolution of 267 ppi, i.e. one-sixth the printer's dot resolution. Non-integer scaling can be performed on both the contone and bi-level images. Only integer scaling can be performed on the tag data. The black bi-level layer and the contone layer are both in compressed form for efficient storage in the printer's internal memory.
WO 2005/120835 PCT/AU2004/000706 368 8.1.1 Page structure A single SoPEC is able to print with full edge bleed for A4/Letter paper using the linking printhead. It imposes no margins and so has a printable page area which corresponds to the size of its paper. The target page size is constrained by the printable page area, less the explicit (target) left and top margins specified in 5 the page description. These relationships are illustrated below. 8.1.2 Compressed page format Apart from being implicitly defined in relation to the printable page area, each page description is complete and self-contained. There is no data stored separately from the page description to which the page description refers. The page description consists of a page header which describes the size and resolution of the page, 10 followed by one or more page bands which describe the actual page content. 8.1.2.1 Page header Table 3 shows an example format of a page header. Table 3. Page header format Signature 16-bit Page header format signature. integer Version 16-bit Page header format version number. integer structure size 16-bit Size of page header. integer band count 16-bit Number of bands specified for this page. integer target resolution (dpi) 16-bit Resolution of target page. This is always 1600 for the integer Memjet printer. target page width 16-bit Width of target page, in dots. integer target page height 32-bit Height of target page, in dots. integer target left margin for black 16-bit Width of target left margin, in dots, for black and and contone integer contone. target top margin for black 16-bit Height of target top margin, in dots, for black and and contone integer contone. target right margin for black 16-bit Width of target right margin, in dots, for black and and contone integer contone. target bottom margin for 16-bit Height of target bottom margin, in dots, for black and black and contone integer contone. target left margin for tags 16-bit Width of target left margin, in dots, for tags. integer target top margin for tags 16-bit Height of target top margin, in dots, for tags. integer WO 2005/120835 PCT/AU2004/000706 369 target right margin for tags 16-bit Width of target right margin, in dots, for tags. integer target bottom margin for tags 16-bit Height of target bottom margin, in dots, for tags. integer generate tags 16-bit Specifies whether to generate tags for this page (0 integer no, 1 - yes). fixed tag data 128-bit This is only valid if generate tags is set. integer tag vertical scale factor 16-bit Scale factor in vertical direction from tag data integer resolution to target resolution. Valid range = 1-511. Integer scaling only tag horizontal scale factor 16-bit Scale factor in horizontal direction from tag data integer. resolution to target resolution. Valid range = 1-511. Integer scaling only. bi-level layer vertical scale 16-bit Scale factor in vertical direction from bi-level resolution factor integer to target resolution (must be 1 or greater). May be non-integer. Expressed as a fraction with upper 8-bits the numerator and the lower 8 bits the denominator. bi-level layer horizontal scale 16-bit Scale factor in horizontal direction from bi-level factor integer resolution to target resolution (must be 1 or greater). May be non-integer. Expressed as a fraction with upper 8-bits the numerator and the lower 8 bits the denominator. bi-level layer page width 16-bit Width of bi-level layer page, in pixels. integer bi-level layer page height 32-bit Height of bi-level layer page, in pixels. integer contone flags 16 bit Defines the color conversion that is required for the integer JPEG data. Bits 2-0 specify how many contone planes there are (e.g. 3 for CMY and 4 for CMYK). Bit 3 specifies whether the first 3 color planes need to be converted back from YCrCb to CMY. Only valid if b2-0 = 3 or 4. 0 - no conversion, leave JPEG colors alone 1 - color convert. Bits 7-4 specifies whether the YCrCb was generated directly from CMY, or whether it was converted to RGB first via the step: R = 255-C, G = 255-M, B = 255-Y. Each of the color planes can be individually inverted. Bit 4: 0 - do not invert color plane 0 1 - invert color plane 0 Bit 5: 0 - do not invert color plane 1 1 - invert color plane 1 Bit 6: 0 - do not invert color plane 2 1 - invert color plane 2 Bit 7: 0 - do not invert color plane 3 1 - invert color plane 3 Bit 8 specifies whether the contone data is JPEG compressed or non-compressed: 0 - JPEG compressed 1 - non-compressed The remaining bits are reserved (0).
WO 2005/120835 PCT/AU2004/000706 370 contone vertical scale factor 16-bit Scale factor in vertical direction from contone channel integer resolution to target resolution. Valid range = 1-255. May be non-integer. Expressed as a fraction with upper 8-bits the numerator and the lower 8 bits the denominator. contone horizontal scale 16-bit Scale factor in horizontal direction from contone factor integer channel resolution to target resolution. Valid range = 1 255. May be non-integer. Expressed as a fraction with upper 8-bits the numerator and the lower 8 bits the denominator. contone page width 16-bit Width of contone page, in contone pixels. integer contone page height 32-bit Height of contone page, in contone pixels. integer Reserved up to 128 Reserved and 0 pads out page header to multiple of bytes 128 bytes. The page header contains a signature and version which allow the CPU to identify the page header format. If the signature and/or version are missing or incompatible with the CPU, then the CPU can reject the page. 5 The contone flags define how many contone layers are present, which typically is used for defining whether the contone layer is CMY or CMYK. Additionally, if the color planes are CMY, they can be optionally stored as YCrCb, and further optionally color space converted from CMY directly or via RGB. Finally the contone data is specified as being either JPEG compressed or non-compressed. The page header defines the resolution and size of the target page. The bi-level and contone layers are clipped 10 to the target page if necessary. This happens whenever the bi-level or contone scale factors are not factors of the target page width or height. The target left, top, right and bottom margins defme the positioning of the target page within the printable page area. The tag parameters specify whether or not Netpage tags should be produced for this page and what orientation 15 the tags should be produced at (landscape or portrait mode). The fixed tag data is also provided. The contone, bi-level and tag layer parameters define the page size and the scale factors. 8.1.2.2 Band format Table 4 shows the format of the page band header. Table 4. Band header format signature 16-bit Page band header format signature. integer WO 2005/120835 PCT/AU2004/000706 371 Version 16-bit Page band header format version integer number. structure size 16-bit Size of page band header. integer bi-level layer band height 16-bit Height of bi-level layer band, in black integer pixels. bi-level layer band data size 32-bit Size of bi-level layer band data, in integer bytes. contone band height 16-bit Height of contone band, in contone integer pixels. contone band data size 32-bit Size of contone plane band data, in integer bytes. tag band height 16-bit Height of tag band, in dots. integer tag band data size 32-bit Size of unencoded tag data band, in integer bytes. Can be 0 which indicates that no tag data is provided. reserved up to 128 Reserved and 0 pads out band header bytes to multiple of 128 bytes. The bi-level layer parameters define the height of the black band, and the size of its compressed band data. The variable-size black data follows the page band header. The contone layer parameters define the height of the contone band, and the size of its compressed page data. The variable-size contone data follows the black data. 5 The tag band data is the set of variable tag data half-lines as required by the tag encoder. The format of the tag data is found in Section 28.5.2. The tag band data follows the contone data. Table 5 shows the format of the variable-size compressed band data which follows the page band header. Table 5. Page band data format black data Modified G4 facsimile bitstream Compressed bi-level layer. contone data JPEG bytestream Compressed contone datalayer. tag data map Tag data array Tag data format. See Section 28.5.2. The start of each variable-size segment of band data should be aligned to a 256-bit DRAM word boundary. The following sections describe the format of the compressed bi-level layers and the compressed contone 10 layer. section 28.5.1 on page 546 describes the format of the tag data structures. 8.1.2.3 Bi-level data compression The (typically 1600 dpi) black bi-level layer is losslessly compressed using Silverbrook Modified Group 4 (SMG4) compression which is a version of Group 4 Facsimile compression without Huffman and with WO 2005/120835 PCT/AU2004/000706 372 simplified run length encodings. Typically compression ratios exceed 10:1. The encoding are listed in Table 6 and Table 7 Table 6. Bi-Level group 4 facsimile style compression encodings Encoding Description 1000 Pass Command: a0 <- b2, skip next two edges 110Vertical(l): aO bi + 1, color = color E o Vertical(-1): aO <- b1 - 1, color = !color Vertical(2): aO <- b1 + 2, color = !color E =. 2010000 Vertical(-2): a0 <- b1 - 2, color = !color C0 Vac 000000 Vertical(3): aO <- bI + 3, color = !color U)O- 000000 Vertical(-3): aO *-bi - 3, color = !color 0 C <RL><RL>100 Horizontal: aO <- aO + <RL> + <RL> WE SMG4 has a pass through mode to cope with local negative compression. Pass through mode is activated by a special run-length code. Pass through mode continues to either end of line or for a pre-programmed number of bits, whichever is shorter. The special run length code is always executed as a run-length code, followed by pass through. The pass through escape code is a medium length run-length with a run of less than or equal to 31. Table 7. Run length (RL) encodings RRRRR1 Short Black Runlength (5 bits) RRRRRR1 Short White Runlength (5 bits) RRRRRRRRRR10 Medium Black Runlength (10 bits) RRRRRRRR10 Medium White Runlength (8 bits) RRRRRRRRRR10 Medium Black Runlength with RRRRRRRRRR <= 31, Enter pass through RRRRRRRR10 Medium White Runlength with RRRRRRRR <= 31, Enter pass through .~.2 ;5 RRRRRRRRRRRRRRR Long Black Runlength (15 bits) 00 WE RRRRRRRRRRRRRRR Long White Runlength (15 bits) c E 00 5 WO 2005/120835 PCT/AU2004/000706 373 Since the compression is a bitstream, the encodings are read right (least significant bit) to left (most significant bit). The run lengths given as RRRR in Table 7 are read in the same way (least significant bit at the right to most significant bit at the left). Each band of bi-level data is optionally self contained. The first line of each band therefore is based on a 5 'previous' blank line or the last line of the previous band. 8.1.2.3.1 Group 3 and 4 facsimile compression The Group 3 Facsimile compression algorithm losslessly compresses bi-level data for transmission over slow and noisy telephone lines. The bi-level data represents scanned black text and graphics on a white background, and the algorithm is tuned for this class of images (it is explicitly not tuned, for example, for 10 halftoned bi-level images). The ID Group 3 algorithm runlength-encodes each scanline and then Huffman encodes the resulting runlengths. Runlengths in the range 0 to 63 are coded with terminating codes. Runlengths in the range 64 to 2623 are coded with make-up codes, each representing a multiple of 64, followed by a terminating code. Runlengths exceeding 2623 are coded with multiple make-up codes followed by a terminating code. The Huffman tables are fixed, but are separately tuned for black and white runs (except 15 for make-up codes above 1728, which are common). When possible, the 2D Group 3 algorithm encodes a scanline as a set of short edge deltas (0, ±1, ±2, ±3) with reference to the previous scanline. The delta symbols are entropy-encoded (so that the zero delta symbol is only one bit long etc.) Edges within a 2D-encoded line which can't be delta-encoded are runlength-encoded, and are identified by a prefix. ID- and 2D-encoded lines are marked differently. ID-encoded lines are generated at regular intervals, whether actually required or not, 20 to ensure that the decoder can recover from line noise with minimal image degradation. 2D Group 3 achieves compression ratios of up to 6:1. The Group 4 Facsimile algorithm losslessly compresses bi-level data for transmission over error-free communications lines (i.e. the lines are truly error-free, or error-correction is done at a lower protocol level). The Group 4 algorithm is based on the 2D Group 3 algorithm, with the essential modification that since 25 transmission is assumed to be error-free, 1D-encoded lines are no longer generated at regular intervals as an aid to error-recovery. Group 4 achieves compression ratios ranging from 20:1 to 60:1 for the CCITT set of test images. The design goals and performance of the Group 4 compression algorithm qualify it as a compression algorithm for the bi-level layers. However, its Huffman tables are tuned to a lower scanning resolution (100 30 400 dpi), and it encodes runlengths exceeding 2623 awkwardly. 8.1.2.4 Contone data compression The contone layer (CMYK) is either a non-compressed bytestream or is compressed to an interleaved JPEG bytestream. The JPEG bytestream is complete and self-contained. It contains all data required for decompression, including quantization and Huffman tables. 35 The contone data is optionally converted to YCrCb before being compressed (there is no specific advantage in color-space converting if not compressing). Additionally, the CMY contone pixels are optionally converted WO 2005/120835 PCT/AU2004/000706 374 (on an individual basis) to RGB before color conversion using R=255-C, G=255-M, B=255-Y. Optional bitwise inversion of the K plane may also be performed. Note that this CMY to RGB conversion is not intended to be accurate for display purposes, but rather for the purposes of later converting to YCrCb. The inverse transform will be applied before printing. 5 8.1.2.4.1 JPEG compression The JPEG compression algorithm lossily compresses a contone image at a specified quality level. It introduces imperceptible image degradation at compression ratios below 5:1, and negligible image degradation at compression ratios below 10:1 . JPEG typically first transforms the image into a color space which separates luminance and chrominance into 10 separate color channels. This allows the chrominance channels to be subsampled without appreciable loss because of the human visual system's relatively greater sensitivity to luminance than chrominance. After this first step, each color channel is compressed separately. The image is divided into 8x8 pixel blocks. Each block is then transformed into the frequency domain via a discrete cosine transform (DCT). This transformation has the effect of concentrating image energy in 15 relatively lower-frequency coefficients, which allows higher-frequency coefficients to be more crudely quantized. This quantization is the principal source of compression in JPEG. Further compression is achieved by ordering coefficients by frequency to maximize the likelihood of adjacent zero coefficients, and then runlength-encoding runs of zeroes. Finally, the runlengths and non-zero frequency coefficients are entropy coded. Decompression is the inverse process of compression. 20 8.1.2.4.2 Non-compressed format If the contone data is non-compressed, it must be in a block-based format bytestream with the same pixel order as would be produced by a JPEG decoder. The bytestream therefore consists of a series of 8x8 block of the original image, starting with the top left 8x8 block, and working horizontally across the page (as it will be printed) until the top rightmost 8x8 block, then the next row of 8x8 blocks (left to right) and so on until the 25 lower row of 8x8 blocks (left to right). Each 8x8 block consists of 64 8-bit pixels for color plane 0 (representing 8 rows of 8 pixels in the order top left to bottom right) followed by 64 8-bit pixels for color plane 1 and so on for up to a maximum of 4 color planes. If the original image is not a multiple of 8 pixels in X or Y, padding must be present (the extra pixel data will be ignored by the setting of margins). 30 8.1.2.4.3 Compressed format If the contone data is compressed the first memory band contains JPEG headers (including tables) plus MCUs (minimum coded units). The ratio of space between the various color planes in the JPEG stream is 1:1:1:1. No subsampling is permitted. Banding can be completely arbitrary i.e there can be multiple JPEG images per band or 1 JPEG image divided over multiple bands. The break between bands is only memory alignment 35 based.
WO 2005/120835 PCT/AU2004/000706 375 8.1.2.4.4 Conversion of RGB to YCrCb (in RIP) YCrCb is defined as per CCIR 601-1 except that Y, Cr and Cb are normalized to occupy all 256 levels of an 8-bit binary encoding and take account of the actual hardware implementation of the inverse transform within SoPEC. 5 The exact color conversion computation is as follows: S Y*= (9805/32768)R + (19235/32768)G + (3728/32768)B e Cr* = (16375/32768)R - (13716/32768)G - (2659/32768)B + 128 e Cb*= -(5529/32768)R - (10846/32768)G + (16375/32768)B + 128 Y, Cr and Cb are obtained by rounding to the nearest integer. There is no need for saturation since ranges of 10 Y*, Cr* and Cb* after rounding are [0-255], [1-255] and [1-255] respectively. Note that full accuracy is possible with 24 bits. SOPEC ASIC 9 FEATURES AND ARCHITECTURE 15 The Small Office Home Office Print Engine Controller (SoPEC) is a page rendering engine ASIC that takes compressed page images as input, and produces decompressed page images at up to 6 channels of bi-level dot data as output. The bi-level dot data is generated for the Memjet linking printhead. The dot generation process takes account of printhead construction, dead nozzles, and allows for fixative generation. A single SoPEC can control up to 12 linking printheads and up to 6 color channels at >10,000 lines/sec, 20 equating to 30 pages per minute. A single SoPEC can perform full-bleed printing of A4 and Letter pages. The 6 channels of colored ink are the expected maximum in a consumer SOHO, or office Memjet printing environment: * CMY, for regular color printing. * K, for black text, line graphics and gray-scale printing. 25 e IR (infrared), for Netpage-enabled applications. * F (fixative), to enable printing at high speed. Because the Memjet printer is capable of printing so fast, a fixative may be required on specific media types (such as calendared paper) to enable the ink to dry before the page touches a previously printed page. Otherwise the pages may bleed on each other. In low speed printing environments, and for plain and photo paper, the fixative is not be 30 required. SoPEC is color space agnostic. Although it can accept contone data as CMYX or RGBX, where X is an optional 4th channel (such as black), it also can accept contone data in any print color space. Additionally, SoPEC provides a mechanism for arbitrary mapping of input channels to output channels, including combining dots for ink optimization, generation of channels based on any number of other channels etc. 35 However, inputs are typically CMYK for contone input, K for the bi-level input, and the optional Netpage tag WO 2005/120835 PCT/AU2004/000706 376 dots are typically rendered to an infra-red layer. A fixative channel is typically only generated for fast printing applications. SoPEC is resolution agnostic. It merely provides a mapping between input resolutions and output resolutions by means of scale factors. The expected output resolution is 1600 dpi, but SoPEC actually has no knowledge 5 of the physical resolution of the linking printhead. SoPEC is page-length agnostic. Successive pages are typically split into bands and downloaded into the page store as each band of information is consumed and becomes free. SoPEC provides mechanisms for synchronization with other SoPECs. This allows simple multi-SoPEC solutions for simultaneous A3/A4/Letter duplex printing. However, SoPEC is also capable of printing only a 10 portion of a page image. Combining synchronization functionality with partial page rendering allows multiple SoPECs to be readily combined for alternative printing requirements including simultaneous duplex printing and wide format printing. Table 8 lists some of the features and corresponding benefits of SoPEC. Table 8. Features and Benefits of SoPEC Optimised print architecture in 30ppm full page photographic quality color hardware printing from a desktop PC 0.13micron CMOS High speed (>36 million transistors) Low cost High functionality 900 Million dots per second Extremely fast page generation >10,000 lines-per second at 1600 dpi 0.5 A4/Letter pages per SoPEC chip per second 1 chip drives up to 92,160 nozzles Low cost page-width printers 1 chip drives up to 6 color planes 99% of SoHo printers can use 1 SoPEC device Integrated DRAM No external memory required, leading to low cost systems Power saving sleep mode SoPEC can enter a power saving sleep mode to reduce power dissipation between print jobs JPEG expansion Low bandwidth from PC Low memory requirements in printer Lossless bitplane expansion High resolution text and line art with low bandwidth from PC. Netpage tag expansion Generates interactive paper Stochastic dispersed dot dither Optically smooth image quality No moire effects WO 2005/120835 PCT/AU2004/000706 377 Hardware compositor for 6 image Pages composited in real-time planes Dead nozzle compensation Extends printhead life and yield Reduces printhead cost Color space agnostic Compatible with all inksets and image sources including RGB, CMYK, spot, CIE L*a*b*, hexachrome, YCrCbK, sRGB and other Color space conversion Higher quality / lower bandwidth USB2.0 device interface Direct, high speed (480Mb/s) interface to host PC. USB2.0 host interface Enables alternative host PC connection types (IEEE1394, Ethernet, WiFi, Bluetooth etc.). Enables direct printing from digital camera or other device. Media Interface Direct connection to a wide range of external devices e.g. scanner Integrated motor controllers Saves expensive external hardware. Cascadable in resolution Printers of any resolution Cascadable in color depth Special color sets e.g. hexachrome can be used Cascadable in image size Printers of any width Cascadable in pages Printers can print both sides simultaneously Cascadable in speed Higher speeds are possible by having each SoPEC print one vertical strip of the page. Fixative channel data generation Extremely fast ink drying without wastage Built-in security Revenue models are protected Undercolor removal on dot-by-dot Reduced ink usage basis Does not require fonts for high No font substitution or missing fonts speed operation Flexible printhead configuration Many configurations of printheads are supported by one chip type Drives linking printheads directly No print driver chips required, results in lower cost Determines dot accurate ink usage Removes need for physical ink monitoring system in ink cartridges 9.1 PRINTING RATES The required printing rate for a single SoPEC is 30 sheets per minute with an inter-sheet spacing of 4 cm. To achieve a 30 sheets per minute print rate, this requires: 300mm x 63 (dot/mm) / 2 sec = 105.8 seconds per line, with no inter-sheet gap. 5 340mm x 63 (dot/mm) / 2 sec = 93.3 seconds per line, with a 4 cm inter-sheet gap.
WO 2005/120835 PCT/AU2004/000706 378 A printline for an A4 page consists of 13824 nozzles across the page. At a system clock rate of 192 MHz, 13824 dots of data can be generated in 69.2 seconds. Therefore data can be generated fast enough to meet the printing speed requirement. Once generated, the data must be transferred to the printhead. Data is transferred to the printhead ICs using a 5 288MHz clock (3/2 times the system clock rate). SoPEC has 6 printhead interface ports running at this clock rate. Data is 8b/10b encoded, so the thoughput per port is 0.8 x 288 = 230.4Mb/sec. For 6 color planes, the total number of dots per printhead IC is 1280 x 6 = 7680, which takes 33.3 p seconds to transfer. With 6 ports and 11 printhead ICs, 5 of the ports address 2 ICs sequentially, while one port addresses one IC and is idle otherwise. This means all data is transferred on 66.7 seconds (plus a slight overhead). Therefore one SoPEC 10 can transfer data to the printhead fast enough for 30ppm printing, 9.2 SoPEC BASIC ARCHITECTURE From the highest point of view the SoPEC device consists of 3 distinct subsystems e CPU Subsystem * DRAM Subsystem 15 e Print Engine Pipeline (PEP) Subsystem See Figure 14 for a block level diagram of SoPEC. 9.2.1 CPU Subsystem The CPU subsystem controls and configures all aspects of the other subsystems. It provides general support for interfacing and synchronising the external printer with the internal print engine. It also controls the low 20 speed communication to the QA chips. The CPU subsystem contains various peripherals to aid the CPU, such as GPIO (includes motor control), interrupt controller, LSS Master, MMI and general timers. The CPR block provides a mechanism for the CPU to powerdown and reset individual sections of SoPEC. The UDU and UHU provide high-speed USB2.0 interfaces to the host, other SoPEC devices, and other external devices. For security, the CPU supports user and supervisor mode operation, while the CPU subsystem contains some 25 dedicated security components. 9.2.2 DRAM Subsystem The DRAM subsystem accepts requests from the CPU, UJHU, UDU, MMI and blocks within the PEP subsystem. The DRAM subsystem (in particular the DIU) arbitrates the various requests and determines which request should win access to the DRAM. The DIU arbitrates based on configured parameters, to allow 30 sufficient access to DRAM for all requestors. The DIU also hides the implementation specifics of the DRAM such as page size, number of banks, refresh rates etc.
WO 2005/120835 PCT/AU2004/000706 379 9.2.3 Print Engine Pipeline (PEP) subsystem The Print Engine Pipeline (PEP) subsystem accepts compressed pages from DRAM and renders them to bi level dots for a given print line destined for a printhead interface that communicates directly with up to 12 linking printhead ICs. 5 The first stage of the page expansion pipeline is the CDU, LBD and TE. The CDU expands the JPEG compressed contone (typically CMYK) layer, the LBD expands the compressed bi-level layer (typically K), and the TE encodes Netpage tags for later rendering (typically in IR, Y or K ink). The output from the first stage is a set of buffers: the CFU, SFU, and TFU. The CFU and SFU buffers are implemented in DRAM. The second stage is the HCU, which dithers the contone layer, and composites position tags and the bi-level 10 spotO layer over the resulting bi-level dithered layer. A number of options exist for the way in which compositing occurs. Up to 6 channels of bi-level data are produced from this stage. Note that not all 6 channels may be present on the printhead. For example, the printhead may be CMY only, with K pushed into the CMY channels and IR ignored. Alternatively, the position tags may be printed in K or Y if IR ink is not available (or for testing purposes). 15 The third stage (DNC) compensates for dead nozzles in the printhead by color redundancy and error diffusing dead nozzle data into surrounding dots. The resultant bi-level 6 channel dot-data (typically CMYK-IRF) is buffered and written out to a set of line buffers stored in DRAM via the DWU. Finally, the dot-data is loaded back from DRAM, and passed to the printhead interface via a dot FIFO. The 20 dot FIFO accepts data from the LLU up to 2 dots per system clock cycle, while the PHI removes data from the FIFO and sends it to the printhead at a maximum rate of 1.5 dots per system clock cycle (see Section 9.1). 9.3 SoPEC BLOCK DESCRIPTION Looking at Figure 14, the various units are described here in summary form: Table 9. Units within SoPEC DRAM DIU DRAM interface unit Provides the interface for DRAM read and write access for the various PEP units, CPU, UDU, UHU and MMI. The DIU provides arbitration between competing units controls DRAM access. DRAM Embedded DRAM 20Mbits of embedded DRAM, CPU CPU Central Processing CPU for system configuration and control Unit MMU Memory Management Limits access to certain memory address Unit areas in CPU user mode WO 2005/120835 PCT/AU2004/000706 380 RDU Real-time Debug Unit Facilitates the observation of the contents of most of the CPU addressable registers in SoPEC in addition to some pseudo-registers in realtime. TIM General Timer Contains watchdog and general system timers LSS Low Speed Serial Low level controller for interfacing with the Interfaces QA chips GPIO General Purpose 10s General 10 controller, with built-in Motor control unit, LED pulse units and de-glitch circuitry MMI Multi-Media Interface Generic Purpose Engine for protocol generation and control with integrated DMA controller. ROM Boot ROM 16 KBytes of System Boot ROM code ICU Interrupt Controller Unit General Purpose interrupt controller with configurable priority, and masking. CPR Clock, Power and Central Unit for controlling and generating Reset block the system clocks and resets and powerdown mechanisms PSS Power Save Storage Storage retained while system is powered down USB PHY Universal Serial Bus USB multiport (4) physical interface. (USB) Physical UHU USB Host Unit USB host controller interface with integrated DIU DMA controller UDU USB Device Unit USB Device controller interface with integrated DIU DMA controller Print Engine PCU PEP controller Provides external CPU with the means to Pipeline read and write PEP Unit registers, and read (PEP) and write DRAM in single 32-bit chunks. CDU Contone decoder unit Expands JPEG compressed contone layer and writes decompressed contone to DRAM CFU Contone FIFO Unit Provides line buffering between CDU and HCU LBD Lossless Bi-level Expands compressed bi-level layer. Decoder SFU Spot FIFO Unit Provides line buffering between LBD and HCU TE Tag encoder Encodes tag data into line of tag dots. TFU Tag FIFO Unit Provides tag data storage between TE and HCU HCU Halftoner compositor Dithers contone layer and composites the bi unit level spot 0 and position tag dots. DNC Dead Nozzle Compensates for dead nozzles by color Compensator redundancy and error diffusing dead nozzle data into surrounding dots. DWU Dotline Writer Unit Writes out the 6 channels of dot data for a given printline to the line store DRAM WO 2005/120835 PCT/AU2004/000706 381 LLU Line Loader Unit Reads the expanded page image from line store, formatting the data appropriately for the linking printhead. PHI PrintHead Interface Is responsible for sending dot data to the linking printheads and for providing line synchronization between multiple SoPECs. Also provides test interface to printhead such as temperature monitoring and Dead Nozzle Identification. 9.4 ADDRESSING SCHEME IN SoPEC SoPEC must address e 20 Mbit DRAM. 5 e PCU addressed registers in PEP. * CPU-subsystem addressed registers. SoPEC has a unified address space with the CPU capable of addressing all CPU-subsystem and PCU-bus accessible registers (in PEP) and all locations in DRAM. The CPU generates byte-aligned addresses for the whole of SoPEC. 10 22 bits are sufficient to byte address the whole SoPEC address space. 9.4.1 DRAM addressing scheme The embedded DRAM is composed of 256-bit words. Since the CPU-subsystem may need to write individual bytes of DRAM, the DIU is byte addressable. 22 bits are required to byte address 20 Mbits of DRAM. Most blocks read or write 256-bit words of DRAM. For these blocks only the top 17 bits i.e. bits 21 to 5 are 15 required to address 256-bit word aligned locations. The exceptions are * CDU which can write 64-bits so only the top 19 address bits i.e. bits 21-3 are required. * The CPU-subsystem always generates a 22-bit byte-aligned DIU address but it will send flags to the DIU indicating whether it is an 8, 16 or 32-bit write. 20 0 The UHU and UDU generate 256-bit aligned addresses, with a byte-wise write mask associated with each data word, to allow effective byte addressing of the DRAM. Regardless of the size no DIU access is allowed to span a 256-bit aligned DRAM word boundary. 9.4.2 PEP Unit DRAM addressing PEP Unit configuration registers which specify DRAM locations should specify 256-bit aligned DRAM 25 addresses i.e. using address bits 21:5. Legacy blocks from PECI e.g. the LBD and TE may need to specify 64 bit aligned DRAM addresses if these reused blocks DRAM addressing is difficult to modify. These 64-bit WO 2005/120835 PCT/AU2004/000706 382 aligned addresses require address bits 21:3. However, these 64-bit aligned addresses should be programmed to start at a 256-bit DRAM word boundary. Unlike PEC 1, there are no constraints in SoPEC on data organization in DRAM except that all data structures must start on a 256-bit DRAM boundary. If data stored is not a multiple of 256-bits then the last word should 5 be padded. 9.4.3 CPU subsystem bus addressed registers The CPU subsystem bus supports 32-bit word aligned read and write accesses with variable access timings. See section 11.4 for more details of the access protocol used on this bus. The CPU subsystem bus does not currently support byte reads and writes. 10 9.4.4 PCU addressed registers in PEP The PCU only supports 32-bit register reads and writes for the PEP blocks. As the PEP blocks only occupy a subsection of the overall address map and the PCU is explicitly selected by the MMU when a PEP block is being accessed the PCU does not need to perform a decode of the higher-order address bits. See Table 11 for the PEP subsystem address map. 15 9.5 SoPEC MEMORY MAP 9.5.1 Main memory map The system wide memory map is shown in Figure 15 below. The memory map is discussed in detail in Section 11 Central Processing Unit (CPU). 9.5.2 CPU-bus peripherals address map 20 The address mapping for the peripherals attached to the CPU-bus is shown in Table 10 below. The MMvU performs the decode of cpuadr[21:12] to generate the relevant cpu block select signal for each block. The addressed blocks decode however many of the lower order bits of cpu adr as are required to address all the registers or memory within the block.The effect of decoding fewer bits is to cause the address space within a block to be duplicated many times (i.e. mirrored) depending on how many bits are required. Table 10. CPU-bus peripherals address map ROMbase Ox0000_0000 MMUbase Ox0003_0000 TIMbase Ox0003_1000 LSSbase OxOO032000 GPIObase 0x0003_3000 WO 2005/120835 PCT/AU2004/000706 383 MMIbase Ox0003_4000 ICUbase Ox0003_5000 CPRbase Ox0003_6000 DIUbase Ox0003_7000 PSSbase Ox0003_8000 UHUbase Ox0003_9000 UDUbase 0x0003_A000 Reserved OxOO03_BOOO to 0x0003_FFFF PCUbase Ox0004_0000 to 0x0004_BFFF A write to a undefined register address within the defined address space for a block can have undefined consequences, a read of an undefined address will return undefined data. Note this is a consequence of only using the low order bits of the CPU address for an address decode (cpu_adr). 5 9.5.3 PCU Mapped Registers (PEP blocks) address map The PEP blocks are addressed via the PCU. From Figure 15, the PCU mapped registers are in the range Ox0004_0000 to 0x0004_BFFF. From Table 11 it can be seen that there are 12 sub-blocks within the PCU address space. Therefore, only four bits are necessary to address each of the sub-blocks within the PEP part of SoPEC. A further 12 bits may be used to address any configurable register within a PEP block. This gives 10 scope for 1024 configurable registers per sub-block (the PCU mapped registers are all 32-bit addressed registers so the upper 10 bits are required to individually address them). This address will come either from the CPU or from a command stored in DRAM. The bus is assembled as follows: " address[15:12]= sub-block address, e address[n:2] = register address within sub-block, only the number of bits required to decode the 15 registers within each sub-block are used, e address[ 1:0] = byte address, unused as PCU mapped registers are all 32-bit addressed registers. So for the case of the HCU, its addresses range from 0x7000 to Ox7FFF within the PEP subsystem or from 0x0004_7000 to 0x0004_7FFF in the overall system. Table 11. PEP blocks address map PCUbase Ox0004_0000 CDUbase Ox0004_1000 CFUbase Ox0004_2000 LBD-base Ox0004_3000 SFUbase Ox0004_4000 WO 2005/120835 PCT/AU2004/000706 384 TEbase Ox0004_5000 TFUbase Ox00046000 HCU-base 0x00047000 DNCbase Ox00048000 DWUbase Ox0004_9000 LLUbase 0x0004_A000 PHIbase Ox0004_B000 to 0x0004_BFFF 9.6 BUFFER MANAGEMENT IN SoPEC As outlined in Section 9.1, SoPEC has a requirement to print 1 side every 2 seconds i.e. 30 sides per minute. 9.6.1 Page buffering Approximately 2 Mbytes of DRAM are reserved for compressed page buffering in SoPEC. If a page is 5 compressed to fit within 2 Mbyte then a complete page can be transferred to DRAM before printing. USB2.0 in high speed mode allows the transfer of 2 Mbyte in less than 40ms, so data transfer from the host is not a significant factor in print time in this case. For a host PC running in USB1.1 compatible full speed mode, the transfer time for 2 Mbyte approaches 2 seconds, so the cycle time for full page buffering approaches 4 seconds. 10 9.6.2 Band buffering The SoPEC page-expansion blocks support the notion of page banding. The page can be divided into bands and another band can be sent down to SoPEC while the current band is being printed. Therefore printing can start once at least one band has been downloaded. The band size granularity should be carefully chosen to allow efficient use of the USB bandwidth and DRAM 15 buffer space. It should be small enough to allow seamless 30 sides per minute printing but not so small as to introduce excessive CPU overhead in orchestrating the data transfer and parsing the band headers. Band finish interrupts have been provided to notify the CPU of free buffer space. It is likely that the host PC will supervise the band transfer and buffer management instead of the SoPEC CPU. If SoPEC starts printing before the complete page has been transferred to memory there is a risk of a buffer 20 underrun occurring if subsequent bands are not transferred to SoPEC in time e.g. due to insufficient USB bandwidth caused by another USB peripheral consuming USB bandwidth. A buffer underrun occurs if a line synchronisation pulse is received before a line of data has been transferred to the printhead and causes the print job to fail at that line. If there is no risk of buffer underrun then printing can safely start once at least one band has been downloaded. 25 If there is a risk of a buffer underrun occurring due to an interruption of compressed page data transfer, then the safest approach is to only start printing once all of the bands have been loaded for a complete page. This means that some latency (dependent on USB speed) will be incurred before printing the first page. Bands for WO 2005/120835 PCT/AU2004/000706 385 subsequent pages can be downloaded during the printing of the first page as band memory is freed up, so the transfer latency is not incurred for these pages. A Storage SoPEC (Section 6.2.6), or other memory local to the printer but external to SoPEC, could be added to the system, to provide guaranteed bandwidth data delivery. 5 The most efficient page banding strategy is likely to be determined on a per page/ print job.basis and so SoPEC will support the use of bands of any size. 9.6.3 USB Operation in Multi-SoPEC Systems In a system containing more than one SoPECs, the high bandwidth communication path between SoPECs is via USB. Typically, one SoPEC, the ISCMaster, has a USB connection to the host PC, and is responsible for 10 receiving and distributing page data for itself and all other SoPECs in the system. The ISCMaster acts as a USB Device on the host PC's USB bus, and as the USB Host on a USB bus local to the printer. Any local USB bus in the printer is logically separate from the host PC's USB bus; a SoPEC device does not act as a USB Hub. Therefore the host PC sees the entire printer system as a single USB function. The SoPEC UHU supports three ports on the printer's USB bus, allowing the direct connection of up to three 15 additional SoPEC devices (or other USB devices). If more than three USB devices need to be connected, two options are available: * Expand the number of ports on the printer USB bus using a USB Hub chip. * Create one or more additional printer USB busses, using the UHU ports on other SoPEC devices Figure 16 shows these options. 20 Since the UDU and UHU for a single SoPEC are on logically different USB busses, data flow between them is via the on-chip DRAM, under the control of the SoPEC CPU. There is no direct communication, either at control or data level, between the UDU and the UHU. For example, when the host PC sends compressed page data to a multi-SoPEC system, all the data for all SoPECs must pass via the DRAM on the ISCMaster SoPEC. Any control or status messages between the host and any SoPEC will also pass via the ISCMaster's DRAM. 25 Further, while the UDU on SoPEC supports multiple USB interfaces and endpoints within a single USB device function, it typically does not have a mechanism to identify at the USB level which SoPEC is the ultimate destination of a particular USB data or control transfer. Therefore software on the CPU needs to redirect data on a transfer-by-transfer basis, either by parsing a header embedded in the USB data, or based on previously communicated control information from the host PC. The software overhead involved in this 30 management adds to the overall latency of compressed page download for a multi-SoPEC system. The UDU and UHU contain highly configurable DMA controllers that allow the CPU to direct USB data to and from DRAM buffers in a flexible way, and to monitor the DMA for a variety of conditions. This means that the CPU can manage the DRAM buffers between the UDU and the UHU without ever needing to physically move or copy packet data in the DRAM.
WO 2005/120835 PCT/AU2004/000706 386 10 SOPEC USE CASES 10.1 INTRODUCTION This chapter is intended to give an overview of a representative set of scenarios or use cases which SoPEC 5 can perform. SoPEC is by no means restricted to the particular use cases described and not every SoPEC system is considered here. In this chapter, SoPEC use is described under four headings: 1) Normal operation use cases. 2) Security use cases. 10 3) Miscellaneous use cases. 4) Failure mode use cases. Use cases for both single and multi-SoPEC systems are outlined. Some tasks may be composed of a number of sub-tasks. The realtime requirements for SoPEC software tasks are discussed in "Central Processing Unit (CPU)" under 15 Section 11.3 Realtime requirements. 10.2 NORMAL OPERATION IN A SINGLE SOPEC SYSTEM WITH USB HOST CONNECTION SoPEC operation is broken up into a number of sections which are outlined below. Buffer management in a SoPEC system is normally performed by the host. 10.2.1 Powerup 20 Powerup describes SoPEC initialisation following an external reset or the watchdog timer system reset. A typical powerup sequence is: 1) Execute reset sequence for complete SoPEC. 2) CPU boot from ROM. 3) Basic configuration of CPU peripherals, UDU and DIU. DRAM initialisation. USB Wakeup. 25 4) Download and authentication of program (see Section 10.5.2). 5) Execution of program from DRAM. 6) Retrieve operating parameters from PRINTERQA and authenticate operating parameters. 7) Download and authenticate any further datasets.
WO 2005/120835 PCT/AU2004/000706 387 10.2.2 Wakeup The CPU can put different sections of SoPEC into sleep mode by writing to registers in the CPR block (chapter 18). This can include disabling both the DRAM and the CPU itself, and in some circumstances the UDU as well. Some system state is always stored in the power-safe storage (PSS) block. 5 Wakeup describes SoPEC recovery from sleep mode with the CPU and DRAM disabled. Wakeup can be initiated by a hardware reset, an event on the device or host USB interfaces, or an event on a GPIO pin. A typical USB wakeup sequence is: 1) Execute reset sequence for sections of SoPEC in sleep mode. 2) CPU boot from ROM, if CPU-subsystem was in sleep mode. 10 3) Basic configuration of CPU peripherals and DIU, and DRAM initialisation, if required. 4) Download and authentication of program using results in Power-Safe Storage (PSS) (see Section 10.5.2). 5) Execution of program from DRAM. 6) Retrieve operating parameters from PRINTERQA and authenticate operating parameters. 15 7) Download and authenticate using results in PSS of any further datasets (programs). 10.2.3 Print initialization This sequence is typically performed at the start of a print job following powerup or wakeup: 1) Check amount of ink remaining via QA chips. 2) Download static data e.g. dither matrices, dead nozzle tables from host to DRAM. 20 3) Check printhead temperature, if required, and configure printhead with firing pulse profile etc. accordingly. 4) Initiate printhead pre-heat sequence, if required. 10.2.4 First page download Buffer management in a SoPEC system is normally performed by the host. 25 First page, first band download and processing: 1) The host communicates to the SoPEC CPU over the USB to check that DRAM space remaining is sufficient to download the first band. 2) The host downloads the first band (with the page header) to DRAM. 3) When the complete page header has been downloaded the SoPEC CPU processes the page header, 30 calculates PEP register commands and writes directly to PEP registers or to DRAM. 4) If PEP register commands have been written to DRAM, execute PEP commands from DRAM via PCU. Remaining bands download and processing: WO 2005/120835 PCT/AU2004/000706 388 1) Check DRAM space remaining is sufficient to download the next band. 2) Download the next band with the band header to DRAM. 3) When the complete band header has been downloaded, process the band header according to whichever band-related register updating mechanism is being used. 5 10.2.5 Start printing 1) Wait until at least one band of the first page has been downloaded. 2) Start all the PEP Units by writing to their Go registers, via PCU commands executed from DRAM or direct CPU writes. A rapid startup order for the PEP units is outlined in Table 12. Table 12. Typical PEP Unit startup order for printing a page. 1 DNC 2 DWU 3 HCU 4 PHI 5 LLU 6 CFU,SFUTFU 7 CDU 8 TE, LBD 10 3) Print ready interrupt occurs (from PHI). 4) Start motor control, if first page, otherwise feed the next page. This step could occur before the print ready interrupt. 5) Drive LEDs, monitor paper status. 15 6) Wait for page alignment via page sensor(s) GPIO interrupt. 7) CPU instructs PHI to start producing line syncs and hence commence printing, or wait for an external device to produce line syncs. 8) Continue to download bands and process page and band headers for next page. 10.2.6 Next page(s) download 20 As for first page download, performed during printing of current page.
WO 2005/120835 PCT/AU2004/000706 389 10.2.7 Between bands When the finished band flags are asserted band related registers in the CDU, LBD, TE need to be re programmed before the subsequent band can be printed. The finished band flag interrupts the CPU to tell the CPU that the area of memory associated with the band is now free. Typically only 3-5 commands per 5 decompression unit need to be executed. These registers can be either: * Reprogrammed directly by the CPU after the band has finished e Update automatically from shadow registers written by the CPU while the previous band was being processed 10 Alternatively, PCU commands can be set up in DRAM to update the registers without direct CPU intervention. The PCU commands can also operate by direct writes between bands, or via the shadow registers. 10.2.8 During page print Typically during page printing ink usage is communicated to the QA chips. 15 1) Calculate ink printed (from PHI). 2) Decrement ink remaining (via QA chips). 3) Check amount of ink remaining (via QA chips). This operation may be better performed while the page is being printed rather than at the end of the page. 10.2.9 Page finish 20 These operations are typically performed when the page is finished: 1) Page finished interrupt occurs from PHI. 2) Shutdown the PEP blocks by de-asserting their Go registers. A typical shutdown order is defined in Table 13. This will set the PEP Unit state-machines to their idle states without resetting their configuration registers. 25 3) Communicate ink usage to QA chips, if required. Table 13. End of page shutdown order for PEP Units 1 PHI (will shutdown by itself in the normal case at the end of a page) 2 DWU (shutting this down stalls the DNC and therefore the HCU and above) 3 LLU (should already be halted due to PHI at end of last line of page) 4 TE (this is the only dot supplier likely to be running, halted by the HCU) WO 2005/120835 PCT/AU2004/000706 390 5 CDU (this is likely to already be halted due to end of contone band) 6 CFU, SFU, TFU, LBD (order unimportant, and should already be halted due to end of band) 7 HCU, DNC (order unimportant, should already have halted) 10.2.10 Start of next page These operations are typically performed before printing the next page: 1) Re-program the PEP Units via PCU command processing from DRAM based on page header. 2) Go to Start printing. 5 10.2.11 End of document 1) Stop motor control. 10.2.12 Sleep mode The CPU can put different sections of SoPEC into sleep mode by writing to registers in the CPR block described in Section 18. 10 1) Instruct host PC via USB that SoPEC is about to sleep. 2) Store reusable authentication results in Power-Safe Storage (PSS). 3) Put SoPEC into defined sleep mode. 10.3 NORMAL OPERATION IN A MULTI-SOPEC SYSTEM - ISCMASTER SoPEC In a multi-SoPEC system the host generally manages program and compressed page download to all the 15 SoPECs. Inter-SoPEC communication is over local USB links, which will add a latency. The SoPEC with the USB connection to the host is the ISCMaster. In a multi-SoPEC system one of the SoPECs will be the PrintMaster. This SoPEC must manage and control sensors and actuators e.g. motor control. These sensors and actuators could be distributed over all the SoPECs in the system. An ISCMaster SoPEC may also be the PrintMaster SoPEC. 20 In a multi-SoPEC system each printing SoPEC will generally have its own PRINTER_QA chip (or at least access to a PRINTERQA chip that contains the SoPEC's SOPEC id-key) to validate operating parameters and ink usage. The results of these operations may be communicated to the PrintMaster SoPEC. In general the ISCMaster may need to be able to: * Send messages to the ISCSlaves which will cause the ISCSlaves to send their status to the 25 ISCMaster. e Instruct the ISCSlaves to perform certain operations. As the local USB links represent an insecure interface, commands issued by the ISCMaster are regarded as user mode commands. Supervisor mode code running on the SoPEC CPUs will allow or disallow these commands. The software protocol needs to be constructed with this in mind.
WO 2005/120835 PCT/AU2004/000706 391 The ISCMaster will initiate all communication with the ISCSlaves. SoPEC operation is broken up into a number of sections which are outlined below. 10.3.1 Powerup Powerup describes SoPEC initialisation following an external reset or the watchdog timer system.reset. 5 1) Execute reset sequence for complete SoPEC. 2) CPU boot from ROM. 3) Basic configuration of CPU peripherals, UDU and DIU. DRAM initialisation. USB device wakeup. 4) Download and authentication of program (see Section 10.5.3). 5) Execution of program from DRAM. 10 6) Retrieve operating parameters from PRINTERQA and authenticate operating parameters. These parameters (or the program itself) will identify SoPEC as an ISCMaster. 7) Download and authenticate any further datasets (programs). 8) Send datasets (programs) to all attached ISCSlaves. 9) ISCMaster master SoPEC then waits for a short time to allow the authentication to take place on 15 the ISCSlave SoPECs. 10) Each ISCSlave SoPEC is polled for the result of its program code authentication process. 10.3.2 Wakeup The CPU can put different sections of SoPEC into sleep mode by writing to registers in the CPR block (chapter 18). This can include disabling both the DRAM and the CPU itself, and in some circumstances the 20 UDU as well. Some system state is always stored in the power-safe storage (PSS) block. Wakeup describes SoPEC recovery from sleep mode with the CPU and DRAM disabled. Wakeup can be initiated by a hardware reset, an event on the device or host USB interfaces, or an event on a GPIO pin. A typical USB wakeup sequence is: 1) Execute reset sequence for sections of SoPEC in sleep mode. 25 2) CPU boot from ROM, if CPU-subsystem was in sleep mode. 3) Basic configuration of CPU peripherals and DIU, and DRAM initialisation, if required. 4) SoPEC identification from USB activity whether it is the ISCMaster (unless the SoPEC CPU has explicitly disabled this function). 5) Download and authentication of program using results in Power-Safe Storage (PSS) (see Section 30 10.5.3). 6) Execution of program from DRAM. 7) Retrieve operating parameters from PRINTERQA and authenticate operating parameters. 8) Download and authenticate any further datasets (programs) using results in Power-Safe Storage (PSS) (see Section 10.5.3).
WO 2005/120835 PCT/AU2004/000706 392 9) Following steps as per Powerup. 10.3.3 Print initialization This sequence is typically performed at the start of a print job following powerup or wakeup: 1) Check amount of ink remaining via QA chips which may be present on a ISCSlave SoPEC. 5 2) Download static data e.g. dither matrices, dead nozzle tables from host to DRAM. 3) Check printhead temperature, if required, and configure printhead with firing pulse profile etc. accordingly. Instruct ISCSlaves to also perform this operation. 4) Initiate printhead pre-heat sequence, if required. Instruct ISCSlaves to also perform this operation 10.3.4 First page download 10 Buffer management in a SoPEC system is normally performed by the host. 1) The host communicates to the SoPEC CPU over the USB to check that DRAM space remaining is sufficient to download the first band to all SoPECs. 2) The host downloads the first band (with the page header) to each SoPEC, via the DRAM on the ISCMaster. 15 3) When the complete page header has been downloaded the SoPEC CPU processes the page header, calculates PEP register commands and write directly to PEP registers or to DRAM. 4) If PEP register commands have been written to DRAM, execute PEP commands from DRAM via PCU. Remaining first page bands download and processing: 20 1) Check DRAM space remaining is sufficient to download the next band in all SoPECs. 2) Download the next band with the band header to each SoPEC via the DRAM on the ISCMaster. 3) When the complete band header has been downloaded, process the band header according to whichever band-related register updating mechanism is being used. 10.3.5 Start printing 25 1) Wait until at least one band of the first page has been downloaded. 2) Start all the PEP Units by writing to their Go registers, via PCU commands executed from DRAM or direct CPU writes, in the suggested order defined in Table 12. 3) Print ready interrupt occurs (from PHI). Poll ISCSlaves until print ready interrupt. 4) Start motor control (which may be on an ISCSlave SoPEC), if first page, otherwise feed the next 30 page. This step could occur before the print ready interrupt. 5) Drive LEDS, monitor paper status (which may be on an ISCSlave SoPEC). 6) Wait for page alignment via page sensor(s) GPIO interrupt (which may be on an ISCSlave SoPEC). 7) If the LineSyncMaster is a SoPEC its CPU instructs PHI to start producing master line syncs. Otherwise wait for an external device to produce line syncs.
WO 2005/120835 PCT/AU2004/000706 393 8) Continue to download bands and process page and band headers for next page. 10.3.6 Next page(s) download As for first page download, performed during printing of current page. 10.3.7 Between bands 5 When the finished band flags are asserted band related registers in the CDU, LBD, TE need to be re programmed before the subsequent band can be printed. The finished band flag interrupts the CPU to tell the CPU that the area of memory associated with the band is now free. Typically only 3-5 commands per decompression unit need to be executed. These registers can be either: 10 * Reprogrammed directly by the CPU after the band has finished Update automatically from shadow registers written by the CPU while the previous band was being processed Alternatively, PCU commands can be set up in DRAM to update the registers without direct CPU intervention. The PCU commands can also operate by direct writes between bands, or via the shadow 15 registers. 10.3.8 During page print Typically during page printing ink usage is communicated to the QA chips. 1) Calculate ink printed (from PHI). 2) Decrement ink remaining (via QA chips). 20 3) Check amount of ink remaining (via QA chips). This operation may be better performed while the page is being printed rather than at the end of the page. 10.3.9 Page finish These operations are typically performed when the page is finished: 1) Page finished interrupt occurs from PHI. Poll ISCSlaves for page finished interrupts. 25 2) Shutdown the PEP blocks by de-asserting their Go registers in the suggested order in Table 13. This will set the PEP Unit state-machines to their startup states. 3) Communicate ink usage to QA chips, if required. 10.3.10 Start of next page These operations are typically performed before printing the next page: 30 1) Re-program the PEP Units via PCU command processing from DRAM based on page header. 2) Go to Start printing.
WO 2005/120835 PCT/AU2004/000706 394 10.3.11 End of document 1) Stop motor control. This may be on an ISCSlave SoPEC. 10.3.12 Sleep mode The CPU can put different sections of SoPEC into sleep mode by writing to registers in the CPR block (see 5 Section 18). This may be as a result of a command from the host or as a result of a timeout. 1) Inform host PC of which parts of SoPEC system are about to sleep. 2) Instruct ISCSlaves to enter sleep mode. 3) Store reusable cryptographic results in Power-Safe Storage (PSS). 4) Put ISCMaster SoPEC into defined sleep mode. 10 10.4 NORMAL OPERATION IN A MULTI-SoPEC SYSTEM - ISCSLAVE SoPEC This section the outline typical operation of an ISCSlave SoPEC in a multi-SoPEC system. ISCSlave SoPECs communicate with the ISCMaster SoPEC via local USB busses. Buffer management in a SoPEC system is normally performed by the host. 10.4.1 Powerup 15 Powerup describes SoPEC initialisation following an external reset or the watchdog timer system reset. A typical powerup sequence is: 1) Execute reset sequence for complete SoPEC. 2) CPU boot from ROM. 3) Basic configuration of CPU peripherals, UDU and DIU. DRAM initialisation. 20 4) Download and authentication of program (see Section 10.5.3). 5) Execution of program from DRAM. 6) Retrieve operating parameters from PRINTERQA and authenticate operating parameters. 7) SoPEC identification by sampling GPIO pins to determine ISCId. Communicate ISCId to ISCMaster. 25 8) Download and authenticate any further datasets. 10.4.2 Wakeup The CPU can put different sections of SoPEC into sleep mode by writing to registers in the CPR block (chapter 18). This can include disabling both the DRAM and the CPU itself, and in some circumstances the UDU as well. Some system state is always stored in the power-safe storage (PSS) block. 30 Wakeup describes SoPEC recovery from sleep mode with the CPU and DRAM disabled. Wakeup can be initiated by a hardware reset, an event on the device or host USB interfaces, or an event on a GPIO pin.
WO 2005/120835 PCT/AU2004/000706 395 A typical USB wakeup sequence is: 1) Execute reset sequence for sections of SoPEC in sleep mode. 2) CPU boot from ROM, if CPU-subsystem was in sleep mode. 3) Basic configuration of CPU peripherals and DIU, and DRAM initialisation, if required. 5 4) Download and authentication of program using results in Power-Safe Storage (PSS) (see Section 10.5.3). 5) Execution of program from DRAM. 6) Retrieve operating parameters from PRINTERQA and authenticate operating parameters. 7) SoPEC identification by sampling GPIO pins to determine ISCId. Communicate ISCId to 10 ISCMaster. 8) Download and authenticate any further datasets. 10.4.3 Print initialization This sequence is typically performed at the start of a print job following powerup or wakeup: 1) Check amount of ink remaining via QA chips. 15 2) Download static data e.g. dither matrices, dead nozzle tables via USB to DRAM. 3) Check printhead temperature, if required, and configure printhead with firing pulse profile etc. accordingly. 4) Initiate printhead pre-heat sequence, if required. 10.4.4 First page download 20 Buffer management in a SoPEC system is normally performed by the host via the ISCMaster. 1) Check DRAM space remaining is sufficient to download the first band. 2) The host downloads the first band (with the page header) to DRAM, via USB from the ISCMaster. 3) When the complete page header has been downloaded, process the page header, calculate PEP register commands and write directly to PEP registers or to DRAM. 25 4) If PEP register commands have been written to DRAM, execute PEP commands from DRAM via PCU. Remaining first page bands download and processing: 1) Check DRAM space remaining is sufficient to download the next band. 2) The host downloads the first band (with the page header) to DRAM via USB from the ISCMaster. 30 3) When the complete band header has been downloaded, process the band header according to whichever band-related register updating mechanism is being used. 10.4.5 Start printing 1) Wait until at least one band of the first page has been downloaded.
WO 2005/120835 PCT/AU2004/000706 396 2) Start all the PEP Units by writing to their Go registers, via PCU commands executed from DRAM or direct CPU writes, in the order defined in Table 12. 3) Print ready interrupt occurs (from PHI). Communicate to PrintMaster via USB. 4) Start motor control, if attached to this ISCSlave, when requested by PrintMaster, if first page, 5 otherwise feed next page. This step could occur before the print ready interrupt 5) Drive LEDS, monitor paper status, if on this ISCSlave SoPEC, when requested by PrintMaster 6) Wait for page alignment via page sensor(s) GPIO interrupt, if on this ISCSlave SoPEC, and send to PrintMaster. 7) Wait for line sync and commence printing. 10 8) Continue to download bands and process page and band headers for next page. 10.4.6 Next page(s) download As for first band download, performed during printing of current page. 10.4.7 Between bands When the finished band flags are asserted band related registers in the CDU, LBD, TE need to be re 15 programmed before the subsequent band can be printed. The finished band flag interrupts the CPU to tell the CPU that the area of memory associated with the band is now free. Typically only 3-5 commands per decompression unit need to be executed. These registers can be either: Reprogrammed directly by the CPU after the band has finished 20 * Update automatically from shadow registers written by the CPU while the previous band was being processed Alternatively, PCU commands can be set up in DRAM to update the registers without direct CPU intervention. The PCU commands can also operate by direct writes between bands, or via the shadow registers. 25 10.4.8 During page print Typically during page printing ink usage is communicated to the QA chips. 1) Calculate ink printed (from PHI). 2) Decrement ink remaining (via QA chips). 3) Check amount of ink remaining (via QA chips). This operation may be better performed while the 30 page is being printed rather than at the end of the page. 10.4.9 Page finish These operations are typically performed when the page is finished: 1) Page finished interrupt occurs from PHI. Communicate page finished interrupt to PrintMaster.
WO 2005/120835 PCT/AU2004/000706 397 2) Shutdown the PEP blocks by de-asserting their Go registers in the suggested order in Table 13. This will set the PEP Unit state-machines to their startup states. 3) Communicate ink usage to QA chips, if required. 10.4.10 Start of next page 5 These operations are typically performed before printing the next page: 1) Re-program the PEP Units via PCU command processing from DRAM based on page header. 2) Go to Start printing. 10.4.11 End of document Stop motor control, if attached to this ISCSlave, when requested by PrintMaster. 10 10.4.12 Powerdown In this mode SoPEC is no longer powered. 1) Powerdown ISCSlave SoPEC when instructed by ISCMaster. 10.4.13 Sleep The CPU can put different sections of SoPEC into sleep mode by writing to registers in the CPR block (see 15 Section 18). This may be as a result of a command from the host or ISCMaster or as a result of a timeout. 1) Store reusable cryptographic results in Power-Safe Storage (PSS). 2) Put SoPEC into defined sleep mode. 10.5 SECURITY USE CASES Please see the 'SoPEC Security Overview' document for a more complete description of SoPEC security 20 issues. The SoPEC boot operation is described in the ROM chapter of the SoPEC hardware design specification, Section 19.2. 10.5.1 Communication with the QA chips Communication between SoPEC and the QA chips (i.e. INKQA and PRINTERQA) will take place on at least a per power cycle and per page basis. Communication with the QA chips has three principal purposes: 25 validating the presence of genuine QA chips (i.e the printer is using approved consumables), validation of the amount of ink remaining in the cartridge and authenticating the operating parameters for the printer. After each page has been printed, SoPEC is expected to communicate the number of dots fired per ink plane to the QA chipset. SoPEC may also initiate decoy communications with the QA chips from time to time. Process: 30 * When validating ink consumption SoPEC is expected to principally act as a conduit between the PRINTERQA and INKQA chips and to take certain actions (basically enable or disable printing WO 2005/120835 PCT/AU2004/000706 398 and report status to host PC) based on the result. The communication channels are insecure but all traffic is signed to guarantee authenticity. Known Weaknesses * If the secret keys in the QA chips are exposed or cracked then the system, or parts of it, is 5 compromised. * The SoPEC unique key must be kept safe from JTAG, scan or user code access if possible. Assumptions: [1] The QA chips are not involved in the authentication of downloaded SoPEC code [ 2] The QA chip in the ink cartridge (INKQA) does not directly affect the operation of the cartridge 10 in any way i.e. it does not inhibit the flow of ink etc. 10.5.2 Authentication of downloaded code in a single SoPEC system Process: 1) SoPEC identifies where to download program from (LSS interface, USB or indirectly from Flash). 2) The program is downloaded to the embedded DRAM. 15 3) The CPU calculates a SHA- 1 hash digest of the downloaded program. 4) The ResetSrc register in the CPR block is read to determine whether or not a power-on reset occurred. 5) If a power-on reset occurred the signature of the downloaded code (which needs to be in a known location such as the first or last N bytes of the downloaded code) is decrypted via RSA using the 20 appropriate Silverbrook public bootOkey stored in ROM. This decrypted signature is the expected SHA-1 hash of the accompanying program. If a power-on reset did not occur then the expected SHA-1 hash is retrieved from the PSS and the compute intensive decryption is not required. 6) The calculated and expected hash values are compared and if they match then the programs authenticity has been verified. 25 7) If the hash values do not match then the host PC is notified of the failure and the SoPEC will await a new program download. 8) If the hash values match then the CPU starts executing the downloaded program. 9) If, as is very likely, the downloaded program wishes to download subsequent programs (such as OEM code) it is responsible for ensuring the authenticity of everything it downloads. The 30 downloaded program may contain public keys that are used to authenticate subsequent downloads, thus forming a hierarchy of authentication. The SoPEC ROM does not control these authentications - it is solely concerned with verifying that the first program downloaded has come from a trusted source. 10) At some subsequent point OEM code starts executing. The Silverbrook supervisor code acts as an 35 O/S to the OEM user mode code. The OEM code must access most SoPEC functionality via system calls to the Silverbrook code.
WO 2005/120835 PCT/AU2004/000706 399 11) The OEM code is expected to perform some simple 'turn on the lights' tasks after which the host PC is informed that the printer is ready to print and the Start Printing use case comes into play. 10.5.3 Authentication of downloaded code in a multi-SoPEC system, USB download case 10.5.3.1 ISCMaster SoPEC Process: 5 1) The program is downloaded from the host to the embedded DRAM. 2) The CPU calculates a SHA- 1 hash digest of the downloaded program. 3) The ResetSrc register in the CPR block is read to determine whether or not a power-on reset occurred. 4) If a power-on reset occurred the signature of the downloaded code (which needs to be in a known 10 location such as the first or last N bytes of the downloaded code) is decrypted via RSA using the appropriate Silverbrook public boot0key stored in ROM. This decrypted signature is the expected SHA- 1 hash of the accompanying program. If a power-on reset did not occur then the expected SHA- 1 hash is retrieved from the PSS and the compute intensive decryption is not required. 5) The calculated and expected hash values are compared and if they match then the programs 15 authenticity has been verified. 6) If the hash values do not match then the host PC is notified of the failure and the SoPEC will await a new program download. 7) If the hash values match then the CPU starts executing the downloaded program. 8) The downloaded program will contain directions on how to send programs to the ISCSlaves 20 attached to the ISCMaster. 9) The ISCMaster downloaded program will poll each ISCSlave SoPEC for the results of its authentication process and to determine their ISCIds if required. 10) If any ISCSlave SoPEC reports a failed authentication then the ISCMaster communicates this to the host PC and the SoPEC will await a new program download. 25 11) If all ISCSlaves report successful authentication then the downloaded program is responsible for the downloading, authentication and distribution of subsequent programs within the multi-SoPEC system. 12) At some subsequent point OEM code starts executing. The Silverbrook supervisor code acts as an O/S to the OEM user mode code. The OEM code must access most SoPEC functionality via system 30 calls to the Silverbrook code. 13) The OEM code is expected to perform some simple 'turn on the lights' tasks after which the master SoPEC determines that all SoPECs are ready to print. The host PC is informed that the printer is ready to print and the Start Printing use case comes into play.
WO 2005/120835 PCT/AU2004/000706 400 10.5.3.2 ISCSIave SoPEC Process: 1) When the CPU comes out of reset the UDU is already configured to receive data from the USB. 2) The program is downloaded (via USB) to embedded DRAM. 3) The CPU calculates a SHA- 1 hash digest of the downloaded program. 5 4) The ResetSrc register in the CPR block is read to determine whether or not a power-on reset occurred. 5) If a power-on reset occurred the signature of the downloaded code (which needs to be in a known location such as the first or last N bytes of the downloaded code) is decrypted via RSA using the appropriate Silverbrook public bootOkey stored in ROM. This decrypted signature is the expected 10 SHA-1 hash of the accompanying program. The encryption algorithm is likely to be a public key algorithm such as RSA. If a power-on reset did not occur then the expected SHA-1 hash is retrieved from the PSS and the compute intensive decryption is not required. 6) The calculated and expected hash values are compared and if they match then the programs authenticity has been verified. 15 7) If the hash values do not match, then the ISCSlave device will await a new program again 8) If the hash values match then the CPU starts executing the downloaded program. 9) It is likely that the downloaded program will communicate the result of its authentication process to the ISCMaster. The downloaded program is responsible for determining the SoPECs ISCId, receiving and authenticating any subsequent programs. 20 10) At some subsequent point OEM code starts executing. The Silverbrook supervisor code acts as an O/S to the OEM user mode code. The OEM code must access most SoPEC functionality via system calls to the Silverbrook code. 11) The OEM code is expected to perform some simple 'turn on the lights' tasks after which the master SoPEC is informed that this slave is ready to print. The Start Printing use case then comes 25 into play. 10.5.4 Authentication and upgrade of operating parameters for a printer The SoPEC IC will be used in a range of printers with different capabilities (e.g. A3/A4 printing, printing speed, resolution etc.). It is expected that some printers will also have a software upgrade capability which 30 would allow a user to purchase a license that enables an upgrade in their printer's capabilities (such as print speed). To facilitate this it must be possible to securely store the operating parameters in the PRINTERQA chip, to securely communicate these parameters to the SoPEC and to securely reprogram the parameters in the event of an upgrade. Note that each printing SoPEC (as opposed to a SoPEC that is only used for the storage of data) will have its own PRINTERQA chip (or at least access to a PRINTERQA that contains the WO 2005/120835 PCT/AU2004/000706 401 SoPEC's SoPECid key). Therefore both ISCMaster and ISCSlave SoPECs will need to authenticate operating parameters. Process: 1) Program code is downloaded and authenticated as described in sections 10.5.2 and 10.5.3 above. 5 2) The program code has a function to create the SoPECid-key from the unique SoPECid that was programmed when the SoPEC was manufactured. 3) The SoPEC retrieves the signed operating parameters from its PRINTERQA chip. The PRINTERQA chip uses the SoPEC_id_key (which is stored as part of the pairing process executed during printhead assembly manufacture & test) to sign the operating parameters which are 10 appended with a random number to thwart replay attacks. 4) The SoPEC checks the signature of the operating parameters using its SoPECid-key. If this signature authentication process is successful then the operating parameters are considered valid and the overall boot process continues. If not the error is reported to the host PC. 10.6 MISCELLANEOUS USE CASES 15 There are many miscellaneous use cases such as the following examples. Software running on the SoPEC CPU or host will decide on what actions to take in these scenarios. 10.6.1 Disconnect / Re-connect of QA chips. 1) Disconnect of a QA chip between documents or if ink runs out mid-document. 2) Re-connect of a QA chip once authenticated e.g. ink cartridge replacement should allow the system 20 to resume and print the next document 10.6.2 Page arrives before print ready interrupt. 1) Engage clutch to stop paper until print ready interrupt occurs. 10.6.3 Dead-nozzle table upgrade This sequence is typically performed when dead nozzle information needs to be updated by performing a 25 printhead dead nozzle test. 1) Run printhead nozzle test sequence 2) Either host or SoPEC CPU converts dead nozzle information into dead nozzle table. 3) Store dead nozzle table on host. 4) Write dead nozzle table to SoPEC DRAM.
WO 2005/120835 PCT/AU2004/000706 402 10.7 FAILURE MODE USE CASES 10.7.1 System errors and security violations System errors and security violations are reported to the SoPEC CPU and host. Software running on the SoPEC CPU or host will then decide what actions to take. 5 Silverbrook code authentication failure. 1) Notify host PC of authentication failure. 2) Abort print run. OEM code authentication failure. 1) Notify host PC of authentication failure. 10 2) Abort print run. Invalid QA chip(s). 1) Report to host PC. 2) Abort print run. MMU security violation interrupt. 15 1) This is handled by exception handler. 2) Report to host PC 3) Abort print run. Invalid address interrupt from PCU. 1) This is handled by exception handler. 20 2) Report to host PC. 3) Abort print run. Watchdog timer interrupt. 1) This is handled by exception handler. 2) Report to host PC. 25 3) Abort print run. Host PC does not acknowledge message that SoPEC is about to power down. 1) Power down anyway. 10.7.2 Printing errors Printing errors are reported to the SoPEC CPU and host. Software running on the host or SoPEC CPU will 30 then decide what actions to take.
WO 2005/120835 PCT/AU2004/000706 403 Insufficient space available in SoPEC compressed band-store to download a band. 1) Report to the host PC. Insufficient ink to print. 1) Report to host PC. 5 Page not downloaded in time while printing. 1) Buffer underrun interrupt will occur. 2) Report to host PC and abort print run. JPEG decoder error interrupt. 1) Report to host PC.CPU Subsystem 10 11 CENTRAL PROCESSING UNIT (CPU) 11.1 OVERVIEW The CPU block consists of the CPU core, caches, MMU, RDU and associated logic. The principal tasks for the program running on the CPU to fulfill in the system are: 15 Communications: * Control the flow of data to and from the USB interfaces to and from the DRAM * Communication with the host via USB e Communication with other USB devices (which may include other SoPECs in the system, digital cameras, additional communication devices such as ethernet-to-USB chips) when SoPEC is 20 functioning as a USB host e Communication with other devices (utilizing the MMI interface block) via miscellaneous protocols (including but not limited to Parallel Port, Generic 68K/i960 CPU interfaces, serial interfaces Intel SBB, Motorola SPI etc.). * Running the USB device drivers 25 e Running additional protocol stacks (such as ethernet) PEP Subsystem Control: * Page and band header processing (may possibly be performed on host PC) * Configure printing options on a per band, per page, per job or per power cycle basis * Initiate page printing operation in the PEP subsystem 30 0 Retrieve dead nozzle information from the printhead and forward to the host PC or process locally " Select the appropriate firing pulse profile from a set of predefined profiles based on the printhead characteristics * Retrieve printhead information (from printhead and associated serial flash) WO 2005/120835 PCT/AU2004/000706 404 Security: * Authenticate downloaded program code e Authenticate printer operating parameters e Authenticate consumables via the PRINTERQA and INKQA chips 5 0 Monitor ink usage e Isolation of OEM code from direct access to the system resources Other: * Drive the printer motors using the GPIO pins e Monitoring the status of the printer (paper jam, tray empty etc.) 10 e Driving front panel LEDs and/or other display devices " Perform post-boot initialisation of the SoPEC device * Memory management (likely to be in conjunction with the host PC) e Handling higher layer protocols for interfaces implemented with the MMI e Image processing functions such as image scaling, cropping, rotation, white-balance, color space 15 conversion etc. for printing images directly from digital cameras (e.g. via PictBridge application software) * Miscellaneous housekeeping tasks To control the Print Engine Pipeline the CPU is required to provide a level of performance at least equivalent to a 16-bit Hitachi H8-3664 microcontroller running at 16 MHz. An as yet undetermined amount of additional 20 CPU performance is needed to perform the other tasks, as well as to provide the potential for such activity as Netpage page assembly and processing, RIPing etc. The extra performance required is dominated by the signature verification task, direct camera printing image processing functions (i.e. color space conversion) and the USB (host and device) management task. A number of CPU cores have been evaluated and the LEON P1754 is considered to be the most appropriate solution. A diagram of the CPU block is shown in Figure 17 25 below. 11.2 DEFINITIONS OF I/Os Table 14. CPU Subsystem I/Os E........o.................... ... ........ Clocks and Resets prstn 1 In Global reset. Synchronous to pclk, active low. Pclk 1 In Global clock CPU to DIU DRAM interface Cpu adr[21:2] 20 Out Address bus for both DRAM and peripheral access Dram cou-data[255 256 In Read data from the DRAM WO 2005/120835 PCT/AU2004/000706 405 :0] Cpu_diu-rreq 1 Out Read request to the DIU DRAM Diu-cpu-rack 1 In Acknowledge from DIU that read request has been accepted. Diu.cpu-rvalid 1 In Signal from DIU telling the CPU that valid read data is on the dram-cpudata bus Cpu-diu.wdatavalid 1 Out Signal from the CPU to the DIU indicating that the data currently on the cpu_diu_wdata bus is valid and should be committed to the DIU posted write buffer Diu-cpuwwrite-rdy 1 In Signal from the DIU indicating that the posted write buffer is empty cpu diu wdadr[21:4 18 Out Write address bus to the DIU cpu-diuwdata[1 27: 128 Out Write data bus to the DIU 0] cpudiuwmask[1 5: 16 Out Write mask for the cpudiu_ wdata bus. Each bit 0] corresponds to a byte of the 128-bit cpu.diu_wdata bus. CPU to peripheral blocks Cpu-rwn 1 Out Common read/not-write signal from the CPU Cpu.acode[1:0] 2 Out CPU access code signals. cpu-acode[0] - Program (0) / Data (1) access cpu-acode[1] - User (0) / Supervisor (1) access Cpu-dataout[31:0] 32 Out Data out to the peripheral blocks. This is driven at the same time as the cpuadr and request signals. Cpu-cpr-sel 1 Out CPR block select. Cpr.cpu-rdy 1 In Ready signal to the CPU. When cpr._cpu.rdy is high it indicates the last cycle of the access. For a write cycle this means cpu.dataout has been registered by the CPR block and for a read cycle this means the data on cprcpu_data is valid. Cpr.cpu.berr 1 In CPR bus error signal to the CPU. Cpr-cpu-data[31:0] 32 In Read data bus from the CPR block Cpu-gpiosel 1 Out GPIO block select. gpio-cpu-rdy 1 In GPIO ready signal to the CPU. gpioscpu-berr 1 In GPIO bus error signal to the CPU. gpiocpudata[31:0] 32 In Read data bus from the GPIO block Cpu-icu-sel 1 Out ICU block select. Icu-cpurdy 1 In ICU ready signal to the CPU. Icu-cpuberr 1 In ICU bus error signal to the CPU. lcu.cpu-data[31:0] 32 In Read data bus from the ICU block CpuIss-sel 1 Out LSS block select. lssscpu-rdy 1 In LSS ready signal to the CPU. Isscpu-berr 1 In LSS bus error signal to the CPU.
WO 2005/120835 PCT/AU2004/000706 406 Iss-cpu-data[31:0] 32 In Read data bus from the LSS block Cpu-pcusel 1 Out PCU block select. Pcu-cpu-rdy 1 In PCU ready signal to the CPU. Pcu_cpuberr 1 In PCU bus error signal to the CPU. Pcu-cpu-data[31:0] 32 In Read data bus from the PCU block Cpu.mmi-sel 1 Out MMI block select. mmi-cpu-rdy 1 In MMI ready signal to the CPU. mmi-cpu-berr 1 In MMI bus error signal to the CPU. mmi-cpu-data[31:0] 32 In Read data bus from the MMI block Cpu-tim-sel 1 Out Timers block select. Timcpu-rdy 1 In Timers block ready signal to the CPU. Timcpuberr 1 In Timers bus error signal to the CPU. Tim.cpu-data31:0] 32 In Read data bus from the Timers block Cpu-rom.sel 1 Out ROM block select. Rom-cpu-rdy 1 In ROM block ready signal to the CPU. Rom-cpu-berr 1 In ROM bus error signal to the CPU. Rom-cpu.data[31:0 32 In Read data bus from the ROM block Cpu-pss-sel 1 Out PSS block select. Pss-cpu-rdy 1 In PSS block ready signal to the CPU. Pss-cpu-berr 1 In PSS bus error signal to the CPU. Psscpudata[31:0] 32 In Read data bus from the PSS block Cpu-diu-sel 1 Out DIU register block select. Diu-cpu-rdy 1 In DIU register block ready signal to the CPU. Diucpuberr 1 In DIU bus error signal to the CPU. Diucpu-data[31:0] 32 In Read data bus from the DIU block Cpu-uhusel 1 Out UHU register block select. Uhu-cpu-rdy 1 In UHU register block ready signal to the CPU. Uhu-cpu-berr 1 In UHU bus error signal to the CPU. Uhu-cpu-data[31:0] 32 In Read data bus from the UHU block Cpu-udu.sel 1 Out UDU register block select. Uducpu-rdy 1 In UDU register block ready signal to the CPU. Udu-cpu-berr 1 In UDU bus error signal to the CPU. Udu-cpudata[31:0] 32 In Read data bus from the UDU block Interrupt signals WO 2005/120835 PCT/AU2004/000706 407 Icu.cpu-ilevel[3:0] 3 In An interrupt is asserted by driving the appropriate priority level on icu cpuiLevel. These signals must remain asserted until the CPU executes an interrupt acknowledge cycle. Cpu-icu-ilevel[3:0] 3 Out Indicates the level of the interrupt the CPU is acknowledging when cpuLack is high Cpu~iack 1 Out Interrupt acknowledge signal. The exact timing depends on the CPU core implementation Debug signals diuscpudebug-vali 1 In Signal indicating the data on the diu-cpudata bus is d valid debug data. tim cpu-debug-vali 1 In Signal indicating the data on the timcpudata bus is d valid debug data. mmi-cpu-debug-va 1 In Signal indicating the data on the mmi-cpudata bus is lid valid debug data. pcu-cpu-debugval 1 In Signal indicating the data on the pcucpLdata bus is id valid debug data. Isscpu debug-vali 1 In Signal indicating the data on the Iss.cpudata bus is d valid debug data. icu-cpu-debug-vali 1 In Signal indicating the data on the icu-cpudata bus is d valid debug data. gpio-cpu-debug-va 1 In Signal indicating the data on the gpio-cpu_data bus is lid valid debug data. cpr-cpu-debug-vali 1 In Signal indicating the data on the cprcpudata bus is d valid debug data. uhucpudebugval 1 In Signal indicating the data on the uhu-cpudata bus is id valid debug data. udu cpudebugval 1 In Signal indicating the data on the udu-cpu~data bus is id valid debug data. debug.dataout 32 Out Output debug data to be muxed on to the GPIO pins debugdata_valid 1 Out Debug valid signal indicating the validity of the data on debugdataout. This signal is used in all debug configurations debugcntr 33 Out Control signal for each debug data line indicating whether or not the debug data should be selected by the pin mux 11.2 11.3 Realtime requirements The SoPEC realtime requirements can be split into three categories: hard, firm and soft 11.3.1 Hard realtime requirements 5 Hard requirements are tasks that must be completed before a certain deadline or failure to do so will result in an error perceptible to the user (printing stops or functions incorrectly). There are three hard realtime tasks: WO 2005/120835 PCT/AU2004/000706 408 e Motor control: The motors which feed the paper through the printer at a constant speed during printing are driven directly by the SoPEC device. The generation of these signals is handled by the GPIO hardware (see section 14 for more details) but the CPU is responsible for enabling these signals (i.e. to start or stop the motors) and coordinating the movement of the paper with the 5 printing operation of the printhead. e Buffer management: Data enters the SoPEC via the USB (device/host) or MMI at an uneven rate and is consumed by the PEP subsystem at a different rate. The CPU is responsible for managing the DRAM buffers to ensure that neither overrun nor underrun occur. In some cases buffer management is performed under the direction of the host. 10 e Band processing: In certain cases PEP registers may need to be updated between bands. As the timing requirements are most likely too stringent to be met by direct CPU writes to the PCU a more likely scenario is that a set of shadow registers will programmed in the compressed page units before the current band is finished, copied to band related registers by the finished band signals and the processing of the next band will continue immediately. An alternative solution is that the CPU 15 will construct a DRAM based set of commands (see section 23.8.5 for more details) that can be executed by the PCU. The task for the CPU here is to parse the band headers stored in DRAM and generate a DRAM based set of commands for the next number of bands. The location of the DRAM based set of commands must then be written to the PCU before the current band has been processed by the PEP subsystem. It is also conceivable (but currently considered unlikely) that the 20 host PC could create the DRAM based commands. In this case the CPU will only be required to point the PCU to the correct location in DRAM to execute commands from. 11.3.2Firm requirements Firm requirements are tasks that should be completed by a certain time or failure to do so will result in a degradation of performance but not an error. The majority of the CPU tasks for SoPEC fall into this category 25 including all interactions with the QA chips, program authentication, page feeding, configuring PEP registers for a page or job, determining the firing pulse profile, communication of printer status to the host over the USB and the monitoring of ink usage. Compute-intensive operations for the CPU include authentication of downloaded programs and messages, and image processing functions such as cropping, rotation, white balance, color-space conversion etc. for printing images directly from digital cameras (e.g. via PictBridge 30 application software). Initial investigations indicate that the LEON processor, running at 192 MHz, will easily perform three authentications in under a second. Table 15. Expected firm requirements u_ 7 S M, Power-on to start of printing first page [USB and slave SoPEC enumeration, 3 - 3 secs or more RSA signature verifications, code and compressed page data download and chip initialisation] WO 2005/120835 PCT/AU2004/000706 409 Wakeup from sleep mode to start printing [3 or more SHA-1 / RSA operations, - 2 secs code and compressed page data download and chip re-initialisation Authenticate ink usage in the printer ~ 0.5 secs Determining firing pulse profile - 0.1 secs Page feeding, gap between pages OEM dependent Communication of printer status to host PC - 10 ms Configuring PEP registers 11.3.3 Soft requirements Soft requirements are tasks that need to be done but there are only light time constraints on when they need to be done. These tasks are performed by the CPU when there are no pending higher priority tasks. As the SoPEC CPU is expected to be lightly loaded these tasks will mostly be executed soon after they are 5 scheduled. 11.4 Bus PROTOCOLS As can be seen from Figure 17 above there are different buses in the CPU block and different protocols are used for each bus. There are three buses in operation: 11.4.1 AHB bus 10 The LEON CPU core uses an AMBA2.0 AHB bus to communicate with memory and peripherals (usually via an APB bridge). See the AMBA specification , section 5 of the LEON users manual and section 11.6.6.1 of this document for more details. 11.4.2 CPU to DIU bus This bus conforms to the DIU bus protocol described in Section 22.14.8. Note that the address bus used for 15 DIU reads (i.e. cpuadr(21:2)) is also that used for CPU subsystem with bus accesses while the write address bus (cpu_diu_wadr) and the read and write data buses (dramcpu__data and cpudiuwdata) are private buses between the CPU and the DIU. The effective bus width differs between a read (256 bits) and a write (128 bits). As certain CPU instructions may require byte write access this will need to be supported by both the DRAM write buffer (in the AHB bridge) and the DIU. See section 11.6.6.1 for more details. 20 11.4.3 CPU Subsystem Bus For access to the on-chip peripherals a simple bus protocol is used. The MMU must first determine which particular block is being addressed (and that the access is a valid one) so that the appropriate block select signal can be generated. During a write access CPU write data is driven out with the address and block select signals in the first cycle of an access. The addressed slave peripheral responds by asserting its ready signal 25 indicating that it has registered the write data and the access can complete. The write data bus (cpudataout) is common to all peripherals and is independent of the cpudiuwdata bus (which is a private bus between the WO 2005/120835 PCT/AU2004/000706 410 CPU and DRAM). A read access is initiated by driving the address and select signals during the first cycle of an access. The addressed slave responds by placing the read data on its bus and asserting its ready signal to indicate to the CPU that the read data is valid. Each block has a separate point-to-point data bus for read accesses to avoid the need for a tri-stateable bus. 5 All peripheral accesses are 32-bit (Programming note: char or short C types should not be used to access peripheral registers). The use of the ready signal allows the accesses to be of variable length. In most cases accesses will complete in two cycles but three or four (or more) cycles accesses are likely for PEP blocks or IP blocks with a different native bus interface. All PEP blocks are accessed via the PCU which acts as a bridge. The PCU bus uses a similar protocol to the CPU subsystem bus but with the PCU as the bus master. 10 The duration of accesses to the PEP blocks is influenced by whether or not the PCU is executing commands from DRAM. As these commands are essentially register writes the CPU access will need to wait until the PCU bus becomes available when a register access has been completed. This could lead to the CPU being stalled for up to 4 cycles if it attempts to access PEP blocks while the PCU is executing a command. The size and probability of this penalty is sufficiently small to have no significant impact on performance. 15 In order to support user mode (i.e. OEM code) access to certain peripherals the CPU subsystem bus propagates the CPU function code signals (cpuacode[1:0]). These signals indicate the type of address space (i.e. User/Supervisor and Program/Data) being accessed by the CPU for each access. Each peripheral must determine whether or not the CPU is in the correct mode to be granted access to its registers and in some cases (e.g. Timers and GPIO blocks) different access permissions can apply to different registers within the 20 block. If the CPU is not in the correct mode then the violation is flagged by asserting the block's bus error signal (block cpu berr) with the same timing as its ready signal (block cpu rdy) which remains reasserted. When this occurs invalid read accesses should return 0 and write accesses should have no effect. Figure 18 shows two examples of the peripheral bus protocol in action. A write to the LSS block from code running in supervisor mode is successfully completed. This is immediately followed by a read from a PEP 25 block via the PCU from code running in user mode. As this type of access is not permitted the access is terminated with a bus error. The bus error exception processing then starts directly after this - no further accesses to the peripheral should be required as the exception handler should be located in the DRAM. Each peripheral acts as a slave on the CPU subsystem bus and its behavior is described by the state machine in section 11.4.3.1 30 11.4.3.1 CPU subsystem bus slave state machine CPU subsystem bus slave operation is described by the state machine in Figure 19. This state machine will be implemented in each CPU subsystem bus slave. The only new signals mentioned here are the validaccess and regavailable signals. The validaccess is determined by comparing the cpu acode value with the block or register (in the case of a block that allow user access on a per register basis such as the GPIO block) access 35 permissions and asserting validaccess if the permissions agree with the CPU mode. The regavailable signal is only required in the PCU or in blocks that are not capable of two-cycle access (e.g. blocks containing imported IP with different bus protocols). In these blocks the regavailable signal is an internal signal used to WO 2005/120835 PCT/AU2004/000706 411 insert wait states (by delaying the assertion of block cpu rdy) until the CPU bus slave interface can gain access to the register. When reading from a register that is less than 32 bits wide the CPU subsystem's bus slave should return zeroes on the unused upper bits of the blockcpudata bus. 5 To support debug mode the contents of the register selected for debug observation, debugreg, are always output on the block cpudata bus whenever a read access is not taking place. See section 11.8 for more details of debug operation. 11.5 LEON CPU The LEON processor is an open-source implementation of the IEEE-1754 standard (SPARC V8) instruction 10 set. LEON is available from and actively supported by Gaisler Research (www.gaisler.com). The following features of the LEON-2 processor are utilised on SoPEC: * IEEE- 1754 (SPARC V8) compatible integer unit with 5-stage pipeline e Separate instruction and data caches (Harvard architecture), each a 1Kbyte direct mapped cache * 16 x 16 hardware multiplier (4-cycle latency) and radix-2 divider to implement the 15 MUL/DIV/MAC instructions in hardware * Full implementation of AMBA-2.0 AHB on-chip bus The standard release of LEON incorporates a number of peripherals and support blocks which are not included on SoPEC. The LEON core as used on SoPEC consists of: 1) the LEON integer unit, 2) the instruction and data caches (lKbyte each), 3) the cache control logic, 4) the AHB interface and 5) possibly the 20 AHB controller (although this functionality may be implemented in the LEON AHB bridge). The version of the LEON database that the SoPEC LEON components are sourced from is LEON2-1.0.7 although later versions can be used if they offer worthwhile functionality or bug fixes that affect the SoPEC design. The LEON core is clocked using the system clock, pclk, and reset using the prst-n section[1] signal. The 25 ICU asserts all the hardware interrupts using the protocol described in section 11.9. The LEON floating-point unit is not required. SoPEC will use the recommended 8 register window configuration. 11.5.1 LEON Registers Only two of the registers described in the LEON manual are implemented on SoPEC - the LEON configuration register and the Cache Control Register (CCR). The addresses of these registers are shown in 30 Table 19. The configuration register bit fields are described below and the CCR is described in section 11.7.1.1. 11.5.1.1 LEON configuration register The LEON configuration register allows runtime software to determine the settings of LEONs various configuration options. This is a read-only register whose value for the SoPEC ASIC will be Ox1271_8F00.
WO 2005/120835 PCT/AU2004/000706 412 Further descriptions of many of the bitfields can be found in the LEON manual. The values used for SoPEC are highlighted in bold for clarity. Table 16. LEON Configuration Register 4_k_ .. -. . U.1A Field Name bits) Description WriteProtection 1:0 Write protection type. 00 - none 01 - standard PCICore 3:2 PCI core type 00 - none 01 - InSilicon 10 - ESA 11 -Other FPUType 5:4 FPU type. 00 - none 01 - Meiko MemStatus 6 0 - No memory status and failing address register present 1 - Memory status and failing address register present Watchdog 7 0 - Watchdog timer not present (Note this refers to the LEON watchdog timer in the LEON timer block). 1 - Watchdog timer present UMUL/SMUL 8 0 - UMULJSMUL instructions are not implemented 1 - UMUL/SMUL Instructions are Implemented UDIV/SDIV 9 0 - UDIV/SDIV instructions are not implemented 1 - UDIV/SDIV Instructions are implemented DLSZ 11:10 Data cache line size in 32-bit words: 00 - 1 word 01 - 2 words 10 - 4 words 11 - 8 words DCSZ 14:12 Data cache size in kBbytes = 2". SoPEC DCSZ = 0. ILSZ 16:15 Instruction cache line size in 32-bit words: 00 - 1 word 01 - 2 words 10 - 4 words 11 - 8 words ICSZ 19:17 Instruction cache size in kBbytes = 2's. SoPEC ICSZ = 0. RegWin 24:20 The implemented number of SPARC register windows - 1. SoPEC value = 7. UMAC/SMAC 25 0 - UMAC/SMAC instructions are not implemented 1 - UMAC/SMAC instructions are implemented Watchpoints 28:26 The implemented number of hardware watchpoints. SoPEC value = 4. SDRAM 29 0 - SDRAM controller not present 1 - SDRAM controller present DSU 30 0 - Debug Support Unit not present 1 - Debug Support Unit present Reserved 31 Reserved. SoPEC value = 0.
WO 2005/120835 PCT/AU2004/000706 413 11.6 MEMORY MANAGEMENT UNIT (MMU) Memory Management Units are typically used to protect certain regions of memory from invalid accesses, to perform address translation for a virtual memory system and to maintain memory page status (swapped-in, swapped-out or unmapped) 5 The SoPEC MMU is a much simpler affair whose function is to ensure that all regions of the SoPEC memory map are adequately protected. The MMU does not support virtual memory and physical addresses are used at all times. The SoPEC MMU supports a full 32-bit address space. The SoPEC memory map is depicted in Figure 20 below. The MMU selects the relevant bus protocol and generates the appropriate control signals depending on the 10 area of memory being accessed. The MMU is responsible for performing the address decode and generation of the appropriate block select signal as well as the selection of the correct block read bus during a read access. The MMU supports all of the AHB bus transactions the CPU can produce. When an MMU error occurs (such as an attempt to access a supervisor mode only region when in user mode) a bus error is generated. While the LEON can recognise different types of bus error (e.g. data store error, 15 instruction access error) it handles them in the same manner as it handles all traps i.e it will transfer control to a trap handler. No extra state information is stored because of the nature of the trap. The location of the trap handler is contained in the TBR (Trap Base Register). This is the same mechanism as is used to handle interrupts. 11.6.1 CPU-bus peripherals address map 20 The address mapping for the peripherals attached to the CPU-bus is shown in Table 17 below. The MMU performs the decode of the high order bits to generate the relevant cpu blockselect signal. Apart from the PCU, which decodes the address space for the PEP blocks, and the ROM (whose final size has yet to be determined), each block only needs to decode as many bits of cpuadr[11:2] as required to address all the registers within the block. The effect of decoding fewer bits is to cause the address space within a block to be 25 duplicated many times (i.e. mirrored) depending on how many bits are required. Table 17. CPU-bus peripherals address map ROMbase Ox0000.0000 MMUbase Ox0003_0000 TIMbase Ox0003_1000 LSSbase Ox0003_2000 GPIObase Ox0003_3000 MMbase 0x0003_4000 ICU-base 0x0003_5000 WO 2005/120835 PCT/AU2004/000706 414 CPRbase 0x0003_6000 DIUbase 0x0003_7000 PSS-base Ox00038000 UHUbase Ox0003_9000 UDU-base 0x0003_A000 Reserved 0x0003_B000 to 0x0003_FFFF PCUbase Ox0004_0000 11.6.2 DRAM Region Mapping The embedded DRAM is broken into 8 regions, with each region defined by a lower and upper bound address and with its own access permissions. The association of an area in the DRAM address space with a MMvU region is completely under software 5 control. Table 18 below gives one possible region mapping. Regions should be defined according to their access requirements and position in memory. Regions that share the same access requirements and that are contiguous in memory may be combined into a single region. The example below is purely for indicative purposes - real mappings are likely to differ significantly from this. Note that the RegionBottom and RegionTop fields in this example include the DRAM base address offset (0x4000 0000) which is not required 10 when programming the RegionNTop and RegionNBottom registers. For more details, see 11.6.5.1 and 11.6.5.2. Table 18. Example region mapping Region RegionBotto-m RegionTopDecito 0 0x4000_0000 0x4000OFF Silverbrook OS (supervisor) data F 1 0x4000_1000 0x4000_BFF Silverbrook OS (supervisor) code F 2 0x4000_C000 0x4000_C3F Silverbrook (supervisor/user) data F 3 0x4000_C400 0x4000OCFF Silverbrook (supervisor/user) code F 4 0x4026_DOO 0x4026_D3F OEM (user) data F 5 0x4026_D400 0x4026_DFF OEM (user) code F 6 0x4027_EOOO 0x4027_FFF Shared Silverbrook/OEM space F 7 0x4000_DO00 0x4026_CFF Compressed page store (supervisor data) ] F Note that additional DRAM protection due to peripheral access is achieved in the DIU, see section 22.14.12.8 WO 2005/120835 PCT/AU2004/000706 415 11.6.3 Non-DRAM regions As shown in Figure 20 the DRAM occupies only 2.5 MBytes of the total 4 GB SoPEC address space. The non-DRAM regions of SoPEC are handled by the MMU as follows: ROM (0x0000_0000 to 0x0002_FFFF): The ROM block controls the access types allowed. The 5 cpu acode[:O] signals will indicate the CPU mode and access type and the ROM block asserts rom_cpuberr if an attempted access is forbidden. The protocol is described in more detail in section 11.4.3. Like the other peripheral blocks the ROM block controls the access types allowed. MMIU Internal Registers (0x0003_0000 to 0x0003_0FFF): The MMU is responsible for controlling the accesses to its own internal registers and only allows data reads and writes (no instruction fetches) from 10 supervisor data space. All other accesses results in the mmucpu berr signal being asserted in accordance with the CPU native bus protocol. CPU Subsystem Peripheral Registers (0x0003_1000 to 0x0003_FFFF): Each peripheral block controls the access types allowed. Each peripheral allows supervisor data accesses (both read and write) and some blocks (e.g. Timers and GPIO) also allow user data space accesses as outlined in the relevant chapters of this 15 specification. Neither supervisor nor user instruction fetch accesses are allowed to any block as it is not possible to execute code from peripheral registers. The bus protocol is described in section 11.4.3. Note that the address space from 0x0003_B000 to 0x0003_FFFF is reserved and any access to this region is treated as a unused address apace access and will result in a bus error. PCU Mapped Registers (0x0004_0000 to 0x0004_BFFF): All of the PEP blocks registers which are 20 accessed by the CPU via the PCU inherits the access permissions of the PCU. These access permissions are hard wired to allow supervisor data accesses only and the protocol used is the same as for the CPU peripherals. Unused address space (0x0004_C000 to Ox3FFFFFFF and 0x4028_0000 to OxFFFF_FFFF): All accesses to these unused portions of the address space results in the mmucpu_berr signal being asserted in 25 accordance with the CPU native bus protocol. These accesses do not propagate outside of the MMU i.e. no external access is initiated. 11.6.4 Reset exception vector and reference zero traps When a reset occurs the LEON processor starts executing code from address 0x0000_0000. A common software bug is zero-referencing or null pointer de-referencing (where the program attempts to 30 access the contents of address OxOOOO_0000). To assist software debug the MMU asserts a bus error every time the locations OxOOOO_0000 to OxOOOO OOF (i.e. the first 4 words of the reset trap) are accessed after the reset trap handler has legitimately been retrieved immediately after reset.
WO 2005/120835 PCT/AU2004/000706 416 11.6.5 MMU Configuration Registers The MMU configuration registers include the RDU configuration registers and two LEON registers. Note that all the MMU configuration registers may only be accessed when the CPU is running in supervisor mode. Table 19. MMU Configuration Registers offset from Register #bits Reset Description MMU Ibase 1 .--- , -V;, , 3 Ox00 Region0Bottom[21 17 Ox0_000 This register contains the physical :5 0 address that marks the bottom of region 0 0x04 Region0Top[21:5] 17 Ox1_FFF This register contains the physical F address that marks the top of region 0. Region 0 covers the entire address space after reset whereas all other regions are zero-sized initially. Ox08 Region 1 Bottom[21 17 0x1_FFF This register contains the physical :5] F address that marks the bottom of region 1 Ox0C Region1Top[21:5] 17 OxO_000 This register contains the physical 0 address that marks the top of region 1 OxI 0 Region2Bottom[21 17 0x1_FFF This register contains the physical :5] F address that marks the bottom of region 2 0x14 Region2Top[21:5] 17 x0_000 This register contains the physical 0 address that marks the top of region 2 Ox1 8 Region3Bottom[21 17 Ox1_FFF This register contains the physical :5] F address that marks the bottom of region 3 OxI C Region3Top[21:5]. 17 0x0_000 This register contains the physical 0 address that marks the top of region 3 0x20 Region4Bottom[21 17 0x1_FFF This register contains the physical :5] F address that marks the bottom of region 4 0x24 Region4Top[21:5] 17 x0_000 This register contains the physical 0 address that marks the top of region 4 0x28 Region5Bottom[21 17 OxI _FFF This register contains the physical :5] F address that marks the bottom of region 5 x2C Region5Top[21:5] 17 x0_000 This register contains the physical 0 address that marks the top of region 5 0x30 Region6Bottom[21 17 0x1_FFF This register contains the physical :5] F address that marks the bottom of region 6 0x34 Region6Top[21:5] 17 x0_000 This register contains the physical 0 address that marks the top of region 6 0x38 Region7Bottom[21 17 OxI_FFF This register contains the physical :5] F address that marks the bottom of region 7 WO 2005/120835 PCT/AU2004/000706 417 0x3C Region7Top[21:5] 17 0x0_000 This register contains the physical 0 address that marks the top of region 7 0x40 RegionOControl 6 0x07 Control register for region 0 Ox44 Region1Control 6 0x07 Control register for region 1 Ox48 Region2Control 6 0x07 Control register for region 2 Ox4C Region3Control 6 0x07 Control register for region 3 0x50 Region4Control 6 0x07 Control register for region 4 0x54 Region5Control 6 0x07 Control register for region 5 Ox58 Region6Control 6 0x07 Control register for region 6 Ox5C Region7Control 6 0x07 Control register for region 7 0x60 RegionLock 8 Ox00 Writing a 1 to a bit in the RegionLock register locks the value of the corresponding RegionTop, RegionBottom and RegionControl registers. The lock can only be cleared by a reset and any attempt to write to a locked register will result in a bus error. Ox64 BusTimeout 8 OxFF This register should be set to the number of pc/k cycles to wait after an access has started before aborting the access with a bus error. Writing 0 to this register disables the bus timeout feature. Ox68 ExceptionSource 6 Ox00 This register identifies the source of the last exception. See Section 11.6.5.3 for details. Ox6C DebugSelect[8:2] 7 0x00 Contains address of the register selected for debug observation. It is expected that a number of pseudo registers will be made available for debug observation and these will be outlined during the implementation phase. Ox80 to 0x108 RDU Registers See Table 31 for details. 0x140 LEON 32 Ox1271 The LEON configuration register is used Configuration 8F00 by software to determine the Register configuration of this LEON implementation. See section 11.5.1.1 for details. This register is ReadOnly. Ox1 44 LEON Cache 32 Ox0000_ The LEON Cache Control Register is Control Register 0000 used to control the operation of the caches. See section 11.7.1.1 for details. 11.6.5.1 RegionTop and RegionBottom registers The 20 Mbit of embedded DRAM on SoPEC is arranged as 81920 words of 256 bits each. All region boundaries need to align with a 256-bit word. Thus only 17 bits are required for the RegionNTop and RegionNBottom registers. Note that the bottom 5 bits of the RegionNTop and RegionNBottom registers cannot 5 be written to and read as'0' i.e. the RegionNTop and RegionNBottom registers represent 256-bit word aligned DRAM addresses WO 2005/120835 PCT/AU2004/000706 418 Both the RegionNTop and RegionNBottom registers are inclusive i.e. the addresses in the registers are included in the region. Thus the size-of a region is (RegionNTop - RegionNBottom) +1 DRAM words. If DRAM regions overlap (there is no reason for this to be the case but there is nothing to prohibit it either) then only accesses allowed by all overlapping regions are permitted. That is if a DRAM address appears in 5 both Region1 and Region3 (for example) the cpu_acode of an access is checked against the access permissions of both regions. If both regions permit the access then it proceeds but if either or both regions do not permit the access then it is not be allowed. The MMU does not support negatively sized regions i.e. the value of the RegionNTop register should always be greater than or equal to the value of the RegionNBottom register. If RegionNTop is lower in the address 10 map than RegionNBottom then the region is considered to be zero-sized and is ignored. When both the RegionNTop and RegionNBottom registers for a region contain the same value the region is then simply one 256-bit word in length and this corresponds to the smallest possible active region. 11. 6.5.2 Region Control registers Each memory region has a control register associated with it. The RegionNControl register is used to set the 15 access conditions for the memory region bounded by the RegionNTop and RegionNBottom registers. Table 20 describes the function of each bit field in the RegionNControl registers. All bits in a RegionNControl register are both readable and writable by design. However, like all registers in the MMU, the RegionNControl registers can only be accessed by code running in supervisor mode. Table 20. Region Control Register 4 Fleid Namne bit(s) Decription SupervisorAccess 2:0 Denotes the type of access allowed when the CPU is running in Supervisor mode. For each access type a 1 indicates the access is permitted and a 0 indicates the access is not permitted. bitO - Data read access permission bit1 - Data write access permission bit2 - Instruction fetch access permission UserAccess 5:3 Denotes the type of access allowed when the CPU is running in User mode. For each access type a 1 indicates the access is permitted and a 0 indicates the access is not permitted. bit3 - Data read access permission bit4 - Data write access permission bit5 - Instruction fetch access permission 11.6.5.3 ExceptionSource Register 20 The SPARC V8 architecture allows for a number of types of memory access error to be trapped. However on the LEON processor only datastoreerror and data_access_exception trap types result from an external (to LEON) bus error. According to the SPARC architecture manual the processor automatically moves to the next register window (i.e. it decrements the current window pointer) and copies the program counters (PC and nPC) to two local registers in the new window. The supervisor bit in the PSR is also set and the PSR can be WO 2005/120835 PCT/AU2004/000706 419 saved to another local register by the trap handler (this does not happen automatically in hardware). The ExceptionSource register aids the trap handler by identifying the source of an exception. Each bit in the ExceptionSource register is set when the relevant trap condition and should be cleared by the trap handler by writing a 'I' to that bit position. Table 21. ExceptionSource Register Field Name bits) Description DramAccessExcptn 0 The permissions of an access did not match those of the DRAM region it was attempting to access. This bit will also be set if an attempt is made to access an undefined DRAM region (i.e. a location that is not within the bounds of any RegionTop/RegionBottom pair) PeriAccessExcptn 1 An access violation occurred when accessing a CPU subsystem block. This occurs when the access permissions disagree with those set by the block. UnusedAreaExcptn 2 An attempt was made to access an unused part of the memory map LockedWriteExcptn 3 An attempt was made to write to a regions registers (RegionTop/Bottom/Control) after they had been locked. Note that because the MMU (which is a CPU subsystem block) terminates a write to a locked register with a bus error it will also cause the PeriAccessExcptn bit to be set. ResetHandlerExcptn 4 An attempt was made to access a ROM location between Ox0000_0000 and 0x0000_000F after the reset handler was executed. The most likely cause of such an access is the use of an uninitialised pointer or structure. Note that due to the pipelined nature of the processor any attempt to execute code in user mode from locations 0x4, Ox8 or 0xC will result in the PeriAccessExcptn bit also being set. This is because the processor will request the contents of location Ox1 0 (and above) before the trap handler is invoked and as the ROM does not permit user mode access it will respond with a bus error which causes PeriAccessExcptn to be set in addition to ResetHandlerExcptn TimeoutExcptn 5 A bus timeout condition occurred. 5 11.6.6 MMU Sub-block partition As can be seen from Figure 21 and Figure 22 the MMU consists of three principal sub-blocks. For clarity the connections between these sub-blocks and other SoPEC blocks and between each of the sub-blocks are shown in two separate diagrams. 11.6.6.1 LEON AHB Bridge 10 The LEON AHB bridge consists of an AHB bridge to DIU and an AHB to CPU subsystem bus bridge. The AHB bridge converts between the AHB and the DIU and CPU subsystem bus protocols but the address decoding and enabling of an access happens elsewhere in the MMU. The AHB bridge is always a slave on the AHB. Note that the AMBA signals from the LEON core are contained within the ahbso and ahbsi records.
WO 2005/120835 PCT/AU2004/000706 420 The LEON records are described in more detail in section 11.7. Glue logic may be required to assist with enabling memory accesses, endianness coherency, interrupts and other miscellaneous signalling. Table 22. LEON AHB bridge I/Os DecIton Global SoPEC signals prst1n 1 In Global reset. Synchronous to pc/k, active low. Pck 1 In Global clock LEON core to LEON AHB signals (ahbsi and ahbso records) ahbsi.haddr[31:0] 32 In AHB address bus ahbsi.hwdata[31:0] 32 In AHB write data bus ahbso.hrdata[31:0] 32 Out AHB read data bus ahbsi.hsel 1 In AHB slave select signal ahbsi.hwrite 1 In AHB write signal: 1 - Write access 0 - Read access ahbsi.htrans 2 In Indicates the type of the current transfer: 00 - IDLE 01 - BUSY 10- NONSEQ 11-SEQ ahbsi.hsize 3 In Indicates the size of the current transfer: 000 - Byte transfer 001 - Halfword transfer 010 - Word transfer 011 - 64-bit transfer (unsupported?) 1 xx - Unsupported larger wordsizes ahbsi.hburst 3 In Indicates if the current transfer forms part of a burst and the type of burst: 000 - SINGLE 001 - INCR 010- WRAP4 011 - INCR4 100 - WRAP8 101 - INCR8 110 - WRAP16 111 - INCR16 ahbsi.hprot 4 In Protection control signals pertaining to the current access: hprot[0] - Opcode(0) / Data(1) access hprot[1] - User(0) / Supervisor access hprot[2] - Non-bufferable(0) / Bufferable(1) access (unsupported) hprot[3] - Non-cacheable(0) / Cacheable access ahbsi.hmaster 4 in Indicates the identity of the current bus master. This will always be the LEON core. ahbsi.hmastlock 1 In Indicates that the current master is performing a locked sequence of transfers. ahbso.hready 1 Out Active high ready signal indicating the access has completed WO 2005/120835 PCT/AU2004/000706 421 ahbso.hresp 2 Out Indicates the status of the transfer: 00 - OKAY 01 - ERROR 10 - RETRY 11 -SPLIT ahbso.hsplit[15:0] 16 Out This 16-bit split bus is used by a slave to indicate to the arbiter which bus masters should be allowed attempt a split transaction. This feature will be unsupported on the AHB bridge Toplevel/ Common LEON AHB bridge signals cpu-dataout[31:0] 32 Out Data out bus to both DRAM and peripheral devices. cpu_rwn 1 Out Read/NotWrite signal. 1 = Current access is a read access, 0 = Current access is a write access icucpu-ilevel[3:0] 4 In An interrupt is asserted by driving the appropriate priority level on icu.cpu_ieve. These signals must remain asserted until the CPU executes an interrupt acknowledge cycle. cpu-icu-ilevel[3:0] 4 In Indicates the level of the interrupt the CPU is acknowledging when cpujack is high cpu-iack 1 Out Interrupt acknowledge signal. The exact timing depends on the CPU core implementation cpu-startaccess 1 Out Start Access signal indicating the start of a data transfer and that the cpu.adr, cpu.dataout, cpu_rwn and cpu.acode signals are all valid. This signal is only asserted during the first cycle of an access. cpu-ben[1:0] 2 Out Byte enable signals. Dram cpu-data[255:0] 256 In Read data from the DRAM. diucpurreq 1 Out Read request to the DIU. diu_cpu_rack 1 In Acknowledge from DIU that read request has been accepted. diu_cpurvalid 1 In Signal from DIU indicating that valid read data is on the dram cpu data bus cpu-diuwdatavalid 1 Out Signal from the CPU to the DIU indicating that the data currently on the cpLLdiuwdata bus is valid and should be committed to the DIU posted write buffer diu_cpu_write_rdy 1 In Signal from the DIU indicating that the posted write buffer is empty cpudiuwdadr[21:4] 18 Out Write address bus to the DIU cpu._diu-wdata[127:0] 128 Out Write data bus to the DIU cpu-diu wmask[1 5:0] 16 Out Write mask for the cpudiuLwdata bus. Each bit corresponds to a byte of the 128-bit cpudiu_ wdata bus. LEON AHB bridge to MMU Control Block signals cpu-mmuadr 32 Out CPU Address Bus. Mmucpudata 32 In Data bus from the MMU Mmu-cpu-rdy 1 In Ready signal from the MMU cpu-mmu-acode 2 Out Access code signals to the MMU WO 2005/120835 PCT/AU2004/000706 422 Mmu_cpuberr 1 In Bus error signal from the MMU Dram_access_en 1 In DRAM access enable signal. A DRAM access cannot be initiated unless it has been enabled by the MMU control unit. Description: The LEON AHB bridge ensures that all CPU bus transactions are functionally correct and that the timing requirements are met. The AHB bridge also implements a 128-bit DRAM write buffer to improve the efficiency of DRAM writes, particularly for multiple successive writes to DRAM. The AHB bridge is also 5 responsible for ensuring endianness coherency i.e. guaranteeing that the correct data appears in the correct position on the data buses (hrdata, cpudataout and cpummu wdata) for every type of access. This is a requirement because the LEON uses big-endian addressing while the rest of SoPEC is little-endian. The LEON AHB bridge asserts request signals to the DIU if the MMU control block deems the access to be a legal access. The validity (i.e. is the CPU running in the correct mode for the address space being accessed) of 10 an access is determined by the contents of the relevant RegionNControl register. As the SPARC standard requires that all accesses are aligned to their word size (i.e. byte, half-word, word or double-word) and so it is not possible for an access to traverse a 256-bit boundary (thus also matching the DIU behaviour). Invalid DRAM accesses are not propagated to the DIU and will result in an error response (ahbso.hresp = '01') on the AHB. The DIU bus protocol is described in more detail in section 22.9. The DIU returns a 256-bit dataword 15 on dramcpudata[255:01 for every read access. The CPU subsystem bus protocol is described in section 11.4.3. While the LEON AHB bridge performs the protocol translation between AHB and the CPU subsystem bus the select signals for each block are generated by address decoding in the CPU subsystem bus interface. The CPU subsystem bus interface also selects the correct read data bus, ready and error signals for the block being addressed and passes these to the LEON 20 AHB bridge which puts them on the AHB bus. It is expected that some signals (especially those external to the CPU block) will need to be registered here to meet the timing requirements. Careful thought will be required to ensure that overall CPU access times are not excessively degraded by the use of too many register stages. 11.6.6.1.1 DRAM write buffer 25 The DRAM write buffer improves the efficiency of DRAM writes by aggregating a number of CPU write accesses into a single DIU write access. This is achieved by checking to see if a CPU write is to an address already in the write buffer. If it is the write is immediately acknowledged (i.e. the ahbsi.hready signal is asserted without any wait states) and the DRAM write buffer is updated accordingly. When the CPU write is to a DRAM address other than that in the write buffer then the current contents of the write buffer are sent to 30 the DIU (where they are placed in the posted write buffer) and the DRAM write buffer is updated with the address and data of the CPU write. The DRAM write buffer consists of a 128-bit data buffer, an 18-bit write address tag and a 16-bit write mask. Each bit of the write mask indicates the validity of the corresponding byte of the write buffer as shown in Figure 23 below.
WO 2005/120835 PCT/AU2004/000706 423 The operation of the DRAM write buffer is summarised by the following set of rules: 1) The DRAM write buffer only contains DRAM write data i.e. peripheral writes go directly to the addressed peripheral. 2) CPU writes to locations within the DRAM write buffer or to an empty write buffer (i.e. the write 5 mask bits are all 0) complete with zero wait states regardless of the size of the write (byte/half word/word/double-word). 3) The contents of the DRAM write buffer are flushed to DRAM whenever a CPU write to a location outside the write buffer occurs, whenever a CPU read from a location within the write buffer occurs or whenever a write to a peripheral register occurs. 10 4) A flush resulting from a peripheral write does not cause any extra wait states to be inserted in the peripheral write access. 5) Flushes resulting from a DRAM access causes wait states to be inserted until the DIU posted write buffer is empty. If the DIU posted write buffer is empty at the time the flush is required then no wait states are inserted for a flush resulting from a CPU write or one wait state will be inserted for a 15 flush resulting from a CPU read (this is to ensure that the DIU sees the write request ahead of the read request). Note that in this case further wait states are additionally inserted as a result of the delay in servicing the read request by the DIU. 11.6.6.1.2 DIU interface waveforms Figure 24 below depicts the operation of the AHB bridge over a sample sequence of DRAM transactions 20 consisting of a read into the DCache, a double-word store to an address other than that currently in the DRAM write buffer followed by an ICache line refill. To avoid clutter a number of AHB control signals that are inputs to the MMU have been grouped together as ahbsi.CONTROL and only the ahbso.HREADY is shown of the output AHB control signals. The first transaction is a single word load ('LD'). The MMU (specifically the MMU control block) uses the 25 first cycle of every access (i.e. the address phase of an AHB transaction) to determine whether or not the access is a legal access. The read request to the DIU is then asserted in the following cycle (assuming the access is a valid one) and is acknowledged by the DIU a cycle later. Note that the time from cpudiurreq being asserted and diucpurack being asserted is variable as it depends on the DIU configuration and access patterns of DIU requestors. The AHB bridge inserts wait states until it sees the diucpurvalid signal is high, 30 indicating the data ('LD1') on the dram_cpu data bus is valid. The AHB bridge terminates the read access in the same cycle by asserting the ahbso.HREADY signal (together with an 'OKAY' HRESP code). The AHB bridge also selects the appropriate 32 bits ('RD1') from the 256-bit DRAM line data ('LD1') returned by the DIU corresponding to the word address given by Al. The second transaction is an AHB two-beat incrementing burst issued by the LEON acache block in response 35 to the execution of a double-word store instruction. As LEON is a big endian processor the address issued ('A2') during the address phase of the first beat of this transaction is the address of the most significant word of the double-word while the address for the second beat ('A3') is that of the least significant word i.e. A3 = WO 2005/120835 PCT/AU2004/000706 424 A2 +4. The presence of the DRAM write buffer allows these writes to complete without the insertion of any wait states. This is true even when, as shown here, the DRAM write buffer needs to be flushed into the DIU posted write buffer, provided the DIU posted write buffer is empty. If the DIU posted write buffer is not empty (as would be signified by diu cpu write rdy being low) then wait states would be inserted until it 5 became empty. The cpudiuwdata buffer builds up the data to be written to the DIU over a number of transactions ('BDI' and 'BD2' here) while the cpudiu_wmask records every byte that has been written to since the last flush - in this case the lowest word and then the second lowest word are written to as a result of the double-word store operation. The final transaction shown here is a DRAM read caused by an ICache miss. Note that the pipelined nature of 10 the AHB bus allows the address phase of this transaction to overlap with the final data phase of the previous transaction. All ICache misses appear as single word loads ('LD') on the AHB bus. In this case, the DIU is slower to respond to this read request than to the first read request because it is processing the write access caused by the DRAM write buffer flush. The ICache refill will complete just after the window shown in Figure 24. 15 11.6.6.2 CPU Subsystem Bus Interface The CPU Subsystem Interface block handles all valid accesses to the peripheral blocks that comprise the CPU Subsystem. Table 23. CPU Subsystem Bus Interface 1/Os Global SoPEC signals prstn 1 In Global reset. Synchronous to pclk, active low. Pclk 1 In Global clock Toplevel/Common CPU Subsystem Bus Interface signals cpu-cpr..sel 1 Out CPR block select. cpugpio-sel 1 Out GPIO block select. cpu-icu-sel 1 Out ICU block select. cpu-lss-sel 1 Out LSS block select. cpujpcu-sel 1 Out PCU block select. cpu-mmi-sel 1 Out MMI block select. cpu_tim.sel 1 Out Timers block select. cpu-romsel 1 Out ROM block select. cpu-pss.sel 1 Out PSS block select. cpudiusel 1 Out DIU block select. cpu-uhu-sel 1 Out UHU block select. cpuudusel 1 Out UDU block select.
WO 2005/120835 PCT/AU2004/000706 425 cpr-cpu-data[31:0] 32 In Read data bus from the CPR block gpiocpu.data[31:0] 32 In Read data bus from the GPIO block icu cpu data[31:0] 32 In Read data bus from the ICU block Iss-cpu-data[31:0] 32 In Read data bus from the LSS block pcu-cpu-data[31:0] 32 In Read data bus from the PCU block mmi-cpu-data[31:0] 32 In Read data bus from the MMI block tim-cpu-data[31:0] 32 In Read data bus from the Timers block romscpu-data[31:0] 32 In Read data bus from the ROM block pss.cpu-data[31:01 32 In Read data bus from the PSS block diu-cpu.data[31:0] 32 In Read data bus from the DIU block udu.cpu-data[31:0] 32 In Read data bus from the UDU block uhu-cpu-data[31:0] 32 In Read data bus from the UHU block cprscpu-rdy 1 In Ready signal to the CPU. When cprzcpu.rdy is high it indicates the last cycle of the access. For a write cycle this means cpudataout has been registered by the CPR block and for a read cycle this means the data on cprzcpucdata is valid. gpio-cpu-rdy 1 In GPIO ready signal to the CPU. icu-cpu-rdy 1 In ICU ready signal to the CPU. Iss-cpu-rdy 1 In LSS ready signal to the CPU. pcuscpu-rdy 1 In PCU ready signal to the CPU. mmi-cpu-rdy 1 In MMI ready signal to the CPU. tim-cpu-rdy 1 In Timers block ready signal to the CPU. rom-cpu-rdy 1 In ROM block ready signal to the CPU. pss-cpu-rdy 1 In PSS block ready signal to the CPU. diu-cpu-rdy 1 In DIU register block ready signal to the CPU. uhu-cpu-rdy 1 In UHU register block ready signal to the CPU. uducpu-rdy 1 In UDU register block ready signal to the CPU. cpr-cpu-berr 1 In Bus Error signal from the CPR block gpio-cpu-berr 1 In Bus Error signal from the GPIO block icucpu-berr 1 In Bus Error signal from the ICU block iss_cpuberr 1 In Bus Error signal from the LSS block pcu-cpu-berr 1 In Bus Error signal from the PCU block mmi-cpu-berr 1 In Bus Error signal from the MMI block tim-cpu-berr 1 In Bus Error signal from the Timers block rom_cpuberr 1 In Bus Error signal from the ROM block pss-cpu-berr 1 In Bus Error signal from the PSS block WO 2005/120835 PCT/AU2004/000706 426 diu-cpuberr 1 In Bus Error signal from the DIU block uhu_cpuberr 1 In Bus Error signal from the UHU block udu_cpuberr 1 In Bus Error signal from the UDU block CPU Subsystem Bus Interface to MMU Control Block signals cpu-adr[19:12] 8 In Toplevel CPU Address bus. Only bits 19-12 are required to decode the peripherals address space peri_accessen 1 In Enable Access signal. A peripheral access cannot be initiated unless it has been enabled by the MMU Control Unit peri-mmu-data[31:0] 32 Out Data bus from the selected peripheral peri-mmu-rdy 1 Out Data Ready signal. Indicates the data on the perimmudata bus is valid for a read cycle or that the data was successfully written to the peripheral for a write cycle. perimmuberr 1 Out Bus Error signal. Indicates a bus error has occurred in accessing the selected peripheral CPU Subsystem Bus Interface to LEON AHB bridge signals cpustartaccess 1 In Start Access signal from the LEON AHB bridge indicating the start of a data transfer and that the cpu.adr, cpu.dataout, cpujrwn and cpuacode signals are all valid. This signal is only asserted during the first cycle of an access. Description: The CPU Subsystem Bus Interface block performs simple address decoding to select a peripheral and multiplexing of the returned signals from the various peripheral blocks. The base addresses used for the decode operation are defined in Table 17. Note that access to the MMU configuration registers are handled by 5 the MMU Control Block rather than the CPU Subsystem Bus Interface block. The CPU Subsystem Bus Interface block operation is described by the following pseudocode: maskedcpu-adr = cpu-adr[18:12] case (maskedcpuadr) 10 when TIMLbase[18:12] cpu_timsel = periaccessen // The peri_accessen signal will have the peri-mmu-data = tim-cpu-data // timing required for block selects perimmu-rdy = timcpurdy 15 peri_mmu_berr = tiM_cpu_berr allotherselects = 0 // Shorthand to ensure other cpu-blocksel signals // remain deasserted when LSS-base(18:12] 20 cpu-iss-sel = periaccess-en peri-mmudata = lsscpudata perimmurdy = lsscpurdy perimmuberr = lss-cpuberr all-other-selects = 0 25 when GPIObase[18:12] cpu-gpio-sel = peri-accessen WO 2005/120835 PCT/AU2004/000706 427 peri-mmu-data = gpiocpudata perimmuurdy = gpio-cpu-rdy perinmmuberr = gpiocpuberr allotherselects = 0 5 when MMIVbase[18:12] cpu mmisel = peri_access_en peri-mundata = mmi_cpu-data perimmu_rdy = mmiicpu-rdy peri_mmu_berr = mmicpu-berr 10 allother-selects = 0 when ICU_base[18:12] cpu-icu-sel = periaccess_en perimmu_data = icu-cpu-data periimmurdy = icu-cpurdy 15 peri-mmuuberr = icu_cpu-berr allotherselects = 0 when CPRbase[18:12] cpu-cpr-sel = peritaccessen perimmudata = cprcpudata 20 peri-mmu-rdy = cpr-cpu-rdy peri_mmu_berr = cprcpuberr allotherselects = 0 when ROMbase[18:12] cpurom_sel = peri_access_en 25 peri-mmu-data = romicpu-data peri-mmu-rdy = rom_cpurdy perimmu_berr = romcpuberr all-other-selects = 0 when PSS_base[18:12] 30 cpu-pss-sel = peri-access_en peri-mmu-data = pss-cpu-data peri-mmu-rdy = pss-cpu-rdy peri-mmu-berr = psscpu_berr allotherselects = 0 35 when DIUbase[18:12] cpu-diu-sel = peri-access-en perimmudata = diu-cpu-data peri-mmu-rdy = diu-cpu-rdy peri_mmu_berr = diu-cpu_berr 40 allotherselects = 0 when UHUbase[18:12] cpu-uhu-sel = peri_access_en peri-mmudata = uhucpudata perimmuurdy = uhucpu-rdy 45 peri-mmu-berr = uhu_cpu_berr allotherselects = 0 when UDU-base[18:12] cpuudu_sel = peri_access_en perinmmu-data = uducpudata 50 peri_mmu_rdy = udu-cpu_rdy perimmu-berr = udu-cpu-berr allotherselects = 0 when PCU_base[18:12] cpu-pcu-sel = periaccess-en 55 peri_mmu_data = pcu_cpu_data peri_mmurdy = pcu-cpurdy peri-mmuuberr = pcu-cpuberr WO 2005/120835 PCT/AU2004/000706 428 allotherselects = 0 when others allblockselects = 0 perimmu data = 0x00000000 5 peri-mmu-rdy = o peri-mmu-berr = 1 end case 11.6.6.3 MMU Control Block The MMU Control Block determines whether every CPU access is a valid access. No more than one cycle is 10 consumed in determining the validity of an access and all accesses terminate with the assertion of either mmucpurdy or mmucpuberr. To safeguard against stalling the CPU a simple bus timeout mechanism is supported. Table 24. MMU Control Block /Os F~oba oP! Global SoPEC signals prstn 1 In Global reset. Synchronous to pck, active low. Pcik 1 In Global clock Toplevel/Common MMU Control Block signals cpu-adr[21:2] 22 Out Address bus for both DRAM and peripheral access. cpu-acode[1:0] 2 Out CPU access code signals (cpummu acode) retimed to meet the CPU Subsystem Bus timing requirements dram.accessen 1 Out DRAM Access Enable signal. Indicates that the current CPU access is a valid DRAM access. MMU Control Block to LEON AHB bridge signals cpu-mmu-adr[31:0] 32 In CPU core address bus. cpu-dataout[31:0] 32 In Toplevel CPU data bus mmu-cpu-data[31:0] 32 Out Data bus to the CPU core. Carries the data for all cpurwn 1 In Toplevel CPU Read/notWrite signal. cpu-mmuacode[1:0] 2 In CPU access code signals mmu-cpu-rdy 1 Out Ready signal to the CPU core. Indicates the completion of all valid CPU accesses. mmu.cpu3berr 1 Out Bus Error signal to the CPU core. This signal is asserted to terminate an invalid access. cpu.start2access 1 In Start Access signal from the LEON AHB bridge indicating the start of a data transfer and that the cpiadr, cpLdataout, cpUrwn and cpuacode signals are all valid. This signal is only asserted during the first cycle of an access. cpu-iack 1 In Interrupt Acknowledge signal from the CPU. This signal is only asserted during an interrupt acknowledge cycle.
WO 2005/120835 PCT/AU2004/000706 429 cpu-ben[1:0] 2 in Byte enable signals indicating which bytes of the 32 Ibit bus are being accessed. MMU Control Block to CPU Subsystem Bus Interface signals cpu-adr18:12] 8 Out Toplevel CPU Address bus. Only bits 18-12 are required to decode the peripherals address space periaccessen I Out Enable Access signal. A peripheral access cannot be initiated unless it has been enabled by the MMU Control Unit pen-mmu-data[31 :0] 32 In Data bus from the selected peripheral pen _mmu-rdy 1 In Data Ready signal. Indicates the data on the permmudata bus is valid for a read cycle or that the data was successfully written to the peripheral for _ _ _ a write cycle. perimmuberr 1 In Bus Error signal. Indicates a bus error has occurred in I_ accessing the selected peripheral Description: The MMU Control Block is responsible for the MMU's core functionality, namely determining whether or not an access to any part of the address map is valid. An access is considered valid if it is to a mapped area of the address space and if the CPU is running in the appropriate mode for that address space. Furthermore the 5 MMU control block correctly handles the special cases that are: an interrupt acknowledge cycle, a reset exception vector fetch, an access that crosses a 256-bit DRAM word boundary and a bus timeout condition. The following pseudocode shows the logic required to implement the MMU Control Block functionality. It does not deal with the timing relationships of the various signals - it is the designer's responsibility to ensure that these relationships are correct and comply with the different bus protocols. For simplicity the pseudocode 10 is split up into numbered sections so that the functionality may be seen more easily. It is important to note that the style used for the pseudocode will differ from the actual coding style used in the RTL implementation. The pseudocode is only intended to capture the required functionality, to clearly show the criteria that need to be tested rather than to describe how the implementation should be performed. In particular the different comparisons of the address used to determine which part of the memory map, which 15 DRAM region (if applicable) and the permission checking should all be performed in parallel (with results ORed together where appropriate) rather than sequentially as the pseudocode implies. PSO Description: This first segment of code defines a number of constants and variables that are used elsewhere in this description. Most signals have been defined in the 1/0 descriptions of the MMU sub-blocks that precede this section of the document. The postresetstate variable is used later (in section PS4) to 20 determine if a null pointer access should be trapped. PSO: const CPUBusTop = OxOO04BFFF const CPUBusGapTop = OxOO03FFFF 25 const CPUBusGapBottom = OxOO03BOOO const DRAMTop = 0x4027FFFF const DRAMBOttom = 0x40000000 const UserDataSpace = bOl WO 2005/120835 PCT/AU2004/000706 430 const UserProgramSpace = bOO const SupervisorDataSpace = bl const SupervisorProgramSpace = blO const ResetExceptionCycles = Ox4 5 cpu-adr-peri-masked[6:0] = cpummuuadr[18:12] cpu-adrdram-masked[16:0] = cpu_mmu_adr & 0xO03FFFEO if (prstn == 0) then // Initialise everything 10 cpuadr = cpumuadr[21:2] periaccess_en = 0 dramaccess-en = 0 mmucpu-data = perijmmu-data mmu_cpurdy = 0 15 mmu_cpu_berr = 0 postresetstate = TRUE access-initiated = FALSE cpuaccess_cnt = 0 20 // The following is used to determine if we are coming out of reset for the purposes of // detecting invalid accesses to the reset handler (e.g. null pointer accesses). There // may be a convenient signal in the CPU core that we could use instead of 25 this. if ((cpustartaccess == 1) AND (cpuaccesscnt <= ResetExceptionCycles) AND (clock-tick == TRUE)) then cpuaccesscnt = cpu-access-cnt +1 30 else post-reset-state = FALSE PS1 Description: This section is at the top of the hierarchy that determines the validity of an access. The address is tested to see which macro-region (i.e. Unused, CPU Subsystem or DRAM) it falls into or whether 35 the reset exception vector is being accessed. PS1: if (cpummuadr < OxOO000010) then // The reset exception is being accessed. See section PS2 40 elsif ((cpu_nmuadr >= OxOO000010) AND (cpunmmu-adr < CPUBusGapBottom)) then // We are in the CPU Subsystem address space. See section PS3 elsif ((cpu_mmuadr > CPUBusGapTop) AND (cpumuadr <= CPUBusTop)) then // We are in the PEP Subsystem address space. See section PS3 45 elsif ( ((cpummuadr >= CPUBusGapBottom) AND (cpu-mmu-adr <= CPUBusGapTop)) OR ((cpummu_adr > CPUBusTop) AND (cpummu_adr < DRAMBottom)) OR ((cpu_mmuadr > DRAMTop) AND (cpummuadr <= OxFFFFFFFF)) )then // The access is to an invalid area of the address space. See section 50 PS4 // Only remaining possibility is an access to DRAM address space 55 elsif ((cpu-adrdrammasked >= RegionOBottom) AND (cpuadrdrammasked <= WO 2005/120835 PCT/AU2004/000706 431 RegionOTop) ) then // We are in RegionO. See section PS5 elsif ((cpuadr-dram-masked >= RegionNBottom) AND (cpu-adrdrammasked <= 5 RegionNTop) ) then // we are in RegionN // Repeat the RegionO (i.e. section PS5) logic for each of Region to Region7 else // We could end up here if there were gaps in the DRAM regions 10 periaccess-en = 0 dram_accessen = 0 mmu_cpuberr = 1 // we have an unknown access error, most likely due to hitting mmu-cpu-rdy = 0 // a gap in the DRAM regions 15 // Only thing remaining is to implement a bus timeout function. This is done in PS6 end 20 PS2 Description: The only correct accesses to the locations beneath OxOOOOOO10 are fetches of the reset trap handling routine and these should be the first accesses after reset. Here all other accesses to these locations are trapped, regardless of the CPU mode. The most likely cause of such an access is the use of a null pointer in the program executing on the CPU. 25 PS2: elsif (cpummuadr < x00000010) then if (post_reset_state == TRUE)) then cpuadr = cpummuadr[21:2] 30 periaccess_en = 1 dram_access_en = 0 mmu_cpudata = perimmudata mmu-cpurdy = perimmurdy mmucpu-berr = peri-mmuberr 35 else // we have a problem (almost certainly a null pointer) periaccessen = 0 dramaccessen = 0 mmu-cpu_berr = 1 mmu_cpurdy = 0 40 PS3 Description: This section deals with accesses to CPU and PEP subsystem peripherals, including the MMU itself. If the MMU registers are being accessed then no external bus transactions are required. Access to the MMU registers is only permitted if the CPU is making a data access from supervisor mode, otherwise a bus error is asserted and the access terminated. For non-MMU accesses then transactions occur over the CPU 45 Subsystem Bus and each peripheral is responsible for determining whether or not the CPU is in the correct mode (based on the cpu acode signals) to be permitted access to its registers. Note that all of the PEP registers are accessed via the PCU which is on the CPU Subsystem Bus. PS3: WO 2005/120835 PCT/AU2004/000706 432 elsif ((cpu_mmuadr >= Ox00000010) AND (cpu-jnmuadr < CPUBusGapBottom)) then I/ We are in the CPU Subsystem/PEP Subsystem address space 5 cpu..adr = cpu~jmuadr[21:2] if (cpu5adrperi masked == MIt-base) then // access is to local registers pen -access-en = 0 dramr_access-en = 0 10 if (cpulacode == SupervisorDatagpace) then for (i=0; i<8l; i++) { if ((i == cpmmuadr[8:2]) them selects the addressed register if (cpu-rwn == 1) then 15 mmucpudata[31:0] = lhUReg~i] / MtReg[i] is one of the mucpu-rdy = 1 IIregisters in Table 19 mucpu-err = 0 20 else // write cycle cmmUReg(i] = cpudataout[31: mucpurdy = 1 inucpuberr 0 else // there is no register mapped to this address 25 mmucpuberr i1 f cdo we really want a buserror here as registers ucpurdy 0 are just mirrored in other blocks else ( = we have an access violation 30 muccpubberr 1 m cupcpurrdy =0 else // access is to something else on the CPU Subsystem Bus pen _access_en = 1 35 dram access-en = 0 mu-cpudata = perijnnmu_data mucpurdy = peri-mmurdy mmucpumberr = perimuberr 40 PS4 Description: Accesses to the large unused areas of the address space are trapped by this section. No bus transactions are initiated and the mmw cprlberr signal is asserted. PS4: elsif ( ((cpummuadr = 0PUBusGapottom) AND (cpummmuiadr b CPUBusGapTop)) OR 45 ((cpujmu-adr > CPUBusTop) AND (cpuMmuadr < DRAMBottom)) OR ((cpujnnuadr > DRAMTop) AND (cpumnuadr <= OxFFFFFFFF)) ) then perlaccessen = 0 // The access is to an invalid area of the address space dramrLaccess-en = 0 50 mmucpu_berr = 1 mmumcpucrdy = 0 PS5 Description: This large section Of pseudocode simply checks whether the access is within the bounds of DRAM RegionO and if so whether or not the access is of a type permitted by the RegionOControl register. If WO 2005/120835 PCT/AU2004/000706 433 the access is permitted then a DRAM access is initiated. If the access is not of a type permitted by the RegionOControl register then the access is terminated with a bus error. PS5: 5 elsif ((cpu_adrdrammasked >= RegionOBottom) AND (cpu-adrdrammasked <= RegionOTop) ) then // we are in RegionO cpuadr = cpummuadr[21:2} if (cpurwn == 1) then 10 if ((cpu_acode == SupervisorProgramSpace AND RegionOControl[2} == 1)) OR (cpu-acode == UserProgramSpace AND RegionOControl[5] == 1)) then // this is a valid instruction fetch from 15 RegionO // The dramcpudata bus goes directly to the LEON // AHB bridge which also handles the hready generation 20 peri-access_en = 0 dramaccess_en = 1 mmucpu-berr = 0 elsif ((cpu-acode == SupervisorDataSpace AND RegionOControl[0] == 1) 25 OR (cpu-acode == UserDataSpace AND RegionOControl[3] == 1)) then // this is a valid read access from RegionO periaccessen = 0 dram-accessen = 1 30 mmu_cpuberr = 0 else // we have an access violation peri-access_en = 0 dram access-en = 0 35 mmu-cpu_berr = 1 mmu_cpurdy = 0 else // it is a write access if ((cpuacode == SupervisorDataSpace AND RegionOControl[l] == 1) 40 OR (cpuacode == UserDataSpace AND RegionOControl[4] == 1)) then // this is a valid write access to RegionO periaccessen = 0 dramaccessen = 1 45 mmu_cpu-berr = 0 else // we have an access violation peri_access-en = 0 dram access-en = 0 mmucpuberr = 1 50 mmu-cpu-rdy = 0 PS6 Description: This final section of pseudocode deals with the special case of a bus timeout. This occurs when an access has been initiated but has not completed before the BusTimeout number of pclk cycles. While access to both DRAM and CPU/PEP Subsystem registers will take a variable number of cycles (due to WO 2005/120835 PCT/AU2004/000706 434 DRAM traffic, PCU command execution or the different timing required to access registers in imported IP) each access should complete before a timeout occurs. Therefore it should not be possible to stall the CPU by locking either the CPU Subsystem or DIU buses. However given the fatal effect such a stall would have it is considered prudent to implement bus timeout detection. 5 PS6: // only thing remaining is to implement a bus timeout function. if ((cpustartaccess == 1) then 10 access-initiated = TRUE timeout-countdown = BusTimeout if ((mmu-cpu-rdy == 1 ) OR (mmu_cpuberr ==l )) then access-initiated = FALSE 15 periaccessen = 0 dramaccess-en = 0 if ((clocktick == TRUE) AND (access-initiated == TRUE) AND (BusTimeout 0)) 20 if (timeoutcountdown > 0) then timeout-countdownelse // timeout has occurred periaccess_en = 0 // abort the access dram-access-en = 0 25 mmucpuberr 1 mmu-cpu-rdy = 0 11.7 LEON CACHES The version of LEON implemented on SoPEC features 1 kB of ICache and 1 kB of DCache. Both caches are direct mapped and feature 8 word lines so their data RAMs are arranged as 32 x 256-bit and their tag RAMs 30 as 32 x 30-bit (itag) or 32 x 32-bit (dtag). Like most of the rest of the LEON code used on SoPEC the cache controllers are taken from the leon2-1.0.7 release. The LEON cache controllers and cache RAMs have been modified to ensure that an entire 256-bit line is refilled at a time to make maximum use of the memory bandwidth offered by the embedded DRAM organization (DRAM lines are also 256-bit). The data cache controller has also been modified to ensure that user mode code can only access Dcache contents that 35 represent valid user-mode regions of DRAM as specified by the MMU. A block diagram of the LEON CPU core as implemented on SoPEC is shown in Figure 25 below. In this diagram dotted lines are used to indicate hierarchy and red items represent signals or wrappers added as part of the SoPEC modifications. LEON makes heavy use of VHDL records and the records used in the CPU core are described in Table 25. Unless otherwise stated the records are defined in the iface.vhd file (part 40 of the LEON release) and this should be consulted for a complete breakdown of the record elements. Table 25. Relevant LEON records WO 2005/120835 PCT/AU2004/000706 435 rfi Register File Input record. Contains address, datain and control signals for the register file. rfo Register File Output record. Contains the data out of the dual read port register file. ici Instruction Cache In record. Contains program counters from different stages of the pipeline and various control signals ico Instruction Cache Out record. Contains the fetched instruction data and various control signals. This record is also sent to the DCache (i.e. icol) so that diagnostic accesses (e.g. Ida/sta) can be serviced. dci Data Cache In record. Contains address and data buses from different stages of the pipeline (execute & memory) and various control signals dco Data Cache Out record. Contains the data retrieved from either memory or the caches and various control signals. This record is also sent to the ICache (i.e. dcol) so that diagnostic accesses (e.g. Ida/sta) can be serviced. iui Integer Unit In record. This record contains the interrupt request level and a record for use with LEONs Debug Support Unit (DSU) iuo Integer Unit Out record. This record contains the acknowledged interrupt request level with control signals and a record for use with LEONs Debug Support Unit (DSU) mcii Memory to Cache Icache In record. Contains the address of an Icache miss and various control signals mcio Memory to Cache Icache Out record. Contains the returned data from memory and various control signals mcdi Memory to Cache Dcache In record. Contains the address and data of a Dcache miss or write and various control signals mcdo Memory to Cache Dcache Out record. Contains the returned data from memory and various control signals ahbi AHB In record. This is the input record for an AHB master and contains the data bus and AHB control signals. The destination for the signals in this record is the AHB controller. This record is defined in the amba.vhd file ahbo AHB Out record. This is the output record for an AHB master and contains the address and data buses and AHB control signals. The AHB controller drives the signals in this record. This record is defined in the amba.vhd file ahbsi AHB Slave In record. This is the input record for an AHB slave and contains the address and data buses and AHB control signals. It is used by the DCache to facilitate cache snooping (this feature is not enabled in SoPEC). This record is defined in the amba.vhd file crami Cache RAM In record. This record is composed of records of records which contain the address, data and tag entries with associated control signals for both the ICache RAM and DCache RAM cramo Cache RAM Out record. This record is composed of records of records which contain the data and tag entries with associated control signals for both the ICache RAM WO 2005/120835 PCT/AU2004/000706 436 and DCache RAM iline-rdy Control signal from the ICache controller to the instruction cache memory. This signal is active (high) when a full 256 bit line (on dramcpudata) is to be written to cache memory. dline-rdy Control signal from the DCache controller to the data cache memory. This signal is active (high) when a full 256 bit line (on dram-cpu-data) is to be written to cache memory. dram-cpu-data 256-bit data bus from the embedded DRAM 11.7.1 Cache controllers The LEON cache module consists of three components: the ICache controller (icache.vhd), the DCache controller (dcache.vhd) and the AHB bridge (acache.vhd) which translates all cache misses into memory requests on the AHB bus. 5 In order to enable full line refill operation a few changes had to be made to the cache controllers. The ICache controller was modified to ensure that whenever a location in the cache was updated (i.e. the cache was enabled and was being refilled from DRAM) all locations on that cache line had their valid bits set to reflect the fact that the full line was updated. The illne rdy signal is asserted by the ICache controller when this happens and this informs the cache wrappers to update all locations in the idata RAM for that line. 10 A similar change was made to the DCache controller except that the entire line was only updated following a read miss and that existing write through operation was preserved. The DCache controller uses the dline rdy signal to instruct the cache wrapper to update all locations in the ddata RAM for a line. An additional modification was also made to ensure that a double-word load instruction from a non-cached location would only result in one read access to the DIU i.e. the second read would be serviced by the data cache. Note that if 15 the DCache is turned off then a double-word load instruction will cause two DIU read accesses to occur even though they will both be to the same 256-bit DRAM line. The DCache controller was further modified to ensure that user mode code cannot access cached data to which it does not have permission (as determined by the relevant RegionNControl register settings at the time the cache line was loaded). This required an extra 2 bits of tag information to record the user read and write 20 permissions for each cache line. These user access permissions can be updated in the same manner as the other tag fields (i.e. address and valid bits) namely by line refill, STA instruction or cache flush. The user access permission bits are checked every time user code attempts to access the data cache and if the permissions of the access do not agree with the permissions returned from the tag RAM then a cache miss occurs. As the MMU evaluates the access permissions for every cache miss it will generate the appropriate 25 exception for the forced cache miss caused by the errant user code. In the case of a prohibited read access the trap will be immediate while a prohibited write access will result in a deferred trap. The deferred trap results from the fact that the prohibited write is committed to a write buffer in the DCache controller and program execution continues until the prohibited write is detected by the MMU which may be several cycles later. Because the errant write was treated as a write miss by the DCache controller (as it did not match the stored WO 2005/120835 PCT/AU2004/000706 437 user access permissions) the cache contents were not updated and so remain coherent with the DRAM contents (which do not get updated because the MMU intercepted the prohibited write). Supervisor mode code is not subject to such checks and so has free access to the contents of the data cache. In addition to AHB bridging, the ACache component also performs arbitration between ICache and DCache 5 misses when simultaneous misses occur (the DCache always wins) and implements the Cache Control Register (CCR). The leon2-1.0.7 release is inconsistent in how it handles cacheability: For instruction fetches the cacheability (i.e. is the access to an area of memory that is cacheable) is determined by the ICache controller while the ACache determines whether or not a data access is cacheable. To further complicate matters the DCache controller does determine if an access resulting from a cache snoop by another AHB 10 master is cacheable (Note that the SoPEC ASIC does not implement cache snooping as it has no need to do so). This inconsistency has been cleaned up in more recent LEON releases but is preserved here to minimise the number of changes to the LEON RTL. The cache controllers were modified to ensure that only DRAM accesses (as defined by the SoPEC memory map) are cached. The only functionality removed as a result of the modifications was support for burst fills of the ICache. 15 When enabled burst fills would refill an ICache line from the location where a miss occurred up to the end of the line. As the entire line is now refilled at once (when executing from DRAM) this functionality is no longer required. Furthermore, more substantial modifications to the ICache controller would be needed to preserve this function without adversely affecting full line refills. The CCR was therefore modified to ensure that the instruction burst fetch bit (bit16) was tied low and could not be written to. 20 11.7.1.1 LEON Cache Control Register The CCR controls the operation of both the I and D caches. Note that the bitfields used on the SoPEC implementation of this register are based on the LEON vl.0.7 implementation and some bits have their values tied off. See section 4 of the LEON manual for a description of the LEON cache controllers. Table 26. LEON Cache Control Register ICS 1:0 Instruction cache state: 00 - disabled 01 -frozen 10 - disabled 11 - enabled DCS 3:2 Data cache state: 00 - disabled 01 -frozen 10 - disabled 11 - enabled IF 4 lCache freeze on interrupt 0 - Do not freeze the ICache contents on taking an interrupt 1 - Freeze the lCache contents on taking an interrupt WO 2005/120835 PCT/AU2004/000706 438 DF 5 DCache freeze on interrupt 0 - Do not freeze the DCache contents on taking an interrupt 1 - Freeze the DCache contents on taking an interrupt Reserved 13:6 Reserved. Reads as 0. DP 14 Data cache flush pending. 0 - No DCache flush in progress 1 - DCache flush in progress This bit is ReadOnly. IP 15 Instruction cache flush pending. 0 - No ICache flush in progress 1 - ICache flush in progress This bit is ReadOnly. lB 16 Instruction burst fetch enable. This bit is tied low on SoPEC because it would interfere with the operation of the cache wrappers. Burst refill functionality is automatically provided in SoPEC by the cache wrappers. Reserved 20:17 Reserved. Reads as 0. Fl 21 Flush instruction cache. Writing a 1 this bit will flush the ICache. Reads as 0. FD 22 Flush data cache. Writing a 1 this bit will flush the DCache. Reads as 0. DS 23 Data cache snoop enable. This bit is tied low in SoPEC as there is no requirement to snoop the data cache. Reserved 31:24 Reserved. Reads as 0. 11.7.2 Cache wrappers The cache RAMs used in the leon2-1.0.7 release needed to be modified to support full line refills and the correct IBM macros also needed to be instantiated. Although they are described as RAMs throughout this document (for consistency), register arrays are actually used to implement the cache RAMs. This is because 5 IBM SRAMs were not available in suitable configurations (offered configurations were too big) to implement either the tag or data cache RAMs. Both instruction and data tag RAMs are implemented using dual port (1 Read & 1 Write) register arrays and the clocked write-through versions of the register arrays were used as they most closely approximate the single port SRAM LEON expects to see. 11.7.2.1 Cache Tag RAM wrappers 10 The itag and dtag RAMs differ only in their width - the itag is a 32x30 array while the dtag is a 32x32 array with the extra 2 bits being used to record the user access permissions for each line. When read using a LDA instruction both tags return 32-bit words. The tag fields are described in Table 27 and Table 28 below. Using the IBM naming conventions the register arrays used for the tag RAMs are called RA032X3OD2P2WlRlM3 for the itag and RA032X32D2P2WlRlM3 for the dtag. The ibm_syncram wrapper used for the tag RAMs is 15 a simple affair that just maps the wrapper ports on to the appropriate ports of the IBM register array and ensures the output data has the correct timing by registering it. The tag RAMs do not require any special modifications to handle full line refills. Because an entire line of cache is updated during every refill the 8 WO 2005/120835 PCT/AU2004/000706 439 valid bits in the tag RAMs are superfluous (i.e. all 8 bit will either be set or clear depending on whether the line is in cache or not despite this only requiring a single bit). Nonetheless they have been retained to minimise changes and to maintain simplistic compatibility with the LEON core. Table 27. LEON Instruction Cache Tag Valid 7:0 Each valid bit indicates whether or not the corresponding word of the cache line contains valid data Reserved 9:8 Reserved - these bits do not exist in the itag RAM. Reads as 0. Address 31:10 The tag address of the cache line Table 28. LEON Data Cache Tag Valid 7:0 Each valid bit indicates whether or not the corresponding word of the cache line contains valid data URP 8 User read permission. 0 - User mode reads will force a refill of this line 1 - User mode code can read from this cache line. UWP 9 User write permission. 0 - User mode writes will not be written to the cache 1 - User mode code can write to this cache line. Address 31:10 The tag address of the cache line 5 11.7.2.2 Cache Data RAM wrappers The cache data RAM contains the actual cached data and nothing else. Both the instruction and data cache data RAMs are implemented using 8 32x32-bit register arrays and some additional logic to support full line refills. Using the IBM naming conventions the register arrays used for the tag RAMs are called RA032X32D2P2WlRIM3. The ibmcdramwrap wrapper used for the tag RAMs is shown in Figure 26 10 below. To the cache controllers the cache data RAM wrapper looks like a 256x32 single port SRAM (which is what they expect to see) with an input to indicate when a full line refill is taking place (the linerdy signal). Internally the 8-bit address bus is split into a 5-bit lineaddress, which selects one of the 32 256-bit cache lines, and a 3-bit word address which selects one of the 8 32-bit words on the cache line. Thus each of the 8 32x32 15 register arrays contains one 32-bit word of each cache line. When a full line is being refilled (indicated by both the line rdy and write signals being high) every register array is written to with the appropriate 32 bits from the linedatain bus which contains the 256-bit line returned by the DIU after a cache miss. When just one word of the cache line is to be written (indicated by the write signal being high while the line rdy is low) then the word address is used to enable the write signal to the selected register array only - all other write enable WO 2005/120835 PCT/AU2004/000706 440 signals are kept low. The data cache controller handles byte and half-word write by means of a read-modify write operation so writes to the cache data RAM are always 32-bit. The word address is also used to select the correct 32-bit word from the cache line to return to the LEON integer unit. 5 11.8 REALTIME DEBUG UNIT (RDU) The RDU facilitates the observation of the contents of most of the CPU addressable registers in the SoPEC device in addition to some pseudo-registers in realtime. The contents of pseudo-registers, i.e. registers that are collections of otherwise unobservable signals and that do not affect the functionality of a circuit, are defined in each block as required. Many blocks do not have pseudo-registers and some blocks (e.g. ROM, PSS) do not 10 make debug information available to the RDU as it would be of little value in realtime debug. Each block that supports realtime debug observation features a DebugSelect register that controls a local mux to determine which register is output on the block's data bus (i.e. block cpudata). One small drawback with reusing the blocks data bus is that the debug data cannot be present on the same bus during a CPU read from the block. An accompanying active high blockcpudebugvalid signal is used to indicate when the data bus 15 contains valid debug data and when the bus is being used by the CPU. There is no arbitration for the bus as the CPU will always have access when required. A block diagram of the RDU is shown in Figure 27. Table 29. RDU I/Os diu-cpudata 32 In Read data bus from the DIU block cprscpu.data 32 In Read data bus from the CPR block gpio_cpudata 32 In Read data bus from the GPIO block icucpudata 32 In Read data bus from the ICU block Iss-cpulata 32 In Read data bus from the LSS block pcu.cpu-debug-dat 32 In Read data bus from the PCU block a mmicpu.data 32 In Read data bus from the MMI block timcpu-data 32 In Read data bus from the TIM block uhu_cpu.data 32 In Read data bus from the UHU block udu..cpu...data 32 In Read data bus from the UDU block diu-cpu.debugyali 1 In Signal indicating the data on the diutcpudata bus is valid d debug data. tim-cpudebug-vali 1 In Signal indicating the data on the timcpu._data bus is valid d debug data. mmi_cpudebugya 1 In Signal indicating the data on the mmi cputdata bus is valid lid debug data.
WO 2005/120835 PCT/AU2004/000706 441 pcu-cpu-debug-val 1 In Signal indicating the data on the pcu.cpudata bus is valid id debug data. Iss-cpu-debug-vali 1 In Signal indicating the data on the /ss cpudata bus is valid d debug data. icu cpu debug.vali 1 In Signal indicating the data on the icucpLdata bus is valid d debug data. gpio.cpu-debugva 1 In Signal indicating the data on the gpiqcpLLdata bus is valid lid debug data. cpr-cpu-debug-vali 1 In Signal indicating the data on the cprcpu.data bus is valid d debug data. uhu cpu-debugval 1 In Signal indicating the data on the uhu cpuQdata bus is valid id debug data. udu cpu-debug-val 1 In Signal indicating the data on the uducpudata bus is valid id debug data. debugdataout 32 Out Output debug data to be muxed on to the GPIO pins debug-data-valid 1 Out Debug valid signal indicating the validity of the data on debug data_out. This signal is used in all debug I__ Iconfigurations debugcntrI 33 Out Control signal for each debug data line indicating whether or not the debug data should be selected by the pin mux As there are no spare pins that can be used to output the debug data to an external capture device some of the existing I/Os have a debug multiplexer placed in front of them to allow them be used as debug pins. Furthermore not every pin that has a debug mux will always be available to carry the debug data as they may be engaged in their primary purpose e.g. as a GPIO pin. The RDU therefore outputs a debugcntrl signal with 5 each debug data bit to indicate whether the mux associated with each debug pin should select the debug data or the normal data for the pin. The DebugPinSell and DebugPinSel2 registers are used to determine which of the 33 potential debug pins are enabled for debug at any particular time. As it may not always be possible to output a full 32-bit debug word every cycle the RDU supports the outputting of an n-bit sub-word every cycle to the enabled debug pins. Each debug test would then need to be 10 re-run a number of times with a different portion of the debug word being output on the n-bit sub-word each time. The data from each run should then be correlated to create a full 32-bit (or whatever size is needed) debug word for every cycle. The debug_data_valid and pclk out signals accompanies every sub-word to allow the data to be sampled correctly. The pclk out signal is sourced close to its output pad rather than in the RDU to minimise the skew between the rising edge of the debug data signals (which should be registered 15 close to their output pads) and the rising edge ofpclk out. If multiple debug runs are be needed to obtain a complete set of debug data the n-bit sub-word will need to contain a different bit pattern for each run. For maximum flexibility each debug pin has an associated DebugDataSrc register that allows any of the 32 bits of the debug data word to be output on that particular debug data pin. The debug data pin must be enabled for debug operation by having its corresponding bit in the 20 DebugPinSel registers set for the selected debug data bit to appear on the pin. The size of the sub-word is determined by the number of enabled debug pins which is controlled by the DebugPinSel registers. Note that the debugdatavalid signal is always output. Furthermore debugcntrl[O] WO 2005/120835 PCT/AU2004/000706 442 (which is configured by DebugPinSell) controls the mux for both the debugdata_valid and pclk out signals as both of these must be enabled for any debug operation. The mapping of debugdataout[n] signals onto individual pins takes place outside the RDU. This mapping is described in Table 30 below. Table 30. DebugPinSel mapping bit # Pin DebugPinSell gpio[32]. The debug data -valid signal will appear on this pin when enabled. Enabling this pin also automatically enables the gpio[33] pin which will output the pc/k out signal DebugPinSel2(0-31) gpio[0...31] 5 Table 31. RDU Configuration Registers Address Offset n ffrnm Regisfer #hits nn Dencrinfirm Ox80 DebugSrc 4 0x00 Denotes which block is supplying the debug data. The encoding of this block is given below. 0 - MMU 1 -TIM 2 - LSS 3- GPIO 4 - MMI 5 - ICU 6 - CPR 7 - DIU 8 - UHU 9 - UDU 10 - PCU Ox84 DebugPinSell 1 Ox0 Determines whether the gpio[33:32] pins are used for debug output. 1 - Pin outputs debug data 0 - Normal pin function Ox88 DebugPinSel2 32 Ox000 Determines whether a gpio[31:0]pin is 0_000 used for debug data output. 0 1 - Pin outputs debug data 0 - Normal pin function Ox8C to 0x108 DebugDataSrc[31 32 x 5 Ox00 Selects which bit of the 32-bit debug data :0] word will be output on debug-dataout[N] 11.9 INTERRUPT OPERATION The interrupt controller unit (see chapter 16) generates an interrupt request by driving interrupt request lines with the appropriate interrupt level. LEON supports 15 levels of interrupt with level 15 as the highest level (the SPARC architecture manual states that level 15 is non-maskable, but it can be masked if desired). The 10 CPU will begin processing an interrupt exception when execution of the current instruction has completed and WO 2005/120835 PCT/AU2004/000706 443 it will only do so if the interrupt level is higher than the current processor priority. If a second interrupt request arrives with the same level as an executing interrupt service routine then the exception will not be processed until the executing routine has completed. When an interrupt trap occurs the LEON hardware will place the program counters (PC and nPC) into two 5 local registers. The interrupt handler routine is expected, as a minimum, to place the PSR register in another local register to ensure that the LEON can correctly return to its pre-interrupt state. The 4-bit interrupt level (ir) is also written to the trap type (tt) field of the TBR (Trap Base Register) by hardware. The TBR then contains the vector of the trap handler routine the processor will then jump. The TBA (Trap Base Address) field of the TBR must have a valid value before any interrupt processing can occur so it should be configured 10 at an early stage. Interrupt pre-emption is supported while ET (Enable Traps) bit of the PSR is set. This bit is cleared during the initial trap processing. In initial simulations the ET bit was observed to be cleared for up to 30 cycles. This causes significant additional interrupt latency in the worst case where a higher priority interrupt arrives just as a lower priority one is taken. 15 The interrupt acknowledge cycles shown in Figure 28 below are derived from simulations of the LEON processor. The SoPEC toplevel interrupt signals used in this diagram map directly to the LEON interrupt signals in the iui and iuo records. An interrupt is asserted by driving its (encoded) level on the icucpuieve[3:0] signals (which map to iui.irl[3:0]). The LEON core responds to this, with variable timing, by reflecting the level of the taken interrupt on the cpuicuieve[3:0 signals (mapped to 20 iuo.irl[3:0]) and asserting the acknowledge signal cpu iack (iuo.intack).The interrupt controller then removes the interrupt level one cycle after it has seen the level been acknowledged by the core. If there is another pending interrupt (of lower priority) then this should be driven on icucpuilevel[3:0J and the CPU will take that interrupt (the level 9 interrupt in the example below) once it has finished processing the higher priority interrupt. The cpu icuieve[3:0] signals always reflect the level of the last taken interrupt, even when the 25 CPU has finished processing all interrupts. 12 USB HOST UNIT (UHU) 12.1 OVERVIEW The UHU sub-block contains a USB2.0 host core and associated buffer/control logic, permitting 30 communication between SoPEC and external USB devices, e.g. digital camera or other SoPEC USB device cores in a multi-SoPEC system. UHU dataflow in a basic multi-SoPEC system is illustrated in the functional block diagram of Figure 29. The multi-port PHY provides three downstream USB ports for the UH{U. The host core in the UHU is a USB2.0 compliant 3rd party Verilog IP core from Synopsys, the ehciohci. It 35 contains an Enhanced Host Controller Interface (EHCI) controller and an Open Host Controller Interface (OHCI) controller. The EHCI controller is responsible for all High Speed (HS) USB traffic. The OHCI controller is responsible for all Full Speed (FS) and Low Speed (LS) USB traffic.
WO 2005/120835 PCT/AU2004/000706 444 12.1.1USB Effective Bandwidth The USB effective bandwidth is dependent on the bus speed, the transfer type and the data payload size of each USB transaction. The maximum packet size for each transaction data payload is defined in the bMaxPacketSizeO field of the USB device descriptor for the default control endpoint (EPO) and in the 5 wMaxPacketSize field of USB EP descriptors for all other EPs. The payload sizes that a USB host is required to support at the various bus speeds for all transfer types are listed in Table 32. It should be noted that the host is required by USB to support all transfer types and all speeds. The capacity of the packet buffers in the EHCI/OHCI controllers will be influenced by these packet constraints. Table 32. USB Packet Constraints Trer Mxaxt ack tS (Eyes) Control 8 8, 16, 32, 64 64 Isochrono n/a 0-1023 0-1024 us Interrupt 0-8 0-64 0-1024 Bulk n/a 8,16, 32, 512 64 10 The maximum effective bandwidth using the maximum packet size for the various transfer types is listed in Table 33. Table 33. USB Transaction Limits Transfer Max Ewandwidth (MHits/s) C nt t E TypeLS FS M Control 0.192 6.656 12.698 Assuming one data stage and zero length status stage. Isochronous 8.184 393.216 A maximum transfer size of 3072 suppotec bytes per microframe is allowed for at LShigh bandwidth HS isochronous EPs, using multiple transactions per microframe. It is unlikely that a host would allocate this much bandwidth on -A OL A:a shared bus. Interrupt 0.384 9.728 393.216 A maximum transfer size of 3072 bytes per microframe is allowed for high bandwidth HS interrupt EPs, using multiple transactions. It is unlikely that a host would allocate this much bandwidth on a shared bus.
WO 2005/120835 PCT/AU2004/000706 445 Bulk N 9.728 425.984 Can only be realised during a s t (micro)frame that has no isochronous or interrupt transactions scheduled, because bulk transfers are only allocated the remaining bandwidth. 12.1.2 DRAM Effective Bandwidth The DRAM effective bandwidth available to the UHU is allocated by the DRAM Interface Unit (DIU). The DIU allocates time-slots to UHU, during which it can access the DRAM in fixed bursts of 4 x 64 bit words. A single read or write time-slot, based on a DIU rotation period of 256 cycles, provides a read or write 5 transfer rate of 192 Mbits/s, however this is programmable. It is possible to configure the DIU to allocate more than one time-slot, e.g. 2 slots = 384 Mbits/s, 3 slots = 576 Mbits/s, etc. The maximum possible USB bandwidth during bulk transfers is 425 M/bits per second, assuming a single bulk EP with complete USB bandwidth allocation. The effective bandwidth will probably be less than this due to latencies in the ehciohci core. Therefore 2 DIU time-slots for the UHU will probably be sufficient to 10 ensure acceptable utilization of available USB bandwidth. 12.2 IMPLEMENTATION 12.2.1 UH U I/Os NOTE: P is a constant used in Table 34 to represent the number of USB downstream ports. P=3. Table 34. UHU top-level VOs Clocks and Resets Pclk 1 In Primary system clock. Prstn 1 In Reset for pclk domain. Active low. Synchronous to pclk. Uhu_48clk 1 In 48MHz USB clock. Uhu_12clk 1 In 12MHz USB clock. Synchronous to uhu_48c/k. Phy.clk 1 In 30MHz PHY clock. Phyjrstn 1 In Reset for phyclk domain. Active low. Synchronous to phy.clk. Phy-uhu-port-clk[2:0] 3 In 30MHz PHY clock, per port. Synchronous to phy clk. Phy-uhu-rst-n[2:0] 3 In Resets for phy uhu port~clk[2:0] domains, per port. Active low.
WO 2005/120835 PCT/AU2004/000706 446 Synchronous to corresponding bit of phy-uhu-portclk[2:0]. ICU Interface Uhuicuirq 1 Out Interrupt signal to the ICU. Active high. CPU Interface Cpu-adr[9:2] 8 In CPU address bus. Only bits 9:2 of the CPU address bus are required to address the UHU register map. Cpu-dataout[31:0] 32 In Shared write data bus from the CPU Cpu-rwn 1 In Common read/not-write signal from the CPU Cpu-acode[1:0] 2 In CPU Access Code signals. These decode as follows: 00: User program access 01: User data access 10: Supervisor program access 11: Supervisor data access Cpu-uhu-sel 1 In UHU select from the CPU. When cpu..uhusel is high both cpu..adr and cpu.dataout are valid Uhucpu-rdy 1 Out Ready signal to the CPU. When uhucpurdy is high it indicates the last cycle of the access. For a write cycle this means cpudataout has been registered by the UHU and for a read cycle this means the data on uhu.cpu..data is valid. Uhu.cpu-data[31:0] 32 Out Read data bus to the CPU Uhucpu-berr 1 Out Bus error signal to the CPU indicating an invalid access. Uhu-cpu_debug_valid 1 Out Signal indicating that the data currently on uhu..cpudata is valid debug data. DIU Interface diuuhuwack 1 In Acknowledge from the DIU that the write request was accepted. diuuhurack 1 In Acknowledge from the DIU that the read request was accepted. diuuhurvalid 1 In Signal from the DIU to the UHU indicating that the data currently on the diu data[63:0] bus is valid diu-data[63:0] 64 In Common DIU data bus. Uhudiuwadr[21:5] 17 Out Write address bus to the DIU Uhudiudata[63:0] 64 Out Data bus to the DIU. Uhudiuwreq 1 Out Write request to the DIU Uhudiuwvalid 1 Out Signal from the UHU to the DIU indicating that the data currently on the uhu_diudata[63:0] bus is valid Uhudiuwmask[7:0] 8 Out Byte aligned write mask. A '1' in a bit field of uhu_diu_wmask[7:0] means that the corresponding byte will be written to DRAM. Uhudiurreq 1 Out Read request to the DIU.
WO 2005/120835 PCT/AU2004/000706 447 Uhudiuradr[21:5] 17 Out Read address bus to the DIU GPIO Interface Signals gpio-uhu-over current[2:0 3 In Over-current indication, per port. Driven by an external VBUS current monitoring circuit. Each bit of the bus is as follows: 0: normal 1: over-current condition uhugpiopowerswitch[2: 3 Out Power switching for downstream USB ports. 0] Each bit of the bus is as follows: 0: port power off 1: port power on Test Interface Signals uhuohciscanmode-i-n 1 In OHCI Scan mode select. Active low. Maps to ohci_0 scanmodeti n ehci_ohci core input signal. 0: scan mode, entire OHCI host controller runs on 12 MHz clock input. 1: normal clocking mode. NOTE: This signal should be tied high during normal operation. PHY Interface Signals - UTMI Tx phy-uhujtxready[P-1:0] P In Tx ready, per port. Acknowledge signal from the PHY to indicate that the Tx data on uhuphy txdata[P-1:0][7:0] and uhuphyxdatah[P- 1:0][7:0] has been registered and the next Tx data can be presented. uhu-phy-jxvalid[P-1:0] P Out Tx data low byte valid, per port. Indicates to the PHY that the Tx data on uhu-phy txdata[P-1:0][7:0] is valid. uhu-phy-jxvalidh[P-1:0] P Out Tx data high byte valid, per port. Indicates to the PHY that the Tx data on uhu-phy txdatah[P-1:0][7:0] is valid. uhu-phytxdata[P- P x Out Tx data low byte, per port. 1:0][7:0] 8 The least significant byte of the 16 bit Tx data word. uhu-phytxdatah[P- P x Out Tx data high byte, per port. 1:0][7:0] 8 The most significant byte of the 16 bit Tx data word. PHY Interface Signals - UTMI Rx phy-uhu-rxvalid[P-1:0] P In Rx data low byte valid, per port. Indication from the PHY that the Rx data on phy uhu_rxdata[P- 1:0][7:0] is valid. phy-uhu-rxvalidh[P-1:0] P In Rx data high byte valid, per port. Indication from the PHY that the Rx data on phy uhu-rxdatah[P- 1:0][7:0] is valid. phy-uhu-rxactive[P-1:0] P In Rx active, per port. Indication from the PHY that a SYNC has been detected and the receive state-machine is in an active state. phy-uhu-rxerr[P-1:0] P In Rx error, per port, Indication from the PHY that a receive error has been detected.
WO 2005/120835 PCT/AU2004/000706 448 phy-uhu-rxdata[P- P x In Rx data low byte, per port. 1:0][7:0] 8 The least significant byte of the 16 bit Rx data word. phy-uhu-rxdatah[P- P x In Rx data high byte, per port. 1:0][7:0] 8 The most significant byte of the 16 bit Rx data word. PHY Interface Signals - UTMI Control phy-uhu-line-state[P- P x In Line state signal, per port. 1:0][1:0] 2 Line state signal from the PHY. Indicates the state of the single ended receivers D+/D 00: SEO 01: J state 10: K state 11: SE1 phy-uhu-discon-det[P- P In HS disconnect detect, per port. 1:0] Indicates that a HS disconnect was detected. uhu-phy-xver-select[P- P Out Transceiver select, per port. 1:0] 0: HS transceiver selected. 1: LS transceiver selected. uhu-phy-term-select[P- P x Out Termination select, per port. 1:0][1:0] 2 00: HS termination enabled 01: FS termination enabled for HS device 10: LS termination enabled for LS serial mode. 11: FS termination enabled for FS serial modes uhu-phy-opmode[P- P x Out Operational mode, per port. 1:0][1:0] 2 Selects the operational mode of the PHY. 00: Normal operation 01: Non-driving 10: Disable bit-stuffing and NRZI encoding 11: Reserved uhu-phy-suspendm[P-1:0] P Out Suspend mode for PHY port logic, per port. Active low. Places the PHY port logic in a low-power state. PHY Interface Signals - Serial. phy-uhuIsfsrcv[P-1:0] P In Rx serial data, per port. FS/LS differential receiver output. phyuhuvpi[P-1:0] P In D+ single-ended receiver output, per port. phy-uhu-vmi[P-1:0] P In D- single-ended receiver output, per port. uhu_phyjfs_xver-own[P- P Out Transceiver ownership, per port. 1:0] Selects between UTMI and serial interface transceiver control. 0: UTMI interface. The data on D+/D- is transmitted/received under the control of the UTMI interface, i.e. uhu-phy fs data[P-1:0], uhuphy fsseO[P-1:0], uhu-phy fsoe[P-1:0] are inactive. 1: Serial interface. The data on D+/D- is transmitted/received under the control of the serial interface, i.e. uhu-phy fsdata[P-1:0], uhuphy_fs~se0[P-1:0], uhu-phy fs._oe[P-1:0] are active.
WO 2005/120835 PCT/AU2004/000706 449 uhu..phyjs data[P-1 :0] P Out Tx serial data, per port. 0: D+/D- are driven to a differential '0' 1: D+/D- are driven to a differential '1' Only valid when uhu-phy fs_xver_own[P-1:0]=1. uhuphyjsse[P-1:0] P Out Tx Single-Ended '0' (SEO) assert, per port. 0: D+/D- are driven by the value of uhuphy_fsdata[P- 1:0] 1: D+/D- are driven to SEO Only valid when uhu_phy fs_xver_own[P-1:0]=1. uhu_phy_fsoe[P-1:0] P Out Tx output enable, per port. 0: uhuphy_fsdata[P- 1:0] and uhu-phy fsseO[P 1:0] disabled. 1: uhu phyfskdata[P-1:0] and uhu_phy fs~seO[P 1:0] enabled. Only valid when uhu phy fs xverown[P-1:0]=1. PHY Interface Signals - Vendor Control and Status. These signals are optional and may not be present on a specific PHY implementation. phy-uhu-vstatus[P- P x In Vendor status, per port. 1:0][7:0] 8 Optional vendor specific control bus. uhu-phyvcontrol[P- P x Out Vendor control, per port. 1:0][3:0] 4 Optional vendor specific status bus. uhu-phyyvloadm[P-1:0] P Out Vendor control load, per port. Asserting this signal loads the vendor control register. 12.2.2 Configuration Registers The UHU register map is listed in Table 35. All registers are 32 bit word aligned. Supervisor mode access to all UHU configuration registers is permitted at any time. User mode access to UHU configuration registers is only permitted when UserModeEn=1. A CPU bus error 5 will be signalled on cpuberr if user mode access is attempted when UserModeEn=0. UserModeEn can only be written in supervisor mode. Table 35. UHU register map UHU-Specific Control/Status Registers Ox000 Reset 1 Ox1 Reset register. Writing a '0' or a '1' to this register resets all UHU logic, including the ehci ohci host core. Equivalent to a hardware reset. NOTE: This register always reads 0x1. Ox004 IntStatus 7 OxO Interrupt status register. Read only. Refer to section 12.2.2.2 on page 126 for IntStatus register description.
WO 2005/120835 PCT/AU2004/000706 450 0x008 UhuStatus 11 OxO General UHU logic status register. Read only. Refer to section 12.2.2.3 on page 128 for UhuStatus register description. Ox00C IntMask 7 OxO Interrupt mask register. Enables/disables the generation of interrupts for individual events detected by the IntStatus register. Refer to section 12.2.2.4 on page 128 for IntMask register description. Ox010 IntClear 4 OxO Interrupt clear register. Clears interrupt fields in the IntStatus register. Refer to section 12.2.2.5 on page 129 for IntClear register description. NOTE: This register always reads x0. Ox01 4 EhciOhciCtl 6 0x1 000 EHCI/OHCI general control register. Refer to section 12.2.2.6 on page 129 for EhciOhciCti register description. 0x018 EhciFladjCtl 24 0x0202020 EHCI frame length adjustment (FLADJ) 2 controlregister. Refer to section 12.2.2.7 on page 130 for EhciFladjCtl register description. Ox01C AhbArbiterEn 2 OxO AHB arbiter enable register. Enable/disable AHB arbitration for EHCI/OHCI controllers. When arbitration is disabled for a controller, the AHB arbiter will not respond to AHB requests from that controller. Refer to section 12.2.3.3.4 on page 147 for details of arbitration. [4] EhciEn 0: disabled 1: enabled [3:1] Reserved [0] OhciEn 0: disabled 1: enabled 0x020 DmaEn 2 OxO DMA read/write channel enable register. Enables/disables the generation of DMA read/write requests from the UHU to the DIU. When disabled, all UHU to DIU control signals will be de-asserted. [4] ReadEn 0: disabled 1: enabled [3:1] Reserved [0] WriteEn 0: disabled 1: enabled WO 2005/120835 PCT/AU2004/000706 451 0x024 DebugSelect[9:2 8 OxO Debug select register. Address of the register selected for debug observation. NOTE: DebugSelect[9:2] can only select UHU specific control/status registers for debug observation, i.e. EHCI/OHCI host controller registers can not be selected for debug observation. Ox028 UserModeEn 1 OxO User mode enable register. Enables CPU user mode access to UHU register map. 0: Supervisor mode access only. 1: Supervisor and user mode access. NOTE: UserModeEn can only be written in supervisor mode. Ox02C - Reserved 0x09F OHCI Host Controller Operational Registers. The OHCI register reset values are all given as 32 bit hex numbers because all the register fields are not contained within the least significant bits of the 32 bit registers, i.e. every register uses bit #31, regardless of number of bits used in register. Ox1 00 HcRevision 32 0x0000001 A BCD representation of the OHCI spec 0 revision. Ox104 HcControl 32 0x0000000 Defines operating modes for the host 0 controller. Ox108 HcCommandSta 32 0x0000000 Used by the Host Controller to receive tus 0 commands issued by the Host Controller Driver, as well as reflecting the current status of the Host Controller. Ox10C HcInterruptStatu 32 0x0000000 Provides status on various events that s 0 cause hardware interrupts. When an event occurs, Host Controller sets the corresponding bit in this register. Ox110 HcInterruptEnab 32 0x0000000 Each enable bit corresponds to an le 0 associated interrupt bit in the HcInterruptStatus register. Ox114 HcInterruptDisa 32 0x0000000 Each disable bit corresponds to an ble 0 associated interrupt bit in the HcInterruptStatus register. Ox118 HcHCCA 32 Ox0000000 Physical address in DRAM of the Host 0 Controller Communication Area. Ox11C HcPeriodCurren 32 OxOOOOOOO Physical address in DRAM of the current tED 0 Isochronous or Interrupt Endpoint Descriptor. 0x120 HcControlHead 32 OxOO000 Physical address in DRAM of the first ED 0 Endpoint Descriptor of the Control list. Ox124 HcControlCurre 32 Ox00000 Physical address in DRAM of the current ntED 0 Endpoint Descriptor of the Control list. Ox128 HcBulkHeadED 32 OxOO00 Physical address in DRAM of the first 0 Endpoint Descriptor of the Bulk list. Ox12C HcBulkCurrentE 32 0x0000000 Physical address in DRAM of the current D 0 endpoint of the Bulk list.
WO 2005/120835 PCT/AU2004/000706 452 OxI 30 HcDoneHead 32 0x0000000 Physical address in DRAM of the last 0 completed Transfer Descriptor that was ____________added to the Done queue Ox134 HcFminterval 32 0002E Indicates the bit time interval in a Frame DF and the Full Speed maximum packet size that the Host Controller may transmit or ______________receive without causing scheduling overrun. 0x138 HcFmRemainin 32 OxOOOOCO Contains a down counter showing the bit __ _ 0 time remaining in the current Frame. 0x13C HcFmNumber 0x1C c~mumer32 OxOOQOOCO Provides a timing reference among events 0 happening in the Host Controller and the _________Host Controller Driver. Cxl 40 HcPeriodicStart 32 OxOOCOOQOO Determines when is the earliest time Host 0 Controller should start processing the periodic list. Ox144 HcLSThreshold 32 0x0000062 Used by the Host Controller to determine 8 whether to commit to the transfer of a ______maximum of 8-byte LS packet before EOF. 0x148 HcRhDescriptor 32 impl. First of 2 registers describing the A specific characteristics of the Root Hub. Reset __________values are implementation-specific. 0x1 4C HcRhDescriptor 32 impl. Second of 2 registers describing the B specific characteristics of the Root Hub. Reset _________values are implementation-specific. Ox150 HcRhStatus 32 impl. Represents the Hub Status field and the ______ specific Hub Status Change field. 0x154 HcRhPortStatus 32 impl. Used to control and report port events on [0] specific port #0. 0x158 HcRhPortStatus 32 impl. Used to control and report port events on [1] specific port #1. 0x15C HcRhPortStatus 32 impl. Used to control and report port events on [2] specific port #2. Cx1 60 - Reserved Cxl 9F EHCI Host Controller Capability Registers. There are subtle differences between capability register map in the EHCI spec and the register map in the Synopsys databook. The Synopsys core interface to the Capability registers is DWORD in size, whereas the Capability register map in the EHCI spec is byte aligned. Synopsys placed the first 4 bytes of EHOI capability registers into a single 32 bit register, HCCAPBASE, in the same order as they appear in the EHCI spec register map. The HCSP-PORTROUTE register that appears on the EHCI spec register map is optional and not implemented in the Synopsys core. OO HCCAPBASE 32 0x0096001 Capability register. t [31:16] HCIVERSION [15:8] reserved [7:0] CAPLENGTH Cx204 HCSPARAMS 32 OxO00 0 11 Structural parameter. 6 Cx208 HCCPARAMS 32 OxCOOA00 Capability parameter. Ox2H n - Reserved Ox2OF WO 2005/120835 PCT/AU2004/000706 453 EHCI Host Controller Operational Registers. 0x210 USBCMD 32 0x0008090 USB command 0 0x214 USBSTS 32 0x0000100 USB status. 0 0x218 USBINTR 32 0x0000000 USB interrupt enable. 0 0x21C FRINDEX 32 OxOO00 USB frame index. 0 0x220 CTRLDSSEGM 32 OxOO00 4G segment selector. ENT 0 0x224 PERIODICLIST 32 0x0000000 Periodic frame list base register. BASE 0 0x228 ASYNCLISTAD 32 0x0000000 Asynchronous list address. DR 0 0x22C - Reserved 0x24F 0x250 CONFIGFLAG 32 0x0000000 Configured flag register. 0 0x254 PORTSCO 32 0x0000200 Port #0 Status/Control. 0 0x258 PORTSC1 32 0x0000200 Port #1 Status/Control. 0 0x25C PORTSC2 32 0x0000200 Port #2 Status/Control. 0 0x260 - Reserved 0x28F EHCI Host Controller Synopsys-specific Registers. Ox290 INSNREGOO 32 Ox0000000 EHCI programmable micro-frame base 0 value. Refer to section 12.2.2.8 on page 131. NOTE: Clear this register during normal operation. Ox294 INSNREGO1 32 0x100010 EHCI internal packet buffer programmable 0 OUT/IN threshold values. Refer to section 12.2.2.9 on page 131. Ox298 INSNREGO2 32 0x0000010 EHCI internal packet buffer programmable 0 depth. Refer to section 12.2.2.10 on page 132. Ox29C INSNREGO3 32 0x0000000 Break memory transfer. 0 Refer to section 12.2.2.11 on page 132. Ox2AO INSNREG04 32 OxOO00 EHCI debug register. 0 Refer to section 12.2.2.12 on page 133. NOTE: Clear this register during normal operation. Ox2A4 INSNREG05 32 0x0000100 UTMI PHY control/status registers. 0 Refer to section 12.2.2.13 on page 133. NOTE: Software should read this register to ensure that INSNREGO5. VBusy=0 before writing any fields in INSNREGO5.
WO 2005/120835 PCT/AU2004/000706 454 Debug Registers. Ox300 EhciOhciStatus 26 OxOOOOOOO EHCI/OHCI host controller status signals. Read only. Mapped to EHCI/OHCI status output signals on the ehcLohci core top-level. [25:23] ehci_prtpwo[2:0] [22] ehciinterruptLo [21] ehci pme~status_o [20] ehci power stateack_o [19] ehciusbstso [18] ehcibufacco [17:15] ohcL0ccsLo[2:0] [14:12] ohcLOspeedo[2:0] [11:9] ohcL0_suspendo[2:0] [8] ohcL_lgcy irqlo [7] ohci_0Lgcy irq12_o (6] ohcLCirq-o_n [5] ohci_0_smio_n [4] ohci_0_rmtwkp_o [3] ohci_0_sof_o_n [2] ohci_0_globalsuspend o [1] ohci_0_drwe_o [0] ohcl_0_rwe_o 12.2.2.1 OHCI Legacy System Support Register fields in the EhciOhciCtl and EhciOhciStatus refer to "OHCI Legacy" signals. These are 1/0 signals on the ehciohci core that are provided by the OHCI controller to support the use of a USB keyboard and 5 USB mouse in an environment that is not USB aware, e.g DOS on a PC. Emulation of PS/2 mouse and keyboard operation is possible with the hardware provided and emulation software drivers. Although this is not relevant in the context of a SoPEC environment, access to these signals is provided via the UHU register map for debug purposes, i.e. they are not used during normal operation. 12.2.2.2 IntStatus Register Description 10 All IntStatus bits are active high. All interrupt event fields in the IntStatus register are edge detected from the relevant UHU signals, unless otherwise stated. A transition from '0' to '1' on any status field in this register will generate an interrupt to the Interrupt Controller Unit (ICU) on uhu_icu_irq, if the corresponding bit in the IntMask register is set. IntStatus is a read only register. IntStatus bits are cleared by writing a '1' to the corresponding bit in the IntClear register, unless otherwise stated. Table 36. IntStatus .: Field Name Bit(s) Reset -Description Ehcilrq 24 Ox0 EHCI interrupt. Generated from ehci interrupt~o output signal from ehci~ohci core. Used to alert the host controller driver to events such as: - Interrupt on Async Advance - Host system error (assertion of sys-interruptLi) - Frame list roll-over WO 2005/120835 PCT/AU2004/000706 455 - Port change - USB error - USB interrupt. NOTE: The UHU EHCI driver software should read the EHCI controller internal operational register USBSTS to determine the nature of the interrupt. NOTE: This interrupt is synchronized with posted writes in the EHCI DIU buffer. See section 12.2.3.3 on page 144. NOTE: This is a level-sensitive field. It reflects the ehciohci active high interrupt signal ehciinterrupLo. There is no corresponding field in the IntClear register for this field because it is cleared when the EHCI host controller driver clears the interrupt condition via the EHCI host controller operational registers, causing ehci_interrupLo to be de-asserted. 23:21 OxO Reserved Ohcilrq 20 OxO OHCI general interrupt. Generated from ohci_0_irq-on output signal from ehciohcicore. One of 2 interrupts that the host controller uses to inform the host controller driver of interrupt conditions. This interrupt is used when HcControl.IR is cleared. NOTE: The UHU OHCI driver software should read the OHCI controller internal operational register HcInterruptStatus to determine the nature of the interrupt. NOTE: This interrupt is synchronized with posted writes in the OHCI DIU buffer. See section 12.2.3.3 on page 144. NOTE: This is a level-sensitive field. It reflects the inverse of the ehci_ohci active low interrupt signal ohcLOjirqg.o-n. There is no corresponding field in the IntClear register for this field because it is cleared when the OHCI host controller driver clears the interrupt condition via the OHCI host controller operational registers, causing ohcL_irqon to be de-asserted. 19:17 OxO Reserved OhciSmi 16 OxO OHCI system management interrupt. Generated from ohci_0_smi_o_n output signal from ehci_ohci core. One of 2 interrupts that the host controller uses to inform the host controller driver of interrupt conditions. This interrupt is used when HcControl.IR is set. NOTE: The UHU OHCI driver software should read the OHCI controller internal operational register HcInterruptStatus to determine the nature of the interrupt. NOTE: This interrupt is synchronized with posted writes in the OHCI DIU buffer. See section 12.2.3.3 on page 144 NOTE: This is a level-sensitive field. It reflects the inverse of the ehciohci active low interrupt signal ohci_0_smion. There is no corresponding field in the IntClear register for this field because it is cleared when the OHCI host controller driver clears the interrupt r'nnriitinn uin thea CWCI hnet Pnntrnlaor WO 2005/120835 PCT/AU2004/000706 456 operational registers, causing ohci_0_smio_n to be de-asserted. 15:13 Ox Reserved EhciAhbHrespErr 12 OxO EHCI AHB slave HRESP error. Indicates that the EHCI AHB slave responded to an AHB request with HRESP=0x1 (ERROR). 11:9 Ox0 Reserved OhciAhbHrespErr 8 Ox0 OHCI AHB slave HRESP error. Indicates that the OHCI AHB slave responded to an AHB request with HRESP=Oxl (ERROR). 7:5 Ox Reserved EhciAhbAdrErr 4 OxO EHCI AHB master address error. Indicates that the EHCI AHB master presented an address to the uhudma AHB arbiter that was out of range during a valid AHB access. See section 12.2.3.3.4 on page 147. 3:1 Ox0 Reserved OhciAhbAdrErr 0 Ox0 OHCI AHB master address error. Indicates that the OHCI AHB master presented an address to the uhudma AHB arbiter that was out of range during a valid AHB access. See section 12.2.3.3.4 on page 147. 12.2.2.3 UhuStatus Register Description Table 37. UhuStatus Field Name Bit() "Reset Description EhcilrqPending 24 Wx EHCI interrupt pending. Indicates that an /ntStatus.Ehci/rq interrupt condition has been detected, but the interrupt has been delayed due to posted writes in the EHCI DIU buffer. Cleared when ntStatus.Ehcilrq is cleared. 23:21 Ox0 Reserved WO 2005/120835 PCT/AU2004/000706 457 OhcilrqPending 20 OxO OHCI general interrupt pending. Indicates that an IntStatus.Ohci/rq interrupt condition has been detected, but the interrupt has been delayed due to posted writes in the OHCI DIU buffer. Cleared when IntStatus.Ohcilrq is cleared. 19:17 OxO Reserved EhciSmiPending 16 OxO OHCI system management interrupt pending. Indicates that an IntStatus.OhciSmi interrupt condition has been detected, but the interrupt has been delayed due to posted writes in the OHCI DIU buffer. Cleared when IntStatus.OhciSmi is cleared. 15:14 OxO Reserved OhciDiuRdBufCnt 13:12 OxO OHCl DIU read buffer count. Indicates the number of 4 x 64 bit buffer locations that contain valid DIU read data for the OHCI controller. Range 0 to 2. 11:10 OxO Reserved EhciDiuRdBufCnt 9:8 OxO EHCI DIU read buffer count. Indicates the number of 4 x 64 bit buffer locations that contain valid DIU read data for the EHCI controller. Range 0 to 2. 7:6 OxO Reserved OhciDiuWrBufCnt 5:4 OxO OHCl DIU write buffer count. Indicates the number of 4 x 64 bit buffer locations that contain valid DIU write data from the OHCI controller. Range 0 to 2. 3:2 OxO Reserved EhciDiuWrBufCnt 1:0 OxO EHCI DIU write buffer count. Indicates the number of 4 x 64 bit buffer locations that contain valid DIU write data from the EHCI controller. Range 0 to 2. 12.2.2.4 IntMask Register Description Enable/disable the generation of interrupts for individual events detected by the IntStatus register. All IntMask bits are active low. Writing a '1' to a field in the IntMask register enables interrupt generation for the corresponding field in the IntStatus register. Writing a '0' to a field in the IntMask register disables interrupt 5 generation for the corresponding field in the IntStatus register. Table 38. lntMask Field Name Bit(s) Reset - Descriptionj " EhciAhbHrespErr 12 OxO EHCl AHB slave HRESP error mask. 11:9 Ox0 Reserved OhciAhbHrespErr 8 0x0 OHCI AHB slave HRESP error mask. 7:5 OxO Reserved EhciAhbAdrErr 4 OxO EHCI AHB master address error mask. 3:1 Ox0 Reserved WO 2005/120835 PCT/AU2004/000706 458 OhciAhbAdrErr 0 Ox0 OHCI AHB master address error mask. 12.2.2.5 IntClear Register Description Clears interrupt fields in the IntStatus register. All fields in the IntClear register are active high. Writing a '1' to a field in the IntClear register clears the corresponding field in the IntStatus register. Writing a '0' to a field in the IntClear register has no effect. Table 39. IntClear EhciAhbHrespErr 12 OxO EHCI AHB slave HRESP error clear. 11:9 OxO Reserved OhciAhbHrespErr 8 OxO OHCI AHB slave HRESP error clear. 7:5 OxO Reserved EhciAhbAdrErr 4 OxO EHCl AHB master address error clear. 3:1 Ox0 Reserved OhciAhbAdrErr 0 Ox 0OHCI AHIB master address error clear. 12.2.2.6 EhciOhciCti Register Description The EhciOhciCtl register fields are mapped to the ehciohci core top-level control/configuration signals. Table 40. EhciOhciCtl Field Naoe J: Descripti EhciSimMode 20 0x0 EHC1 Simulation mode select. Mapped to ss_simulation_rode_i input signal to ehci ohci core. When set to l'b1, this bit sets the PHY in non-driving mode so the host can detect device connection. 0: Normal operation 1: Simulation mode NOTE: Clear this field during normal operation. 19:17 Ox0 Reserved OhciSimClkRstN 16 0x1 OHCI Simulation clock circuit reset. Active low. Mapped to ohci_0_c/kcktrst i n input signal to ehci ohci core. |nitial reset signal for rh-pl/ module. Refer to Section 12.2.4 Clocks and Resets, for reset requirements. 0: Reset rh-p// module for simulation 1: Normal operation. NOTE: Set this field during normal operation. 15:13 Ox0 Reserved WO 2005/120835 PCT/AU2004/000706 459 OhciSimCountN 12 OxO OHCI Simulation count select. Active low. Mapped to ohci_0_cntseLin input signal to ehci-ohci core. Used to scale down the millisecond counter for simulation purposes. The 1-ms period (12000 clocks of 12 MHz clock) is scaled down to 7 clocks of 12 MHz clock, during PortReset and PortResume. 0: Count full 1 ms 1: Count simulation time. NOTE: Clear this field during normal operation. 11:9 OxO Reserved OhciloHit 8 OxO OHCI Legacy - application 1/O hit. Mapped to ohcL0app_io&hiLi input signal to ehci ohci core. PCI I/O cycle strobe to access the PCI 1/O addresses of Ox60 and 0x64 for legacy support. NOTE: Clear this field during normal operation. CPU access to this signal is only provided for debug purposes. Legacy system support is not relevant in the context of SoPEC. 7:5 OxO Reserved OhciLegacylrql 4 OxO OHCI Legacy - external interrupt #1 - PS2 keyboard. Mapped to ohci_0_app-irq1i input signal to ehci_ohcicore. External keyboard interrupt #1 from legacy PS2 keyboard/mouse emulation. Causes an emulation interrupt. NOTE: Clear this field during normal operation. CPU access to this signal is only provided for debug purposes. Legacy system support is not relevant in the context of SoPEC. 3:1 OxO Reserved OhciLegacylrql2 0 OxO OHCI Legacy - external interrupt #12 - PS2 mouse. Mapped to ohci_0_app-irql2i input signal to ehciohci core. External keyboard interrupt #12 from legacy PS2 keyboard/mouse emulation. Causes an emulation interrupt. NOTE: Clear this field during normal operation. CPU access to this signal is only provided for debug purposes. Legacy system support is not relevant in the context of SoPEC. 12.2.2.7 EhciFladjCtl Register Description Mapped to EHCI Frame Length Adjustment (FLADJ) input signals on the ehciohci core top-level. Adjusts any offset from the clock source that drives the SOF microframe counter. Table 41. EhciFladjCtl 31:30 Ox0 Reserved FladjPort2 29:24 Wx2 FLADJ value for port #2. 23:22 Ox0 Reserved WO 2005/120835 PCT/AU2004/000706 460 FladjPortl 21:16 0x20 FLADJ value for port #1. 15:14 x0 Reserved FladjPortO 13:8 0x20 FLADJ value for port #0. 7:6 Ox0 Reserved FladjHost 5:0 0x20 FLADJ value for host controller. NOTE: The FLADJ register setting of Ox20 yields a micro-frame period of 125us (60000 HS clk cycles), for an ideal clock, provided that INSNREG00.Enable=0. The FLADJ registers should be adjusted according to the clock offset in a specific implementation. 5 NOTE: All FLADJ register fields should be set to the same value for normal operation, or the host controller will yield undefined results. Port specific FLADJ register fields are only provided for debug purposes. NOTE: The FLADJ values should only be modified when the USBSTS.HcHalted field of the EHCI host controller operational registers is set, or the host controller will yield undefined results. Some examples of FLADJ values are given in Table 42. Table 42. FLADJ Examples 0x00 59488 0x01 59504 0x02 59520 0x20 60000 Ox3F 60496 10 12.2.2.8 INSNREGOO Register Description EHCI programmable micro-frame base register. This register is used to set the micro-frame base period for debug purposes. NOTE: Field names have been added for reference. They do not appear in any Synopsys documentation. Table 43. INSNREGOO Field Name Bit(s) Reset Description Reserved 31:14 Ox0 Reserved. MicroFrCnt 13:1 Wx Micro-frame base value for the micro-frame counter. Each unit corresponds to a UTMI (30MHz) clk cycle.
WO 2005/120835 PCT/AU2004/000706 461 Enable 0 Ox 0: Use standard micro-frame base count, OxE86 (3718 decimal). 1: Use programmable micro-frame count, MicroFrCnt. INSNREG.MicroFrCnt corresponds to the base period of the micro-frame, i.e. the micro-frame base count value in UTMI (30MHz) clock cycles. The micro-frame base value is used in conjunction with the FLADJ value to determine the total micro-frame period. An example is given below, using default values which result 5 in the nominal USB micro-frame period. INSNREG.MicroFrCnt: 3718 (decimal) FLADJ: 32 (decimal) UTMI clk period: 33.33ns Total micro-frame period = (NSNREG.MicroFrCnt + FLADJ) * UTMI clk period = 125us 10 12.2.2.9 INSNREGO1 Register Description EHCI internal packet buffer programmable threshold value register. NOTE: Field names have been added for reference. They do not appear in any Synopsys documentation Table 44. INSNREGO1 OutThreshold 31:16 0x1 00 OUT transfer threshold value for the internal packet buffer. Each unit corresponds to a 32 bit word. InThreshold 15:0 0x1 00 IN transfer threshold value for the internal packet buffer. Each unit corresponds to a 32 bit word. During an IN transfer, the host controller will not begin transferring the USB data from its internal packet 15 buffer to system memory until the buffer fill level has reached the IN transfer threshold value set in INSNREGO.In Threshold. During an OUT transfer, the host controller will not begin transferring the USB data from its internal packet buffer to the USB until the buffer fill level has reached the OUT transfer threshold value set in INSNREGO1. OutThreshold. 20 NOTE: It is recommended to set INSNREGO1.OutThreshold to a value large enough to avoid an under-run condition on the internal packet buffer during an OUT transfer. The INSNREGO1.OutThreshold value is therefore dependent on the DIU bandwidth allocated to the UHU. To guarantee that an under-run will not occur, regardless of DIU bandwidth, set INSNREG01.OutThreshold=0x100 (1024 bytes). This will cause the host controller to wait until a complete packet has been transferred to the internal packet buffer before WO 2005/120835 PCT/AU2004/000706 462 initiating the OUT transaction on the USB. Setting INSNREG01.OutThreshod=0x100 is guaranteed safe but will reduce the overall USB bandwidth. NOTE: A maximum threshold value of 1024 bytes is possible, i.e. INSNREGO1. *Threshold=0x100. The fields are wider than necessary to allow for expansion of the packet buffer in future releases, according to 5 Synopsys. 12.2.2.10 INSNREGO2 Register Description EHCI internal packet buffer programmable depth register. NOTE: Field names have been added for reference. They do not appear in any Synopsys documentation Table 45. INSNREGO2 Reserved 31:12 OxO Reserved. Depth 11:0 0x100 Programmable buffer depth. Each unit corresponds to a 32 bit word. 10 Can be used to set the depth of the internal packet buffer. NOTE: It is recommended to set INSNREG.Depth=Ox1OO (1024 bytes) during normal operation, as this will accommodate the maximum packet size permitted by the USB. NOTE: A maximum buffer depth of 1024 bytes is possible, i.e. INSNREG02.Depth=0x100. The field is wider than necessary to allow for expansion of the packet buffer in future releases, according to Synopsys. 15 12.2.2.11 INSNREGO3 Register Description Break memory transfer register. This register controls the host controller AHB access patterns. NOTE: Field names have been added for reference. They do not appear in any Synopsys documentation Table 46. INSNREGO3 Field N am e B t )R e etD e c pt o Reserved 31:1 x0 Reserved. MaxBurstEn 0 OxO 0: Do not break memory transfers, continuous burst. 1: Break memory transfers into burst lengths corresponding to the threshold values in INSNREGO1. When INSNREG.MaxBurstEn=0 during a USB IN transfer, the host will request a single continuous write 20 burst to the AHB with a maximum burst size equivalent to the contents of the internal packet buffer, i.e. if the DIU bandwidth is higher than the USB bandwidth then the transaction will be broken into smaller bursts as the internal packet buffer drains. When INSNREG.MaxBurstEn=0 during a USB OUT transfer, the host will WO 2005/120835 PCT/AU2004/000706 463 request a single continuous read burst from the AHB with a maximum burst size equivalent to the depth of the internal packet buffer. When INSNREG.MaxBurstEn=1, the host will break the transfer to/from the AHB into multiple bursts with a maximum burst size corresponding to the IN/OUT threshold value in INSNREGO1. 5 NOTE: It is recommended to set INSNREG03=OxO and allow the uhudma AHB arbiter to break up the bursts from the EHCI/OHCI AHB masters. If INSNREG03=Ox 1, the only really useful AHB burst size (as far as the UHU is concerned) is 8 x 32 bits (a single DIU word). However, if INSNREGO1.OutThreshold is set to such a low value, the probability of encountering an under-run during an OUT transaction significantly increases. 10 12.2.2.12 INSNREGO4 Register Description EHCI debug register. NOTE: Field names have been added for reference. They do not appear in any Synopsys documentation Table 47. INSNREGO4 Fld Name Bit(s) Reset Descriptio Reserved 31:3 OxO Reserved PortEnumScale 2 Ox0 0: Normal port enumeration time. Normal operation. 1: Port enumeration time scaled down. Debug. HccParamsWrEn 1 x0 0: HCCPARAMS register read only. Normal operation. 1: HCCPARAMS register read/write. Debug. HcsParamsWrEn 0 x0 0: HCSPARAMS register read only. Normal operation. 1: HCSPARAMS register read/write. Debug. 12.2.2.13 INSNREGO5 Register Description 15 UTMI PHY control/status. UTMI control/status registers are optional and may not be present in some PHY implementations. The functionality of the UTMI control/status registers are PHY implementation specific. NOTE: Field names have been added for reference. They do not appear in any Synopsys documentation Table 48. INSNREGO5 Reserved 31:18 Ox0 Reserved VBusy 17 x0 Host busy indication. Read Only. 0: NOP. 1: Host busy. NOTE: No writes to INSNREG05 should be performed when host busy.
WO 2005/120835 PCT/AU2004/000706 464 PortNumber 16:13 OxO Port Number. Set by software to indicate which port the control/status fields apply to. Vload 12 OxO Vendor control register load. 0: Load VControl. 1: NOP. Vcontrol 11:8 OxO Vendor defined control register. Vstatus 7:0 OxO Vendor defined status register. 12.2.3 UHU Partition The three main components of the UHU are illustrated in the block diagram of Figure 30. The ehci_ohci top block is the top-level of the USB2.0 host IP core, referred to as ehciohci. 5 12.2.3.1 ehci ohci 12.2.3.1.1 ehci ohci I/Os The ehciohci I/Os are listed in Table 49. A brief description of each 1/0 is given in the table. NOTE: P is a constant used in Table 49 to represent the number of USB downstream ports. P=3. NOTE: The 1/0 convention adopted in the ehciohci core for port specific bus signals on the PHY is to have 10 a separate signal defined for each bit of the bus, its width equal to [P-1:0]. The resulting bus for each port is made up of I bit from each of these signals. Therefore a 2 bit port specific bus called examplebus_ i from each port on the PHY to the core, would appear as 2 separate signals example bus _i[P-1:0] and examplebus_0i[P-1:0]. The bus from PHY port #0 would consist of examplebus 1i[0] and examplebusif[0], the bus from PHY port #1 would consist of examplebusJi[] and 15 examplebusOfi], the bus from PHY port #2 would consist of examplebus 1_i[2] and examplebus_0_f[2], etc. These buses are combined at the VHDL wrapper around the host verilog IP core to give the UHU top-level I/Os listed in Table 34. Table 49. ehciohci 1/Os Clock & Reset Signals phyclk_i 1 In 30MHz local EHCI PHY clock. phy rst i-n 1 In Reset for phy.clkji domain. Active low. Resets all Rx/Tx logic. Synchronous to phy c/kJi. ohci_0_clk48_i 1 In 48 MHz OHCI clock. ohci_0_clkl2_i 1 In 12 MHz OHCI clock. hclk_i 1 In AHB clock. System clock for AHB interface (pck). hresetin 1 In Reset for hclk i domain. Active low. Synchronous to hclk_i.
WO 2005/120835 PCT/AU2004/000706 465 utmi-phy-clock-i[P-1:0] P In 30MHz UTMI PHY clocks. PHY clock for each downstream port. Used to clock Rx/Tx port logic. Synchronous to phyc/ki. utmireset_i n[P-1:01 P In UTMI PHY port resets. Active low. Resets for each utmi phyclock_i domain. Synchronous to corresponding bit of utmi phy clock-i. ohci_0_clkcktrst-i-n 1 In Simulation - clear clock reset. Active low. EHCI Interface Signals - General sysinterrupt.i 1 In System interrupt. ss_word_if_i 1 In *Word interface select. Selects the width of the UTMI Rx/Tx data buses. 0: 8 bit 1: 16 bit NOTE: This signals will be tied high in the RTL, UHU UTMI interface is 16 bits wide. ss_simulation_mode_i 1 In Simulation mode. ssjfladjval-hosti[5:0] 6 In Frame length adjustment register (FLADJ). ss_fladj_yal_5_i[P-1:0] P In Frame length adjustment register per port, bit #5 for each port. ss-fladj-val_4_i[P-1:0] P In Frame length adjustment register per port, bit #4 for each port. ss_fladj_val_3_i[P-1:01 P In Frame length adjustment register per port, bit #3 for each port. ssfladjLval_2_i[P-1:0] P In Frame length adjustment register per port, bit #2 for each port. ss_fladjyal_1_i[P-1:0] P In Frame length adjustment register per port, bit #1 for each port. ss_fladj_val_0_i[P-1:0] P In Frame length adjustment register per port, bit #0 for each port. ehci-interrupLo 1 Out USB interrupt. Asserted to indicate a USB interrupt condition. ehci_usbsts_o 6 Out USB status. Reflects EHCI USBSTS[5:0] operational register bits. [5] Interrupt on async advance. [4] Host system error [3] Frame list roll-over [2] Port change detect. [1] USB error interrupt (USBERRINT) [0] USB interrupt (USBINT) ehci_bufacco 1 Out Host controller buffer access indication. indicates the EHCI Host controller is accessing the system memory to read/write USB packet payload data. EHCI Interface Signals - PCI Power Management NOTE: This interface is intended for use with the PCI version of the Synopsys Host controller, i.e. it provides hooks for the PCI controller module. The AHB version of the core is used in SoPEC as PCI functionality is not required. The PCI Power Management input signals will be tied to an inactive state. sspower-state-i[1:0] 2 In PCI Power management state. NOTE: Tied to Oxo.
WO 2005/120835 PCT/AU2004/000706 466 ssnext_powerstatei[1:0] 2 In PCI Next power management state. NOTE: Tied to x0. ss-nxtpowerstatevalidI 1 In PCI Next power management state valid. NOTE: Tied to x0. ss_pme-enableI 1 In PCI Power Management Event (PME) Enable. NOTE: Tied to x0. ehci-pmestatuso 1 Out PME status. ehci-powerstateack o 1 Out Power state ack. OHCI Interface Signals - General ohci_0_scanmode i n 1 In Scan mode select. Active low. ohci_0_cntsel-i-n 1 In Count select. Active low. ohci_O_irq_o_n 1 Out HCI bus general interrupt. Active low. ohci_0_smi_o_n 1 Out HCI bus system management interrupt (SMI). Active low. ohciOrmtwkpo 1 Out Host controller remote wake-up. Indicates that a remote wake-up event occurred on one of the root hub ports, e.g. resume, connect or disconnect. Asserted for one clock when the controller transitions from Suspend to Resume state. Only enabled when HcControl.RWE is set. ohci_0_sof_o_n 1 Out Host controller Start Of Frame. Active low. Asserted for 1 clock cycle when the internal frame counter (HcFmRemaining) reaches OxO, while in its operational state. ohciOspeed-o[P-1:0] P Out Transmit speed. 0: Full speed 1: Low speed ohciOsuspendo[P-1:0] P Out Port suspend signal Indicates the state of the port. 0: Active 1: Suspend NOTE: This signal is not connected to the PHY because the EHCI/OHCI suspend signals are combined within the core to produce utmi suspendcLn[P- 1:0], which connects to the PHY. ohci_0_globalsuspend-o 1 Out Host controller global suspend indication. This signal is asserted 5ms after the host controller enters the Suspend state and remains asserted for the duration of the host controller Suspend state. Not necessary for normal operation but could be used if external clock gating logic implemented. ohci_0_drweo 1 Out Device remote wake up enable. Reflects HcRhStatus.DRWE bit. If HcRhStatus.DRWE is set it will cause the controller to exit global suspend state when a connect/disconnect is detected. If HcRhStatus.DRWE is cleared, a connect/disconnect condition will not cause the host controller to exit global suspend. ohci_0_rweo 1 Out Remote wake up enable. Reflects HcControl.RWE bit. HcControl.RWE is used to enable/disable remote wake-up upon upstream resume signalling.
WO 2005/120835 PCT/AU2004/000706 467 ohciOccso[P-1:01 P Out Current connect status. 1: port state-machine is in a connected state. 0: port state-machine is in a disconnected or powered-off state. Reflects HcRhPortStatus.CCS. OHCI Interface Signals - Legacy Support ohci_0_app-iohiti 1 In Legacy - application 1/O hit. ohciOapp-irql_i 1 In Legacy - external interrupt #1 - PS2 keyboard. ohci_0_app-irq12_i 1 In Legacy - external interrupt #12 - PS2 mouse. ohciO_gcy-irqlo 1 Out Legacy - IRQ1 - keyboard data. ohciO_gcy-irql2_o 1 Out Legacy - IRQ12 - mouse data. External Interface Signals These signals are used to control the external VBUS port power switching of the downstream USB ports. appprtovrcuri[P-1:0] P In Port over-current indication from application. These signals are driven externally to the ASIC by a circuit that detects an over-current condition on the downstream USB ports. 0: Normal current. 1: Over-current condition detected. ehci_prt_pwro[P-1:0] P Out Port power. Indicates the port power status of each port. Reflects PORTSC.PP. Used for port power switching control of the external regulator that supplies VBSUS to the downstream USB ports. 0: Power off 1: Power on PHY Interface Signals - UTMI utmilinestateO_i[P-1:0] P In Line state DP. utmiline state_1_i[P-1:0] P In Line state DM. utmitxreadyji[P-1:0]] P In Transmit data ready handshake. utmirxdatah_7_i[P-1:0] P In Rx data high byte, bit #7 utmirxdatah_6_i[P-1:01 P In Rx data high byte, bit #6 utmirxdatah_5_i[P-1:0] P In Rx data high byte, bit #5 utmi_rxdatah_4_i[P-1:0] P In Rx data high byte, bit #4 utmi_rxdatah_3_i[P-1:0] P In Rx data high byte, bit #3 utmirxdatah_2_i[P-1:0] P In Rx data high byte, bit #2 utmi rxdatah_1_i[P-1:0] P In Rx data high byte, bit #1 utmirxdatahOi[P-1:0] P In Rx data high byte, bit #0 utmirxdata_7_i[P-1:0] P In Rx data low byte, bit #7 utmirxdata_6_i[P-1:0] P In Rx data low byte, bit #6 utmi_rxdata_5_i[P-1:0] P In Rx data low byte, bit #5 utmi_rxdata_4_i[P-1:0] P In Rx data low byte, bit #4 utmi_rxdata_3_i[P-1:0] P In Rx data low byte, bit #3 WO 2005/120835 PCT/AU2004/000706 468 utmirxdata_2_i[P-1:0] P In Rx data low byte, bit #2 utmirxdata_1 _i[P-1:0] P In Rx data low byte, bit #1 utmi-rxdata_0_i[P-1:0] P In Rx data low byte, bit #0 utmi-rxvldhji[P-1:0] P In Rx data high byte valid. utmi-rxvld-i[P-1:0] P In Rx data low byte valid. utmirxactivei[P-1:0] P In Rx active. utmi-rxerrji[P-1:0] P In Rx error. utmidiscondet i[P-1:0] P In HS disconnect detect. utmitxdatah_7_o[P-1:0] P Out Tx data high byte, bit #7 utmitxdatah_6_o[P-1:0] P Out Tx data high byte, bit #6 utmitxdatah_5_o[P-1:0] P Out Tx data high byte, bit #5 utmitxdatah_4_o[P-1:0] P Out Tx data high byte, bit #4 utmi_txdatah_3_o[P-1:0] P Out Tx data high byte, bit #3 utmitxdatah_2_o[P-1:0] P Out Tx data high byte, bit #2 utmitxdatah_1_o[P-1:0] P Out Tx data high byte, bit #1 utmitxdatah_0_o[P-1:0] P Out Tx data high byte, bit #0 utmi_txdata_7_o[P-1:0] P Out Tx data low byte, bit #7 utmi_txdata_6_o[P-1:0] P Out Tx data low byte, bit #6 utmitxdata_5_o[P-1:0] P Out Tx data low byte, bit #5 utmi_txdata_4_o[P-1:0] P Out Tx data low byte, bit #4 utmitxdata_3_o[P-1:0] P Out Tx data low byte, bit #3 utmitxdata_2_o[P-1:0] P Out Tx data low byte, bit #2 utmitxdata_1_o[P-1:0] P Out Tx data low byte, bit #1 utmitxdata_0_o[P-1:0] P Out Tx data low byte, bit #0 utmiltxvdh.o[P-1:0] P Out Tx data high byte valid. utmi.txvld-o[P-1:0] P Out Tx data low byte valid. utmi-opmodelo[P-1:0] P Out Operational mode (M1). utmi-opmode_0_o[P-1:0] P Out Operational mode (MO). utmi~suspend-o-n[P-1:0] P Out Suspend mode. utmixver_select o[P-1:0] P Out Transceiver select. utmitermselect1 _o[P-1:0] P Out Termination select (Ti). utmi_termselectoo[P-1:0] P Out Termination select (TO). PHY Interface Signals - Serial. phyIsfs-rcvi[P-1:0] P In Rx differential data from PHY, per port. Reflects the differential voltage on the D+/D- lines. Only valid when utmi fs xver owno=1.
WO 2005/120835 PCT/AU2004/000706 469 utmi-vpi-i[P-1:0] P In Data plus, per port. I USB D+ line value. utmi-vmi-i[P-1:0] P In Data minus, per port. USB D+ line value. utmi-fs-xver-own-o[P-1:0] P Out UTMI/Serial interface select, per port. 1 = Serial interface enabled. Data is received/transmitted to the PHY via the serial interface. utmi_fsdata_o, utmJfsseoo, . utmifsoeo signals drive Tx data on to the PHY D+ and D- lines. Rx data from the PHY is driven onto the utmi vpi i and utmivmi_i signals. 0 = UTMI interface enabled. Data is received/transmitted to the PHY via the UTMI interface. utmijfs_data~o[P-11:0] P Out Tx differential data to PHY, per port. Drives a differential voltage on to the D+/D- lines. Only valid when utmi fsxverowno=1. utmi_fs~seQ_o[P-1 :0] P Out SEO output to PHY, per port. Drives a single ended zero on to D+/D- lines, independent of utmifsdata-o. Only valid when utmi fsxver own-o=1. utmijfs oe-o[P-1:0] P Out Tx enable output to PHY, per port. Output enable signal for utmi fs data and utmifsseCo. Only valid when utmi fs xver own o=1. PHY Interface Signals - Vendor Control and Status. phy vstatus_7_i[P-1:0] P In Vendor status, bit #7 phyvstatus_6_i[P-1:0] P In Vendor status, bit #6 phy-vstatus_5_i[P-11:0] P In Vendor status, bit #5 phyvstatus_4_i[P-1:0] P In Vendor status, bit #4 phy vstatus_3_i[P-1:0] P In Vendor status, bit #3 phyvstatus_2_i[P-1:0] P In Vendor status, bit #2 phyvstatus_1_i[P-1:0] P In Vendor status, bit #1 phyvstatus_0_i[P-1:0] P In Vendor status, bit #0 ehcivcontrol_3_o[P-1:0] P Out Vendor control, bit #3 ehcivcontrol2_o[P-1:0] P Out Vendor control, bit #2 ehcivcontrol_lo[P-1:0] P Out Vendor control, bit #1 ehci-vcontrolOo[P-1:0] P Out Vendor control, bit #0 ehci-vloadm-o[P-1:0] P Out Vendor control load. AHB Master Interface Signals - EHCI. ehci-hgrant-i 1 In AHB grant. ehci-hbusreqo 1 Out AHB bus request. ehci-hwrite-o 1 Out AHB write. ehci-haddr-o[31:0] 32 Out AHB address.
WO 2005/120835 PCT/AU2004/000706 470 ehci-htranso[1:0] 2 Out AHB transfer type. ehci-hsize-o[2:0] 3 Out AHB transfer size. ehci-hburst-o[2:0] 3 Out AHB burst size. NOTE: only the following burst sizes are supported: 000: SINGLE 001: INCR ehcihwdata o[31:0] 32 Out AHB write data. AHB Master Interface Signals - OHCI. ohci_0_hgrant-i 1 In AHB grant. ohci_0_hbusreqo 1 Out AHB bus request. ohci_0_hwrite o 1 Out AHB write. ohci_0_haddro[31:0] 32 Out AHB address. ohci_0_htrans o[1:0] 2 Out AHB transfer type. ohci_0_hsize_o[2:0] 3 Out AHB transfer size. ohci_0_hbursto[2:0] 3 Out AHB burst size. NOTE: only the following burst sizes are supported: 000: SINGLE 001: INCR ohci_0_hwdatao[31:0] 32 Out AHB write data. AHB Master Signals - common to EHCI/OHCI. ahb-hrdata-i[31:0] 32 In AHB read data. ahb-hrespi[1:0] 2 In AHB transfer response. NOTE: The AHB masters treat RETRY and SPLIT responses from AHB slaves the same as automatic RETRY. For ERROR responses, the AHB master cancels the transfer and asserts ehci interrupLo. ahb-hready-mbiui 1 In AHB ready. AHB Slave Signals - EHCI. ehcihseli 1 In AHB slave select. ehci_hrdatao[31:0] 32 Out AHB read data. ehci-hresp-o[1:0] 2 Out AHB transfer response. NOTE: The AHB slaves only support the following responses: 00: OKAY 01: ERROR ehci-hready-o 1 Out AHB ready. AHB Slave Signals - OHCI. ohci_0_hseli 1 In AHB slave select. ohci_0_hrdata_0[31:0] 32 Out AHB read data. ohci_0_hresp-o[1:0] 2 Out AHB transfer response. NOTE: The AHB slaves only support the following responses: 00: OKAY 01: ERROR WO 2005/120835 PCT/AU2004/000706 471 ohci_0_hready o 1 Out AHB ready. AHB Slave Signals - common to EHCVOHCI. ahb-hwrite-i 1 In AHB write data. ahbhaddri[31:0] 32 In AHB address. ahb-htransi[1:0] 2 In AHB transfer type. NOTE: The AHB slaves only support the following transfer types: 00: IDLE 01 BUSY 10: NONSEQUENTIAL Any other transfer types will result in an ERROR response. ahb-hsize-i[2:0] 3 In AHB transfer size. NOTE: The AHB slaves only support the following transfer sizes: 000: BYTE (8 bits) 001: HALFWORD (16 bits) 010: WORD (32 bits) NOTE: Tied to 0x10 (WORD). The CPU only requires 32 bit access. ahb.hburstji[2:0] 3 In AHB burst type. NOTE: Tied to OxO (SINGLE). The AHB slaves only support SINGLE burst type. Any other burst types will result in an ERROR response. ahb-hwdata-i[31:0] 32 In AHB write data. ahb-hreadyjtbiu-i 1 In AHB ready. 12.2.3.1.2 ehci ohci Partition The main functional components of the ehci_ohci sub-system are shown in Figure 31. Figure 31. ehciohci Basic Block Diagram. 5 The EHCI Host Controller (eHC) handles all HS USB traffic and the OHCI Host Controller (oHC) handles all FS/LS USB traffic. When a USB device connects to one of the downstream facing USB ports, it will initially be enumerated by the eHC. During the enumeration reset period the host determines if the device is HS capable. If the device is HS capable, the Port Router routes the port to the eHC and all communications proceed at HS via the eHC. If the device is not HS capable, the Port Router routes the port to the oHC and all 10 communications proceed at FS/LS via the oHC. The eHC communicates with the EHCI Host Controller Driver (eHCD) via the EHCI shared communications area in DRAM. Pointers to status/control registers and linked lists in this area in DRAM are set up via the operational registers in the eHC. The eHC responds to AHB read/write requests from the CPU-AHB bridge, targeted for the EHCI operational/capability registers located in the eHC via an AHB slave interface on the 15 ehciohci core. The eHC initiates AHB read/write requests to the AHB-DIU bridge, via an AHB master interface on the ehci ohci core.
WO 2005/120835 PCT/AU2004/000706 472 The oHC communicates with the OHCI Host Controller Driver (oHCD) via the OHCI shared communications area in DRAM. Pointers to status/control registers and linked lists in this area in DRAM are set up via the operational registers in the oHC. The oHC responds to AHB read/write requests from the CPU-AHB bridge, targeted for the OHCI operational registers located in the oHC via an AHB slave interface on the ehci ohci 5 core. The oHC initiates AHB (DIU) read/write requests to the AHB-DIU bridge, via an AHB master interface on the ehci ohci core. The internal packet buffers in the EHCI/OHCI controllers are implemented as flops in the delivered RTL, which will be replaced by single port register arrays or SRAMs to save on area. 12.2.3.2 uhu ctl 10 The uhu_ctl is responsible for the control and configuration of the UHU. The main functional components of the uhu_ctl and the uhu_ctl interface to the ehciohci core are shown in Figure 32. The uhu ctl provides CPU access to the UHU control/status registers via the CPU interface. CPU access to the EHCI/OHCI controller internal control/status registers is possible via the CPU-AHB bridge functionality of the uhu cd. 15 12.2.3.2.1 AHB Master and Decoder The uhuctl AHB master and decoder logic interfaces to the EHCI/OHCI controller AHB slaves via a shared AHB. The uhuctl AHB master initiates all AHB read/write requests to the EHCI/OHCI AHB slaves. The AHB decoder performs all necessary CPU-AHB address mapping for access to the EHCI/OHCI internal control/status registers. The EHCI/OHCI slaves respond to all valid read/write requests with zero wait state 20 OKAY responses, i.e. low latency for CPU access to EHCI/OHCI internal control/status registers. 12.2.3.3 uhu dma The uhudma is essentially an AHB-DIU bridge. It translates AHB requests from the EHCI/OHCI controller AHB masters into DIU reads/writes from/to DRAM. The uhudma performs all necessary AHB-DIU address mapping, i.e. it generates the 256 bit aligned DIU address from the 32 bit aligned AHB address. 25 The main functional components of the uhudma and the uhudma interface to the ehci_ohci core are shown in Figure 33. EHCI/OHCI control/status DIU accesses are interleaved with USB packet data DIU accesses, i.e. a write to DRAM could affect the contents of the next read from DRAM. Therefore it is necessary to preserve the DMA read/write request order for each host controller, i.e. all EHCI posted writes in the EHCI DIU buffer must be 30 completed before an EHCI DIU read is allowed and all OHCI posted writes in the OHCI DIU buffer must be completed before an OHCI DIU read is allowed. As the EHCI DIU buffer and the OHCI DIU buffer are separate buffers, EHCI posted writes do not impede OHCI reads and OHCI posted writes do not impede EHCI reads.
WO 2005/120835 PCT/AU2004/000706 473 EHCI/OHCI controller interrupts must be synchronized with posted writes in the EHCI/OHCI DIU buffers to avoid interrupt/data incoherence for IN transfers. This is necessary because the EHCI/OHCI controller could write the last data/status of an IN transfer to the EHCI/OHCI DIU buffer and generate an interrupt. However, the data will take a finite amount of time to reach DRAM, during which the CPU may service the interrupt, 5 reading an incomplete transfer buffer from DRAM. The UHU prevents the EHCI/OHCI controller interrupts from setting their respective bits in the IntStatus register while there are any posted writes in the corresponding EHCI/OHCI DIU buffer. This delays the generation of an interrupt on uhu icuirq until the posted writes have been transferred to DRAM. However, coherency is not protected in the situation where the SW polls the EHCI/OHCI interrupt status registers HcInterruptStatus and USBSTS directly. The affected 10 interrupt fields in the IntStatus register are IntStatus.Ehcilrq, IntStatus.OhciIrq and IntStatus.OhciSmi. The UhuStatus register fields UhuStatus.EhciIrqPending, UhuStatus. OhciIrqPending and UhuStatus. OhciSmiPending indicate that the interrupts are pending, i.e. the interrupt from the core has been detected and the UHU is waiting for DIU writes to complete before generating an interrupt on uhu_icu_irq. 12.2.3.3.1 EHCI DIU Buffer 15 The EHCI DIU buffer is a bidirectional double buffer. Bidirectional implies that it can be used as either a read or a write buffer, but not both at the same time, as it is necessary to preserve the DMA read/write request order. Double buffer implies that it has the capacity to store 2 DIU reads or 2 DIU writes, including write enables. When the buffer switches direction from DIU read mode to DIU write mode, any read data contained in the 20 buffer is discarded. Each DIU write burst is 4 x 64 bits of write data (uhudiudata) and 4 x 8 bits byte enable (uhu diuwmask). Each DIU read burst is 4 x 64 bits of read data (diudata). Therefore each buffer location is partitioned as shown in Figure 29. Only 4 x 64 bits of each location is used in read mode. The EHCI DIU buffer is implemented with an 8 x 72 bit register array. The 256 bit aligned DRAM address 25 (uhudiuwadr) associated with each DIU read/write burst will be stored in flops. Provided that sufficient DIU write time-slots have been allocated to the UHU, the buffer should absorb any latencies associated with the DIU granting a UHU write request. This reduces back-pressure on the downstream USB ports during USB IN transactions. Back-pressure on downstream USB ports during OUT transactions will be influenced by DIU read bandwidth and DIU read request latency. 30 It should be noted that back-pressure on downstream USB ports refers to inter-packet latency, i.e. delays associated with the transfer of USB payload data between the DIU and the internal packet buffers in each host controller. The internal packet buffers are large enough to accommodate the maximum packet size permitted by the USB protocol. Therefore there will be no bandwidth/latency issues within a packet, provided that the host controllers are correctly configured. 35 12.2.3.3.2 OHCI DIU Buffer The OHCI DIU buffer is identical in operation and configuration to the EHCI DIU buffer.
WO 2005/120835 PCT/AU2004/000706 474 12.2.3.3.3 DMA Manager The DMA manager is responsible for generating DIU reads/writes. It provides independent DMA read/write channels to the shared address space in DRAM that the EHCI/OHCI controller drivers use to communicate with the EHCI/OHCI host controllers. Read/write access is provided via a 64 bit data DIU read interface and a 5 64 bit data DIU write interface with byte enables, which operate independently of each other. DIU writes are initiated when there is sufficient valid write data in the EHCI DIU buffer or the OHCI DIU buffer, as detailed in Section 12.2.3.3.4 below. DIU reads are initiated when requested by the uhudma AHB slave and arbiter logic. The DmaEn register enables/disables the generation of DIU read/write requests from the DMA manager. 10 It is necessary to arbitrate access to the DIU read/write interfaces between the OHCI DIU buffer and the EHCI DIU buffer, which will be performed in a round-robin manner. There will be separate arbitration for the read and write interfaces. This arbitration can not be disabled because read/write requests from the EHCI/OHCI controllers can be disabled in the uhudma AHB slave and arbiter logic, if required. 12.2.3.3.4 AHB Slave & Arbiter 15 The uhudma AHB slave and arbiter logic interfaces to the EHCI/OHCI controller AHB masters via a shared AHB. The EHCI/OHCI AHB masters initiate all AHB requests to the uhudma AHB slave. The AHB slave translates AHB read requests into DIU read requests to the DMA manager. It translates all AHB write requests into EHCI/OHCI DIU buffer writes. In write mode, the uhudma AHB slave packs the 32 bit AHB write data associated with each EHCI/OHCI 20 AHB master write request into 64 bit words in the EHCI/OHCI DIU buffer, with byte enables for each 64 bit word. The buffer is filled until one of the following flush conditions occur: * the 256 bit boundary of the buffer location is reached * the next AHB write address is not within the same 256 bit DIU word boundary e if an EHCI interrupt occurs (ehci interrupto goes high) the EHCI buffer is flushed and the IntStatus 25 register is updated when the DIU write completes. * if an OHCI interrupt occurs (ohci_0_irqo._n or ohci_0_smi o-n goes low) the OHCI buffer is flushed and the IntStatus register is updated when the DIU write completes. The 256 bit aligned DIU write address is generated from the first AHIB write address of the AHB write burst and a DIU write is initiated. Non-contiguous AHB writes within the same 256 bit DIU word boundary result 30 in a single DIU write burst with the byte enables de-asserted for the unused bytes. In read mode, the uhudma AHB slave generates a 256 bit aligned DIU read address from the first EHCI/OHCI AHB master read address of the AHB read burst and initiates a DIU read request. The resulting 4 x 64 bit DIU read data is stored in the EHCI/OHCI DIU buffer. The uhudma AHB slave unpacks the relevant 32 bit data for each read request of the AHB read burst from the EHCI/OHCI DIU buffer, providing 35 that the AHB read address corresponds to a 32 bit slice of the buffered 4 x 64 bit DIU read data.
WO 2005/120835 PCT/AU2004/000706 475 DIU reads/writes associated with USB packet data will be from/to a transfer buffer in DRAM with contiguous addressing. However control/status reads/writes may be more random in nature. An AHB read/write request may translate to a DIU read/write request that is not 256 bit aligned. For a write request that is not 256 bit aligned, the AHB slave will mask any invalid bytes with the DIU byte enable signals (uhudiuwmask). For a 5 read request that is not 256 bit aligned, the AHB slave will simply discard any read data that is not required. The uhudma Arbiter controls access to the uhudma AHB slave. The AhbArbiterEn.EhciEn and AhbArbiterEn.OhciEn registers control the arbitration mode for the EHCI and OHCI AHB masters respectively. The arbitration modes are: * Disabled. AhbArbiterEn.EhciEn=0 and AhbArbiterEn.OhciEn=O. Arbitration for both EHCI and 10 OHCI AHB masters is disabled. No AHB requests will be granted from either master. e OHCI enabled only. AhbArbiterEn.EhciEn=O and AhbArbiterEn.OhciEn=1. The OHCI AHB master requests will have absolute priority over any AHB requests from the EHCI AHB master. * EHCI enabled only. AhbArbiterEn.EhciEn=1 and AhbArbiterEn.OhciEn=O. The EHCI AHB master requests will have absolute priority over any AHB requests from the OHCI AHB master. 15 e OHCI and EHCI enabled. AhbArbiterEn.EhciEn=1 and AhbArbiterEn.OhciEn=J. Arbitration will be performed in a round-robin manner between the EHCI/OHCI AHB masters, at each DIU word boundary. If both masters are requesting, the grant changes at the DIU word boundary. The uhudma slave can insert wait states on the AHB by de-asserting the EHCI/OHCI controller AHB HREADY signal ahb hready mbiui. The uhudma AHB slave never issues a SPLIT or RETRY response. 20 The uhudma slave issues an AHB ERROR response if the AHB master address is out of range, i.e. bits 31:22 were not zero (DIU read/write addresses have a range of 21:5). The uhudma will also assert the ehci ohci input signal sysinterrupt i to indicate a fatal error to the host. 13 USB USB DEVICE UNIT (UDU) 13.1 OVERVIEW 25 The USB Device Unit (UDU) is used in the transfer of data between the host and SoPEC. The host may be a PC, another SoPEC, or any other USB 2.0 host. The UDU consists of a USB 2.0 device core plus some buffering, control logic and bus adapters to interface to SoPEC's CPU and DIU buses. The UDU interfaces to a USB PHY via a UTMI interface. In accordance with the USB 2.0 specification, the UDU supports both high speed (480MHz) and full-speed (12MHz) operation on the USB bus. The UDU provides the default IN and 30 OUT control endpoints as well as four bulk IN, five bulk OUT and two interrupt IN endpoints. 13.2 UDU I/Os The toplevel I/Os of the UDU are listed in Table 50.
WO 2005/120835 PCT/AU2004/000706 476 Table 50. UDU I/O ~P t nm; Pins- VIO L.EDbctpti L Clocks and Resets Pclk 1 In System clock. prst n 1 In System reset signal Active low phyclk 1 In 30MHz clock for UTMI interface, generated in PHY. phyrst-n 1 In Reset in phy c/k domain from CPR block. Active low. UTMI transmit signals Phy-udtred 1 In An acknowledgement from the PHY of data transfer phyudu:txready 1 frmnDU uduphyjtxvalid 1 Out Idctst h H htdt d h ~aa70 is valid for transfer. udu-phy-_txvalidh 1 out IniaetotePYtadaau pyxaah70 uduphy-txdata[7: 8 Out Low byte of data to be transmitted to the USB bus. 01 udu-phytxdatah[ 8 Out High byte of data to be transmitted to the USB bus. 7:01 UTMI receive signals phy-udu-rxvalid 1 In Indicates that there is valid data on the PhY-udu rxdata':O] bus. phy-udu-rxvalidh 1 In Indicates that there is valid data on the dPhYuudtrxdatah[7ie bus. phy-udu-rxactive 1 In Indicates that the PHY's receive state machine has
-
detected SYNC and is active. PhY-udu-rxerr I in Indicates that a receive error has been detected. Active high. phy-udu-rxdata 8 In Low byte of data received from the USB bus. [7:0] phy-udu rxdaa 8 EHn o phudrdatah 8E In High byte of data received from the USB bus. [7:0] UTMI control signals udu-phy-xver-sel 1 Out Transceiver select 0: HS transceiver enabled 1: FS transceiver enabled udu-phy-termsel 1 Out Termination select 0: HS termination enabled 1: FS termination enabled udu-phy-opmode[ 2 Out Select between operational modes 1:0] 00: Normal operation 01: Non-driving 10: Disables bit stuffing & NRZI coding 11: reserved WO 2005/120835 PCT/AU2004/000706 477 phy udu-line-stat 2 In The current state of the D+ D- receivers e[1:0] 00: SEO 01: J State 10: K State 11: SE1 udu.phy-detectv 1 Out Indicates whether the Vbus signal is active. bus CPU Interface cpu-adr[1 0:2] 9 In CPU address bus. cpu-dataout[31:0] 32 In Shared write data bus from the CPU. udu-cpudata[31: 32 Out Read data bus to the CPU. 0] cpurwn 1 In Common read/not-write signal from the CPU. cpu-acode[1:0] 2 In CPU Access Code signals. These decode as follows: 00: User program access 01: User data access 10: Supervisor program access 11: Supervisor data access Supervisor Data is always allowed. User Data access is programmable. cpu_udusel 1 In Block select from the CPU. When cpuuduselis high both cpuadr and cpu dataout are valid. udu-cpu.rdy 1 Out Ready signal to the CPU. When uducpurdy is high it indicates the last cycle of the access. For a write cycle this means cpu.dataout has been registered by the UDU and for a read cycle this means the data on uducpudata is valid. udu-cpu-berr 1 Out Bus error signal to the CPU indicating an invalid access. udu-cpu-debugv 1 Out Signal indicating that the data currently on alid udu cpudata is valid debug data. GPIO signal gpiouduvbusst 1 In GPIO pin indicating status of Vbus. atus 0: Vbus not present 1: Vbus present Suspend signal udu-cpr-suspend 1 Out Indicates a Suspend command from the external USB host. Active high. Interrupt signal udujicujirq USB device interrupt signal to the ICU (Interrupt Control Unit). DIU write port udu-diu~wadr[21: 17 Out Write address bus to the DIU. 5] udu diu data[63:0 64 Out Data bus to the DIU.
WO 2005/120835 PCT/AU2004/000706 478 udu-diu wreq 1 Out Write request to the DIU. diu-udu-wack 1 In Acknowledge from the DIU that the write request was accepted. udu-diu-wvalid 1 Out Signal from the UDU to the DIU indicating that the data currently on the ududiu.data[63:0] bus is valid. udu-diu- wmask[7 8 Out Byte aligned write mask. A 1 in a bit field of :0] ududiuwmask[7:O] means that the corresponding byte will be written to DRAM. DIU read port udu-diujrreq 1 Out Read request to the DIU. ududiuradr[21:5 17 Out Read address bus to the DIU. I diuudurack 1 In Acknowledge from the DIU that the read request was accepted. diuudurvalid 1 In Signal from the DIU to the UDU indicating that the data currently on the diudata[63:0] bus is valid. diu-data[63:0] 64 In Common DIU data bus. 13.3 UDU BLOCK ARCHITECTURE OVERVIEW The UDU digital block interfaces to the mixed signal PHY block via the UTMI (USB 2.0 Transceiver Macrocell Interface) industry standard interface. The PHY implements the physical and bus interface level 5 functionality. It provides a clock to send and receive data to/from the UDU. The UDC20 is a third party IP block which implements most of the protocol level device functions and some command functions. The UDU contains some configuration registers, which are programmed via SoPEC's CPU interface. They are listed in Table 53. 10 There are more configuration registers in UDC20 which must be configured via the UDC20's VCI (Virtual Socket Alliance) slave interface. This is an industry standard interface. The registers are programmed using SoPEC's CPU interface, via a bus adapter. They are listed in Table 53 under the section UDC20 control/status registers. The main data flow through the UDU occurs through endpoint data pipes. The OUT data streams come in to 15 SoPEC (they are out data streams from the USB host controller's point of view). Similarly, the IN data streams go out of SoPEC. There are four bulk IN endpoints, five bulk OUT endpoints, two interrupt IN endpoints, one control IN endpoint and one control OUT endpoint.
WO 2005/120835 PCT/AU2004/000706 479 The UDC20's VCI master interface initiates reads and writes for endpoint data transfer to/from the local packet buffers. The DMA controller reads and writes endpoint data to/from the local packet buffers to/from endpoint buffers in DRAM. The external USB host controller controls the UDU device via the default control pipe (endpoint 0). Some low 5 level command requests over this pipe are taken care of by UDC20. All others are passed on to SoPEC's CPU subsystem and are taken care of at a higher level. The list of standard USB commands taken care of by hardware are listed in Table 57. A description of the operation of the UDU when the application takes care of the control commands is given in Section 13.5.5. 13.4 UDU CONFIGURATIONS 10 The UDU provides one configuration, six interfaces, two of which have one alternate setting, five bulk OUT endpoints, four bulk IN endpoints and two interrupt IN endpoints. An example USB configuration is shown in Table 51 below. However, a subset of this could instead be defined in the descriptors which are supplied by the UDU driver software. The UDU is required to support two speed modes, high speed and full speed. However, separate 15 configurations are not required for these due to the devicequalifier and otherspeed configuration features of the USB. Table 51. A supported UDU configuration Endpoint type .... ... ....... M L Interface 0 EP1 IN Bulk 64 512 Alternate setting 0 EP1 OUT Bulk 64 512 Interface 1 EP2 IN Bulk 64 512 Alternate setting 0 EP2 OUT Bulk 64 512 Interface 2 EP3 IN Interrupt 64 64 Alternate setting 0 EP4 IN Bulk 64 512 EP4 OUT Bulk 64 512 Interface 2 EP3 IN Interrupt 64 1024 Alternate EP4 IN Bulk 64 512 setting 1 EP4 OUT Bulk 64 512 Interface 3 EP5 IN Bulk 64 512 Alternate setting 0 EP5 OUT Bulk 64 512 Interface 4 EP6 IN Interrupt 64 64 Alternate setting 0 WO 2005/120835 PCT/AU2004/000706 480 Interface 4 EP6 IN Interrupt 64 1024 Alternate setting 1 Interface 5 EP7 OUT Bulk 64 512 Alternate setting 0 The following table lists what is fixed in HW and what is programmable in SW. Table 52. Programmability of device endpoints .Fi.ed.in.. 7 - SW prormal Number of Configurations = 1 At boot up, the SW can set the Configuration Descriptor to be bus-powered/self powered, support remote wakeup or not, set the bMaxPowerO consumption of the device, number of interfaces, etc. Max number of Interfaces = 6 The SW can set this from 1 to 6. Max number of Alternate Settings in Must be set to 1. Interface 0 = 1 Max number of Alternate Settings in Must be set to 1. Interface 1 = 1 Max number of Alternate Settings in The SW can set this to 1 or 2. Interface 2 = 2 Max number of Alternate Settings in Must be set to 1. Interface 3 = 1 Max number of Alternate Settings in The SW can set this to 1 or 2. Interface 4 = 2 Max number of Alternate Settings in Must be set to 1. Interface 5 = 1 The logical endpoints are fixed types and The SW cannot change the endpoint type and directions: direction. e.g. EP3 IN interrupt cannot be EP1 IN bulk changed to an OUT endpoint or to a bulk EP1 OUT bulk endpoint. However, a subset of these may be EP2 IN bulk defined by SW in the descriptors, e.g. SW can EP2 OUT bulk decide that EP4 IN does not exist. EP3 IN interrupt EP4 IN bulk EP4 OUT bulk EP5 IN bulk EP5 OUT bulk EP6 IN interrupt EP7 OUT bulk Max Packet Sizes are not fixed in HW. The SW can program the endpoints' max packet sizes to any values allowed by the USB spec. But it must program both the UDC2 and the UDU with the same values that are in the device descriptors.
WO 2005/120835 PCT/AU2004/000706 481 The HW does not fix which endpoints The endpoints can be assigned to any interface belong to different interfaces. supported. E.g. SW could place all endpoints into interface 0. The UDC20 must be programmed consistently with the device descriptors. 13.5 UDU OPERATION 13.5.1 Configuration Registers The configuration registers in the UDU are programmed via the CPU interface. Table 53 below describes the UDU configuration registers. Some of these registers are located within the UDC20 block. These come under 5 the heading "UDC20 control/status registers" in Table 53. Table 53. UDU Registers A dd resD esalpeon Control registers 0x000 Reset 1 Ox1I Soft reset. Writing either a '1' or '0' to this register causes a soft reset of the UDU and the UDC20. This register is cleared automatically, therefore it will always be read as '1'. Ox004 DebugSelect[1 0:2] 9 Ox000 Debug address select. This indicates the address of the register to report on the udu..cpu_data bus when it is not otherwise being used. Ox008 UserModeEnable 1 Ox0 Enable User Data mode access. When set to '1', User Data access is allowed in addition to Supervisor Data access. When set to '0' only Supervisor Data access is allowed. NOTE: UserModeEnable can only be written in supervisor mode. Ox00C Resume 1 Ox0 If remote wakeup is enabled (under the control of the external USB host) then writing a '1' to this register will take the USB bus out of suspend mode. Ox01 0 EpStall 11 Ox000 Writing a '1' to the relevant bit position causes the associated endpoint to be stalled. Note that endpoint 0 cannot be stalled. Bits 10-6 correspond to EP OUT 7, 5, 4, 2, 1 Bits 5-0 correspond to EP IN 6, 5, 4, 3, 2, 1 WO 2005/120835 PCT/AU2004/000706 482 0x014 CsrsDone 1 Ox0 Writing a '1' to this register in response to a IntSetCsrs interrupt instructs the UDU to respond to a status inquiry for the previous control command SetConfiguration or SetInterface with a zero length data packet (i.e. an ACK). Until this register is set to '1', following the generation of the IntSetCsrsCfg or IntSetCsrslntf interrupt, the UDU will respond to any status requests with a NAK. This register is cleared automatically once the signal udc20_set csrs goes low. Ox018 SOFTimeStamp 11 Ox000 The SOF frame number received from the host. This is updated each (micro)Frame. Read only. Ox01 C EnumSpeed 1 Ox1 The speed of operation after enumeration. Read only. 0: High Speed 1 : Full Speed 0x020 StatuslnResponse 2 Ox0 This register indicates the status of the current Control-Out transaction. This is required for responding to the host during the Status-In stage of the transfer. The Status-In request will be NAK'd until this register has been written to. 00: No response yet (issue a NAK) 01: Issue an ACK (a zero length data pkt) 10: Issue a STALL 11 : reserved This register is cleared automatically at the end of the Status stage of the transfer. Ox024 StatusOutRespon 2 Ox0 This register indicates the status of the se current Control-in transaction. This is required for responding to the host during the Status-Out stage of the transfer. The Status-Out request will be NAK'd until this register has been written to. 00: No response yet (issue a NAK) 01 : Issue an ACK and accept any data 10: Issue a STALL 11: Issue an ACK and discard data (if any). This register is cleared automatically at the end of the Status stage of the ___________transfer.
WO 2005/120835 PCT/AU2004/000706 483 0x028 CurrentConfigurati 12 Ox000 Indicates the current configuration the on UDU is running, and the Interface and Alternate Interface last set by the USB host's Setinterface command. Read only. Bits 11-8 : Current Configuration Bits 7-4: Interface Number Bits 3-0 : Alternate Interface Number Note that the reset value of OxOOO indicates that the device is not yet configured. The only values that Current Configuration can be set to are 0000 and 0001. When the Setinterface command is issued, the alternate setting being set and the relevant interface number are programmed into this register. OxO2C VbusStatus 1 Ox0 Indicates the current status of the input pin gpioudu vbus status. Read only. 0x030 DetectVbus 1 Ox1 This drives the input pin detectvbus on the PHY. It indicates that Vbus is active. This should be set to ' when gpio-uduvbus status goes low. 0x034 DisconnectDevice 1 Ox1 This register drives the UDC20 signal app-dev..discon. Writing a '1'to this register effectively disconnects the D+/D lines. Once the UDU has been configured and the CPU is ready for USB operation to begin, this register should be set to 0'. Please refer to Section 13.5.22. Ox038 UDC20Strap 20 0x03071 UDC20 strap signals. Please refer to Section 13.5.22 for explanation of each signal. Note that it is not recommended to modify the reset value of these registers during normal operation. Bit 19: app-utmi dir (Read only) Bit 18: app-setdescsup (Read only) Bit 17: appsynccmd sup (Read only) Bit 16: app-ramjif (Read only) Bit 15: app-phyiLf8bit (Read only) Bit 14: app-csrprg sup (Read only) Bits 13-11: fstimeout_calib[2:0] Bits 10-8: hstimeoutcalib[2:0] Bit 7: app-stall clr ephalt Bit 6: app-enable_erratic_err Bit 5: app_n.zen_pktstalall Bit 4: appnzjenpkt stall Bits 3-2: app-exp-speed[1:0] Bit 1: app-devrmtwkup Bit 0: app-self pwr Ox03C InterruptEpSize 22 0x004000 Max packet size for the two Interrupt 40 endpoints, from 0 to 1024 bytes. Bits 31-27 : reserved Bits 26-16: Ep6 IN Bits 15-11 : reserved Bits 10-0 : Ep3 IN WO 2005/120835 PCT/AU2004/000706 484 0x040 FsEpSize 20 OxFFFFF Max pkt size for the control and bulk endpoints in Full Speed. Bits 19-18 Ep7 Out Bits 17-16 Ep5 Out Bits 15-14 Ep5 In Bits 13-12 Ep4 Out Bits 11-10 Ep4 In Bits 9-8 Ep2 Out Bits 7-6 Ep2 In Bits 5-4 EpI Out Bits 3-2 Ep1 In Bits 1-0 Ep 0 where the bits decode as: 00 : 8 bytes 01 :16 bytes 10 :32 bytes 11: 64 bytes 0x044 DmaModes 2 Ox3 Indicates whether the non-control IN and OUT high speed transfers operate in streaming or non-streaming modes. Writing a '0' to a bit position enables streaming mode, and writing a '1' enables non-streaming mode. Bit 1: OUT endpoints Bit 0: IN endpoints Endpoint 0 OUT (n=0) OxO5O DmaOutnDoubleB 1 Ox0 Indicates whether the DRAM buffer uf associated with Epn OUT is a circular buffer or double buffer. A '1' enables double buffer mode, a '0' enables circular buffer mode. Ox054 DmaOutnStopDes 1 Ox0 Writing a '1' to this register causes the c UDU to clear the HwOwned bits DmaEpnOutDescA and DmaEpnOutDescB if they are set. The UDU first finishes transferring the current packet and then returns ownership of the descriptors to SW. This register is cleared automatically when both descriptors become SW owned. 0x058 DmaOutnTopAdr[ 17 Ox000000 The top address of the EPn OUT buffer 21:5] in DRAM. This is the highest writable address of the buffer. This is only valid when it is a circular buffer. Ox05C DmaOutnBottomA 17 Ox000000 The bottom address of the EPn OUT dr[21:5] buffer in DRAM. This is the lowest writable address of the buffer. This is only valid when it is a circular buffer. Ox060 DmaOutnCurAdrA 22 Ox000000 Descriptor A's current write pointer to the [21:0] EPn OUT buffer in DRAM. This is the next address that will be written to by the UDU. This is a working register. Ox064 DmaOutnMaxAdr 22 Ox000000 The stop address marker for Epn OUT A[21:0] descriptor A. DmaOutnCurAdrA advances after each write until it reaches this address. This is the last address written.
WO 2005/120835 PCT/AU2004/000706 485 0x068 DmaOutnlntAdrA[ 22 0x000000 The interrupt marker for Epn OUT 21:0] descriptor A. When DmaOutnCurAdrA reaches or passes this address, an interrupt is generated. Ox06C DmaEpnOutDesc 3 Ox0 The control register for Epn OUT A descriptor A. Bit 2: HWOwned (a working register) Bit 1 : DescMRU (read only) Bit 0 : StopOnShort Please refer to Section 13.5.3.3 for more detail on HwOwned and DescMru and Section 13.5.4.1 and Section 13.5.4.3 for more detail on StopOnShort. Ox070 DmaOutnCurAdrB 22 Ox000000 Descriptor B's current write pointer to the [21:0] EPn OUT buffer in DRAM. This is the next address that will be written to by the UDU. This is a working register. Ox074 DmaOutnMaxAdr 22 Ox000000 The stop address marker for Epn OUT B[21:0] descriptor B. DmaOutnCurAdrB advances after each write until it reaches this address. This is the last address written. Ox078 DmaOutnIntAdrB[ 22 OxOOO0 The interrupt marker for Epn OUT 21:0] descriptor B. When DmaOutnCurAdrB reaches or passes this address, an interrupt is generated. Ox07C DmaEpnOutDesc 3 Ox2 The control register for Epn OUT B descriptor B. Bit 2 : HWOwned (a working register) Bit 1: DescMRU (read only) Bit 0: StopOnShort Please refer to Section 13.5.3.3 for more detail on HwOwned and DescMru and Section 13.5.4.1 and Section 13.5.4.3 for more detail on StopOnShort. Endpoint 1 OUT (n=1) 0x080 to 12 different addressable registers. OxOAC Identical to Endpoint 0 OUT listing above, with n=1. Endpoint 2 OUT (n=2) OxOBO to 12 different addressable registers. OxODC Identical to Endpoint 0 OUT listing above, with n=-2. Endpoint 4 OUT (n=4) OxOEO to 12 different addressable registers. Ox10C Identical to Endpoint 0 OUT listing above, with n=4. Endpoint 5 OUT (n=5) 0xI10 to 12 different addressable registers. Ox13C Identical to Endpoint 0 OUT listing above, with n=5. Endpoint 7 OUT (n=7) 0x140 to 12 different addressable registers. Ox16C Identical to Endpoint 0 OUT listing above, with n=7.
WO 2005/120835 PCT/AU2004/000706 486 Endpoint 0 IN (n=0) Ox1 70 DmalnnDoubleBuf 1 Ox0 Indicates whether the DRAM buffer associated with Epn IN is a circular buffer or double buffer. A '1' enables double buffer mode, a 0' enables circular buffer mode. Ox1 74 DmalnnStopDesc 1 Ox0 Writing a '1' to this register causes the UDU to clear the HwOwned bits DmaEpn/nDescA and DmaEpnInDescB if they are set. The UDU first finishes transferring the current packet and then returns ownership of the descriptors to SW. This register is cleared automatically when both descriptors become SW owned. Ox1 78 DmalnnTopAdr[21 17 Ox000000 The top address of the EPn IN buffer in :5] DRAM. This is the highest readable address of the buffer. This is only valid when it is a circular buffer. Ox17C DmalnnBottomAdr 17 Ox000000 The bottom address of the EPn IN buffer [21:5] in DRAM. This is the lowest readable address of the buffer. This is only valid when it is a circular buffer. Ox180 DmalnnCurAdrA[2 22 Ox000000 Descriptor A's current read pointer to the 1:0] EPn IN buffer in DRAM. This is the next address that will be read from by the UDU. This is a working register. Ox184 DmalnnMaxAdrA[ 22 Ox000000 The stop address marker for Epn IN 21:0] descriptor A. DmalnnCurAdrA advances after each read until it reaches this address. This is the last address of the buffer which may be read. Ox188 DmalnnintAdrA[21 22 Ox000000 The interrupt marker for Epn IN :0] descriptor A. When DmalnnCurAdrA reaches this address, an interrupt is generated. Ox18C DmaEpninDescA[ 3 Ox0 The control register for Epn IN descriptor 2:0] A. Bit 2: HWOwned (a working register) Bit 1: DescMRU (read only) Bit 0: SendZero Please refer to Section 13.5.3.3 for more detail on HwOwned and DescMru and Section 13.5.4.2 and Section 13.5.4.4 for more detail on SendZero. Ox190 DmalnnCurAdrB[2 22 Ox000000 Descriptor B's current read pointer to the 1:0] EPn IN buffer in DRAM. This is the next address that will be read from by the UDU. This is a working register. Ox194 DmalnnMaxAdrB[ 22 Ox000000 The stop address marker for Epn IN 21:0] descriptor B. DmalnnCurAdrB advances after each read until it reaches this address. This is the last address of the buffer which may be read. Ox198 DmalnnlntAdrB[21 22 Ox000000 The interrupt marker for Epn IN :0] descriptor B. When DmalnnCurAdrB reaches this address. an interrupt is WO 2005/120835 PCT/AU2004/000706 487 generated. Ox19C DmaEpnInDescB[ 3 0x2 The control register for Epn IN descriptor 2:0] B. Bit 2: HWOwned (a working register) Bit 1: DescMRU (read only) Bit 0: SendZero Please refer to Section 13.5.3.3 for more detail on HwOwned and DescMru and Section 13.5.4.2 and Section 13.5.4.4 for more detail on SendZero. Endpoint 1 IN (n=1) 0x1AO to 12 different addressable registers. Ox1CC Identical to Endpoint 0 IN listing above, with n=1. Endpoint 2 IN (n=2) Ox1DO to 12 different addressable registers. Ox1FC Identical to Endpoint 0 IN listing above, with n=2. Endpoint 3 IN (n=3) 0x200 to 12 different addressable registers. Ox22C Identical to Endpoint 0 IN listing above, with n=3. Endpoint 4 IN (n=4) 0x230 to 12 different addressable registers. Ox25C Identical to Endpoint 0 IN listing above, with n=4. Endpoint 5 IN (n=5) 0x260 to 12 different addressable registers. Ox28C Identical to Endpoint 0 IN listing above, with n=5. Endpoint 6 IN (n=6) 0x290 to 12 different addressable registers. Ox2BC Identical to Endpoint 0 IN listing above, with n=6. Interrupts 0x300 IntStatus 31 Ox000000 Interrupt Status register. Bit listings are 00 given in Table 54. Read only. Ox304 to IntStatusEpnOut 6x9 Ox000 Interrupt Status register for Epn OUT, Ox318 where n is 0, 1, 2, 4, 5, 7. Bit listings are given in Table 55. Read only. Ox31 C to IntStatusEpnin 7x5 Ox00 Interrupt Status register for Epn IN, Ox334 where n is 0 to 6. Bit listings are given in Table 56. Read only. Ox340 IntMask 31 Ox000000 Interrupt Mask register. Setting a 00 particular bit to '1' will enable the equivalent bit in the IntStatus interrupt register.
WO 2005/120835 PCT/AU2004/000706 488 0x344 to IntMaskEpnOut 6x9 0x000 Interrupt Mask register for Epn OUT, Ox358 where n is 0, 1, 2, 4, 5, 7. Setting a particular bit to '1' will enable the equivalent bit in the IntStatusEpnOut interrupt register. Ox35C to IntMaskEpnln 7x5 Ox00 Interrupt Mask register for Epn IN, where Ox374 n is 0 to 6. Setting a particular bit to '1' will enable the equivalent bit in the IntStatusEpnIn interrupt register: Ox380 IntClear 18 Ox0000 Interrupt Clear register. Writing a '1' to the relevant bit position will clear the equivalent bit in the IntStatus[1 7:0] interrupt register. This register is cleared automatically, and will therefore always be read as 0x0000. Ox384 to IntClearEpnOut 6x9 Ox000 Interrupt Clear register for EPn OUT, 0x398 where n is 0, 1, 2, 4, 5, 7. Writing a '1' to the relevant bit position will clear the equivalent bit in the intStatusEpnOut interrupt register. This register is cleared automatically, and will therefore always be read as 0x000. Ox39C to IntClearEpnin 7x5 Ox00 Interrupt Clear register for EPn IN, where Ox3B4 n is 0 to 6. Writing a '1' to the relevant bit position will clear the equivalent bit in the IntStatusEpnOut interrupt register. This register is cleared automatically, and will therefore always be read as OxOO. Debug registers (read only) Ox3C0 DmaOutStrmPtr[2 22 Ox000000 The current write pointer to the OUT 1:0] buffers in DRAM. This is the next address that will be written to by the UDU. Read only. Ox3C4 to DmalnnStrmPtr[21 7x22 Ox000000 The current read pointer to the EPn IN Ox3DC :0] buffer in DRAM, where n is 0 to 6. This is the next address that will be read from by the UDU, when in streaming mode. Read only. Ox3EO ControlStates 3 Ox0 Reflects the current state of the control transfers. Read only. Bits 2-0 Control Transfer State Machine 000: Idle 001 : Setup 010: Dataln 011: DataOut 100 : Statusln 101 : StatusOut 110: reserved 111 : reserved 0x3E4 PhyRxState 20 N/A Bit 19 : phy udurxactive Bit 18 : phy.udurxvalid Bit 17 : phy udu_rxvalidh Bits 16-9 : phy udurxdata[7:0J Bits 8-1 : phy udu-rxdatah[7:0] Bit 0 : phy udurx_err WO 2005/120835 PCT/AU2004/000706 489 0x3E8 PhyTxState 19 N/A Bit 18: uduphy fxvalid Bit 17: phyudutxvalidh Bits 16-9 : udu_phy_txdata[7:0] Bits 8-1 : uduLphy txdatah[7:O0 Bit 0: udu-phyxready 0x3EC PhyCtriState 6 N/A Bit 5 : uduphy xer sel Bits 4-3: udu.phy opmode[1:0] Bit 2 : uduphy termsel Bits 1-0 : phygdujinestate[1:0] UDC20 control/status registers (not available in debug mode) 0x400 SetupCmdAdr 16 0x0555 Setup/Command Address used by UDC20. This must be programmed to 0x0555. Ox404 to EpnCfg 12x32 0x000000 Endpoint configuration register. Ox430 00 Bits 31-30: reserved Bits 29-19: Max pkt size Bits18-15 Alternatesetting Bits14-11 Interfacenumber Bits10-7 Configuration-number Bits 6-5 Endpoint type 00 : Control 01 Isochronous 10 : Bulk 11 : Interrupt Bit 4 : Endpointdirection 0 : Out 1: In Bits 3-0 Endpoint number 13.5.2 Local endpoint packet buffering The partitioning of the local endpoint buffers is illustrated in Figure 36. 13.5.3 DMA Controller 5 There are local endpoint buffers available for temporary storage of endpoint data within the UDU. All OUT data packets are transferred from the UDC20 to the local packet buffer, and from there to the endpoint's buffer in DRAM. Conversely, all IN data packets are transferred from a buffer in DRAM to the local packet buffers, and from there to the UDC20. The UDU's DMA controller handles all of this data transfer. The DMA controller can be configured to handle 10 the IN and OUT data transfers in streaming mode or non-streaming mode. However, non-streaming mode is only a valid option for non-control endpoints and only when in high speed mode. Section 13.5.3.1 and Section 13.5.3.2 below describe streaming and non-streaming modes respectively. Each IN or OUT endpoint's buffer in DRAM can be configured to operate as either a circular buffer or a double buffer. Each IN and OUT endpoint has two DMA descriptors, A and B, which are used to set up the 15 DMA pointers and control for endpoint data transfer in and out of DRAM. Only one of the two descriptors is used by the UDU at any given time. While one descriptor is being used by the UDU, the other may be updated by the SW. The HwOwned registers flag whether the HW (UDU) or the SW owns the DMA pointers.
WO 2005/120835 PCT/AU2004/000706 490 Only the owner may modify the DMA descriptors. Section 13.5.3.3 below describes DMA descriptors in more detail. Both bulk and control OUT local packet buffers share the same DIU write port. Packets are written out to DRAM in the same order they arrive into the local packet buffers. The seven IN packet buffers share the same 5 DIU read port. If more than one IN packet buffer needs to be filled, the highest priority is given to Endpoint 0, lowest to Endpoint 6. 13.5.3.1 Streaming Mode In streaming mode the packet is read out from one end of the local packet buffer while being written in to the other. The buffer may not necessarily be large enough to hold an entire packet for high speed IN data. The 10 DRAM access rate must be sufficient to keep up with the USB bus to ensure no buffer over/underruns. If the DRAM arbiter does not provide adequate timeslots to the UDU, the USB packet transmission will be disrupted in streaming mode. For IN data, the UDU will not be able to provide the data fast enough to the UDC20, and the UDC20 inserts a CRC error in the packet. The USB host is expected to retry the IN packet, but unless the DRAM bandwidth allocated to the UDU read port is increased sufficiently, it is likely that the 15 IN packets will continue to fail. For OUT data, the UDU will be unable to empty the local OUT packet buffer quickly enough before the next packet arrives. The UDC20 NAKs the new packet. If the host retries the new OUT packet, it is possible that the local packet buffer will be empty and the OUT packet can be accepted. Therefore, insufficient DRAM bandwidth will not block the OUT data completely, but will slow it down. 13.5.3.2 Non-Streaming Mode 20 Non-streaming mode is used when there isn't enough DRAM bandwidth available to use streaming mode. For bulk OUT data, the packet is transferred into the local 512-byte packet buffer, and like streaming mode, is written out to DRAM as soon as the data arrives in. However, the UDU's flow control (i.e. ACK, NAK, NYET) for OUT transfers differs between streaming and non-streaming modes. See Section 13.5.9.2.2 for more detail. 25 For IN data, the UDU transfers the data if the entire packet is already stored in the local packet buffer. Otherwise the UDU NAKs the request. IN endpoints are only capable of transferring a maximum of 64-byte packets in non-streaming mode. wMaxPktSize in high speed mode is 512 bytes for bulk and may be up to 1024 bytes for interrupt. If a short packet (less than wMaxPktSize) is transferred, then the host assumes it is the end of the transfer. Due to the limited packet size, the data transfers achieved in non-streaming IN mode 30 are a fraction of the theoretical USB bandwidth. 13.5.3.3 DMA Descriptors Each IN and OUT endpoint has two DMA descriptors, A and B. Each DMA descriptor contains a group of configuration registers which are used to setup and control the transfer of the endpoint data to or from DRAM. Each DMA channel uses just one of the two DMA descriptors at any given time. When the DMA 35 descriptor is finished, the UDU transfers ownership of the DMA descriptor to the SW. This may occur when WO 2005/120835 PCT/AU2004/000706 491 the buffer space provided by DMA descriptor A has filled, for example. Each descriptor is owned by either the HW or the SW, as indicated by the HwOwned bit in the DmaEpnOutDescA, DmaEpnOutDescB, DmaEpnInDescA, DmaEpnInDescB registers. The HwOwned registers are considered working registers because both the HW and SW can modify the contents. The SW can set the HwOwned registers, and the HW 5 can clear them. The SW can only modify the DMA descriptor when HwOwned is '0'. The descriptor is used until one of the following conditions occur: * the OUT buffer space in DRAM provided by the descriptor has filled to within wMaxPktSize, i.e. there is less than wMaxPktSize available e the IN buffer in DRAM provided by the descriptor has emptied 10 e the relevant bit in DmaOutnStopDesc or DmaInnStopDesc is set to '1' e a short or zero length packet is received and transferred to an OUT DRAM buffer and StopOnShort is set to 'I' in DmaEpnOutDescA or DmaEpnOutDescB. e the HwOwned bit in the unused descriptor is set to '1', and the DMA channel is in circular buffer mode. 15 e on endpoint 0 IN, a transfer has completed (indicated by StatusOut) A new descriptor is chosen when the current one completes, or when the relevant bit in DmaOutnStopDesc or DmalnnStopDesc is cleared. The UDU chooses which descriptor to use per DMA channel: * If neither descriptor A or descriptor B's HwOwned bit is set, then no descriptor is assigned to the 20 DMA channel. * If just one of the descriptors' HwOwned bit is set, then that descriptor is used for the DMA channel. - If both descriptors' HwOwned bits are set, then the least recently used descriptor is chosen. The UDU keeps track of the most recently used descriptor and provides this status in the DescMru bit in the DmaEpnOutDescA, DmaEpnOutDescB, DmaEpnInDescA, DmaEpnInDescB registers. If 25 DescMru is set to '', it implies that this descriptor is the most recently used. The UDU always updates the endpoint's descriptor A and B DescMru bits at the same time and these values are always complements of each other. They are both updated whenever either descriptor's HwOwned bit is cleared by the UDU. 13.5.4 DRAM buffers 30 The DMA controller supports the use of circular buffers or double buffers for the endpoint DMA channels. The configuration registers DmaOutnDoubleBuf and DmaInnDoubleBuf are used to set each DMA channels individually into either double or circular buffer mode. The modes differ in the UDU behaviour when a new DMA descriptor is made available by software. In circular buffer mode, a new descriptor contains updates to the parameters of the single buffer area being used for a particular endpoint, to be applied immediately by the 35 hardware. In double buffer mode a new descriptor contains the parameters of a new buffer, to be used only when any current buffer is exhausted.
WO 2005/120835 PCT/AU2004/000706 492 Section 13.5.4.1 & Section 13.5.4.2 below describe the operation of circular buffer DMA writes and reads respectively. Section 13.5.4.3 and Section 13.5.4.4 below describe double buffer DMA writes and reads. 13.5.4.1 Circular buffer write operation Each circular buffer is controlled by eight configuration registers: DmaOutnBottomAdr, DmaOutnTopAdr, 5 DmaOutnMaxAdrA, DmaOutnCurAdrA, DmaOutnntAdrA, DmaOutnMaxAdrB, DmaOutnCurAdrB, DmaOutnIntAdrB and an internal register DmaOutStrnPtr. The operation of the circular buffer is shown in Figure 37 below. When an OUT packet is received and begins filling the local endpoint buffer, the DMA controller begins to write out the packet to the endpoint's buffer in DRAM. Figure 37 shows two snapshots of the status of a 10 circular buffer, starting off using descriptor A, and with (b) occurring sometime after (a) and a changeover from descriptor A to B occurring in between (a) and (b). DmaOutnTopAdr marks the highest writable address of the buffer. DmaOutnBottomAdr marks the lowest writable address of the buffer. DmaOutnMaxAdrA marks the last address of the buffer which may be written to by the UDU. DmaOutStrmPtr register always points to the next address the DMA manager will write to 15 and is incremented after each memory access. There is only one DmaOutStrmPtr register, which is loaded at the start of each packet from the DmaOutnCurAdrA/B register of the endpoint to which the packet is directed. DmaOutnCurAdrA acts as a shadow register of DmaOutStrmPtr. The DMA manager will continue filling the free buffer space depicted in (a), advancing the DmaOutStrmPtr after each write to the DIU. When a packet has been successfully received, as indicated by a status write, DmaOutnCurAdrA is updated to 20 DmaOutStrnPtr. If a packet has not been received successfully, the corrupt data is removed from DRAM by keeping DmaOutnCurAdrA at its original position. When DmaOutnCurAdrA reaches or passes the address in DmaOutnntAdrA it generates an interrupt on IntEpnOutAdrA. The DMA manager continues to fill the free buffer space and when it fills the address in DmaOutnTopAdr it wraps around to the address in DmaOutnBottomAdr and continues from there. DMA transfers will continue 25 indefinitely in this fashion until a stop condition occurs. This occurs if - there is less than wMaxPktSize amount of space left in the circular buffer at the end of a successful packet write, i.e. DmaOutnCurAdrA comes to within wMaxPktSize of DmaOutnMaxAdrA. * the relevant bit is set in DmaOutnStopDesc and the UDU is not currently transferring a packet to DRAM. 30 e a short or zero length packet is received and transferred to an OUT DRAM buffer and StopOnShort is set to '1' in DmaEpnOutDescA * the HwOwned bit in the DmaEpnOutDescB register is set to '1' and the UDU is not currently transferring a packet to DRAM. When the descriptor completes, the UDU clears the HwOwned bit in the DmaEpnOutDescA register and 35 generates an interrupt on IntEpnOutHwDoneA. The UDU copies DmaOutnCurAdrA to DmaOutnCurAdrB and chooses another descriptor, as detailed in Section 13.5.3.3. If descriptor B is chosen, the UDU continues WO 2005/120835 PCT/AU2004/000706 493 writing out data to the circular buffer, but using the new DmaOutnCurAdrB, DmaOutnMaxAdrB and DmaOutnlntAdrB registers. DmaOutnCurAdrA and DmaOutnCurAdrB are working registers, and can be updated by both HW and SW. However, it is inadvisable to write to these when a circular buffer is up and running. 5 The DMA addresses DmaOutStrmPtr, DmaOutnCurAdrA, DmaOutnMaxAdrA, DmaOutnIntAdrA, DmaOutnCurAdrB, DmaOutnMaxAdrB and DmaOutnIntAdrB are byte aligned. DmaOutnTopAdr and DmaOutnBottomAdr are 256-bit word aligned. DRAM accesses are 256-bit word aligned and udu_diuwmask[7:0 is used to mask the bytes. Packets are written out to DRAM without any gaps in the DRAM byte addresses, even if some OUT packets are not multiples of 32 bytes. 10 13.5.4.2 Circular buffer read operation DMA reads operate in streaming or non-streaming mode, depending on the configuration register setting in DmaModes. Note that this can only be modified when all descriptors are inactive. In streaming mode, IN data is transferred from DRAM using DMA reads in a similar manner to the DMA writes described in Section 13.5.4.1 above. There are eight configuration registers used per DMA channel: 15 DmalnnBottomAdr, DmaInnTopAdr, DmaInnMaxAdrA, DmaInnCurAdrA, DmaInnIntAdrA, DmaInnMaxAdrB, DmalnnCurAdrB, DmalnnIntAdrB. An internal register DmaInnStrmPtr is also used per DMA channel. DmalnnTopAdr is the highest buffer address which may be read from. DmalnnBottomAdr is the lowest buffer address which may be read from. DmalnnMaxAdrA/B is the last buffer address which may be read from. DmalnnStrmPtr points to the next address to be read from and is incremented after each 20 memory access. In streaming mode, data transfer from DRAM to the endpoint's local packet buffer is initiated when the local buffer is empty. The DMA controller fills the local packet buffer with up to 64 bytes. If the packet size is larger than this, the DMA controller waits until it receives an IN token for that endpoint. The data in the local buffer is streamed out to the UDC20. The DMA controller continues to stream in the data as space becomes 25 available in the local buffer until an entire packet has been written. If descriptor A is initially used, DmalnnCurAdrA is updated to DmaInnStrmPtr when a packet has been successfully transferred over USB, as indicated by a status write. If the packet was not received successfully by the USB host, DmaInnStrnPtr is returned to DmalnnCurAdrA and the data is streamed out again if requested by the host. When DmalnnCurAdrA reaches or passes DmalnnntAdrA, an interrupt is generated on IntEpnnddrA. If the 30 amount of data available is less than wMaxPktSize (as indicated by DmaInnMaxA drA), then the UDU assumes it is a short packet. If DmalnnMaxAdrA was read from, and the last packet was wMaxPktSize and descriptor A's SendZero configuration register is set to '1', then a zero length data packet is sent to the USB host on the next IN request to the endpoint. This indicates to the USB host that there is no more data to send from that endpoint. 35 A DMA descriptor completes at the end of the current packet transfer if any of the following conditions occur: e DmalnnCurAdrA reaches DmalnnMaxAdrA and the final packet has been successfully received by the USB host (including a zero length packet, if necessary) WO 2005/120835 PCT/AU2004/000706 494 e Descriptor B's HwOwned bit is set to '1' * The relevant bit in DmalnnStopDesc is set to '1' e The end of the control transfer is reached, for control endpoint 0 When a DMA descriptor completes the UDU clears descriptor A's HwOwned bit. DmalnnCurAdrA is copied 5 over to DmalnnCurAdrB. The UDU then chooses the next descriptor to use, as detailed in Section 13.5.3.3. Non-streaming mode operates in a similar manner to streaming mode. In non-streaming mode, the DMA controller begins transfer of data from DRAM to the endpoint's local packet buffer when the local buffer is empty. The data transfer continues until wMaxPktSize is transferred, or the local buffer is full, or until DmaInnMaxAdrA or DmaInnMaxdrB is read from. DmalnnStrnPtr is not used and DmaInnCurAdrA or 10 DmalnnCurAdrB points to the next address that will be read from. The full packet remains in the local packet buffer until it has transferred successfully to the USB host, as indicated by a status write. The DMA descriptors are started and stopped in the same manner as for streaming mode, as detailed above. 13.5.4.3 Double buffer write operation A DMA channel can be configured to use a double buffer in DRAM by setting the relevant register 15 DmaOutnDoubleBuf to ''. A double buffer is used to allow the next data transfer to begin at a totally separate area of memory. An OUT endpoint's double buffer uses six configurable address pointers: DmaOutnCurAdrA, DmaOutnMaxAdrA, DmaOutnIntAdrA, DmaOutnCurAdrB, DmaOutnMaxAdrB, DmaOutnIntAdrB. Note that DmaOutnTopAdr and DmaOutnBottomAdr are not used. DmaOutnMaxAdrA/B marks the last writable address 20 of the buffer. DmaOutStrmPtr points to the next address to write to and is incremented after each memory access. If DMA descriptor A is initially used, the data is transferred to the initial address given by DmaOutnCurAdrA. The internal register, DmaOutStrmPtr is used to advance the addresses until a packet has been successfully written out to DRAM, as indicated by a status write. DmaOutnCurAdrA is then updated to the value in 25 DmaOutStrmPtr. If DmaOutnCurAdrA reaches or passes DmaOutnntAdrA, an interrupt is generated on IntEpnOutAdr. The UDU finishes with DMA descriptor A at the end of a successful packet transfer under the following conditions: e if a short or zero length packet is received and descriptor A's StopOnShort is set to '1' 30 e if there is not enough space left in DRAM for another packet of wMaxPktSize. e if DmaOutnStopDesc is set to '1' When descriptor A completes, the HwOwned bit is cleared by the UDU and an interrupt is generated on IntEpnOutHwDoneA. The UDU chooses another descriptor, as detailed in Section 13.5.3.3. If descriptor B is chosen, the UDU begins data transfer to a new buffer given by DmaOutnCurAdrB, DmaOutnMaxAdrB, 35 DmaOutnIntAdrB.
WO 2005/120835 PCT/AU2004/000706 495 13.5.4.4 Double buffer read operation IN data is transferred in streaming or non-streaming mode. An IN endpoint's double buffer uses the following six configurable address pointers: DmalnnCurAdrA, DmalnnMaxAdrA, DmalnnntAdrA, DmalnnCurAdrB, DmalnnMaxAdrB, DmalnnIntAdrB. Note that DmalnnTopAdr and DmalnnBottomAdr are not used. 5 DmaInnMaxAdrA/B marks the last readable address of the buffer. DmaInnStrmPtr points to the next address to read from and is incremented after each memory access. If DMA descriptor A is initially used, the data is transferred to the initial address given by DmalnnCurAdrA. The internal register, DmalnnStrmPtr, is used in streaming mode to advance the addresses until a packet has been successfully received by the USB host, as indicated by a status write. Then DmalnnCurAdrA is updated 10 to the value in DmalnnStrmPtr. In non-streaming mode, DmalnnStrmPtr is not used. If DmalnnCurAdrA reaches or passes DmaInnIntAdrA, an interrupt is generated on IntEpnInAdrA. If DmaInnCurAdrA reaches DmalnnMaxAdrA and the last packet is wMaxPktSize, and the SendZero bit in DmaEpnnDescA is set to '1', the UDU sends a zero length data packet at the next IN request to that endpoint. The UDU finishes with DMA descriptor A at the end of a successful packet transfer under the following 15 conditions: e if DmalnnCurAdrA reaches DmaInnMaxAdrA and the final packet has been successfully received by the USB host (including a zero length packet, if necessary) e if DmalnnStopDesc is set to '1' * if the end of the control transfer is reached, for control endpoint 0 20 When descriptor A completes, the HwOwned bit in DmaEpnInDescA is cleared by the UDU and an interrupt is generated on IntEpnInHwDoneA. The UDU chooses another descriptor, as detailed in Section 13.5.3.3. If descriptor B is chosen, the UDU begins data transfer from a new buffer given by DmaOutnCurAdrB, DmaOutnMaxAdrB, DmaOutnntAdrB. 13.5.5 Endpoint Data Transfers 25 13.5.5.1 Endpoint 0 IN Transfers Control-In transfers consist of 3 stages: setup, data & status. An EPO IN transfer starts off with a write of 8 bytes of setup data to the local EPO OUT packet buffer, and from there to DRAM. The UDU interrupts the CPU with IntSetupWr. In addition, an interrupt may be generated on one of the DMA descriptors, IntEp00utAdrA/B, if DmaOut0IntAdrA/B address is reached or 30 passed. If the setup data cannot be written out to DRAM because there is no valid DMA descriptor, IntSetupWrErr is asserted instead of IntSetupWr. The setup packet will remain in the local buffer until the CPU sets up a valid DMA descriptor to enable the UDU to transfer the data out to DRAM.
WO 2005/120835 PCT/AU2004/000706 496 The setup command may be GetDescriptor(configuration), for example. The SW must interpret this setup command and set up a DMA descriptor to point to the location of the USB descriptors in DRAM. The UDU then transfers the data into the local EPO IN packet buffer. The Data stage of the control transfer occurs when the USB descriptors are read from the local packet buffer 5 out to the USB bus. There may be more than one data transaction during the Data stage. If the data is unavailable, the UDU issues a NAK to the USB host. The host is expected to retry and continue to send IN tokens to this endpoint. In response, the UDU continues to NAK until the packet is loaded into the local buffer. The third stage of the transfer is the Status stage, when the device indicates to the host whether the transfer 10 was successful or not. When the host issues a StatusOut request, an interrupt is generated on either IntStatusOut or IntNzStatusOut. Which interrupt is triggered depends on whether a zero or non zero data field is received with the StatusOut. The UDU responds to this with an ACK, NAK or STALL, depending on the value programmed into StatusOutResponse configuration register. If the Status transaction has completed successfully, as indicated by a status write, the StatusOutResponse register is cleared. 15 13.5.5.2 Endpoint 0 OUT Transfers An EPO OUT transfer consists of 2 or 3 stages: Setup, Data (may or may not be present), Status. The transfer starts with a write of 8 bytes of setup data to the local EPO OUT packet buffer, and from there to DRAM. The UDU interrupts the CPU with IntSetupWr. In addition, an interrupt may be generated on one of the DMA descriptors, IntEp00utAdrA/B, if DmaOutOIntAdrA/B address is reached. If the setup data cannot be 20 written out to DRAM because there is no valid DMA descriptor, IntSetupWrErr is asserted instead of IntSetupWr. The setup packet will remain in the local buffer until the CPU sets up a valid DMA descriptor to enable the UDU to transfer the data out to DRAM. The setup command may be SetDescriptor, for example. The next stage of the transfer is the Data stage, which consists of zero or more OUT transactions. The number 25 of bytes transferred is defined in the Setup stage. At the start of the data transaction, the data is written to the local packet buffer, and from there to DRAM. One or more interrupts may be generated on one of the DMA descriptors: e IntEp00utAdrA/B, if DmaOut0Int AdrA/B address is reached e IntEp00utPktWrA/B if the packet is successfully written to DRAM 30 e IntEp00utShortWrA/B, if a short packet is successfully written to DRAM or a zero length packet is received If there is insufficient buffer space available (either local packet buffer or DRAM buffer) the UDU does not accept the OUT packet and responds with a NAK. In some cases the UDU NYETs the packet, as described in Section 13.5.9.1.2. 35 The next stage of the transfer is the Status stage, when the device reports the status of the control transfer to the host. When a StatusIn request is received, an interrupt is generated on IntStatusIn. The UDU's response to WO 2005/120835 PCT/AU2004/000706 497 the host depends on the value programmed in the StatusInReponse status register. The response may be a NAK, ACK (a zero length data packet) or STALL. If the Status transaction has completed successfully, as indicated by a status write, the StatusInResponse register is cleared. 13.5.5.3 Bulk OUT Transfers 5 There are five bulk OUT endpoints in the JDU. At full speed, wMaxPktSize can be 8, 16, 32 or 64 bytes, as programmed in the configuration register FsEpSize. At high speed, wMaxPktSize is 512 bytes. The endpoint data is transferred into the local packet buffer, and from there it is written out to DRAM. An interrupt is generated on IntEpnOutPktWrA/B when a packet has been written out to DRAM. If the packet is shorter than wMaxPktSize, IntEpnOutShortWrA/B is also asserted. In addition, an interrupt may be generated 10 on IntEpnOutAdrA/B if the address DmaOutnIntAdrA/B is reached or passed. If there is insufficient buffer space available (either local packet buffer or DRAM buffer) the UDU does not accept the OUT packet and responds with a NAK. In some cases the UDU NYETs the packet, as described in Section 13.5.9.2.2. If the endpoint is stalled, due to the EpStall bit being set, the UDU does not accept the OUT packet and 15 responds with a STALL. 13.5.5.4 Bulk IN Transfers There are four bulk IN endpoints available in the UDU. At full speed, wMaxPktSize can be 8, 16, 32 or 64 bytes, as programmed in the configuration register FsEpSize. At high speed, wMaxPktSize is 512 bytes. Each bulk IN endpoint has a dedicated 64-byte local packet buffer. When data is requested from an endpoint, 20 it is expected that the 64-byte packet buffer has already been filled with data from DRAM. In streaming mode, as this data is read out, more data is written in from DRAM until wMaxPktSize has been retrieved. In non-streaming mode, the entire packet is first written into the local packet buffer, and is then sent out onto the USB bus. The maximum packet size in non-streaming mode is limited to 64 bytes due to the size of the local packet 25 buffer. However, in non-streaming mode, the UDU is operating at high speed, and wMaxPktSize is 512 bytes. When the host receives a packet shorter than wMaxPktSize, it assumes there is no more data available for that transfer. The host may start a new transfer, and retrieve any remaining data, 64 bytes at a time. If the data is unavailable (if the local packet buffer does not contain either a full packet or the first 64 bytes of a packet), the UDU issues a NAK to the USB host. 30 If the endpoint is stalled, due to the EpStall bit being set, the UDU responds with a STALL to the IN token. 13.5.5.5 Interrupt IN Transfers There are two interrupt IN endpoints available in the UDU. Each endpoint has a configurable wMaxPktSize of 0 to 1024 bytes.
WO 2005/120835 PCT/AU2004/000706 498 Each interrupt IN endpoint has a dedicated 64-byte local packet buffer. When data is requested from an endpoint, it is expected that the 64-byte packet buffer has already been filled with data from DRAM. In streaming mode, as this data is read out, more data is written in from DRAM until wMaxPktSize has been retrieved. In non-streaming mode, the entire packet is first written into the local packet buffer, and is then sent 5 out onto the USB bus. The maximum packet size in non-streaming mode is limited to 64 bytes due to the size of the local packet buffer. However, wMaxPktSize may be up to 1024 bytes. If the host receives a packet shorter than wMaxPktSize, it assumes there is no more data available for that transfer. The host may start a new transfer, and retrieve any remaining data, 64 bytes at a time. 10 If the data is unavailable (if the local packet buffer does not contain either a full packet or the first 64 bytes of a packet), the UDU issues a NAK to the USB host. If the endpoint is stalled, due to the EpStall bit being set, the UDU responds with a STALL to the IN token. 13.5.6 Interrupts Table 54, Table 55 and Table 56 below list the interrupts and their bit positions in the IntStatus, 15 IntStatusEpnOut and IntStatusEpnIn configuration registers respectively. Table 54. IntStatus interrupts B1it number interrupt Nm ecito 0 IntSuspend This interrupt triggers when the USB bus goes into suspend ______________ state. 1 IntResume This interrupt occurs when bus activity is detected during ___________suspend state. 2 IntReset This interrupt occurs when a reset is detected on USB bus. 3 IntEnumOn This is asserted when device starts being enumerated by external host. 4 IntEnumOff This is asserted when device finishes being enumerated by external host. 5 IntSof This interrupt triggers when Start of (micro)frame packet is received. 6 IntSetCsrsCfg This indicates that a control command SetConfiguration was issued and that the CSR registers should be updated accordingly. The UDU responds to Status requests with NAKs until the CsrsDone register is set high. 7 lntSetCsrslntf This indicates that a control command SetInterface was issued and that the CSR registers should be updated accordingly. The UDU responds to Status requests with NAKs until the CsrsDone register is set high. 8 lntSetupWr This interrupt occurs when 8 bytes of setup command has been written to EPO OUT DMA buffer. 9 IntSetupWrErr This occurs if the UDU is unable to transfer a setup packet from a local buffer to DRAM, due to the DMA channel being disabled or due to a lack of space.
WO 2005/120835 PCT/AU2004/000706 499 10 IntStatusin This interrupt is generated when a Status-In request is received at the end of a Control-Out transfer. 11 IntStatusOut This interrupt is generated when a Status-Out request is received at the end of a Control-in transfer and a zero length data packet is received. 12 IntNzStatusOut This interrupt is generated when a Status-Out request is received at the end of a Control-In transfer and a non zero length data packet is received. 13 IntErraticErr This indicates that either of the PHY signals phyrxvalid and phy.rxactive are asserted for 2 ms due to a PHY error. UDC20 goes into Suspend State. 14 IntEarlySuspend This indicates that the USB bus has been idle for 3 ms. 15 IntVbusTransition This indicates that the input pin gpioudu_vbus_status has changed state from '0' to '1' or vice versa. The configuration register VbusStatus contains the present value of this signal. 16 IntBufOverrun In streaming mode, an OUT packet was received but the local control or bulk packet buffer was not empty, which caused a NAK on the endpoint. 17 IntBufUnderrun In streaming mode, one of the IN local packet buffers has emptied in the middle of a packet, which caused a CRC error to be inserted in the packet. 23-18 IntEpnOut An interrupt has occurred on one of the interrupts in /ntStatusEpnOut status register. Bits 23 downto 18 correspond to n = 7, 5,4,2,1, 0. 30-24 IntEpnin An interrupt has occurred on one of the interrupts in IntStatusEpn/n status register. Bits 30 downto 24 correspond to n = 6 downto 0. 31 reserved Table 55. IntStatusEpnOut interrupts, where n Is 0, 1, 2, 4, 5, 7 0 intEpnOutHwDone This interrupt is triggered when the HW is finished with DMA A Descriptor A on Epn OUT. 1 IntEpnOutAdrA Triggers when EPn OUT DMA buffer address pointer, DmaOutnCurAdrA, reaches or passes the pre-specified address, DmaOutn/ntAdrA. 2 lntEpnOutPktWrA This interrupt is generated when an Epn OUT packet has been successfully written out to DRAM, using DMA Descriptor A. 3 IntEpnOutShortWr This interrupt is generated when a short Epn OUT packet is A successfully written to DRAM or when a zero length packet has been received for Epn, using DMA Descriptor A. This indicates the end of an OUT IRP transfer. 4 IntEpnOutHwDone This interrupt is triggered when the HW is finished with DMA B Descriptor B on Epn OUT. 5 IntEpnOutAdrB Triggers when EPn OUT DMA buffer address pointer, DmaOutnCurAdrB, reaches or passes the pre-specified address, DmaOutnntAdrB. 6 lntEpnOutPktWrB This interrupt is generated when an Epn OUT packet has been successfully written out to DRAM, using DMA Descriptor B.
WO 2005/120835 PCT/AU2004/000706 500 7 lntEpnOutShortWr This interrupt is generated when a short Epn OUT packet is B successfully written to DRAM or when a zero length packet has been received for Epn, using DMA Descriptor B. This indicates the end of an OUT IRP transfer. 8 IntEpnOutNak This interrupt indicates that an OUT packet was NAK'd for endpoint n because there was no valid DMA Descriptor. 31-9 reserved Table 56. IntStatusEpnin interrupts, where n is 0 to 6 Wmlnu A rece the re-pcfe adress, M Bit number Interrupt Name Description 0 lntEpnInHwDoneA This interrupt is triggered when the HW is finished with DMA Descriptor A on Epn IN. 1 IntEpnInAdrA Triggers when EPn IN DMA buffer address pointer, DmalnnCurAdrA, reaches the pre-specified address, DmalnnntAdrA. 2 IntEpnInHwDoneB This interrupt is triggered when the HW is finished with DMA Descriptor B on Epn IN. 3 intEpninAdrB Triggers when EPn IN DMA buffer address pointer, DmalnnCurAdrB, reaches the pre-specified address, Dmalnnint~drB. 4 lntEpnInNak This interrupt indicates that an IN packet was NAK'd for endpoint n because there was no valid DMA Descriptor. 31-5 reserved There are two levels of interrupts in the UDU. IntStatus is at the higher level and IntStatusEpnOut and IntStatusEpnIn are at the lower level. Each interrupt can be individually enabled/disabled by setting/clearing 5 the equivalent bit in the IntMask, IntMaskEpnOut and IntMaskEpnIn configuration registers. Note that the lower level interrupts must be enabled both at the lower level and the higher level. The interrupt may be cleared by writing a '1' to the equivalent bit position in the IntClear, IntClearEpnOut or IntClearEpnIn register. However, a lower level interrupt may not be cleared by writing a '1' to IntClear. IntClear can only be used to clear IntStatus[17:0]. IntClearEpnOut and IntClearEpnln are used to clear the lower level 10 interrupts. The pseudocode below describes the interrupt operation. // Sequential Section // Clear the high level interrupt if a '1' is written to equivalent bit in IntClear if ConfigWrIntClear == 1 then 15 for n in 0 to HighInts-1 loop if cpudata[n] == 1 then IntStatus[n] = 0 end if end for 20 end if // Clear the low level interrupt if a '1' is written to equivalent bit in // IntClearEpnOut or IntClearEpnIn for n in 1 to MaxOutEps-1 loop if ConfigWrIntClearEpnOut == 1 then WO 2005/120835 PCT/AU2004/000706 501 for i in 0 to LowOutInts-l loop if cpudata[i == 1 then IntStatusEpnOut~i] = 0 end if 5 end for end if end for for n in 1 to MaxInEps-l loop if ConfigWrIntClearEpnIn == 1 then 10 for i in 0 to LowInInts-l loop if cpu-data[i] == 1 then IntStatusEpnIn[i] = 0 end if end for 15 end if end for // The setting of a new interrupt has priority over clearing the interrupt for n in 0 to HighInts-l loop if IntHighEvent[n] == 1 then // IntHighEvent may only occur for 1 clk 20 cycle, IntStatus~n] = 1 end if end for for n in 0 to MaxOutEps-1 loop 25 for i in 0 to LowOutInts-1 loop if IntEpnOutEvent[i] == 1 then IntEpnOutStatus[i] = 1 end if end for 30 end for for n in 0 to MaxInEps-l loop for i in 0 to LowInInts-l loop if IntEpnInEvent(il == 1 then IntEpnInStatus[i] = 1 35 end if end for end for // store the interrupt irqdl = irq 40 // Combinatorial section // OR the result of bitwise AND of IntMask/IntStatus, IntEpnOutMask/IntEpnInStatus, // IntEpnInMask/IntEpnInStatus for n in 0 to MaxOutEps-1 loop 45 IntEpnOut = 0 for i in 0 to LowOutInts-l loop IntEpnOut = (IntEpnOutMask[i] & IntEpnOutStatus[i]) OR IntEpnOut end for end for 50 for n in 0 to MaxInEps-1 loop IntEpnIn = 0 for i in 0 to LowInInts-l loop IntEpnIn = (IntEpnInMask[i] & IntEpnInStatus[i]) OR IntEpnIn end for 55 end for irq = 0 for n in 0 to HighInts-l loop WO 2005/120835 PCT/AU2004/000706 502 irq = (IntMask[n] & IntStatus(n]) OR irq end for for n in 0 to MaxOutEps-1 loop irq = irq OR IntEpnOut 5 end for for n in 0 to MaxInEps-1 loop irq = irq OR IntEpnIn end for // The ICU expects to receive an edge detected interrupt 10 uduicu-irq = irq AND ! (irqodl) 13.5.7Standard USB commands Table 57 below lists the USB commands supported. Table 57. Setup commands supported Standard Device Requests CLEARFEATURE OUT Taken care of by UDC20, not seen by the application GETCONFIGU RATION IN Taken care of by UDC20, not seen by the application GETDESCRIPTOR IN Passed to the application via the Endpoint 0 OUT buffer GETINTERFACE IN Taken care of by UDC20, not seen by the application GETSTATUS IN Taken care of by UDC20, not seen by the application SETADDRESS OUT Taken care of by UDC20, not seen by the application SETCONFIGURATION OUT Passed to the application via an interrupt which must be acknowledged (/ntSetCsrsCfg). SETDESCRIPTOR OUT Passed to the application via the Endpoint 0 OUT buffer SETFEATURE OUT Taken care of by UDC20, not seen by the application SETINTERFACE OUT Passed to the application via an interrupt which must be acknowledged (/ntSetCsrs/nt). SYNCHFRAME OUT This request is not supported. The UDU will respond to this request with a STALL for each Endpoint, since there are no Isochronous Endpoints. This request will not be seen by the application. Non standard Device Requests Class/vendor commands IN/OUT Passed to the application via the Endpoint 0 1 OUT buffer When a command is taken care of by UDC20, there is no indication of this request to the rest of the UDU, 15 except USB reset, USB suspend, connection/enumeration as high speed or full speed, SetConfiguration and WO 2005/120835 PCT/AU2004/000706 503 SetInterface. USB reset and USB suspend are described in Section 13.5.13 and Section 13.5.14 respectively. The bus enumeration is described in Section 13.5.17. The SetConfiguration/Setinterface commands are described in Section 13.5.19. When a control Setup command is not passed on to the application for processing, then neither are the Data or 5 Status stages. 13.5.8UDC20 top level 1/0 Table 58 below lists the top level pinout of the UDC20 Table 58. UDC20 I/O Clocks and Resets app-clk 1 In Application clock. Must be >= 48MHz to operate at high speed. Connected to pclk, 192MHz. rst-appclk 1 In Application reset signal. Synchronous to app-clk. Active high. physclk 1 In 30MHz clock for UTMI interface, generated in PHY. This is asynchronous to app clk (pclk). rsLphyclk 1 In Reset in phy_clk domain from CPR block. Synchronous to physclk. Active high. UTMI transmit signals phyjtxready 1 In An acknowledgement from the PHY of data transfer from UDU. udc20_txvalid 1 Out Indicates to the PHY that data data io[7:0] is valid for transfer. udc20_txvalidh 1 Out Indicates to the PHY that data data io[15:8] is valid for transfer. data io[1 5:0] 16 Out Data to be transmitted to the USB bus. UTMI receive signals phy.rxvalid 1 In Indicates that there is valid data on the dataui[7:0] bus. phyjrxvalidh 1 In Indicates that there is valid data on the dataji[15:8J bus. phy.rxactive 1 In Indicates that the PHY's receive state machine has detected SYNC and is active. phy.rxerr 1 In Indicates that a receive error has been detected. Active high. data-i [15:0] 16 In Data received from the USB bus. UTMI control signals udc20_xver_sel 1 Out Transceiver select 0: HS transceiver enabled 1: FS transceiver enabled WO 2005/120835 PCT/AU2004/000706 504 udc20_phymode[1:0] 2 Out Select between operational modes 00: Normal operation 01: Non-driving 10: Disables bit stuffing & NRZI coding 11: reserved phyjline-state[1:0] 2 In The current state of the D+ D- receivers 00: SEO 01: J State 10: K State 11: SE1 udc20_opmode[1:0] 2 Out Select between LS, FS & HS termination. 00: HS termination enabled 01: FS termination enabled 10: FS termination enabled 11: LS termination enabled VCI Master Interface udc20_cmdvalid 1 Out This indicates that the VCI command is valid. udc20_addr[15:0] 16 Out The address pointer for the current data transfer. udc20_data[31:0] 32 Out The write data for the transaction. udc20_ben[3:0] 4 Out The byte enable for udc20_data[31:0]. udc20_rnw 1 Out Indicates whether the current transaction is a read or write. If the signal is high, the transaction is a read. If the signal is low, the transaction is a write. udc20_burst 1 Out Indicates that the current transaction is a burst transaction. app.ack 1 In Acknowledge from the application. app-err 1 In Issued by the application instead of app-ack to indicate various responses depending on the transaction, e.g. to indicate that the data cannot be accepted yet. app.abort 1 In Issued by the application instead of app-ack to abort the transfer. app-data[31:0] 1 In Read data for the transaction. app-databen[3:0] 1 In The byte enable for app.data[31:0]. VCI Slave Interface app-csrcmdvalid 1 In This indicates that the VCI command is valid. app-csraddr[15:0] 16 In The address pointer for the current data transfer. app-csrdata[31:0] 32 In The write data for the transaction. app-csrrnw 1 In Indicates whether the current transaction is a read or write. If the signal is high, the transaction is a read. If the signal is low, the transaction is a write. app-csrburst 1 In Indicates that the current transaction is a burst transaction. This must always be kept low. udc20_csrack 1 Out Acknowledge from the udc20. udc20_csrerr 1 Out This indicates an error due to app.csrburst being set high. udc20_csrabort 1 Out This is never asserted.
WO 2005/120835 PCT/AU2004/000706 505 udc20_csrdata[31:0] 32 Out Read data for the transaction. EEPROM Interface (not used) udc20_eepdi 1 Out The data signal input to the EEPROM. udc20_eepsk 1 Out Low speed clock to EEPROM. udc20_eepcs 1 Out Chip select to enable the EEPROM. eep-do 1 In The data from EEPROM. Strap signals app-phy_8bit 1 In The data width of the UTMI interface. app-ram-if 1 In Incremental address support. app-setdesc sup 1 In Set Descriptor command support. appsynccmd-sup 1 In Synch Frame command support. app-csrprgsup 1 In Dynamic CSR update support. app-devrmtwkup 1 In Device Remote Wakeup capable. app-selfpwr 1 In Self-power capable device. app-expspeed[1:0] 2 In Expected USB speed. app-utmi-dir 1 In Selects either unidirectional or bidirectional UTMI data bus interface. app-nz-lenpktstall 1 In Response of application to non zero length packet during StatusOut phase of control transfer. app-nzlen_pkt stall 1 In Response of application to non zero length packet during _all StatusOut phase of control transfer. app-stall-cir-epOhal 1 In Respond to a ClearFeature(Halt, EPO) with a STALL. t hstimeout-calib[2:0] 3 In High speed timeout calibration fstimeout_calib[2:0] 3 In Full speed timeout calibration app-enable erratice 1 In Enable erratic error. rr app-dev-discon 1 In Device disconnect. Sideband signals udc20_cfg[3:0] 4 Out Current Configuration the UDC20 is running. udc20_intf[3:0] 4 Out The current interface that is being switched to an alternate setting. udc20_altintf[3:0] 4 Out The current alternate interface number to change to. udc20_hst-setcfg 1 Out Signal for sampling udc20_cfg. udc20_hst-setintf 1 Out Signal for sampling udc2Ointf and udc20_altintf. udc20-setup 1 Out Indicates that the current VCI master transaction is a setup write. udc20_seLcsrs 1 Out Indicates that the SetConfiguration/SetInterface command was issued. Programmable Control signals WO 2005/120835 PCT/AU2004/000706 506 app-resume 1 In Resume signal from the application. app-stall 1 In Signal from application to stall the current endpoint. app-done-csrs 1 In Signal from application to ACK the current SetConfiguration/SetInterface command. Event Notification signals udc20_early-suspen 1 Out Indicates that the USB bus has been idle for 3 ms. d udc20_suspend 1 Out Indicates that the host has issued a Suspend command. udc20_usbreset 1 Out Indicates that the host has issued a Reset command. udc20_sof 1 Out Start of Frame. udc20jimestamp[1 0: 11 Out The SOF frame number. 0] udc20_enumon 1 Out Device is being enumerated. udc20_enumspeed[ 2 Out Indicates the speed the device is running at. 1:0] udc20_erraticerr 1 Out Indicates that phyxactive and phy rxvalid are continuously asserted for 2ms due to a PHY error. 13.5.9 VCI master interface All of the endpoint data flow through the UDU occurs over the JDC20 VCI master interface. The OUT & SETUP endpoint packet transfers occur as writes, followed later by a status write. The IN endpoint packet 5 transfers occur as reads, followed later by a status write. Table 59 below describes how the VCI addresses are decoded. Table 59. VCI master port addresses Control type transactions 0x0000 write Status 0x0004 write Ping 0x0555 read/write Setup/Cmd (i.e. endpoint 0) Endpoint data transactions Oxnnnn read/write Bits 15-12: Configuration[3:0] Bits 11-8 : Interface[3:0] Bits 7-4 : Alternate Interface[3:0] Bits 3-0: Endpoint[3:0] (except EPO) A status write indicates whether the SETUP, IN or OUT packet was transmitted and received successfully. It indicates the response received from the host after sending an IN packet (an ACK or timeout). It indicates WO 2005/120835 PCT/AU2004/000706 507 whether a SETUP/OUT packet was received without CRC, bitstuff, protocol errors etc. Table 60 describes how the data bits of the status write is decoded. Table 60. Status write data 3:0 Endpoint number which the status is addressing 7:4 Data PID received in the previous out data packet. This is not relevant to this device, as it is only useful for isochronous transfers. 29:8 Reserved 30 Setup transfer bit. If this bit is set to '1', it indicates the current data transfer is a Setup transfer. 31 Successful transfer status bit. If this bit is set to '1', it indicates a successful transaction. If set to '0', it indicates an unsuccessful transaction, which may be due to a NAK, STALL, timeout, CRC error, etc. 13.5.9.1 Control Transfers 5 Control transfers consist of Setup, Data and Status stages. These stages are tracked by the Control Transfer State Machine with states: Idle, Setup, Dataln, DataOut, StatusIn, StatusOut. The output signal from the UDC20 udc20_setup indicates that the current transaction on the VCI bus is a Setup transaction. The next transaction (Data) is either a read or write, depending on whether the transaction is Control-In or a Control Out. The final transaction (Status) always involves a change of direction of data flow from the Data stage. If a 10 new control transfer is started before the current one has completed, i.e. a new Setup command is received, the current transfer is aborted. But new transfers to other endpoints may occur before the control transfer has completed. Table 61 below describes the formats of control transfers. Table 61. Stages of Control Transfers -- M ,,, ~ e - -. T ~ ~Machine~ A Control In transfer Host Host Device Setup SETUP 8 bytes of setup data ACK/None Host Device Host DataIn IN Control-In ACK/None data/NAK/STALL/none Host Host Device StatusOut WO 2005/120835 PCT/AU2004/000706 508 OUT Zero length data/Variable length ACK/STALLNAK/non data e A Control Out transfer Host Host Device Setup SETUP 8 bytes of setup data ACK/None Host Host Device DataOut OUT Control-Out data ACK/STALL/NAK/non e Host Device Host StatusIn IN Zero length ACK/none data/NAK/STALUnone Figure 38 below gives an overview of the control transfer state machine. The current state is given in the configuration register ControlState. 13.5.9.1.1 Control IN Transfers 5 A control IN transfer is initiated when 8 bytes of Setup data are written out to the SetupCmd address 0x0555 on the VCI master port. An exception to this is when the command is taken care of by the UDC20, as described in Table 57. These 8 bytes of Setup data are written into the local packet buffer designated for EPO OUT packets. Note that the Setup data must be accepted by the UDU, and a NAK or STALL is not a legal response. 10 The setup data is written out to the EPO OUT circular buffer in DRAM. The next transaction on the VCI port is a status write. If udc20 data[31] = '1' this indicates a successful transaction and the DMA pointers are updated and IntEp00utAdrA/B interrupt may be generated. If udc20_data[30] = '1', this indicates that the current data transaction is 8 bytes of setup data, as opposed to Control-Out data. 15 An interrupt is generated on IntSetupWr once the 8 bytes of setup data have been written out to DRAM. If there isn't a valid DMA descriptor, the setup data cannot be written out to DRAM, and an interrupt is generated on IntSetupWrErr. The setup data remains in the local packet buffer until a valid DMA descriptor is provided. Figure 39 below shows a Setup write. 20 The next stage of a Control-In transfer is the Data stage, where data is transferred out to the USB host. The data should already have been loaded into the local EPO IN packet buffer. The transfer is initiated when the VCI master port starts a read transfer on SetupCmd address 0x0555. - If the local packet buffer contains a full packet of bMaxPktSizeO, the data is read out on to the VCI bus and appack is asserted as each word is read. 25 - If there is a short packet, the UDU completes the transfer by asserting apperr on the last read. Or if the last read contains less than 4 bytes, the relevant byte enables are kept low, and appack is WO 2005/120835 PCT/AU2004/000706 509 asserted as usual. The UDU assumes there is a short packet if there is no more data available in DRAM, i.e. DmaInOMaxAdrA/B has been reached. - If the local packet buffer is empty and there is no data available in DRAM, and the last packet sent from the endpoint was bMaxPktSize0, and the current DMA descriptor's SendZero register is set to 5 '1', then a zero length data packet is sent by asserting apperr instead of appack. This indicates to the USB host the end of the transfer. - If the local packet buffer is empty and there is no valid DMA descriptor available, then the UDU issues a NAK and generates an interrupt on IntEpOlnNak. - If the endpoint's packet buffer does not contain a complete packet but there is data available in 10 DRAM, the UDU responds with a NAK by delaying appack by one cycle during the first read. An interrupt is generated on IntEp0InNak. Figure 40 below shows the VCI transactions during this stage. At the end of the Data stage, a status write will be issued by the UDC20 to indicate whether the transaction was successful. If the transaction was not successful, the IN data is kept in the local buffer and the USB host 15 is expected to retry the transaction. If the transaction was successful, the IN data is flushed from the local buffer. There may be more than one data transaction in the Data stage, if the amount of data to be sent is greater than bMaxPktSizeO. Any extra data packets are transferred in a similar manner to the one described above. The third stage is the Status stage, when the USB host sends an OUT token to the device. The UDC20 does a 20 VCI write cycle on SetupCmd address 0x0555. If the host sends a zero length data packet, the byte enables will all be zero and an interrupt is generated on IntStatusOut. The UDU's response to this status request depends on the configuration register StatusOutResponse. If "01" has been written to this register, the UDU will ACK the status transfer, by asserting appack. If "10" has been written to this register, the UDU respond to the Status request with a STALL, by asserting appstall. If the configuration register StatusOutResponse 25 has not yet been written to, its contents will contain "00", and the UDU will respond to the Status request with a NAK, by delaying the appack response to the write cycle. If the host sends a non zero length data packet, the interrupt IntNzStatusOut will be generated. The UDU's response to this depends on how the configuration register StatusOutResponse is programmed, which is described in Table 53. There are four options: 30 a. the response is a NAK and the data (if present) is discarded b. the response is an ACK and the data (if present) is discarded c. the response is an ACK and the data (if present) is transferred to local packet buffer d. the response is a STALL and the data (if present) is discarded If non zero length StatusOut data has been received into the local packet buffer, this data is transferred to 35 EPO's OUT buffer in DRAM.
WO 2005/120835 PCT/AU2004/000706 510 At the end of the Status stage, a status write is issued by the UDC20 to indicate whether the transfer was successful. If the transfer was successful, the configuration register StatusOutResponse is cleared by the UDU. If data was received during the StatusOut stage, it is transferred to EPO OUT's buffer in DRAM. One or more interrupt may be generated on IntEp00utPktWrA/B, IntEp00utShortWrA/B, IntEp00utAdrA/B. 5 Figure 41 below shows the normal operation of the Status stage. 13.5.9.1.2 Control OUT Transfers A Control-Out transfer begins when 8 bytes of Setup data are written out to the SetupCmd address 0x0555. The behaviour at the Setup stage is exactly the same for Control-Out transactions as for Control-In, described in Section 13.5.9.1.1 above. 10 During the Data stage, writes are initiated on the VCI master port to the SetupCmd address 0x0555. The PING protocol must be adhered to in high speed. The following describes the different scenarios: e Full speed (streaming mode only) - If the local packet buffer is empty and there is at least enough space in DRAM for a bMaxPktSizeO packet, then the UDU accepts the data. The UDU ACKs the transfer by 15 asserting appack. - If there is no valid DMA descriptor for the endpoint, the UDU responds with a NAK by asserting apperr. An interrupt is generated on IntEpO0utNak. - If the local packet buffer is not empty, the UDU responds with a NAK by asserting apperr instead of app__ack for the first write. An interrupt is generated on IntBufOverrun. 20 - High speed (streaming and non-streaming modes) - If the local packet buffer is empty and there is at least enough space in DRAM for two bMaxPktSize0 packets, then the UDU accepts the data. The UDU ACKs the transfer by asserting appack. - If the local packet buffer is empty and there is at least enough space in DRAM for one 25 bMaxPktSizeO packet, then the UDU accepts the data and NYETs the transfer by delaying appack by one cycle on the first write. - If there is no valid DMA descriptor, the UDU responds with a NAK by asserting app_.err. An interrupt is generated on IntEpO0utNak. - In streaming mode, if the local packet buffer is not empty, and there is a valid DMA 30 descriptor, the UDU responds with a NAK by asserting apperr instead of appack for the next write. An interrupt is generated on IntBufOverrun. - In non-streaming mode, if the local packet buffer is not empty, and there is a valid DMA descriptor, the UDU responds with a NAK by asserting apperr instead of appack for the first write. An interrupt is generated on IntEp00utNak. 35 0 PING tokens (high speed only, streaming and non-streaming modes) WO 2005/120835 PCT/AU2004/000706 511 - If the local packet buffer is empty and there is at least enough space in DRAM for one bMaxPktSize0 packet, the UJDU responds with an ACK by asserting appack. - If there is no valid DMA descriptor for the endpoint, the UDU responds with a NAK by asserting apperr. An interrupt is generated on IntEp00utNak. 5 - In streaming mode, if the local packet buffer is not empty, the UDU responds with a NAK by asserting apperr. An interrupt is generated on IntBufOverrun. - In non-streaming mode, if the local packet buffer is not empty, the UDU responds with a NAK by asserting apperr. An interrupt is generated on IntEpO0utNak. A status write indicates whether the transfer was successful or not. If the transfer was successful, 10 an interrupt is generated on IntEp00utPktWrA/B. If it was a short or zero length packet, an interrupt is also generated on IntEp00utShortWrA/B. The DMA controller updates its address pointer, DmaOutOCurAdrA/B, and may generate an interrupt on IntEpOOutAdrA/B. If the transfer was unsuccessful, the DMA controller rewinds DmaOutStrmPtr and discards any remaining data in the local packet buffer. 15 There may be zero or more data transactions during the Data stage of a Control-Out transfer. Figure 42 below shows a typical Data stage of a Control-Out transfer in high speed. The Status stage of a Control-Out transfer occurs when the USB host sends an IN token to the device. The UDC20 initiates a read transaction from SetupCmd address 0x0555 and an interrupt is generated on IntStatusIn. The value programmed in the configuration register StatusInResponse is used to issue the 20 response to the status request. If "01" is written to this register, this indicates that the Control-Out data has been processed. The VCI port's apperr signal is asserted, which causes the UDC20 to send a zero-length data packet to the host, to indicate an ACK. If this register contains "00", this indicates that the Control-Out data has not yet been processed. The VCI 25 handshake signal appack is delayed by one cycle, which has the effect of NAKing the StatusIn token. Typically, the USB host will keep trying to receive StatusIn until it receives a non NAK handshake. If the StatusInResponse register contains "10", this indicates that the application is unable to process the control request. The VCI port's appstall signal is asserted which causes a STALL handshake to be returned to the USB host. 30 The UDC20 then initiates a status write to address xO00 to indicate if the packet has been transferred correctly. If the transfer was successful, the StatusInResponse register is cleared. If the transfer was unsuccessful, the Status transfer will be retried by the USB host. Figure 43 below illustrates a normal StatusIn stage.
WO 2005/120835 PCT/AU2004/000706 512 13.5.9.2 Non Control Transfers 13.5.9.2.1 Bulk/Interrupt IN Transfers A bulk/interrupt IN transfer is initiated with a read from an endpoint address on the VCI master port. The UDU can respond to the IN request with an ACK, NAK or STALL. Data must be pre-fetched from DRAM 5 into the local packet buffer. The local packet buffer is flagged as full if it contains 64 bytes or if it contains less than 64 bytes but there is no more endpoint data available in DRAM or it contains less than 64 bytes but it's a full packet. The options are listed below. Streaming mode - If the endpoint's local packet buffer is flagged as full, the data is read out on to the VCI bus 10 and appack is asserted as each word is read. - If the endpoint's local packet buffer is not flagged as full, and there is some data available in DRAM, the IN request is NAK'd by delaying appack by one cycle during the first read. An interrupt is generated on IntEpnInNak. - If the packet buffer empties in the middle of reading out a packet, then the UDU responds to 15 the next read request with appabort instead of appack. The UDC20 generates a CRC 16 and bit stuffing error. The host is expected to retry reading the packet later. An interrupt is generated on IntBufUnderrun. - If there is a short packet, the UDU completes the transfer by asserting apperr on the last read. Or if the last read contains less than 4 bytes, the relevant byte enables are kept low, and 20 appack is asserted as usual. The UDU assumes there is a short packet if there is no more data available in DRAM, i.e. DmalnnMaxAdrA/B has been reached. - If the local packet buffer is empty and there is no data available in DRAM, and the last packet sent from the endpoint was wMaxPktSize, and the current DMA descriptor's SendZero register is set to '1', then a zero length data packet is sent by asserting apperr instead of 25 appack. This indicates to the USB host the end of the transfer. - If the local packet buffer is empty and there is no valid DMA descriptor available, then the UDU issues a NAK and generates an interrupt on IntEpnInNak. * Non-streaming mode - If the local packet buffer is full, the data is read out on to the VCI bus and appack is asserted 30 as each word is read. - If the local packet buffer is empty and there is no data available in DRAM, and the last packet sent from the endpoint was wMaxPktSize, and the current DMA descriptor's SendZero register is set to '1', then a zero length data packet is sent by asserting apperr instead of appack. This indicates to the USB host the end of the transfer. 35 - If the local packet buffer is empty and there is no valid DMA descriptor available, then the UDU issues a NAK and generates an interrupt on IntEpnlnNak.
WO 2005/120835 PCT/AU2004/000706 513 - If the endpoint's packet buffer is not full but there is data available in DRAM, the UDU responds with a NAK by delaying appack by one cycle during the first read. An interrupt is generated on IntEpnInNak. e All modes 5 - If the endpoint is stalled, due to the relevant bit in EpStall being set, the UDU responds with a STALL by asserting appabort instead of appack during the first read. After the IN packet has been transferred, the host acknowledges with an ACK or timeout (no response). This response is presented to the UDU as a status write, as detailed in Section 13.5.9 above. The options are listed below. 10 - Non-streaming mode - If the packet was transferred successfully the packet is flushed from the local buffer. - If the packet was not transferred successfully, the packet remains in the local buffer. " Streaming mode - If the packet was transferred successfully, the DmalnnCurAdrA/B register is updated to 15 DmaInnStrmPtr. If the DmaInnIntAdrA/B address has been reached or overtaken, an interrupt is generated on IntEpnInAdrA/B. - If the packet was not transferred successfully, DmalnnStrmPtr is returned to the value in DmaInnCurAdrA/B. 13.5.9.2.2 Bulk OUT Transfers 20 A bulk OUT transfer begins with a write to an endpoint address on the VCI master port. The data is accepted and written into the local packet buffer if there is sufficient space available in both the local buffer and the endpoint's buffer in DRAM. The UDU can respond to an OUT packet with an ACK, NAK, NYET or STALL. In high speed mode, the UDU can respond to a PING with an ACK or NAK. The following list describes the different options. 25 - Streaming mode, full speed - If the local packet buffer is empty and there is at least enough space in DRAM for a wMaxPktSize packet, then the UDU accepts the data. The UDU ACKs the transfer by asserting appack. - If there is no valid DMA descriptor for the endpoint, the UDU responds with a NAK by 30 asserting apperr. An interrupt is generated on IntEpnOutNak. - If the local packet buffer is not empty, and there is a valid DMA descriptor, the UDU responds with a NAK by asserting app_err instead of appack for the next write. An interrupt is generated on IntBufOverrun. * Streaming mode, high speed WO 2005/120835 PCT/AU2004/000706 514 - If the local packet buffer is empty and there is at least enough space in DRAM for two wMaxPktSize packets, then the JDU accepts the data. The UDU ACKs the transfer by asserting appack. - If the local packet buffer is empty and there is at least enough space in DRAM for one 5 wMaxPktSize packet, then the UDU accepts the data and NYETs the transfer by delaying appack by one cycle on the first write. - If there is no valid DMA descriptor, the UDU responds with a NAK by asserting apperr. An interrupt is generated on IntEpnOutNak. - If the local packet buffer is not empty, and there is a valid DMA descriptor, the UDU 10 responds with a NAK by asserting apperr instead of appack for the next write. An interrupt is generated on IntBufOverrun. * Non-streaming mode (high speed only) - If the local packet buffer is empty, and there is at least enough space in DRAM for one wMaxPktSize packet, the UDU accepts the data and responds with a NYET by delaying 15 appack by one cycle on the first write. - If there is no valid DMA descriptor, the UDU responds with a NAK by asserting app_err. An interrupt is generated on IntEpnOutNak. - If the local packet buffer is not empty, and there is a valid DMA descriptor, the UDU responds with a NAK by asserting apperr instead of appack for the next write. An interrupt 20 is generated on IntEpnOutNak. - The UDU never ACKs an OUT packet in non-streaming mode. * All modes - If the endpoint is stalled, due to the relevant bit in EpStall being set, the UDU responds to an OUT with a STALL by asserting appabort instead of appack. 25 e PING tokens, streaming and non-streaming modes (high speed only) - If the local packet buffer is empty and there is at least enough space in DRAM for one wMaxPktSize packet, the UDU responds with an ACK by asserting app ack. - If there is no valid DMA descriptor for the endpoint, the UDU responds with a NAK by asserting apperr. An interrupt is generated on IntEpnOutNak. 30 - In streaming mode, if the local packet buffer is not empty, the UDU responds with a NAK by asserting apperr. An interrupt is generated on IntBufOverrun. - In non-streaming mode, if the local packet buffer is not empty, the UDU responds with a NAK by asserting apperr. An interrupt is generated on IntEpnOutNak. - If the endpoint is stalled, due to the relevant bit in EpStall being set, the UDU responds with a 35 NAK by asserting apperr instead of appack.
WO 2005/120835 PCT/AU2004/000706 515 When the packet has been written, the UDC20 issues a status write to indicate whether there were any protocol errors in the packet received. The UDU ensures that only good data ends up in the circular buffer in DRAM. The following lists the different scenarios. - All modes 5 - If the packet was received successfully, any remaining data is written out to DRAM and an interrupt is triggered on IntEpnOutPktWrA/B. If it was a short or zero length packet, an interrupt also occurs on IntEpnOutShortWrA/B. DmaOutnCurAdrA/B is updated to DmaOutStrnPtr. If DmaOutnntAdrA/B has been reached or passed, an interrupt occurs on IntEpnOutAdrA/B. 10 - If the packet was not received successfully, any remaining data in the packet buffer is discarded. DmaOutStrmPtr is returned to DmaOutnCurAdrA/B. Figure 45 below illustrates a normal bulk OUT transfer operating at high speed. 13.5.10 Data transfer rates Table 62 below summarizes the data transfer points of the USB device. Table 62. Data transfers Fl~teraceClock Clock Bit erito inteface freuency name wdtDee n USB bus 480MHz Internal 1 High speed data on the USB bus, to/from to PHY USB host to/from USB device 12MHz Internal 1 Full Speed data on the USB bus, to/from to PHY USB host to/from USB device UTMI interface 30MHz phy clk 16 Data transfer across the UTMI interface, to/from PHY to/from UDC20 VCl master 192MHz pclk 32 Data transfer across the VCl master port, port to/from UDC20 to/from UDU DIU bus 192MHz pclk 64 Data transfer across the DIU bus, to/from UDU to/from DRAM 15 13.5.11 VCI slave interface The VCI slave interface is used to read and write to configuration registers in the UDC20. The CPU initiates all the transactions on the CPU bus. The UDU bus adapter decodes any addresses destined for the UDC20 and converts the transaction from a CPU bus protocol to a VCI protocol. 20 By default, the UDU only allows Supervisor Data access from the CPU, all other CPU access codes are disallowed. If the configuration register UserModeEnable is set to '1', then User Data mode accesses are also allowed for all registers except UserModeEnable itself. The UDU responds with udu_cpuberr instead of uducpurdy if a disallowed access is attempted. Either signal occurs two cycles after cpuudusel goes high.
WO 2005/120835 PCT/AU2004/000706 516 Note that posted writes are not supported by the bus adapter, meaning that the UDU will not assert its udu_cpu rdy signal in response to a CPU bus write until the data has actually been written to the configuration register in the UDC20, when the signal udc20_csrack is asserted. Therefore, bus latency will be a couple of cycles higher for all writes to the UDC20 registers, but this is not a problem because the expected 5 access rate is very low. 13.5.12 Reset Table 63. Resets Re~set I'Domain A ctive level Source Destinato prstn Pclk Low CPR block Resets all pclk logic in UDU and UDC20 Reset Polk High CPU write to the Resets all pclk logic in UDU and (soft reset) Reset UDC20 configuration register UDC20Reset Pclk High CPU write to the Resets all pclk logic in UDC20 (soft reset) UDC20Reset configuration register rstphyck phy-clock High CPR block Resets all phyclock logic in UDC20 udc20_usbres Pclk High UDC20, Generates IntReset, which et generated when interrupts the CPU. USB host sends a reset command Table 63 below lists the resets associated with the UDU. 13.5.13 USB Reset The UDU goes into the Default state when the USB host issues a reset command. The JDC20 asserts the 10 signal udc20_reset and an interrupt is generated on IntReset. This does not cause any configuration registers or logic to be reset in the UDU, but the application may decide to do a soft reset on the UDU. The USB host must re-enumerate and re-configure the UDU before it can communicate with it again. 13.5.14Suspend/Resume The UDU goes into the Suspend state when the USB bus has been idle for more than 3 ms. If the device is 15 operating in high speed mode, it first reverts to full speed and if suspend signalling is observed (as opposed to reset signalling) then the device enters the Suspend state. The UDC20 then asserts the signal udc2O suspend and an interrupt is generated on IntSuspend. The CPR block receives the udc2osuspend signal via the output pin udu cprsuspend. The CPR block then drives suspend low to the PHY and the PHY port may only draw suspend current from Vbus, as specified by the USB specification. The amount of suspend current allowed 20 depends on whether the UDU is configured as self-powered/bus powered low-power/high-power, remote WO 2005/120835 PCT/AU2004/000706 517 wakeup enabled, etc. The PHY keeps a pullup attached to D+ during suspend mode, so during suspend mode the PHY always draws at least some current from Vbus. There are two ways for the device to come out of the Suspend state. a. The first is if any USB bus activity is detected, the device will interpret this as resume signalling 5 and will come out of Suspend state. The UDC20 then deassserts the udc2O suspend signal and an interrupt is generated on IntResume. The CPR block recognises a change of logic levels on the line_state signals from the PHY and drives suspend high to the PHY to allow it to come out of suspend. The UDC20 remembers whether the device was operating in high speed or full speed and transitions to FS/HS Idle state. 10 b. The second is if the device supports Remote Wakeup. It can receive the Remote Wakeup command via a write to its Resume configuration register. The UDU will then assert the appresume signal to UDC20. The device then initiates the resume signalling on the USB bus. The UDC20 then deasserts the udc20_suspend signal and an interrupt is generated on IntResume. Note that the USB host may enable/disable the Remote Wakeup feature of the device with the commands 15 SetFeature/ClearFeature. The CPR block drives suspendm low to the PHY. The UDU and PHY do not require pclk and phyclk to be running whilst in Suspend mode. The SW is in control of whether the UDU, PHY, CPU, DRAM etc are powered down. It is recommended that the SW power down the UDU in a controlled manner before disabling pclk to the UDU in the CPR block. It does this by disabling all DMA descriptors and enabling the interrupt masks required for a wakeup. 20 If resume signalling is received from an external host, the CPR block recognises this (by monitoring linestate) and must quickly enable pclk to the UDU (if it was disabled) and deassert suspend to the PHY port. There is lOms recovery time available before the USB host transmits any packets, which is enough time to enable the PHY's PLL (if it was switched off). 13.5.15 Ping 25 The ping protocol is used for control and bulk OUT transfers in high speed mode. The PING token is issued by the host to an endpoint, and the endpoint responds to it with either an ACK or NAK. The device responds with an ACK if it has enough room available to receive an OUT data packet of wMaxPktSize for that endpoint. If there isn't room available, the device responds with a NAK. If an ACK is issued, the host controller will later send an OUT data packet to that endpoint. Note that there 30 may be transactions to other endpoints in between the ping and data transfer to the pinged endpoint. A ping transaction is initiated on the VCI master port with a write to address 0x0004. The data on the VCI bus contains the endpoint to which the ping is addressed. The data field encoding is described in Table 64 below. In order to respond to the ping with an ACK, the UDU drives the appack signal high. To respond to the ping with a NAK, the UDU drives the apperr signal high.
WO 2005/120835 PCT/AU2004/000706 518 Table 64. Data field of Ping Write Bits 3-0 Endpoint number Bits 7-4 Alternate setting Bits 11 -8 Interface number Bits 15-12 Configuration number 13.5.16 SOF The USB host transmits Start Of Frame packets to the device every (micro)Frame. A frame is every 1 ms in full speed mode. A microframe is every 125 Vs in high speed mode. A SOF token is transmitted, along with 5 the 11 bit frame number. The UDC20 provides the signals udc20_sof and udc2Otimestamp[10:0] to indicate a SOF packet has been received. udc2Osof is used as an enable signal to sample udc2O timestamp[10:0]. When the frame number has been captured by the UDU, an interrupt is generated on IntSof The frame number is available in the configuration register SOFTimeStamp. 10 13.5.17 Enumeration After the host resets the device, which occurs when the device connects to the USB bus or at any other time decided by the host, the device enumerates as either full speed or high speed. The UDC20 provides the signals udc20_enumon and udc20_enumspeed[1:0j to provide enumeration status to the UDU. udc2O enumon indicates when enumeration is occurring. A negative edge trigger on this signal is used to sample 15 udc20_enumspeed[1:0J, which indicates whether the device is operating at full speed or high speed. The UDU generates interrupts IntEnumOn and IntEnumOff to indicate when the UDU's enumeration phase begin and end, respectively. The configuration register EnumSpeed indicates whether the device has been enumerated to operate at high speed or full speed. The CPU may respond to the IntEnumOff by reading the EnumSpeed register and setting the appropriate device descriptor, devicequalifier, otherspeed descriptor etc. 20 The EpnCfg and other UDU registers must also be set up to reflect the required endpoint characteristics. At a minimum, Endpoint 0 must be configured with an appropriate max packet size for the current enumerated speed and the DMA descriptors must be set up for Endpoint 0 IN and OUT. At this stage, the number of endpoints, interfaces, endpoint types, directions, max packet sizes, DMA descriptors etc may also be configured, though this may also be done when the device is configured (see Section 13.5.19). The next host 25 command to the device will normally be SetAddress, followed by GetDescriptor and SetConfiguration. The UDU can force the USB host to re-enumerate the device by effectively disconnecting and re-connecting. The SW can control this by writing a '1' to DisconnectDevice. This will cause the PHY to remove any termination resistors and/or pullups on the D+/D- lines. The USB host will recognise that the device has been removed. While the device is disconnected the SW could reprogram the UDU and/or device descriptors to WO 2005/120835 PCT/AU2004/000706 519 describe a new configuration. The SW can re-connect the device by writing a '1' to DisconnectDevice. The PHY will re-connect the pullup on D+ to indicate that it is a full speed device. The USB host will reset the device and the device may come out of reset in high speed or full speed mode, depending on the host's capabilities, ant the value programmed in the UDC20Strap signal app expspeed. 5 13.5.18 Vbus The UDU needs an external monitoring circuit to detect a drop in voltage level on Vbus. This circuit is connected to a GPIO pin, which is input to the UDU as gpioudu_vbusstatus. When this signal changes state from '0' to '1' or vice versa, an interrupt is generated on IntVbusStatus. The SW can read the logic level of the gpio_udu_vbus-status signal in the configuration register VbusStatus. If Vbus voltage has dropped, the 10 SW is expected to disconnect the USB device from Vbus within 10 seconds by writing a '1' to DisconnectDevice and/or Detect Vbus. 13.5.19 SetConfiguration and Setinterface commands When the host issues a SetConfiguration or SetInterface command, the UDC20 asserts the signal udc20_setcsrs to indicate that the EpnCfg registers may need to be updated. Note that the UDC20 responds 15 to the host with a stall if the configuration/interface/alternate interface number is greater than the maximum allowed in the HW in the UDC20, as detailed in Table 52. Therefore, the only valid configuration number is 0 or 1, the interface number may be 0 to 5, etc. In the case of SetInterface, the USB host commands the device to change the selected interface's alternate setting. The UDC20 supplies the signals udc20_intf[3:0] and udc20_altintff3:0] along with a signal for 20 sampling these values, udc20_hstsetintf The signals udc20_intf3:0] and udc20_altintf[3:O] are captured into the configuration register CurrentConfiguration. An interrupt is generated on IntSetCsrslntf when both udc20set csrs and udc20Ohst-setintf are asserted. The CPU is expected to respond to this interrupt by reading the relevant fields in the CurrentConfiguration register and update the selected interface to the new alternate setting. This will involve updating the EpnCfg registers to update the Alternatesetting fields of the 25 affected endpoints. The Maxpkt_size fields of these registers may also be changed. If they are, the CPU must also update the UDU's InterruptEpSize and/or FsEpSize registers with the new max pkt sizes. When the CPU has finished, it must write a '1' to the CsrsDone register. This causes the UDU to assert the signal appcsrs_done to the UDC20. Only then does the UDC20 complete the Status stage of the control command, because until it receives appdonecsrs the Status-In request is NAK'd. The UDU automatically clears the 30 CsrsDone register once udc20_setcsrs goes low. When the device receives a SetConfiguration command from the host, the signal udc20 setcsrs is asserted. The configuration number is output on udc20_cfg[3:0j and captured into the configuration register CurrentConfiguration using the signal udc20_hst_setcfg. An interrupt is generated on IntSetCsrsCfg. The CPU may respond to this interrupt by setting up all of the UDU's device descriptors and configuration 35 registers for the enumerated speed. The speed of operation is available in the EnumSpeed register. This may already have been set up by the CPU after the IntEnumOff interrupt occurred, see Section 13.5.17. The CPU must acknowledge the SetConfiguration command by writing a '1' to the CsrsDone register. This causes the WO 2005/120835 PCT/AU2004/000706 520 UDU to assert the appdonecsrs signal, which allows the UDC20 to complete the Status-In command. When the signal udc2Oset csrs goes low, the CsrsDone register is cleared by the UDU. 13.5.20 Endpoint Stalling Section 13.5.20.1 and Section 13.5.20.2 below summarize the different occurrences of endpoint stalling for 5 control and non-control data pipes respectively. 13.5.20.1 Stalling Control Endpoints Afunctional stall is not supported for the control endpoint in the UDU. Therefore, if the USB host attempts to set/clear the halt feature for endpoint 0 (using SET FEATURE/CLEARFEATURE), a STALL handshake will be issued. In addition, the application may not halt the UDU's control endpoint through the use of EpStall 10 configuration register, as is the case for the other endpoints. A protocol stall is supported for the control endpoint. If a control command is not supported, or for some reason the command cannot be completed, or if during a Data stage of a control transfer, the control pipe is sent more data or is requested to return more data than was indicated in the Setup stage the application must write a "10" to the StatusOutResponse or StatusInResponse configuration register. The UDU returns a STALL 15 to the host in the Status stage of the transfer. For control-writes, the STALL occurs in the Data phase of the Status In stage. For control-reads, the STALL occurs in the Handshake phase of the Status Out stage. The STALL is generated by setting the UDC20's input signal appstall high instead of appack or apperr during a Status-Out or Status-In transfer, respectively. The stall condition persists for all IN/OUT transactions (not just for endpoint 0) and terminates at the beginning of the next Setup received. The 20 StatusInResponse/StatusOutResponse register is cleared by the UDU after a status write. 13.5.20.2 Stalling Non-Control Endpoints A non-control endpoint may be stalled/unstalled by the USB host by setting/clearing the halt feature on that endpoint. This command is taken care of by the UDC20 and is not passed on to the application. In this case, both IN/OUT endpoint directions are stalled. 25 A non-control endpoint may be stalled by setting the relevant bit in the EpStall configuration register to '1'. Each IN/OUT direction may be stalled/unstalled independently. If an endpoint is stalled, its response to an IN/OUT/PING token will be a STALL handshake. If a buffer is full or there is no data to send, this does not constitute a stall condition. The UDU stalls an endpoint transfer by asserting appabort instead of appack during the VCI read/write 30 cycle. 13.5.21 UDC20 EpnCfg registers The UDC20 EpnCfg registers are listed in Table 53 under the heading "UDC20 control/status registers". These must be programmed to set up the endpoints to match the device descriptor provided to the USB host.
WO 2005/120835 PCT/AU2004/000706 521 Default endpoint 0 must be programmed in one of the 12 EpnCfg registers. There is just one register used for endpoint 0, and the Endpointdirection, Configurationnumber, Interface-number, Alternatesetting fields can be programmed to any values, as these fields are ignored. The non control endpoints are programmed into the rest of the EpnCfg registers, in any address order. There is 5 a separate register for each endpoint direction, i.e. Epl IN and Epl OUT each have their own EpnCfg registers. The Maxfpktsize field must be consistent with what is programmed into the InterruptEpSize and FsEpSize registers. If the UDU is to provide a subset of the maximum endpoints, the unused EpnCfg registers can be left at their reset values of 0x00000000. 10 If the host issues a SetConfiguration command, to configure the device, the CPU must ensure the EpnCfg registers are up to date with the device descriptors. Whenever the SetInterface command is received from the host, the affected endpoints' EpnCfg register must be updated to reflect the new alternate setting and possibly a changed max pkt size. InterruptEpSize and FsEpSize registers must also be updated if the max pkt size is changed. 15 Whenever the device is enumerated to either FS or HS, the max pkt sizes of some endpoints may change. Also, the alternate settings must all reset to the default setting for each interface. The CPU must update the EpnCfg registers to reflect this, when the IntEnumOff interrupt occurs. 13.5.22 UDC20 Strap Signals Table 65 below lists the UDC20 strap signals. These may be programmed by the CPU, but it is only allowed 20 to do so when appdevdiscon is asserted. The UDC20 drives the udc20_phymode[1:Oj = 10 when appdev_discon is asserted, which instructs the PHY to go into non-driving mode. The USB device is effectively disconnected from the host when the D+/D- lines are non-driving. Table 65. UDC20 Strap Signals Dynamic strap signals app-dev-discon 1 This signal generates a "soft disconnect" signal to the UDC20, which will then set udc20_phymode-01. This instructs the PHY to set the D+/D- signal levels to "disconnect" levels. This signal should be set high until the CPU has booted up and set up the UDU configuration registers and circular buffers in DRAM. Then this signal should be set low, so that the UDU can be detected by an external USB host. Read only strap signals app utmi-dir 0 Data bus interface of the PHY's UTMI interface. 0 unidirectional 1: bidirectional This is set to '0'. Read only.
WO 2005/120835 PCT/AU2004/000706 522 app-setdesc-sup 1 SET-DESCRIPTOR command support. When set to '0' the UDC20 responds to this command with a STALL handshake. This is set to '1'. Read only. app-synccmd-sup 0 Synch Frame command support. When set to '0', the UDC20 responds to a SYNCHFRAME command with a STALL handshake. The SYNCHFRAME command is only relevant for isochronous transfers. This is set to 'O'. Read only. app-ramif 0 Sets incremental read addressing on the internal VC master port. This is set to 'O'. Read only. app-phyif_8bit 0 Select either an 8-bit or 16-bit data interface to the PHY. 0: 16-bit interface 1: 8-bit interface This is set to '0'. Read only. app-csrprgsup 1 The UDC20 supports dynamic Control/Status Register programming. This is set to '1'. Read only. Static strap signals app-self-pwr 1 The power status signal, which is passed to the host in response to a GETSTATUS command. 0 The device draws power from the USB bus 1 : The device supplies its own power app-dev-rmtwkup 1 Device Remote Wakeup capability 0 : The device does not support Remote Wakeup 1 The device supports Remote Wakeup appexp-speed[1:0] 00 The expected application speed. 00: HS 01: FS 10: LS (not allowed) 11: FS app-nz-ien-pktstall 0 This signal, together with appnzJenpkLstalall, provides an option for the UDC20 to respond with a STALL or ACK handshake if the USB host has issued a non-zero length data packet during the Status-Out phase of a control transfer. Setting this to '0' ensures that the UDC20 will pass on the data packet to the UDU and return a handshake to the host based on the. app-ack/app-stall received from the UDU. app-nzlen-pktstallall 0 This signal, together with app_njzen_pkt_stall, provides an option for the UDC20 to respond with a STALL or ACK handshake if the USB host has issued a non-zero length data packet during the Status-Out phase of a control transfer. Setting this to '0' ensures that the UDC20 will pass on the data packet to the UDU and return a handshake to the host based on the app-ack/app-stall received from the UDU.
WO 2005/120835 PCT/AU2004/000706 523 app-stall-cir-ep0_hat 1 This signal provides an option for the UDC20 to respond with a STALL or an ACK handshake to the USB host if the USB host issues a CLEAR_FEATURE(HALT) command to endpoint 0. 0: ACK 1 : STALL hstimeout_calib[2:0] 000 This value is used to increase the high speed timeout value in terms of number of PHY clocks. This can be done in order to account for the delay of the PHY in generating the linestate signal. The timeout value can be increased from 736 to 848 bit times as a result of adding 0 to 7 PHY clock periods. fstimeout_calib[2:0] 000 This value is used to increase the full speed timeout value in terms of number of PHY clocks. This can be done in order to account for the delay of the PHY in generating the line state signal. The timeout value can be increased from 16 to 18 bit times as a result of adding 0 to 7 PHY clock periods. app-enable-erraticerr 1 Enable monitoring of the phyxactive and phy rxvalid signals for the error condition. If either of these signals is high for more than 2 ms, then the UDC20 will assert the signal udc20_erratic_err and will switch into the Suspend state. 14 GENERAL PURPOSE 10 (GPIO) 5 14.1 OVERVIEW The General Purpose 10 block (GPIO) is responsible for control and interfacing of GPIO pins to the rest of the SoPEC system. It provides easily programmable control logic to simplify control of GPIO functions. In all there are 64 GPIO pins of which any pin can assume any output or input function. Possible output functions are 10 e 6 Stepper Motor control outputs e 18 Brushless DC Motor control output (total of 3 different controllers each with 6 outputs) e 4 General purpose LED pulsed outputs. - 4 LSS interface control and data e 24 Multiple Media Interface general control outputs 15 - 3 USB over current protect e 2 UART Control and data Each of the pins can be configured in either input or output mode, and each pin is independently controlled. A programmable de-glitching circuit exists for a fixed number of input pins. Each input is a schmidt trigger to increase noise immunity should the input be used without the de-glitch circuit.
WO 2005/120835 PCT/AU2004/000706 524 After reset (and during reset) all GPIO pads are set to input mode to prevent any external conflicts while the reset is in progress. All GPIO pads have an integrated pull-up resistor. Note, ideally all GPIO pads will be highest drive and fastest pads available in the library, but package and 5 power limitations may place restrictions on the exact pads selection and use. 14.2 STEPPER MOTOR CONTROL Pins used for motor control can be directly controlled by the CPU, or the motor control logic can be used to generate the phase pulses for the stepper motors. The controller consists of 3 central counters from which the control pins are derived. The central counters have several registers (see Table 68) used to configure the cycle 10 period, the phase, the duty cycle, and counter granularity. There are 3 motor master counters (0,1 and 2) with identical features. The periods of the master counters are defined by the MCMasClkPeriod[2:0] and MCMasClkSrc[2:0] registers. The MCMasClkSrc defines the timing pulses used by the master counters to determine the timing period. The MCMasClkSrc can select clock sources of Ips, 1 00ps,1 Oms and pclk timing pulses (note the exact period of the pulses is configurable in the 15 TIM block). The MCMasClkPeriod[2:0] registers are set to the number of timing pulses required before the timing period re-starts. Each master counter is set to the relevant MCMasClkPeriod value and counts down a unit each time a timing pulse is received. The master counters reset to MCMasClkPeriod value and count down. Once the value hits zero a new value is 20 reloaded from the MCMasClkPeriod[2:0] registers. This ensures that no master clock glitch is generated when changing the clock period. Each of the 10 pins for the motor controller is derived from the master counters. Each pin has independent configuration registers. The MCMasClkSelect[5:0] registers define which of the 3 master counters to use as the source for each motor control pin. The master counter value is compared with the configured MCLow and 25 MCHigh registers (bit fields of the MCConfig register). If the count is equal to MCHigh value the motor control is set to 1, if the count is equal to MCLow value the motor control pin is set to 0, if the count is not equal to either the motor control doesn't change. This allows the phase and duty cycle of the motor control pins to be varied at pclk granularity. Each phase generator has a cut-out facility that can be enabled or disabled by the MCCutOutEn register. If 30 enabled the phase generator will set its motor control output to zero when the cutout input is high. If the cut_out signal is then subsequently removed the motor control will not return high until the next configured high transition point. The cutout signal does not effect any of the counters, only the output motor control. There is a fixed mapping of deglitch circuit to the cutout inputs of the phase generator, deglitch circuit 13 is connected to phase generator 0 and 1, deglitch circuit 14 to phase generator 2 and 3, and deglitch circuit 15 to 35 phase generator 4 and 5.
WO 2005/120835 PCT/AU2004/000706 525 The motor control generators keep a working copy of the MCLow, MCHigh values and update the configured value to the working copy when it is safe to do so. This allows the phase or duty cycle of a motor control pin to be safely adjusted by the CPU without causing a glitch on the output pin. Note that when reprogramming the MCLow, MCHigh register fields to reorder the sequence of the transition 5 points (e.g changing from low point less than high point to low point greater than high point and vice versa) care must still taken to avoid introducing glitching on the output pin. 14.3 LED CONTROL LED lifetime and brightness can be improved and power consumption reduced by driving the LEDs with a pulsed rather than a DC signal. The source clock for each of the LED pins is a 7.8kHz (128gs period) clock 10 generated from the Ips clock pulse from the Timers block. The LEDDutySelect registers are used to create a signal with the desired waveform. Unpulsed operation of the LED pins can be achieved by using CPU 10 direct control, or setting LEDDutySelect to 0. 14.4 LSS INTERFACE VIA GPIO GPIO pins can be connected to either of the two LSS-controlled buses if desired (by configuring the 15 IOModeSelect registers). When the IOmodeSelect[6:0] register for a particular GPIO pin is set to 31,30,29 and 28 the GPIO pin is connected to LSS clock control 1 to 0, and the LSS data control 1 and 0 respectively. Note that IOmodeSelect[12:7] must be configured to enable output mode control by the LSS also. Although the LSS block within SoPEC only provides 2 simultaneous buses, more than 2 LSS buses can be accessed over time by changing the allocation of pins to the LSS buses. Additionally, there is no need to 20 allocate pins specifically to LSS buses for the life of a SoPEC application, except that the boot ROM makes particular use of certain pins during the boot sequence and any hardware attached to those pins must be compatible with the boot usage (for more information see section 21.2) Several LSS slave devices can be connected to one LSS master. In order to simplify board layout (or reduce pad fanout) it is possible to combine several LSS slave GPIO pin connections internally in the GPIO for 25 connection to one LSS master. For example if the IOmodeSelect[6:0] of pins 0 to 7 are all programmed to 30 (LSS data 0), each of the pins will be driven by the LSS Master 0. The corresponding data in (gpio-lss-din[0]) to the LSS master 0 will be driven by pins 0-7 combined (pins will be ANDed together). Since only one LSS slave can be sending data back to the LSS master at a time (and all other LSS slaves must be tri-stating the bus) LSS slaves will not interfere with each other. 30 14.5 CPU GPIO CONTROL The CPU can assume direct control of any (or all) of the 10 pins individually. On a per pin basis the CPU can turn on direct access to the pin by configuring the IOModeSelect register to CPU direct mode. Once set the IO pin assumes the direction specified by the CpuIODirection register. When in output mode the value in register CpuIOOut will be directly reflected to the output driver. At any time the status of the input pins can be read WO 2005/120835 PCT/AU2004/000706 526 by reading CpuIOIn register (regardless of the mode the pin in). When writing to the CpuIOOut (or the CpulODirection) register the value being written is XORed with the current value in CpuIOOut (or the CpuIODirection) to produce the new value for the register. The CPU can also read the status of the 24 selected de-glitched inputs by reading the CpulOInDeGlitch register. 5 14.6 PROGRAMMABLE DE-GLITCHING LOGIC Each 10 pin can be filtered through a de-glitching logic circuit. There are 24 de-glitching circuits, so a maximum of 24 input pins can be de-glitched at any time. The connections between pins and de-glitching logic is configured by means of the DeGlitchPinSelect registers. Each de-glitch circuit can be configured to sample the 10 pin for a predetermined time before concluding that 10 a pin is in a particular state. The exact sampling length is configurable, but each de-glitch circuit must use one of 4 possible configured values (selected by DeGlitchSelect). The sampling length is the same for both high and low states. The DeGlitchCount is programmed to the number of system time units that a state must be valid for before the state is passed on. The time units are selected by DeGlitchClkSrc and are nominally one of Iss,100 s,10ms and pclk pulses (note that exact timer pulse duration can be re-programmed to different 15 values in the TIM block). The DeGlitchFormSelect can be used to bypass the deglitch function in the deglitch circuits if required. It selects between a raw input or a deglitched input. For example if DeGlitchCount is set to 10 and DeGlitchClkSrc set to 3, then the selected input pin must consistently retain its value for 10 system clock cycles (pclk) before the input state will be propagated from 20 CpuIOIn to CpulOInDeglitch. 14.6.1 Pulse Divider There are 4 pulse divider circuits. Each pulse divider is connected to the output of one of the deglitch circuits (fixed mapping). Each pulse divider circuit is configured to divide the number of input pulses before generating an output pulse, effectively lowering the period frequency. The input to output pulse frequency is 25 configured by the PulseDiv configuration register. Setting the register to 0 allows a direct straight through connection with no delay from input to output allowing the deglitch circuit to behave exactly the same as other deglitch circuits without pulse dividers. Deglitch circuits 0,1,2 and 3 are all filtered through pulse dividers. 14.7 INTERRUPT GENERATION 30 There are 16 possible interrupts from the GPIO to the ICU block. Each interrupt can be generated from a number of sources selected by the InterruptSrcSelect register. The interrupt source register can select the output of any of the deglitch circuits (24 possible sources), the interrupt output of either of the Period measures (2 sources), or the outputs of any of the MMI control sub-block (24 sources), 2 MMI interrupt sources, 1 UART interrupt and 6 Motor Control outputs, giving a total of 59 possible sources.
WO 2005/120835 PCT/AU2004/000706 527 The interrupt type, masking and priority can be programmed in the interrupt controller (ICU). 14.8 CPR WAKEUP The GPIO can detect and generate a wakeup signal to the CPR block. The GPIO wakeup monitors the GPIO to ICU interrupts (gpio icu irq[15:0]) for a wakeup condition to determine when to set a WakeUpDetected 5 bit. The WakeUpDetected bits are ORed together to generate a wakeup condition to the CPR. The WakeUpCondition register defines the type of condition (e.g. positive/negative edge or level) to monitor for on the gpio icuirq interrupts before setting a bit in the WakeUpDetected register. The WakeUpInputMask controls if a met wakeup condition sets a WakeUpDetected bit or is masked. Set WakeUpDetected bits can be cleared by writing a I to the corresponding bit in the WakeUpDetectedClr register. 10 14.9 SoPEC MODE SELECT Each SoPEC die has 3 pads that are not bonded out to package pins. By default (when left unbonded) the 3 pads are pulled high and are read as Is. These die pads can be bonded out to .GND to select possible modes of operation for SoPEC. The status of these pads can be read by accessing the SoPECSel register. They have no direct effect on the operation of SoPEC but are available for software to read and use. 15 The initial package for SoPEC has these pads unbonded, so the SoPECSel register is read as 7. The boot ROM uses SoPECSel during the boot process (further described in Section 19.2). 14.10 BRUSHLESS DC (BLDC) MOTOR CONTROLLERS The GPIO contains 3 brushless DC (BLDC) motor controllers. Each controller consists of 3 hall inputs, a direction input, a brake input (software configured), and six possible outputs. The outputs are derived from 20 the input state and a pulse width modulated (PWM) input from the Stepper Motor controller, and is given by the truth table in Table 66. Table 66. Truth Table for BLDC Motor Controllers Brake direction he hb ha q6 q5 4 q3 q2 q1 0 0 0 0 1 0 0 0 1 PW 0 0 0 0 1 1 PWM 0 0 1 0 0 0 0 0 1 0 PWM 0 0 0 0 1 0 0 1 1 0 0 0 PWM 0 0 1 0 0 1 0 0 0 1 PWM 0 0 0 0 0 1 0 1 0 1 0 0 PWM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 WO 2005/120835 PCT/AU2004/000706 528 0 1 0 0 1 0 0 PWM 0 0 1 0 1 0 1 1 PWM 0 0 0 0 1 0 1 0 1 0 PWM 0 0 1 0 0 0 1 1 1 0 0 0 0 1 PWM 0 0 1 1 0 0 0 1 0 0 PWM 0 0 1 1 0 1 0 1 PWM 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 X X X X 1 0 1 0 1 0 All inputs to a BLDC controller must be de-glitched. Each controller has its inputs hardwired to de-glitch circuits. See Table 76 for fixed mapping details. 5 Each controller also requires a PWM input. The stepper motor controller outputs are reused, output 0 is connected to BLDC controller 1, and output 1 to BLDC controller 2 and output 2 to BLDC controller 3. The controllers have two modes of operation, internal and external direction control (configured by BLDCMode). If a controller is in external direction mode the direction input is taken from a de-glitched circuit, if it is in internal direction mode the direction input is configured by the BLDCDirection register. 10 Each BLDC controller has a brake control input which is configured by accessing the BLDCBrake register. If the brake bit is activated then the BLDC controller outputs are set to fixed state regardless of the state of the other inputs. When writing to the BLDCDirection (or the BLDCBrake) registers the value being written is XORed with the current value in BLDCDirection (or the BLDCBrake) to produce the new value for the register. 15 The BLDC controller outputs are connected to the GPIO output pins by configuring the IOModeSelect register for each pin, e.g setting the mode register to 0x208 will connect ql Controller 1 to drive the pin. 14.11 PERIOD MEASURE There are 2 period measure circuits. The period measure circuit counts the duration (PMCount) between successive positive edges of 1 or 2 input pins (through the deglitch and pulse divider circuit) and reports the 20 last period measured (PMLastPeriod). The period measure can count either the number of pclk cycles between successive positive edges on an input (or both inputs if selected) or count the number of positive edges on the input (or both inputs if selected). The count mode is selected by PMCntSrcSelect register. The period measure can have 1 input or 2 inputs XORed together as an input counter logic, selected by the PMInputModeSel. 25 Both the PMCount and PMLastPeriod can be programmed directly by the CPU, but the PMLastPeriod register can be made read only by clearing the PMLastPeriodWrEn register.
WO 2005/120835 PCT/AU2004/000706 529 There is a direct mapping between deglitch circuits and period measure circuits. Period measure 0 inputs 0 and 1 are connected to deglitch circuits 0 and 1. Period measure 1 inputs 0 and 1 are connected to deglitch circuits 2 and 3. Both deglitch circuits have a pulse divider fixed on their output, which can be used to divide the input pulse 5 frequency if needed. 14.12 FREQUENCY MODIFIER The frequency modifier circuit accepts as input the period measure value and converts it to an output line sync signal. Period measure circuit 0 is always used as the input to the frequency modifier. The incoming frequency from the encoder input (the input to the period measure circuit is an encoder input) is of the range 10 0.5KHz to 10KHz. The modifier converts this to a line sync frequency with a granularity of <0.2% accuracy. The output frequency is of the range of 0.1 to 6 times the input frequency. The output of the frequency modifier is connected to the PHI block via the gpio_phi linesync signal. The generated line sync can also optionally be redirected out any of the GPIO outputs for syncing with other SoPEC devices (via the finlinesync signal). The line sync input in other SoPECs will be deglitched, so the 15 sync generating SoPEC must make sure that line sync pulse is longer than the deglitch duration (to prevent the line sync getting removed by the de-glitch circuit). The line sync pulse duration can be stretched to a configurable number of pclk cycles, configured by FMLsyncHigh. Only the finlinesync signal is stretched, the gpio_philine sync signal remains a single pulse. The line sync is generated from the frequency modifier and shaped for output to another SoPEC. But since the 20 other SoPEC may deglitch the line, it will take some time to arrive at the PHI in that SoPEC. To assist in synchronizing multiple SoPECs in printing sections of the same page it would be desirable if the line syncs arrive at the separate PHI blocks around the same time. To facilitate this the frequency modifier delays the internal line sync (gpiophilinesync) by a programmable amount (FMLsyncDelay). This register should be programmed to an estimate of the delay caused by transmission and deglitching at any recipient SoPEC. Note 25 the FMLsyncDelay register only delays the internal line sync (gpio_philinesync) to the PHI and not the line sync generated for output (finlinesync) to the GPIOs. The frequency modifier block contains a low pass filter for removal of high frequency jitter components in the input measured frequency. The filter structure used is a direct form II IIR filter as shown in Figure 48. The filter co-efficients are programmed via the FMFiltCoeff registers. Care should be taken to ensure that the co 30 efficients chosen ensure the filter is stable for all input values. The internal delay elements of the filter can be accessed by reading or writing to the FMIIRDelay registers. Any CPU writes to these registers will take priority over internal block updates and could cause the filter to become unstable. The frequency modifier circuit is connected directly to the period measure circuit 0, which is connected 35 directly to input deglitch circuits 0 and 1.
WO 2005/120835 PCT/AU2004/000706 530 The frequency modifier calculation can be bypassed by setting the FMBypass register. This bypasses the frequency modifier calculation stage and connects the pm int output of the period measure 0 block to the line sync stretch circuit. 14.13 GENERAL UART 5 The GPIO contains an asynchronous UART which can be connected to any of the GPIO pins. The UART implements 8-bit data frame with one stop bit. The programmable options are e Parity bit (on/off) e Parity polarity (odd/even) e Baud-rate (16-bit programmable divider) 10 e Hardware flow-control (CTS/RTS) e Loop-back test mode The error-detection in the receiver detects parity, framing break and overrun errors. The RX and TX buffers are accessed by reading the RX buffer registers, and writing to the TX buffer registers. Both buffers are 32 bits wide. 15 There is a fixed mapping of deglitch circuits to the UART inputs. See Table 76 for mapping details. 14.14 USB CONNECTIVITY The GPIO block provides external pin connectivity for optional control/monitor functions of the USB host and device. The USB host (UHU) needs to control the Vbus power supply of each individual host port. The UHU 20 indicates to the GPIO whether Vbus should be applied or not via the uhugpio_power switch[2:0] signals. The GPIO redirects the signals to selected output pins to control external power switching logic. The uhugpio_power_switch[2:0] signals can be selected as outputs by configuring the IOModeSelect[6:0j register to 58-56, and the pin is in output mode. The UHU can optionally be required to monitor the Vbus supply current and take appropriate action if the 25 supply current threshold is exceeded. An external circuit monitors the Vbus supply current, and if the current exceeds the threshold it signals the event via GPIO pin. The GPIO pin input is deglitched (deglitch circuits 23,22,21) and is passed to the USB host via the gpiouhu_over_current[2:0] signals, one per port connection. The USB device (UDU) is required to monitor the Vbus to determine the presence or absence of the Vbus supply. An external Vbus monitoring circuit detects the condition and signals an event to a GPIO pin. The 30 GPIO pin input is deglitched (deglitch circuit 3) and is passed to the UDU via the gpio_udu_vbus_status signal.
WO 2005/120835 PCT/AU2004/000706 531 14.15 MMI CONNECTIVITY The GPIO block provides external pin connectivity for the MMI block. GPIO output pins can be connected to any of the MMI outputs, control (mmigpio ctrl[23:0]) or data (mmi_gpiodata[63:0]) by configuring the IOModeSelect registers. When the IOmodeSelect[6:0] register for 5 a particular GPIO pin is set to 127-64 the GPIO pin is connected to the MMI data outputs 63 to 0 respectively. When IOmodeSelect[6:0] is set to 55-32 the GPIO pin is connected to the MMI control outputs 23 to 0 respectively. In all cases IOmodeSelect[12:7] must configure the GPIO pins as outputs. GPIO input pins can be connected to any of the MMI inputs, control (gpio-mmi_ctr[15:0j) or data (gpio-mmidata[63:0]). The MMI control inputs are all deglitched and have a fixed mapping to deglitch 10 circuits (see Table 76 for details). The data inputs are not deglitched. The MMIPinSelect[63:0] registers configure the mapping of GPIO input pins to MMI data inputs. For example setting MMIPinSelect[O] to 32 will connect GPIO pin 32 to gpio mmidata[O]. In all cases IOmodeSelect[12:7] must configure the GPIO pins as inputs. 14.16 IMPLEMENTATION 15 14.16.1 Definitions of 1/0 Table 67. I/O definition Clocks and Resets Pclk 1 In System Clock prstn 1 In System reset, synchronous active low tim-pulse[2:0] 3 In Timers block generated timing pulses. 0 - 1 gs pulse 1 - 100 gs pulse 2 - 10 ms pulse CPU Interface cpu-adr[l0:2] 9 In CPU address bus. Only 9 bits are required to decode the address space for this block cpu.dataout[31:0] 32 In Shared write data bus from the CPU gpio-cpu-data[31:0] 32 Out Read data bus to the CPU cpurwn 1 In Common read/not-write signal from the CPU cpu-gpio-sel 1 In Block select from the CPU. When cpugpio~sel is high both cpuadr and cpudataout are valid gpio.cpu-rdy 1 Out Ready signal to the CPU. When gpio cpujrdy is high it indicates the last cycle of the access. For a write cycle this means cpudataout has been registered by the GPIO block and for a read cvcle this means the data WO 2005/120835 PCT/AU2004/000706 532 on gpiocpudata is valid. gpio-cpu-berr 1 Out Bus error signal to the CPU indicating an invalid access. gpioscpudebugvalid 1 Out Debug Data valid on gpioqcpudata bus. Active high cpu-acode[1:0] 2 In CPU Access Code signals. These decode as follows: 00 - User program access 01 - User data access 10 - Supervisor program access 11 - Supervisor data access 10 Pins gpio-o[ 63:0] 64 Out General purpose 10 output to 10 driver gpioji[ 63:0] 64 In General purpose 10 input from 10 receiver gpio-e[ 63:0] 64 Out General purpose 10 output control. Active high driving GPIO to LSS lss-gpio-dout[1:0] 2 In LSS bus data output Bit 0 - LSS bus 0 Bit 1 - LSS bus 1 gpioiss-din[1:0] 2 Out LSS bus data input Bit 0 - LSS bus 0 Bit 1 - LSS bus 1 Iss_gpio-e[1:0] 2 In LSS bus data output enable, active high Bit 0 - LSS bus 0 Bit 1 - LSS bus 1 Issgpio-clk[1:0] 2 In LSS bus clock output Bit 0 - LSS bus 0 Bit 1 - LSS bus 1 GPIO to USB uhu-gpio-power-switch[ 3 In Port Power enable from the USB host core, one per 2:0] port, active high gpio uhuover-current[2: 3 Out Over current detect to the USB host core, active high 0] gpiouduvbus_status 1 Out Indicates the USB device Vbus status to the UDU. I I Active high GPIO to MMI mmi-gpio-data[63:0] 64 In MMI to GPIO data, for muxing to GPIO pins gpiommidata[63:0] 64 Out GPIO to MMI data, extracted from selected GPIO pins mmi-gpiosctrl[23:0] 24 In MMI to GPIO control inputs, for muxing to GPIO pins All bits can be connected to data out pins in the GPIO, bits 23:16 can also be configured as data out enables (i.e. tri-state enables) on configured output pins. gpiommi-ctrl[15:0] 16 Out GPIO to MMI control outputs, extracted from selected GPIO pins mmi-gpio-irq 2 In MMI interrupts for muxing out through the GPIO interrupts 0 - TX buffer interrupt WO 2005/120835 PCT/AU2004/000706 533 1 - RX buffer interrupt Miscellaneous gpio-icu-irq[15:0] 16 Out GPIO pin interrupts gpio-cpr-wakeup 1 Out SoPEC wakeup to the CPR block active high. gpio-phi-linesync 1 Out GPIO to PHI line sync pulse to synchronise the dot generation output to the printhead with the motor controllers and paper sensors sopec-sel[2:0] 3 In Indicates the SoPEC mode selected by bondout options over 3 pads. When the 3 pads are unbonded as in the current package, the value is 111. Debug debug-data-out[31:0] 32 In Output debug data to be muxed on to the GPIO pins debug-cntrl[32:0] 33 In Control signal for each GPIO bound debug data line indicating whether or not the debug data should be selected by the pin mux debug-data-valid 1 In Debug valid signal indicating the validity of the data on debug.data-out. This signal is used in all debug configurations. It is selected by debug cntr[32] 14.16.1 14.16.2 Configuration registers The configuration registers in the GPIO are programmed via the CPU interface. Refer to section 11.4.3 on page 77 for a description of the protocol and timing diagrams for reading and writing registers in the GPIO. 5 Note that since addresses in SoPEC are byte aligned and the CPU only supports 32-bit register reads and writes, the lower 2 bits of the CPU address bus are not required to decode the address space for the GPIO. When reading a register that is less than 32 bits wide zeros are returned on the upper unused bit(s) of gpio cpudata. Table 68 lists the configuration registers in the GPIO block Table 68. GPIO Register Definition Ox000- IOModeSelect[ 63:0] 64 x1c3 ox Specifies the mode of operation for each Ox0FC GPIO pin. One 13 bit register per gpio pin. Bits 6:0 - Data Out, selects what controls the data out Bits 8:7 - Selects how output mode is applied Bits 12:9 - Selects what controls the pads input or output mode See Table 72, Table 73 and Table 74 for description of mode selections.
WO 2005/120835 PCT/AU2004/000706 534 Ox1 00- MMIPinSelect[63:0] 64x6 Ox00 MMI input data pin select.1 register per 0x1FC gpio_mmi_data output. Specifies the input pin used to drive gpiommi data output to the MMI block. Ox200- DeGlitchPinSelect[23 24x6 Ox00 Specifies which pins should be selected as 0x25C :0] inputs. Used to select the pin source to the DeGlitch Circuits. Ox280- IOPinInvert[1:0] 2x32 Ox0000 Specifies if the GPIO pins should be inverted 0x284 0000 or not. Active High. If a pin is in input mode and the invert bit is set then pin polarity will be inverted. If the pin is in output mode and the inverted bit is set then the output will be inverted. Ox288 Reset 3 Ox7 Active low synchronous reset, self de activating. Writing a 0 to the relevant bit position in this register causes a soft reset of the corresponding unit 0 - Full GPIO block reset (same as hardware reset) 1 - UART block reset 2 - Frequency Modifier reset Self resetting register. CPU 10 Control 0x300- CpulOUserModeMas 2x32 Ox0000 User Mode access mask to CPU GPIO 0x304 k[1:0] 0000 control register. When 1 user access is enabled. One bit per gpio pin. Enables access to CpulODirection, CpuIOOut and CpulOln in user mode. Ox310- CpulOSuperModeMa 2x32 OxFFFF Supervisor Mode access mask to CPU 0x314 sk[1:0] _FFFF GPIO control register. When 1 supervisor access is enabled. One bit per gpio pin. Enables access to CpulODirection, CpulOOut and CpulOln in supervisor mode. Ox320- CpulODirection[1:0] 2x32 Ox0000 Indicates the direction of each 10 pin, when 0x324 0000 controlled by the CPU When written to the register assumes the new value XORed with the current value 0 - Indicates Input Mode 1 - Indicates Output Mode Ox330- CpulOOut[1:0] 2x32 Ox0000 CPU direct mode GPIO access. Ox334 0000 When written to the register assumes the new value XORed with the current value, and value is reflected out the GPIO pins. Bus 0 - GPIO pins 31:0 Bus 1 - GPIO pins 63:32 0x340- CpuIOIn[1:0] 2x32 External Value received on each input pin regardless 0x344 pin of mode. value Bus 0 - GPIO pins 31:0 Bus 1 - GPIO pins 63:32 Read Only register. Ox350 CpuDeGlitchUserMo 24 Ox00_0 User Mode Access Mask to Cpu/OlnDeglitch deMask 00 control register. When 1 user access is enabled, otherwise bit reads as zero. Ox360 CpulOlnDeglitch 24 Ox00_0 Deglitched version of selected input pins. 000 The input pins are selected by the DeGlitchPinSelect register. Note that after reset this register will reflect tho avtornal nin unhia 9% n-ILe ueilac aftar WO 2005/120835 PCT/AU2004/000706 535 they have stabilized. Read Only register. Deglitch control 0x400- DeGlitchSelect[23:0] 24x2 Ox0 Specifies which deglitch count 0x45c (DeGlitchCouno and unit select (DeGlitchCkSrc) should be used with each de-glitch circuit. 0 - Specifies DeGlitchCount[0] and DeGlitchCkSrc[0] 1 - Specifies DeGlitchCount[1] and DeGlitchCkSrc[1] 2 - Specifies DeGlitchCount[2] and DeGlitchClkSrc[2] 3 - Specifies DeGlitchCount[3] and DeGlitchC/kSrc[3] One bus per deglitch circuit Ox480- DeGlitchCount[3:0] 4x8 OxFF Deglitch circuit sample count in Ox48C DeGlitchClkSrc selected units. Ox490- DeGlitchClkSrc[3:0] 4x2 Ox3 Specifies the unit use of the GPIO deglitch 0x49C circuits: 0 - 1 gs pulse 1 - 100 ps pulse 2 - 10 ms pulse 3 - pclk Ox4AO DeGlitchFormSelect 24 Ox00_0 Selects which form of selected input is 000 output to the remaining logic, raw or deglitched. 0 - Raw mode (direct from GPIO) 1 - Deglitched mode Ox4BO- PulseDiv[3:0] 4x4 Ox0 Pulse Divider circuit. One register per pulse Ox4BC divider circuit. Indicates the number of input pulses before an output pulse is generated. 0 - Direct straight through connection (no delay) N - Divides the number of pulses by N Motor Control 0x500 MCUserModeEnable 1 Ox0 User Mode Access enable to motor control configuration registers. When 1 user access is enabled. Enables user access to MCMasClockEn, MCCutoutEn,MCMasClkPeriod, MCMasClkSrc, MCConfig, MCMasClkSelect, BLDCMode, BLDCBrake and BLDCDirection registers 0x504 MCMasClockEnable 3 Ox0 Enable the motor master clock counter. When 1 count is enabled Bit 0 - Enable motor master clock 0 Bit 1 - Enable motor master clock 1 Bit 2 - Enable motor master clock 2 0x508 MCCutoutEn 6 0x00 Motor controller cut-out enable, active high, 1 bit per phase generator. 0 - Cut-out disabled 1 - Cut-out enabled 0x51 0- MCMasClkPeriod[2:0 3x1 6 Ox0000 Specifies the motor controller master clock 0x518 ] periods in MCMasClkSrc selected units WO 2005/120835 PCT/AU2004/000706 536 0x520- MCMasClkSrc[2:0] 3x2 Ox0 Specifies the unit use by the motor controller 0x528 master clock generators. One bus per master clock generator 0 - 1 ps pulse 1 - 100 ss pulse 2 - 10 ms pulse 3 - pclk 0x530- MCConfig[5:0] 6x32 0x0000 Specifies the transition points in the clock 0x544 0000 period for each motor control pin. One register per pin bits 15:0 - MCLow, high to low transition point bits 31:16 - MCHigh, low to high transition point Ox550- MCMasClkSelect[5:0] 6x2 Ox0 Specifies which motor master clock should 0x564 be used as a pin generator source, one bus per pin generator 0 - Clock derived from MCMasClockPeriod[0] 1 -Clock derived from MCMasClockPeriod[1] 2 -Clock derived from MCMasClockPeriod[2] 3 - Reserved BLDC Motor Controllers 0x580 BLDCIMode 3 Ox0 Specifies the mode of operation of the BLDC controller. One bit per controller. 0 - Internal direction control 1 - External direction control 0x584 BLDCDirection 3 Ox0 Specifies the direction input of the BLDC controller. Only used when BLDC controller is an internal direction control mode. One bit per controller. 0 - Counter clockwise 1 - Clockwise When written to the register assumes the new value XORed with the current value Ox588 BLDCBrake 3 Ox0 Specifies if the BLDC controller should be held in brake mode. One bit per controller. 0 - Release from brake mode 1 - Hold in Brake mode When written to the register assumes the new value XORed with the current value LED control 0x590 LEDUserModeEnabl 4 Ox0 User mode access enable to LED control e configuration registers. When 1 user access is enabled. One bit per LEDDutySelect select register. Ox594- LEDDutySelect[3:0] 4x6 Ox0 Specifies the duty cycle for each LED control Ox5AO output. See Figure 47 for encoding details. The LEDDutySelect[3:0] registers determine the duty cycle of the LED controller outputs Period Measure Ox5BO PMUserModeEnable 2 Ox0 User mode access enable to period measure configuration registers. When 1 user access is enabled. Controls access to PMCount, PMLastPeriod. Bit 0 - Period measure unit 0 Bit 1 - Period measure unit 1 WO 2005/120835 PCT/AU2004/000706 537 0x5B4 PMCntSrcSelect 2 Ox0 Select the counter increment source for each period measure block. When set to 0 pclk is used, when set to 1 the encoder input is used. One bit per period measure unit. Ox5B8 PMinputModeSel 2 Ox0 Select the input mode for each period measure circuit. 0- Select input 0 only 1- Select both inputs 0 and 1 (XORed together) One register per period measure block Ox5BC PMLastPeriodWrEn 2 Ox0 Enables write access to the PMLastPeriod registers. Bit 0 - Controls PMLastPeriod[0] write access Bit 1 - Controls PMLastPeriod[1J write access Ox5C0- PMLastPeriod[1:0] 2x24 Ox0000 Period Measure last period of selected input 0x5C4 pin (or pins). One bus per period measure circuit. Only writable when PMLastPeriodWrEn is 1, and access permissions are allowed (Limited Write register) Ox5DO- PMCount[1:0] 2x24 Ox0000 Period Measure running counter 0x5D4 0000 (Working register) Frequency Modifier 0x600 FMUserModeEnable 1 Ox0 User mode access enable to frequency modifier configuration registers. When 1 user access is enabled. Controls access to FM* registers. Ox604 FMBypass 1 Ox0 Specifies if the frequency modifier should be bypassed. 0 - Normal straight through mode 1 - Bypass mode Ox608 FMLsyncHigh 15 Ox0000 Specifies the number of pc/k cycles the generated frequency line sync should remain high. Only affects the line sync output through the GPIO pins to other devices. Ox60C FMLsyncDelay 15 Ox0000 Line sync delay length. Specifies the number of pc/k cycles to delay the line sync generation to the PHI. Note the line sync output to the GPIOs is unaffected. Ox610- FMFiltCoeff[4:0] 5x21 BO: Specifies the frequency modifier filter 0x620 Ox1000 coefficients. 00 Values should be expressed in sign Others: magnitude format. Sign bit is MSB. Ox0000 Bus 0- Al Coefficient 00 Bus 1- A2 Coefficient Bus 2- BO Coefficient Bus 3- B1 Coefficient Bus 4- B2 Coefficient Ox624 FMNcoFreqSrc 1 Ox0 Frequency modifier filter output bypass. When 1 the programmed FMNCOFreq is used as input to the NCO, otherwise the calculated FMNCOFiltFreq is used.
WO 2005/120835 PCT/AU2004/000706 538 0x628 FMKConst 32 OxFFFF Specifies the frequency modifier K divider FFFF constant. Value is always positive magnitude. Ox62C FMNCOFreq 24 Ox00_0 Frequency Modifier NCO value programmed 000 by the CPU. Only used when FMNcoFreqSrc is 1. Ox630 FMNCOMax 32 OxFFFF Specifies the value the NCO accumulator _FFFF wrap value. Ox634 FMNCOEnable 2 Ox0 NCO enable bits, NCO generator is enabled control. 0 - NCO is disabled 1 - NCO is enabled, with no immediate line sync 2 - NCO is disabled, immediate line sync 3 - NCO is enabled, with immediate line sync Note any write to this register will cause the NCO accumulator to be cleared. Ox638 FMFreqEst 24 0x00_0 Frequency estimate intermediate value 000 calculated by the frequency modifier the result of the FMKConstlPMLastPeriod calculation, used as input to the low pass filter (Read Only Register) 0x63C FMNCOFiltOut 24 0x00_0 Frequency Modifier calculated filter output 000 frequency value. Used as input to the NCO. (Read Only Register) 0x640 FMStatus 5 0x00 Frequency modifier status. Non-sticky bits are cleared each time a new sample is received. Sticky bits are cleared by the FMStatusClear register. 0 - Divide error (sticky bit) 1 - Filter error (sticky bit) 2 - Calculation running 3 - FreqEst complete and correct 4 - FiltOut complete and correct (Read Only Register) 0x644 FMStatusClear 2 Ox0 FM status sticky bit clear. If written with a one it clears corresponding sticky bit in the FMstatus register 0 - Divide error 1 - Filter error (Reads as zero) 0x648- FMIIRDelay[1 :0] 2x32 Ox0000 Frequency Modifier IIR filter internal delay 64C 0000 registers. CPU write to these register will overwrite the internal update within the IIR filter in the Frequency Modifier. (Working Registers) 0x650 FMDivideOutput 32 Ox0000 Output from K/P divide before saturation to 0000 24 bits. Used for debug only. (Read Only Register) 0x654 FMFilterOutput 32 Ox0000 Output from filter in signed 24.7 format 0000 before rounding to 24.0. Used for debug only. (Read Only Register) UART Control WO 2005/120835 PCT/AU2004/000706 539 0x67C UartUserModeEnable 1 Ox0 User mode access enable to the Uart configuration registers. When 1 user access is enabled. Controls access to Uart* registers. Ox680 UartControl 7 0x00 UART control register. See Table 71 for bit field description Ox684 UartStatus 15 0x06 UART status register See Table 71 for bit field description (Read Only Register) 0x688 UartlntClear 6 Ox0 UART interrupt clear register Clears the underflow, overflow, parity, framing error and break sticky bits. If written with a 1 it clears corresponding bit in the UartStatus register. 0 - TXoverflow 1 - RXunderflow 2 - RX_overflow 3 - Parity error 4 - Framing error 5 - Break (Reads as zero) Ox6BO UartIntMask 8 Ox0 UART interrupt mask register Masks the UART interrupts. If written with a 0 it masks the corresponding interrupt 0 - TXoverflow 1 - RXunderflow 2 - RXoverflow 3 - Parity error 4 - Framing error 5 - Break 6 - Tx buffer register empty 7 - New data in Rx buffer 0x68C UartScaler 16 Ox0000 Determines the baud rate used to generate the data bits. Note that frequency should be set to 8 times the desired baud-rate. 0x690- UartTXData[3:0] 4x32 Ox0000 UART Transmit buffer register. Valid bytes _x69C 0000 are determined by the register address used to access the TX buffer. Bus 0 - 1 byte valid bits[7:0] Bus 1 - 2 bytes valid bits[15:0] Bus 2 - 3 bytes valid bits[23:0] Bus 3 - 4 bytes valid bits[31:01 Ox6AO- UartRXData[3:0] 4x32 OX0000 UART receive buffer register. Valid bytes are Ox6AC 0000 indicated by bits 14:12 in the UART status register. Address used indicates how many bytes to read from RX buffer Bus 0 - Read 1 byte from RX buffer Bus 1 - Read 2 bytes from RX buffer Bus 2 - Read 3 bytes from RX buffer Bus 3 - Read 4 bytes from RX buffer Note unused bytes read as zero. For example a read of 1 byte will return bits 31:8 as zero. (Read Only Register) Miscellaneous WO 2005/120835 PCT/AU2004/000706 540 0x700- InterruptSrcSelect[15 16x6 0x00 Interrupt source select.1 register per 0x73C :0] interrupt output. Determines the source of the interrupt for each interrupt connection to the interrupt controller. Input pins to the DeGlitch circuits are selected by the DeGlitchPinSelect register. See Table 75 selection mode details. Other values are reserved and unused. Ox780 WakeUpDetected 16 OxOOO Indicates active wakeups (wakeup levels) or detected wakeup events (wakeup edges). One bit per interrupt output (gpiojicuirq[15:0J). All bits are ORed together to generate a 1-bit wakeup state to the CPR (gpio.cprzwakeup). (Read Only Register) 0x784 WakeUpDetectedClr 16 Ox0000 Wakeup detect clear register. If written with a 1 it clears corresponding WakeUpDetected bit. Note the CPU clear has a lower priority than a wakeup event. Note that if the wakeup condition is a level and still exists, the bit will remain set. This register always reads as zero. (Write Only Register) 0x788 WakeUpInputMask 16 Ox0000 Wakeup detect input mask. Masks the setting of the WakeUpDetected register bits. When a bit is set to 1 the corresponding WakeUpDetected bit is set when the wakeup condition is met. When a bit is 0 the wakeup condition is masked, and does not set a WakeUpDetected bit. Ox78C WakeUpCondition 32 Ox0000 Defines the wakeup condition used to set 0000 the WakeUpDetected register. 2 bits per interrupt output (gpioLJcu_irq[15:0J) decoded as: 00 - Positive edge detect 01 - Positive level detect 10 - Negative edge detect 11 - Negative level detect Bits 1:0 control gpioicu_irq[0], bits 3:2 control gpioJcu_irq[1] etc. Ox794 USBOverCurrentEna 3 Ox0 Enables the USB over current signals to the ble UHU block. 0 - USB Over current disabled 1 - USB Over current enabled. Ox798 SoPECSel 3 N/A Indicates the SoPEC mode selected by bondout options over 3 pads. When the 3 pads are unbonded as in the current package, the value is 111 (reads as 7). (Read Only Register) Debug Ox7EO- MCMasCount[2:0] 3x16 0x0000 Motor master clock counter values. Ox7E8 Bus 0 - Master clock count 0 Bus 1 - Master clock count 1 Bus 2 - Master clock count 2 (Read Only Register) Ox7EC DebugSelect[10:2] 9 0x00 Debug address select. Indicates the address of the register to report on the nlnin ens I iftM huI Ihen it ic nent nthonmicn WO 2005/120835 PCT/AU2004/000706 541 being used. 14.16.2.1 Supervisor and user mode access The configuration registers block examines the CPU access type (cpu acode signal) and determines if the access is allowed to the addressed register, based on configured user access registers (as shown in Table 69). 5 If an access is not allowed the GPIO issues a bus error by asserting the gpiocpuberr signal. All supervisor and user program mode accesses results in a bus error. Access to the CpuIODirection, CpuIOOut and CpuIOIn is filtered by the CpuIOUserModeMask and CpulOSuperModeMask registers. Each bit masks access to the corresponding bits in the CpuIO* registers for each mode, with CpuIOUserModeMask filtering user data mode access and Cpu!OSuperModeMask filtering 10 supervisor data mode access. The addition of the CpulOSuperModeMask register helps prevent potential conflicts between user and supervisor code read-modify-write operations. For example a conflict could exist if the user code is interrupted during a read-modify-write operation by a supervisor ISR which also modifies the CpuIO* registers. 15 An attempt to write to a disabled bit in user or supervisor mode is ignored, and an attempt to read a disabled bit returns zero. If there are no user mode enabled bits for the addressed register then access is not allowed in user mode and a bus error is issued. Similarly for supervisor mode. When writing to the CpuIOOut, CpulODirection, BLDCBrake or BLDCDirection registers, the value being written is XORed with the current value in the register to produce the new value. In the case of the CpuIOOut 20 the result is reflected on the GPIO pins. The pseudocode for determining access to the CpuIOOut[O] register is shown below. Similar code could be shown for the CpulODirection and CpuIOIn registers. if (cpuacode == SUPERVISORDATAMODE) then 25 // supervisor mode if (CpuIOSuperModeMask[0] [31:0] == 0) then // access is denied, and bus error gpio-cpu-berr = 1 elsif (cpurwn == 1) then 30 // read mode (no filtering needed) gpio-cpu-data(31:0] = CpuIOOut[0](31:0] else // write mode, filtered by mask mask[31:0] = (cpu-dataout(0][31:0] & 35 CpuIOSuperModeMask[0](31:0]) CpuIOOut[0](31:0] = (cpu-dataout[0][31:0] ^ mask(31:0]) // bitwise XOR operator elsif (cpu-acode == USERDATAMODE) then // user datamode WO 2005/120835 PCT/AU2004/000706 542 if (CpuIOUserModeMask(O][31:0] == 0) then // access is denied, and bus error gpio-cpu-berr = 1 elsif (cpurwn == 1) then 5 // read mode, filtered by mask gpio_cpudata(31:0} = ( CpuIOOut(0][31:0] & CpuIOUserModeMask[0][31:0]) else // write mode, filtered by mask mask[31:0] = (cpudataout[0][31:0) & CpuIOUserModeMask{0]{3l:0]) 10 CpuIOOut(0][31:0] = (cpudataout(0][31:0] - mask[31:0] ) // bitwise XOR operator else // access is denied, bus error gpiocpuberr = 1 15 The PMLastPeriod register has limited write access enabled by the PMLastPeriodWrEn register. If the PMLastPeriodWrEn is not set any attempt to write to PMLastPeriod register has no effect and no bus error is generated (assuming the access permissions allowed an access). The PMLastPeriod register read access is unaffected by the PMLastPeriodWrEn register is governed by normal user and supervisor access rules. 20 Table 69 details the access modes allowed for registers in the GPIO block. In supervisor mode all registers are accessible. In user mode forbidden accesses result in a bus error (gpiocpu berr asserted). Table 69. GPIO supervisor and user access modes IOModeSelect[ 63:0] Supervisor data mode only MMIPinSelect[63:0] Supervisor data mode only DeGlitchPinSelect[23:0] Supervisor data mode only 1OPinlnvert[1:0] Supervisor data mode only Reset Supervisor data mode only CPU 10 Control CpulOUserModeMask[1:0] Supervisor data mode only CpulOSuperModeMask[1:0] Supervisor data mode only CpulODirection[1:0] CpulOUserModeMask and CpulOSuperModeMask filtered CpulOOut[1:0] CpulOUserModeMask and CpulOSuperModeMask filtered CpulOln[1:0] CpulOUserModeMask and CpulOSuperModeMask filtered CpuDeGlitchUserModeMask Supervisor data mode only CpulOlnDeglitch CpuDeGlitchUserModeMask filtered. Unrestricted supervisor data mode access Deglitch control DeGlitchSelect[23:0] Supervisor data mode only DeGlitchCount[3:0] Supervisor data mode only WO 2005/120835 PCT/AU2004/000706 543 DeGlitchClkSrc[3:0] Supervisor data mode only DeGlitchFormSelect Supervisor data mode only PulseDiv[3:0] Supervisor data mode only Motor Control MCUserModeEnable Supervisor data mode only MCMasClockEnable MCUserModeEnable enabled MCCutoutEn MCUserModeEnable enabled MCMasClkPeriod[2:0] MCUserModeEnable enabled MCMasClkSrc[2:0] MCUserModeEnable enabled MCConfig[5:0] MCUserModeEnable enabled MCMasClkSelect[5:0] MCUserModeEnable enabled BLDC Motor Controllers BLDCMode MCUserModeEnable enabled BLDCDirection MCUserModeEnable enabled BLDCBrake MCUserModeEnable enabled LED control LEDUserModeEnable Supervisor data mode only LEDDutySelect[3:0] LEDUserModeEnable[3:0] enabled Period Measure PMUserModeEnable Supervisor data mode only PMCntSrcSelect[1:0] Supervisor data mode only PMlnputModeSel[1:0] Supervisor data mode only PMLastPeriodWrEn Supervisor data mode only PMLastPeriod[1:0] PMUserModeEnable[1:0] enabled, (write controlled by PMLastPeriodWrEn[1:O]) PMCount[1:0] PMUserModeEnable[1:0] enabled Frequency Modifier FMUserModeEnable Supervisor data mode only FM Bypass FMUserModeEnable enabled FMLsyncHigh FMUserModeEnable enabled FMLsyncDelay FMUserModeEnable enabled FMFiltCoeff[4:0] FMUserModeEnable enabled FMNcoFreqSrc FMUserModeEnable enabled FMKConst FMUserModeEnable enabled FMNCOFreq FMUserModeEnable enabled FMNCOMax FMUserModeEnable enabled FMNCOEnable FMUserModeEnable enabled FMFreqEst FMUserModeEnable enabled WO 2005/120835 PCT/AU2004/000706 544 FMFiltOut FMUserModeEnable enabled FMStatus FMUserModeEnable enabled FMStatusClear FMUserModeEnable enabled FMIIRDelay[1:0] FMUserModeEnable enabled FMDivideOutput FMUserModeEnable enabled FMFilterOutput FMUserModeEnable enabled UART Control UartUserModeEnable Supervisor data mode only UartControl UartUserModeEnable enabled UartStatus UattUserModeEnable enabled UartlntClear UartUserModeEnable enabled UartlntMask UartUserModeEnable enabled UartScalar UartUserModeEnable enabled UartTXData[3:0] UartUserModeEnable enabled UartRXData[3:0] UartUserModeEnable enabled Miscellaneous InterruptSrcSelect[1 5:0] Supervisor data mode only WakeUpDetected Supervisor data mode only WakeUpDetectedCir Supervisor data mode only WakeUpinputMask Supervisor data mode only WakeUpCondition Supervisor data mode only USBOverCurrentEnable Supervisor data mode only SoPECSel Supervisor data mode only 14.16.3 GPIO partition 14.16.4 LEON UART Note the following description contains excerpts from the Leon-2 Users Manual. 5 The UART supports data frames with 8 data bits, one optional parity bit and one stop bit. To generate the bit rate, each UART has a programmable 16-bit clock divider. Hardware flow-control is supported through the RTSN/CTSN hand-shake signals. Figure 51 shows a block diagram of the UART. Transmitter operation The transmitter is enabled through the TE bit in the UartControl register. When ready to transmit, data is 10 transferred from the transmitter buffer register (Tx Buffer) to the transmitter shift register and converted to a serial stream on the transmitter serial output pin (uartlxd). It automatically sends a start bit followed by eight data bits, an optional parity bit, and one stop bit. The least significant bit of the data is sent first.
WO 2005/120835 PCT/AU2004/000706 545 Following the transmission of the stop bit, if a new character is not available in the TX Buffer register, the transmitter serial data output remains high and the transmitter shift register empty bit (TSRE) will be set in the UART control register. Transmission resumes and the TSRE is cleared when a new character is loaded in the Tx Buffer register. If the transmitter is disabled, it will continue operating until the character currently being 5 transmitted is completely sent out. The Tx Buffer register cannot be loaded when the transmitter is disabled. If flow control is enabled, the uart ctsn input must be low in order for the character to be transmitted. If it is deasserted in the middle of a transmission, the character in the shift register is transmitted and the transmitter serial output then remains inactive until uartctsn is asserted again. If the uartctsn is connected to a receivers uart_rtsn, overflow can effectively be prevented. 10 The Tx Buffer is 32-bits wide which means that the CPU can write a maximum of 4 bytes at anytime. If the Tx Buffer is full, and the CPU attempts to perform a write to it, the transmitter overflow (tx overflow) sticky bit in the UartStatus register is set (possibly generating an interrupt). This can only be cleared by writing a 1 to the corresponding bit in the UartIntClear register. The CPU writes to the appropriate address of 4 TX buffer addresses (UartTXdata[3:0]) to indicate the 15 number of bytes that it wishes to load in the TX Buffer but physically this write is to a single register regardless of the address used for the write. The CPU can determine the number of valid bytes present in the buffer by reading the UartStatus register. A CPU read of any of the TX buffer register addresses will return the next 4 bytes to be transmitted by the UART. As the UART transmits bytes, the remaining valid bytes in the TX buffer are shifted down to the least significant byte, and new bytes written are added to the TX buffer 20 after the last valid byte in the TX buffer. For example if the TX buffer contains 2 valid bytes (TX buffer reads as OxOOOOAABB), and the CPU writes OxOOOOCCDD to UartTXData[O], the buffer will then contain 3 valid bytes and will read as OxOODDAABB. If the UART then transmits a byte the new TX buffer will have 2 valid bytes and will read as OxOOOODDAA. Receiver operation 25 The receiver is enabled for data reception through the receiver enable (RE) bit in the UartControl register. The receiver looks for a high to low transition of a start bit on the receiver serial data input pin. If a transition is detected, the state of the serial input is sampled a half bit clock later. If the serial input is sampled high the start bit is invalid and the search for a valid start bit continues. If the serial input is still low, a valid start bit is assumed and the receiver continues to sample the serial input at one bit time intervals (at the theoretical centre 30 of the bit) until the proper number of data bits and the parity bit have been assembled and one stop bit has been detected. The serial input is shifted through an 8-bit shift register where all bits must have the same value before the new value is taken into account, effectively forming a low-pass filter with a cut-off frequency of 1/8 system clock. During reception, the least significant bit is received first. The data is then transferred to the receiver buffer 35 register (Rx buffer) and the data ready (DR) bit is set in the UART status register. The parity and framing error bits are set at the received byte boundary, at the same time as the receiver ready bit is set. If both Rx buffer and shift registers contain an un-read character (i.e. both registers are full) when a new start bit is WO 2005/120835 PCT/AU2004/000706 546 detected, then the character held in the receiver shift register is lost and the rx overflow bit is set in the UART status register (possibly generating an interrupt). This can only be cleared by writing a 1 to the corresponding bit in the UartIntClear register. If flow control is enabled, then the uartrtsn will be negated (high) when a valid start bit is detected and the Rx buffer register is full. When the Rx buffer register is read, the uartrtsn is 5 automatically reasserted again. The Rx Buffer is 32-bits wide which means that the CPU can read a maximum of 4 bytes at anytime. If the Rx Buffer is not full, and the CPU attempts to read more than the number of valid bytes contained in it, the receiver underflow (rxunderflow) sticky bit in the UartStatus register is asserted (possibly generating an interrupt). This can only be cleared writing a 1 to the corresponding bit in the UartIntClear register. 10 The CPU reads from the appropriate address of 4 RX buffer addresses (UartRXdata[3:0]) to indicate the number of bytes that it wishes to read from the RX Buffer but the read is from a single register regardless of the address used for the read. The CPU can determine the number of valid bytes present in the RX buffer by reading the UartStatus register. The UART receiver implements a FIFO style buffer. As bytes are received in the UART they are stored in the 15 most significant byte of the buffer. When the CPU reads the RX buffer it reads the least significant bytes. For example if the Rx buffer contains 2 valid bytes (OxOOOOAABB) and the UART adds a new byte OxCC the new value will be OxOOCCAABB. If the CPU then reads 2 valid bytes (by reading UartRXData[1] address) the CPU read value will be OxOOOOAABB and the buffer status after the read will be OxOOOOOOCC. Baud-rate generation 20 Each UART contains a 16-bit down-counting scaler to generate the desired baud-rate. The scaler is clocked by the system clock and generates a UART tick each time it underflows. The scaler is reloaded with the value of the UartScaler reload register after each underflow. The resulting UART tick frequency should be 8 times the desired baud-rate. If the external clock (EC) bit is set, the scaler will be clocked by the uartextclk input rather than the system clock. In this case, the frequency of uart extclk must be less than half the frequency of 25 the system clock. Loop back mode If the LB bit in the UartControl register is set, the UART will be in loop back mode. In this mode, the transmitter output is internally connected to the receiver input and the uartrtsn is connected to the uartctsn. It is then possible to perform loop back tests to verify operation of receiver, transmitter and associated 30 software routines. In this mode, the outputs remain in the inactive state, in order to avoid sending out data. Interrupt generation All interrupts in the UART are maskable and are masked by the UartlntMask register. All sticky bits are indicated in the following table and are cleared by the corresponding bit in the UartlntClear register. The UART will generate an interrupt (uartirq) under the following conditions: WO 2005/120835 PCT/AU2004/000706 547 Table 70. UART interrupts, masks and interrupt clear bits Kim............... I... 0 Transmitter buffer register is overflowed, i.e. TX Overflow Yes Yes bit is set from 0 to 1. 1 The CPU attempts to read more than the number bytes Yes Yes that the receive buffer register holds, i.e RX Underflow bit is set from 0 to 1. 2 Receiver buffer register is full, the receive shift register is Yes Yes full and another databyte arrives, i.e. RX Overflow bit is set from 0 to 1. 3 A character arrives with a parity error, i.e. PE bit is set Yes Yes from 0 to 1. 4 A character arrives with a framing error, i.e. FE bit is set Yes Yes from 0 to 1. 5 A break occurs, i.e. BR bit is set from 0 to 1. Yes Yes 6 Transmitter buffer register moves from occupied to Yes No empty, i.e. TH bit is set from 0 to 1. 7 Receive buffer register moves from empty to occupied, Yes No i.e. DR bit is set from 0 to 1. UART status and control register bit description Table 71. Control and Status register bit descriptions 0 TX Overflow - indicates that a transmitter Receiver enable (RE) - if set, enables the overflow has occurred receiver. 1 RX Underflow - indicates that a receiver Transmitter enable (TE) - if set, enables the underflow has occurred transmitter. 2 RX Overflow - indicates that a receiver Parity select (PS) - selects parity polarity (0 = overflow has occurred even parity, 1 = odd parity) 3 Parity error (PE) - indicates that a parity Parity enable (PE) - if set, enables parity error was detected. generation and checking. 4 Framing error (FE) - indicates that a Flow control (FL) - if set, enables flow control framing error was detected. using CTS/RTS. 5 Break received (BR) - indicates that a Loop back (LB) - if set, loop back mode will be BREAK has been received enabled. 6 Transmitter buffer register empty (TH) - External clock - if set, the UART scaler will be indicates that the transmitter buffer clocked by uarLextclk register is empty 7 Data ready (DR) - indicates that new data is available in the receiver buffer register.
WO 2005/120835 PCT/AU2004/000706 548 8 Transmitter shift register empty (TSRE) indicates that the transmitter shift register is empty 9 TX buffer fill level (number of valid bytes in -- the TX buffer) 10 11 12 RX buffer fill level (number of valid bytes in the RX buffer) 13 14 14.16.5 10 control The 10 control block connects the 10 pin drivers to internal signalling based on configured setup registers and debug control signals. The IOPinInvert register inverts the levels of all gpio i signals before they get to the internal logic and the level of all gpio o outputs before they leave the device. 5 // Output Control for (i=0; i< 64 ;i++) { // do input pin inversion if needed if (iopin-invert(i} == 1) then gpio-i-var[i] = NOT(gpio-i[i]) 10 else gpio-ivar[i] = gpio-i[i] // debug mode select (pins with i > 33 are unaffected by debug) if (debugcntrl[i] == 1) then // debug mode 15 gpioe[i] = 1;gpio_o_var[i] = debugdataout(i] else // normal mode case io_mode_select[i] [6:0] is X: gpiodata[i] = xxx // see Table 72 for full connection details 20 end case // do output pin inversion if needed if (io-pin-invert[i] == 1) then gpio_o_var[i] = NOT(gpio-data[i]) else 25 gpio_o_var [iI = gpiodata(i] // determine if the pad is input or output case io_mode_select[i][12:9] is 0: outmode[i] = cpu_io_direction[il // see Table 73 for case selection details 30 end case gpio-o-var [i] // determine how to drive the pin if output if (out-mode [i] == 1 ) then 35 // see Table 74 for case selection details case iomodeselect[i](8:71 is 0: gpio_e[i] = 1 1: gpio-e[i] = 1 2: gpio-e[i = NOT(gpio_o_var[i]) 40 3: gpioe[i] = gpio-o_var[i] end case WO 2005/120835 PCT/AU2004/000706 549 else gpio-e[i] = 0 // assign the outputs gpioo(i] = gpio-o-var[i] 5 // all gpio are always readable by the CPU cpuio_in[i] = gpio_i_var[i]; I The input selection pseudocode, for determining which pin connects to which de-glitch circuit. 10 for( i=o ;i < 24 ; i++) { pin-num = deglitchpin-select[i] deglitchinput(i] = gpio-i-var[pin-num] } 15 The IOModeSelect register configures each GPIO pin. Bits 6:0 select the output to be connected to the data out of a GPIO pin. Bits 12:9 select what control is used to determine if the pin in input or output mode. If the pin is in output mode bits 8:7 select how the tri-state enable of the GPIO pin is derived from the data out or if its driven all the time. If the pin is in input mode the tri-state enable is tied to 0 (i.e. never drives). Table 72 defines the output mode connections and Table 73 and Table 74 define the tri-state mode 20 connections. Table 72. 10 Mode selection connections 10Mod e-ec[:0] gpio-vrilDsrito 3-0 led-ctr1[3:0] LED Output 4-1 9-4 mc.ctrl[5:0] Stepper Motor Control 6-1 15-10 bldc-ctrl[0][5:0] BLDC Motor Control 1,output 6-1 21-16 bldc--ctrl[1][5:0] BLDC Motor Control 2,output 6-1 27-22 bidc-ctr1[2][5:0] BLDC Motor Control 3,output 6-1 28 Issgpio-clk[O] LSS Clock 0 29 lss gpioclk[1] LSS Clock 1 30 lssgpio-dout[0] LSS data 0 31 lss gpiodout[1] LSS data 1 55-32 mmi-gpio-ctrl[23:0] MMI Control outputs 23 to 0 58-56 uhu.gpio-powerswitch USB host power switch control [2:0] 59 cpujioout[i] CPU Direct Control 60 fmjlinesync Frequency Modifier line sync pulse (undelayed version) 61 uart txd UART TX data out. 62 uartjrtsn UART request to send out 63 0 Constant 0. Select when the pin is in input mode.
WO 2005/120835 PCT/AU2004/000706 550 127-64 mmi-gpio-data[63:0] MMI data output 63-0 IOModeSelect[12:9] determines the pin direction control Table 73. Pin direction control KOMode"eet[29 outmode[i] Description 0 0 Input mode 1 1 Output mode 2 cpu-io-dir[i] Controlled by CPUIODirection[i register bit 3 Iss.gpioe[0] Controlled by the tri-state enable signals from the LSS master 0 4 Iss.gpioe[1] Controlled by the tri-state enable signals from the LSS master 1 Others N/A Unused (defaults to input mode) 15-8 mmi-gpioctrl[23: Controlled by MMI shared bits 7:0 (passed to the GPIO as 16] mmLgpioctr[23:16]) 5 IOModeSelect[8:7] determines the tri-state control when the pin is in output mode. Table 74. Output Drive mode 00 1 In output mode always drive. 01 1 Unused (default to in output mode always drive) 10 NOT(gpiooqvar[i In output mode when data out is 0, otherwise pad is tri ]) stated. 11 gpio-o-var[i] In output mode when data out is 1, otherwise pad is tri stated. In the case of when LSS data is selected for a pin N, the Issdin signal is connected to the input gpio N. If several pins select LSS data mode then all input gpios are ANDed together before connecting to the Issdin 10 signal. If no pins select LSS data mode the Iss din signal is "11". The MMIPinSelect registers are used to select the input pin to be used to connect to each gpio-mmidata output. The pseudocode is for(i=O ;i<64 ; i++) { index = mmi_pinselect[i] 15 gpiommidata[i] = gpiovar_i[index]
}
WO 2005/120835 PCT/AU2004/000706 551 14.16.6 Interrupt source select The interrupt source select block connects several possible interrupt sources to 16 interrupt signals to the interrupt controller block, based on the configured selection InterruptSrcSelect. for(i=0 ;i<16 ; i++) { 5 case interrupt-srcselect[i] gpio_icu irq[i] = input select // see Table 75 for details end case } Table 75. Interrupt source select 23 to 0 Deglitch-out[23:0] Deglitch circuit outputs 47 to 24 mmi-gpio-ctrl[23:0] MMI controller outputs 49 to 48 mmi-gpiojirq[1:0] MMI buffer interrupt sources 51 to 50 pm-int[1:0] Period Measure interrupt source 52 uartint Uart Buffer ready interrupt source 58 to 53 mcctrl[5:0] Stepper Motor Controller PWM generator outputs Others 0 Reserved 10 The interrupt source select block also contains a wake up generator. It monitors the GPIO interrupt outputs to detect an wakeup condition (configured by WakeUpCondition) and when a conditions is detected (and is not masked) it sets the corresponding WakeUpDetected bit. One or more set WakeUpDetected bits will result in a wakeup condition to the CPR. Wakeup conditions on an interrupt can be masked by setting the corresponding bit in the WakeUpInputMask register to 0. The CPU can clear WakeUpDetected bits by writing a I to the 15 corresponding bit in the WakeUpDetectedClr register. The CPU generated clear has a lower priority than the setting of the WakeUpDetected bit. // default start values wakeup-var =0 20 // register the interrupts gpio-icu-irqff = gpio_icu_irq // test each for wakeup condition for(i=0;i<16;i++)( // extract the condition 25 wakeuptype = wakeup-condition[(i*2)+l: (i*2)] case wakeup-type is 00: bitsetvar = NOT(gpio_icu-irq_ff[i]) AND gpio-icu-irq(i] // positive edge 01: bitsetvar = gpioicuirq[i} // 30 positive level 10: bit_set_var = gpioicuirqff[i] AND NOT(gpio-icu-irq[i]) // negative edge 11: bit-set-var = NOT(gpioicu_irq(i]) // negative level 35 end case WO 2005/120835 PCT/AU2004/000706 552 // apply the mask bit bit_set_var = bitsetvar AND wakeup-inputmask[i] // update the detected bit if (bitsetvar = 1) then 5 wakeup-detected(i] = 1 // set value elsif (wakeup-detected clr(i} == 1) then wakeup-detected[il = 0 // clear value else wakeup~detected[i] = wakeup-detected[i] // hold value 10 1 // assign the output gpio-cprwakeup = (wakeup-detected != OxOOO) // OR all bits together 15 14.16.7 Input deglitch logic The input deglitch logic rejects input states of duration less than the configured number of time units (deglitchcnt), input states of greater duration are reflected on the output deglitchout. The time units used (either pclk, Is, 100s, Ims) by the deglitch circuit is selected by the deglitch_clk_src bus. There are 4 possible sets of deglitch cnt and deglitch_clk_src that can be used to deglitch the input pins. The 20 values used are selected by the deglitch sel signal. There are 24 deglitch circuits in the GPIO. Any GPIO pin can be connected to a deglitch circuit. Pins are selected for deglitching by the DeGlitchPinSelect registers. Each selected input can be used in its deglitched form or raw form to feed the inputs of other logic blocks. The deglitchform select signal determines which form is used. 25 The counter logic is given by if (deglitch input != deglitch inputff) then cnt = deglitchcnt output-en = 0 elsif (cnt == 0 ) then 30 cnt = cnt output-en = 1 elsif (cnt-en == 1) then cnt output-en = 0 35 In the GPIO block GPIO input pins are connected to the control and data inputs of internal sub-blocks through the deglitch circuits. There are a limited number of deglitch circuits (24) and 46 internal sub-block control and data inputs. As a result most deglitch circuits are used for 2 functions. The allocation of deglitch circuits to functions are fixed, and are shown in Table 76. 40 Note that if a deglitch circuit is used by one sub-block, care must be taken to ensure that other functional connection is disabled. For example if circuit 9 is used by the BLDC controller (bldcha[0]), then the MMI block must ensure that is doesn't use its control input 4 (mmi_ctrlin[4]).
WO 2005/120835 PCT/AU2004/000706 553 Table 76. Deglitch circuit fixed connection allocation Circuit Functional Functnld l No. Connection A Connection BDecpto 0 pm_pin[0][0] N/A Period Measure 0 input 0 (connected via pulse divider) 1 pmcpin[0][1] N/A Period Measure 0 input 1 (connected via pulse divider) 2 pmpin[1][0] gpio-mmi-ctrl[ Period Measure 1 input 0 (connected via pulse 0] divider) MMI control input 3 pm-pin[1][1] gpio -mmi -ctrl[ Period Measure 1 input 1 (connected via pulse 1] divider) MMI control input 4 gpio-mmi-ctrl[ MMI control input 2] 5 gpio-uduvbus~sta gpio-mmi-ctrl[ USB device Vbus status tus 3] MMI control input 6 cut-out[0] cutout[l] Stepper Motor controller phase generator 0 and 1 7 cut-out[2] cutout[3] Stepper Motor controller phase generator 2 and 3 8 cut_out[4] cutout[5] Stepper Motor controller phase generator 4 and 5 9 bldc-ha[O] gpio-mmi-ctrl[ BLDC controller 1 hall A input 4] MMI control input 10 bldchb[O] gpio mmi ctrl[ BLDC controller 1 hall B input 5] MMI control input 11 bldc-hc[0] gpio-mmi-ctrl[ BLDC controller 1 hall C input 6] MMI control input 12 bldc-ext dir[0] gpio-mmi ctrl[ BLDG controller 1 external direction input 7] MMI control input 13 bldc-ha[1] gpio-mmi-ctrl[ BLDC controller 2 hall A input 8] MMI control input 14 bldc-hb[1] gpio-mmi-ctrl[ BLDC controller 2 hall B input 9] MMI control input 15 bldc-hc[1] gpio-mmi-ctrl[ BLDC controller 2 hall C input 10] MMI control input 16 bldcext-dir[1] gpio-mmi-ctrl[ BLDC controller 2 external direction input 11] MMI control input 17 bldc-ha[2] uartctsn BLDC controller 3 hall A input UART control input 18 bldc-hb[2] uartrxd BLDC controller 3 hall B input UART data input 19 bldc-hc[2] uart_extclk BLDC controller 3 hall C input UART external clock 20 bldc.ext-dir[2] gpio-mmi-ctrl[ BLDC controller 3 external direction input 12] MMI control input 21 gpiouhuovercur gpio..mmi-ctrl[ USB Over current, only when enabled by rent[0] 13] USBOverCurrentEnable]. MMI control input WO 2005/120835 PCT/AU2004/000706 554 22 gpio uhuover..cur gpio mmi_ctrl[ USB Over current, only when enabled by rent[1] 14] USBOverCurrentEnable[1]. MMI control input 23 gpiouhuover-cur gpio-mmi-ctrl[ USB Over current, only when enabled by rent[2] 15] USBOverCurrentEnable[2]. MMI control input There are 4 deglitch circuits that are connected through pulse divider logic (circuits 0,1,2 and 3). If the pulse divider is not required then they can be programmed to operate in direct mode by setting PulseDiv register to 0. 5 14.16.7.1 Pulse Divider The pulse divider logic divides the input pulse period by the configured PulseDiv value. For example If PulseDiv is set to 3 the output is divided by 3, or for every 3 input pulses received one is generated. The pseudocode is shown below: if (pulse-div != 0 ) then // period divided filtering 10 if (pin-in AND NOT pin-in-ff) then // positive edge detect if (pulse-cnt-ff == 1 ) then pulsecntff = pulse div pin-out = 1 else 15 pulse_cnt_ff = pulse-cnt-ff - 1 pin-out = 0 else pin-out = 0 else 20 pin-out = pin-in // direct straight through connection 14.16.8 LED pulse generator The LED pulse generator is used to generate a period of 128ps with programmable duty cycle for LED control. The LED pulse generator logic consists of a 7-bit counter that is incremented on a 1 gs pulse from the timers block (tim_pulse[O]). The LED control signal is generated by comparing the count value with the 25 configured duty cycle for the LED (led duty sel). The logic is given by: for (i=0 i<4 ;i++) { // for each LED pin // period divided into 64 segments period-div64 = cnt(6:1]; 30 if (perioddiv64 < leddutysel[i)) then led_ctrl[i] = 1 else led_ctrl[i] = 0 35 // update the counter every lus pulse if (tim_pulse[0] == 1) then cnt ++ WO 2005/120835 PCT/AU2004/000706 555 14.16.9 Stepper Motor control The motor controller consists of 3 counters, and 6 phase generator logic blocks, one per motor control pin. The counters decrement each time a timing pulse (cnt en) is received. The counters start at the configured clock period value (mc mas clk_period) and decrement to zero. If the counters are enabled (via 5 mcmas_clk_enable), the counters will automatically restart at the configured clock period value, otherwise they will wait until the counters are re-enabled. The timing pulse period is one of pclk, l s, 100s, Ims depending on the mc masclksrc signal. The counters are used to derive the phase and duty cycle of each motor control pin. // decrement logic 10 if (cnt-en == 1) then if ((mas-cnt == 0) AND (mc mas_clk_enable == 1)) then mas_cnt = mcmas-clkperiod[15:0] elsif ((mas_cnt == 0) AND (mcmasclkenable == 0)) then mas-cnt = 0 15 else mascnt else // hold the value mascnt = mas-cnt The phase generator block generates the motor control logic based on the selected clock generator 20 (mc-mas-clk-sel) the motor control high transition point (curr mc high) and the motor control low transition point (currmclow). The phase generator maintains current copies of the mcconfig configuration value (mc config[31:16] becomes currmc high and mc config[15:0] becomes currmclow). It updates these values to the current register values when it is safe to do so without causing a glitch on the output motor pin. 25 Note that when reprogramming the mc config register to reorder the sequence of the transition points (e.g changing from low point less than high point to low point greater than high point and vice versa) care must taken to avoid introducing glitching on the output pin. The cut-out logic is enabled by the mc cutout en signal, and when active causes the motor control output to get reset to zero. When the cut-out condition is removed the phase generator must wait for the next high 30 transition point before setting the motor control high. There is fixed mapping of the cutout input of each phase generator to deglitch circuit, e.g. deglitch 13 is connected to phase generator 0 and 1, deglitch 14 to phase generator 2 and 3, and deglitch 15 to phase generator 4 and 5. There are 6 instances of phase generator block one per output bit. 35 The logic is given by: // select the input counter to use case mc_mas_clk_sel[1:0] then 0: count = mascnt[0] 1: count = mascnt[l] 40 2: count = mas_cnt[2] 3: count = 0 WO 2005/120835 PCT/AU2004/000706 556 end case // Generate the phase and duty cycle if (cut-out = 1 AND mccutouten = 1) then mcctrl = 0 5 elsif (count == currmclow) then mc-ctrl = 0 elsif (count == curr_mc_high) then mcctrl = 1 else 10 mc-ctrl = mc-ctrl // remain the same // update the current registers at period boundary if (count == 0) then currmchigh = mcconfig[31:16] // update to new high value curr_mclow = mc-config[15:0] // update to new high value 15 14.16.10 BLDC Motor Controller The BLDC controller logic is identical for all instances, only the input connections are different. The logic implements the truth table shown in Table 66. The six q outputs are combinationally based on the direction, ha, hb, hc, brake and pwm inputs. The direction input has 2 possible sources selected by the mode. The 20 pseudocode is as follows // determine if in internal or external direction mode if (mode == 1) then // internal mode direction = intdirection else // external mode 25 direction = extdirection By default the BLDC controller reset to internal direction mode. The direction control is defined with 0 meaning counter clockwise, and 1 meaning clockwise. 14.16.11 Period measure The period measure block monitors 1 or 2 selected deglitched inputs (deglitch out) and detects positive edges. 30 The counter (PMCount) either increments every pclk cycle between successive positive edges detected on the input, or increments on every positive edge on the input, and is selected by PMCntSrcSel register. When a positive edge is detected on the monitored inputs the PMLastPeriod register is updated with the counter value and the counter (PMCount) is reset to 1. The pm int output is pulsed for a one clock each time a positive edge on the selected input is detected. It is 35 used to signal an interrupt to the interrupt source select sub-block (and optionally to the CPU), and to indicate to the frequency modifier that the PMLastPeriod has changed. There are 2 period measure circuits available each one is independent of the other. The pseudocode is given by // determine the input mode 40 case (pminputmode-sel) is 0: inputpin = inO / direct input 1: input-pin = inO ^ inl XOR gate, 2 inputs end case WO 2005/120835 PCT/AU2004/000706 557 // monitored edge detect mon_edge = (input-pin == 1) AND input-pin ff == 0) // monitor positive edge detected // implement the count 5 if (pmncnt-src-sel == 1) then // direct count mode if (monedge == 1)then // monitor positive edge detected pmjlastperiod[23:0) = pm_count[23:0] // update the last period counter 10 pint = 1 pmLcount[23:0] = pmcount[23:0} + 1 else // pclk count mode if (mon-edge == 1)then // monitor positive edge detected 15 pmlastperiod[23:0) = pmcount[23:0] // update the last period counter pmint = 1 pmcount{23:O] = 1 else 20 pmcount[23:0] = pmcount(23:0] + 1 // implement the configuration register write (overwrites logic calculation) if (wrlastperioden == 1) then pm.lastperiod = wrdata 25 elsif (wr-count-en == 1) then pmcount = wr-data 14.16.12 Frequency Modifier The frequency modifier block consists of 3 sub-blocks that together implement a frequency multiplier. 14.16.12.1 Divider filter logic 30 The divider filter block performs the following division and filter operation each time a pulse is detected on the pm_int from the period measure block. if (pmint ==l) then fm-freqest[23:0] =(fm-kconst[31:01 / pm last-count[23:0]) // calculate the filter based on co-efficient 35 fm-tmp[31:0] = fmfregaest + A1[20:0) * fmdel[0)[31:0] + A2[20:0] * fmdel[1] [31:0] // calculate the output fmfiltout[23:0] = BO(20:0]*fmtmp[31:0] + Bl[20:0]*fm_del[0] [31:0] + B2[20:0]*fm-del[1] [31:0] 40 // update delay registers fmde(1] (31:0] = fm-del[0] [31:0] fmdel[0][31:0] = fm-tmp[31:0] I The implementation includes a state machine controlling an adder/subtractor and shifter to execute 3 basic 45 commands * Load, used for moving data between state elements (including shifting) * Divide, used for dividing 2 number of positive magnitude * Multiply, multiplies 2 numbers of positive or negative magnitude WO 2005/120835 PCT/AU2004/000706 558 Add/Subtract, add or subtract 2 positive or negative numbers The state machine implements the following commands in sequence, for each new sample received. With the current example implementation each divide takes 33 cycles, each multiply 21 cycles. An add or subtract 5 takes I cycle, and each load takes 1 cycle. With the simplest implementation (i.e. one load per cycle) the total number of cycles to complete the calculation offinfilt_out is 160, 1 divide (33), 5 multiplies (100), 4 add/sub (4) and 23 loads instructions (23), or maximum frequency of 1.2 MHz which is much faster than the expected sample frequency of 20Khz. Its possible that the calculation frequency could be increased by adding more muxing hardware to increase the number of loads per cycle, or by combining multiply and add operations at 10 the slight increase in accumulator size. Table 77. State machine operation flow Idle None aisfo rin-= LoadDiv Load fm -operb =pmn_last~count Lasu prn o iiefnto fm-acc =fm-k-const Div Divide fmacc = (fm-acc / fm.operb) Divide the fm acc / fm...operb over 33 cycles. See divide description below LoadA2 Load fm freq_est = fmacc Stores the divide result fm acc and loads up fmoperb = fm-coeff[l] the operands for the A2 coefficient fm.acc = fm-del[l] multiplication. MultA2 Mult fmacc = (fm-acc * fm-operb) Multiplies the fmracc and fmoperb and stores the result in fm-acc. Takes 20 cycles. See multiply description LoadAl Load fmjtmp = fm-acc Stores the multiply result fmacc and loads fm...operb = fmscoeff[0] up the operands for the Al coefficient fmacc = fm.del[0] multiplication. MultAl Mult fm-acc = (fmacc * fm-operb) Multiplies the fmacc and fmj perb and ______________________stores the result in fm-acc. Takes 20 cycles. AddAlA2 Add/S fmacc = +/- fmacc +/-Add/subtracts the fmacc and fmjmp and ub fmjtmp stores the result in Fm acc. The add or subtract, and result is dependent on the sign of the inputs. See Add/Sub description. AddFest Add/S fm acc = -/+ fmacc +/-Add/subtracts the fm acc and fm.freqest ub fmfreq-est and stores the result in fm-aco. The add or subtract, and result is dependent on the sign of the inputs. See Add/Sub description. LoadB2 Load fm_tmp = fnacc Stores the result in fm..acc in the temporary fmoperb = fm.coeff[4] register fmjmp. Loads up the operands for fm acc = fmdel[l] the B2 coefficient multiplication. MultB2 Mult finacc = (fm-acc * fm-operb) Multiplies Fmnacc and fm.operb and stores ______________________the result in fmoacc. LoadB1 Load fmdel[l] = fmacc Stores the result in fmacc in the delay fmoperb = fm-coeff[3] register fi-del[l]. Loads up the operands __________ fmacc = fm del[0] for the B coefficient multiplication. MuItBi Mult finmacc = (fmnacc * fioperb) Multiplies fm - acc and fm.operb and stores I__store the result in fmmacc. Takes 20 cycles.
WO 2005/120835 PCT/AU2004/000706 559 AddB1 B2 Add fm_acc = +/- fm.acc +/- Adds the coefficient B2 result (which was fm-del[1] stored in the delay register) with the coefficient B1 result. The calculation result is stored in fm acc. LoadBO Load fmdel[1] = fmacc Stores the result in fmacc in the delay fm..operb = fmscoeff[2] register fm-del[1]. Loads up the operands fmacc = fmjtmp for the B0 coefficient multiplication. MultBO Mult fm.acc = (fm-acc * fm-operb) Multiplies fm acc and fm.operb and stores the result in fmacc. AddBO Add/S fm_acc = +/- fmacc +/- Adds the coefficients B2 81 result (which ub fm-del[1] was stored in the delay register) with the coefficient B0 result. The calculation result is stored in fm acc. LoadOut Load fmfilt_out = fmacc Performs the delay line shift and loads the fmdel[0] = fmjtmp output register with the result. fm-del[1] = fm-del[0] Divide Operation The divide operation is implemented with shift and subtract serial operation over 33 cycles. At startup the LoadDiv state loads the accumulator and operand B registers with the dividend (fin_k_const) and the divisor 5 (pm last period) calculated by the period measure block. For each cycle the logic compares a shifted left version of the accumulator with the divisor, if the accumulator is greater then the next accumulator value is the shifted left value minus the divisor, and the calculated quotient bit is 1. If the accumulator is less than the divisor then accumulator is shifted left and the calculated quotient bit is zero. 10 The accumulator stores the partial remainder and the calculated quotient bits. With each iteration the partial remainder reduces by one bit and the quotient increases by one bit. Storing both together allows for constant minimum sized register to be used, and easy shifting of both values together. As the division remainder is not required it is possible the quotient register can be combined with the acumalator. 15 The pseudocode is: // load up the operands fmwacc[31:0] = fm_k_const[31:0] // load the divisor fmoperb[23:0] = {pm_lastperiod[23:0]} 20 for (i=0;i<33; i++) ( // calculate the shifted value shift-test[32:0]:= {fm-acc[63:32] & 0 // check for overflow or not if (shift-test(32:0] < fm-operb[31:0]) then // subtract zero and shift 25 fmacc[63:0] = (fmiacc[62:0] & 0 3 I/ quotient bit is 0 else // sub fm_operb and shift fmans[31:0] = shift_test[31:0] - fmoperb[31:0] 30 fmacc[63:0] = <fm-ans[31:0] & fnLacc[30:0] & 1 3 // quotient bit is 1 WO 2005/120835 PCT/AU2004/000706 560 } // bottom 32 bits contain the result of the divide, saturated to 24 bits if (fm-acc[31:25] != 0) then fm-acc[23:0] = OxFFFFFF // saturate case 5 The accumulator register in this example implementation could be reduced to 56 bits if required. The exact implementation will depend on other uses of the adder/ shift logic within this block. Multiply Operation In the frequency modifier block the low pass filter uses several multiply operations. The multiply operations are all similar (except in how rounding and saturation are performed). All internal states and coefficients of 10 the filter are in signed magnitude form. The coefficients are stored in 21 bits, bit 20 is the sign and bits 19:0 the magnitude. The magnitude uses fixed point representation 1.19. The internal states of the filter use 32 bits, one sign bit and 31 magnitude bits. The fixed point representation is 24.7. The multiply is implemented as a series of adds and right shifts. 15 // loads up the operands fmacc[19:0] = fmcoeff[A [19:0] fn_acc_s = fm-coeff[A](20] // loads operand B fmoperb[30:0] fmdel[1](30:0] 20 fmoperbs = fmdels[l] [31] for (i=0; i<20;i++) { if ( fm-acc[0] == 0) then // add 0 fmnans(32:0] = fm-acc(63:32] + 0 25 else // add coefficient fmans[32:0] = fm-acc[63:32] + fmoperb[31:0] // do the shift before assigning new value fm-acc[63:0] = {fmans[32:0] & fm-acc[31:1]} } 30 // shift down the acc 12 bits fm_acc[63:0] = (fnacc[63:0] >> 12) // calculate the sign fmacc_s = fmaccs XOR fm-operb-s // round the minor bits to 24.7 representation 35 if ((fmacc[18:0] > 0x40000)then fmacc[63:0] = (fm-acc[63:0] >> 19) + 1 else fm-acc(63:0] = (fmacc[63:0] >> 19) 40 // saturate test if (fmn acc[63:31] != 0) then // any upper bit is 1 fm-acc[30:0] = OxFFFF_FFFF // assign the sign bit fm-acc[31} = fm_acc_s 45 Addition/Subtraction The basic element of both the multiplier and divider is a 32 bit adder. The adder has 2's complement units added to enable easy addition and subtraction of signed magnitude operands. One complement unit on the B WO 2005/120835 PCT/AU2004/000706 561 operand input and one on the adder output. Each operand has an associated sign bit. The sign bits are compared and the complement of the operands chosen, to produce the correct signed magnitude result. There are four possible cases to handle, the control logic is shown below 5 // select operation sel[1:0] = fmacc-s & fmoperb_s // case determines which operation to perform case (sel) 00: // both positive 10 ffmans = fm_acc + fm-operb fnanss = 0 01: // operb neg, acc pos if (fm_operb > fmacc) fans = 2scomplement(fmacc + 2scomplement(fmoperb)) 15 fmans-s = 1 else fans = fnacc + 2scomplement(fm_operb) fmanss = 0 10: // acc neg, operb pos 20 if (fmacc > fmoperb) fans = 2s-complement(fmacc + 2scomplement(f moperb)) fmanss = 1 else fans = fmacc + 2s-complement(fmoperb) 25 fmans-s = 0 11: // both negative fmens = fmacc + fmoperb fmanss = 1 endcase 30 The output from the addition is saturated to 32 bits for divide and multiply operations and to 31 bits for explicit addition operations. FMStatus Error Bits 35 The Divide Error is set whenever saturation occurs in the K/P divide. This includes divide by zero. The Filter Error is set whenever saturation occurs in any addition or multiplication or if a divide error has occurred. Both bits remain set until cleared by the CPU. The other status bits reflect the current status of the filter. 40 14.16.12.2 Numerical Controlled Oscillator (NCO) The NCO generates a one cycle pulse with a period configured by the FMNCOMax and either the calculated fin filt_out value, or the CPU programmed FMNCOFreq value. The configuration bit FMFiltEn controls WO 2005/120835 PCT/AU2004/000706 562 which one is selected. If 3 is written to the FMNCOEnable register a leading pulse is generated as the accumulator is re-enabled. If 1 is written no leading edge is generated. The pseudo code // the cpu bypass enabled 5 if (fm-nco-freq-src == 1) then filtvar = fmfiltout else filtvar = fm-nco-freq // update the NCO accumulator 10 nco_var = nco_ff + filtvar // temporary compare nco-accum-var = ncovar - fm_nco_max // cpu write clears the nco, regardless of value if (cpufmncoenablewrendelay == 1) then 15 nco-ff = 0 ncoedge = fm_nco_enable[1] // leading edge emit pulse elsif (fm-nco-enable[0] == 0) then nco-ff = 0 20 nco_edge = 0 elsif ( nco-accumuvar > 0 ) then ncoff = nco-accumvar nco-edge = 1 else 25 nco_ff = nco_var nco-edge = 0 14.16.12.3 Line sync generator The line sync generator block accepts a pulse from either the numerical controlled oscillator (nco-edge) or 30 directly from the period measure circuit 0 (pm int) and generates a line sync pulse of FMLsyncHigh pclk cycles called finlinesync. The fin bypass signal determines which input pulse is used.It also generates a gpio_phi linesync line sync pulse a delayed number of cycles (finlsyncdelay) later, note that the gpio_phi line sync pulse is not stretched and is 1 pclk wide.Line sync generator diagram The line sync generate logic is given as 35 // the output divider logic // bypass mux if (fmbypass == 1) then pin-in = pm_int // direct from the period measure 0 40 else pin-in = nco-edge // direct from the NCO // calculate the positive edge edgedet = pin-in AND NOT (pin-injff) 45 // implement the line sync logic if (edge-det == 1) then lsynccnt_ff = fm_lsynchigh delay_ff = fm_lsync-delay else 50 if (lsync_cnt_ff != 0 ) then WO 2005/120835 PCT/AU2004/000706 563 lsync-cntff = lsync-cnt-ff - 1 if (delayff 0 ) then delay-ff = delayff - 1 // line sync stretch 5 if (lsync-cnt-ff == 0 ) then fmline-sync = 0 else fm line-sync = 1 // line sync delay, on delay transition from 1 to 0 or edge-det if delay is zero 10 if ((delay_ff == 1 AND delay nxt = 0) OR (fmlsync delay = 0 AND edgedet = 1)) then gpiophi_line_sync = 1 else gpiophiline-sync = 0 15 15 MULTIPLE MEDIA INTERFACE (MMI) The MMI provides a programmable and reconfigurable engine for interfacing with various external devices using existing industry standard protocols such as e Parallel port, (Centronics, ECP, EPP modes) 20 e PECI HSI interface * Generic Motorola 68K Microcontroller I/F e Generic Intel i960 Microcontroller I/F * Serial interfaces, such as Intel SBB, Motorola SPI, etc. e Generic Flash/SRAM Parallel interface 25 * Generic Flash Serial interface * LSS serial protocol, 12C protocol The MMI connects through GPIO to utilize the GPIO pins as an external interface. It provides 2 independent configurable process engines that can be programmed to toggle GPIOs pins, and control RX and TX buffers. The process engines toggle the GPIOs to implement a standard communication protocol. It also controls the 30 RX or TX buffer for data transfer, from the CPU or DRAM out to the GPIO pins (in the TX case) or from the GPIO pin to the CPU or DRAM in the RX case. The MMI has 64 possible input data signals, and can produce up to 64 output data signals. The mapping of GPIO pin to input and/or output signal is accomplished in the GPIO block. The MMI has 16 possible input control signals (8 per process engine), and 24 output control signals (8 per 35 process engine and 8 shared). There is no limit on the amount of inputs, or outputs or shared resources that a process engine uses, but if resources are over allocated care must be taken when writing the microcode to ensure that no resource clashes occur. The process engines communicate to each other through the 8 shared control bits. The shared controls bits are flags that can be set/cleared by either process engine, and can be tested by both process engines. The shared 40 control bits operate exactly the same as the output control bits, and are connected to the GPIO and can be optionally reflected to the GPIO pins.
WO 2005/120835 PCT/AU2004/000706 564 Therefore each process engine has 8 control inputs, 8 control outputs and 8 shared control bits that can be tested and particular action taken based on the result. The MMI contains 1 TX buffer, and 1 RX buffer. Either or both process engines can control either or both buffers. This allows the MMI to operate a RX protocol and TX protocol simultaneously. The MMI cannot 5 operate 2 RX or 2 TX protocols together. In addition to the normal control pin toggling support, the MMI provides support for basic elements of a higher level of a protocol to be implemented within a process engine, relieving the CPU of the task. The MMI has support for parity generation and checking, basic data compare, count and wait instructions. The MMI also provides optional direct DMA access in both the TX and RX directions to DRAM, freeing the 10 CPU from the data transfer tasks if desired. The MMI connects to the interrupt controller (ICU) via the GPIO block. All 24 output control pins and 2 buffer interrupt signals (mmigpio irq[1:0]) are possible interrupt sources for the GPIO interrupts. The mmigpioirq[1] refers to the RX buffer interrupt and the mmisgpioirq[0] the TX buffer interrupt. The buffer interrupts indicate to the CPU that the buffer needs to be serviced, i.e. data needs to transferred from 15 the RX or to the TX using the DMA controller or direct CPU accesses. 15.1 EXAMPLE PROTOCOLS SUMMARY Table 78. Summary of control/pin requirements for various communication protocols Protcol nmeof number o number of bi- aress/ Tmcnto cnro utus is data bus Notes inputs sze bus' PEC1 HSI 1 busy 1 data write, 0 0 Write only mode 1 select per address/8 device data Parallel Port 1 busy, 1 data strobe 0 8 Unidirectional (Centronics) 1 ack only SoPEC receive mode Parallel Port 1 data strobe 1 busy, 0 8 Unidirectional (Centronics) 1 ack only SoPEC transmit mode Parallel Port 1 busy/wait 1 write, 8 (data/add 8 Bi-directional. (EPP) 1 ack/interrupt 1 add strobe, bus) 1 data strobe 1 reset line Parallel Port 1 Peripheral 1 host clk 8 (data/add 8 Bi-directional. (ECP) clk 1 host ack bus) 1 peripheral 1 select/ active ack 1 reverse request 1 ack reverse 1 Select/Xflag 1 Peripheral req WO 2005/120835 PCT/AU2004/000706 565 68K 1 1 add strobe, 16 (data bus) up to 19 In synchronous acknowledge 1 R/W select address, mode extra bus 2 Data strobe 16 data clock required. Address bus can be any size. i960 1 ready/wait 1 address strobe 32 (data bus) up to 32 Several Bus 1 write/read address, access types select 8/16/32 possible 1 wait data bus 1/2 Clocks 2/4 byte selects Intel Flash 1 wait 1 address valid, 8/16/32 (data up to 24 Asynchronous/sy 1 chip select per bus) address nchronous, burst device 8/16/32 and page modes 1 output enable data bus available 1 write enable 1 clock 2 optional byte enable (AO,A1) x86 (386) 1 ready 1 add strobe 16 (data bus) 8/16 data 1 next 1 read/write bus address select up to 24 2 byte enables address 1 data/control select 1 memory select Motorola SPI 1 clock, 1 data Could apply to Intel SBB 1 reset any serial interface 15.1 In the diagrams below all SoPEC output signals are shown in bold. 15.1.1 PECI HSI 15.1.2 Centronics Interface 5 Setup data e Sample busy and wait until low * If not busy then assert the nstrobe line * De-assert the n strobe control line. * Sample nack low to complete transfer 10 15.1.3 Parallel EPP mode Data Write Cycle * Start the write cycle by setting niow low * Setup data on the data line and set nwrite low * Test the n wait signal and set ndatastrobe when n wait is low 15 - Wait for n wait to transition high " Then set ndatastrobe high * Set n_write and n-iow high * Wait for nwait to transition low before starting next transfer WO 2005/120835 PCT/AU2004/000706 566 Address Read Cycle e Start the read cycle by setting nior low e Test the n wait signal and set nadrstrobe low when nwait is low e Wait for n wait to transition high 5 0 Sample the data word * Set nadrstrobe and n-ior high to complete the transaction * Wait for n wait to transition low before starting next transfer 15.1.4 Parallel ECP Mode Forward data and command cycle 10 * Host places data on data bus and sets hostack high to indicate a data transfer e Host asserts host clk low to indicate valid data e Peripheral acknowledges by setting periph ack high e Host set host_clk high e Peripheral set periphack low to indicate that it's ready for next byte 15 e Next cycle starts Reverse data and command cycle * Host initiates reverse channel transfer by setting nreversereq low * The peripheral signals ok to proceed by setting n ack reverse low 20 - The peripheral places data on the data lines and indicates a data cycle by setting periph ack high * Peripheral asserts periph clk low to indicate valid data * Host acknowledges by setting host ack high e Peripheral set periph clk high, which clocks the data into the host * Host sets hostack low to indicate that it is ready for the next byte 25 - Transaction is repeated e All transactions complete, host sets nreverse req high e Peripheral acknowledges by setting n ack reverse high 15.1.5 68K Read and Write transaction Read cycle example 30 e Set FC code and rwn signal to high * Place address on address bus e Set address strobe (asn) to low, and set udsn and Idsn as needed 0 Wait for peripheral to place data on the data bus and set dackn to low * Host samples the data and de-asserts as_n,udsn and Ids_n 35 * Peripheral removes data from data bus and de-asserts dack_n Write cycle * Set FC code and rwn signal to high e Place address on address bus, and data on data bus * Set address strobe (asn) to low, and set udsn and Idsn as needed 40 e Wait for peripheral to sample the data and set dackn to low e Host de-asserts as_n,udsn and ids_n, set rwn to read and removes data from the bus * Peripheral set dack_n to high WO 2005/120835 PCT/AU2004/000706 567 15.1.6 i960 Read and Write example transaction 15.1.7 Generic Flash interface There are several type of communication protocols to/from flash, (synchronous, asynchronous, byte, word, page mode, burst modes etc.) the diagram above shows indicative signals and a single possible protocol. 5 Asynchronous Read * Host set the address lines and brings address valid (adv n) low * Host sets chip enable low (ce n) * Host set adv-n high indicating valid data on the address line. * Peripheral drives the wait low 10 0 Host sets output enable oen low e Peripheral drive data onto the data bus when ready * Peripheral sets wait to high, indicating to the host to sample the data e Hosts set cen and oe-n high to complete the transfer Asynchronous write 15 e Host set the address lines and brings address valid (advn) low * Host sets chip enable low (ce n) * Host set adv n high indicating valid data on the address line. * Host sets write enable wen low, and sets up data on the bus * After a predetermined time host sets wen high, to signal to the peripheral to sample the data 20 0 Host completes transfer by setting ce-n high 15.1.8 Serial Flash interface Serial Write process e Host sets chip select low (csn) * Host send 8 clocks cycles with 8 instruction data bits on each positive edge 25 e Device interprets the instruction as a write, and accepts more data bits on clock cycles generated by the host * Host terminates the transaction by setting csn high Serial Read process e Host sets chip select low (csn) 30 e Host send 8 clocks cycles with 8 instruction data bits on each edge e Device interprets the instruction as a read, and sends data bits on clock cycles generated by the host * Host terminates the transaction by setting csn high 15.2 IMPLEMENTATION 15.2.1 Definition of 10 Table 79. MMI I/O definitions 66 mmk,.14 1 MLM* -W .EWM I Clocks and Resets Pclk 1 In System Clock WO 2005/120835 PCT/AU2004/000706 568 prstn 1 In System reset, synchronous active low MMI to GPIO mmi-gpiosctrl[23:0] 24 Out MMI General Purpose control bits output to the GPIO.All bits can be directly connected to pins in the GPIO. In addition, each of bits 23:16 can be used within the GPIO to control whether particular pins are input or output, and if in output mode, under what conditions to drive or tri-state that pin. gpio-mmictrl[15:01 16 In MMI General Purpose control bits input from the GPIO mmi-gpio-data[63:0] 64 Out MMI parallel data out to the GPIO pins gpio mmidata[63:0] 64 In MMI parallel data in from selected GPIO pins mmi-gpio_irq[1:0] 2 Out MMI interrupts for muxing out through the GPIO interrupts. Indicates the corresponding buffer needs servicing (either a new DMA setup, or CPU must read/write more data). 0 - TX buffer interrupt 1 - RX buffer interrupt CPU Interface cpu-adr[10:2] 9 In CPU address bus. Only 9 bits are required to decode the address space for this block cpu-dataout[31:0] 32 In Shared write data bus from the CPU mmi-cpu-data[31:0] 32 Out Read data bus to the CPU cpurwn 1 In Common read/not-write signal from the CPU cpummisel 1 In Block select from the CPU. When cpu.mmi sel is high both cpu.adr and cpuLdataout are valid mmi-cpu-rdy 1 Out Ready signal to the CPU. When mmi_cpu..rdy is high it indicates the last cycle of the access. For a write cycle this means cpu.dataout has been registered by the MMI block and for a read cycle this means the data on mmi cpudata is valid. mmi-cpu-berr 1 Out Bus error signal to the CPU indicating an invalid access. mmicpudebug_valid 1 Out Debug Data valid on micpudata bus. Active high cpu.acode[1:0] 2 In CPU Access Code signals. These decode as follows: 00 - User program access 01 - User data access 10 - Supervisor program access 11 - Supervisor data access DIU Read interface mmidiu-rreq 1 Out MMI unit requests DRAM read. A read request must be accompanied by a valid read address. mmi-diu-radr[21:5] 17 Out Read address to DIU, 256-bit word aligned. diummirack 1 In Acknowledge from DIU that read request has been accepted and new read address can be placed on mmi diuradr diummirvalid 1 In Read data valid, active high. Indicates that valid read data is now on the read data bus, diudata. diu-data[63:0] 64 In Read data from DIU.
WO 2005/120835 PCT/AU2004/000706 569 DIU Write Interface mmidiuwreq 1 Out MMI requests DRAM write. A write request must be accompanied by a valid write address together with valid write data and a write valid. mmi-diu-wadr[21:5] 17 Out Write address to DIU 17 bits wide (256-bit aligned word) diu-mmi-wack 1 In Acknowledge from DIU that write request has been accepted and new write address can be placed on mmi diuwadr mmidiudata[63:0] 64 Out Data from MMI to DIU. 256-bit word transfer over 4 cycles First 64-bits is bits 63:0 of 256 bit word Second 64-bits is bits 127:64 of 256 bit word Third 64-bits is bits 191:128 of 256 bit word Fourth 64-bits is bits 255:192 of 256 bit word mni_diu_wvalid 1 Out Signal from MMI indicating that data on mmi_diu data ____ ___ ___ ___ _ _ is valid. 15.2.1 15.2.2 MMI Register Map The configuration registers in the MMI are programmed via the CPU interface. Refer to section 11.4 on page 5 76 for a description of the protocol and timing diagrams for reading and writing registers in the MMI. Note that since addresses in SoPEC are byte aligned and the CPU only supports 32-bit register reads and writes, the lower 2 bits of the CPU address bus are not required to decode the address space for the MMI. When reading a register that is less than 32 bits wide zeros are returned on the upper unused bit(s) of mmicpu data. GPIO Register Definition lists the configuration registers in the MMI block. Table 80. MMI Register Definition ~I r Address GPJO-base + L eitr#is Reeecito MMI Control OxOO-Ox3FC MMIConfig[255:0] 256x15 N/A Register access to the Microcode memory. Allows access to configure the MMI reconfigurable engines. Can be written to at any time, can only be read when both MMIGo bits are zero. Ox400 MMIGo 2 Ox0 MMI Go bits. When set to 0 the MMI engine is disabled. When set to 1 the MMI engine is enabled. One bit per process engine.
WO 2005/120835 PCT/AU2004/000706 570 0x404 MMIUserModeEnable 1 Ox0 User Mode Access enable to MMI control configuration registers. When set to 1, user access is enabled. Controls access to MMI registers except MMIUserModeEnable. Ox408 MMIBufferMode 2 Ox0 Selects between DMA or CPU access to the RX and TX buffer. When set to 1, DMA access is selected otherwise CPU access is selected. Bit 0 - TX buffer select Bit 1 - RX buffer select Ox40C MMILdMultMode 2 Ox0 Selects the control bits affected by the LDMULT instruction. One bit per engine: 0 = LDMULT updates Tx control bits 1 = LDMULT updates Rx control bits 0x41 0-0x414 MMIPCAdr[1:0] 2x8 Ox00 Indicates the current engine program counter. Should only be written to by the CPU when Go is 0. Allows the program counter to be set by the CPU. One register per process engine. Bus 0 - Process Engine 0 Bus 1 - Process Engine 1 (Working Register) 0x418-0x41 C MMlOutputControl[1:0] 2x8 Ox00 Provides CPU access to the process engines output bits, one register per engine 0 - Process engine 0, mmi gpioctr[7:0] 1 - Process engine 1, mmLgpio-ctr[15:8] (Working Register) 0x420 MMISharedControl 8 Ox00 Provides CPU access to the process engines' shared output bits (mmi_shar_ctr[7:O0) (Working Register) 0x424 MMIControl 24 OxOO_0 Provides CPU access to both 000 sets of outputs bits and the shared output bits. 7:0 - Process engine 0, mmi gpioctr[7:0] 15:8 - Process engine 1, mmi gpio~ctrl[15:8] 23:16- Shared bits mmishar ctrl[7:O] (Working Register) 0x428 MMIBufReset 2 Ox3 MMI RX & TX buffer clear register. A write of 0 to MMIBufReset[N] resets the RX and TX buffer address pointers as follows: N=0 - Reset all TX buffer address pointers N=1 - Reset all RX buffer address pointers WO 2005/120835 PCT/AU2004/000706 571 (Self Resetting Register) DMA Control 0x430 MMIDmaEn 2 Ox0 MMI DMA enable. Provides a mechanism for controlling DMA access to and from DRAM Bit 0 - Enable DMA TX channel when 1 Bit 1 - Enable DMA RX channel when 1 0x434 MMlDmaTXBottomAdr[21:5] 17 OxOOO MMI DMA TX channel bottom 0 address register. A 256 bit aligned address containing the first DRAM address in the DRAM circular buffer to be read for TX data, see Error! Reference source not found. Ox438 MMIDmaTXTopAdr[21:5] 17 0x0000 MMI DMA TX channel top 0 address register. A 256 bit aligned address containing the last DRAM address to be read for TX data before wrapping to MMlDmaTXBottomAdr. Ox43C MMIDmaTXCurrPtr[21:5] 17 OxOOOO MMI DMA TX channel current 0 read pointer. (Working register) 0x440 MMIDmaTXlntAdr[21:5] 17 0x0000 MMI DMA TX channel interrupt 0 address register. An interrupt is triggered when MMIDmaTXCurrPtr is >= MMIDmaTXIntAdr. The DRAM may not yet have completed transfer of data from this address to the TX buffer when the interrupt is being handled by the CPU. Ox444 MMIDmaTXMaxAdr 22 OxOOOO MMIDmaTXMaxAdr[21:5]: 0 MMI DMA TX channel max address register. A 256 bit aligned address containing the last DRAM address to be read for TX data. MMIDmaTXMaxAdr[4:0]: Indicates the number of valid bytes - 1 in the last 256-bit DMA word fetch from DRAM. 0 - bits 7:0 are valid, 1 - bits 15:0 are valid, 31- bits 255:0 bits are valid etc. Ox448-Ox44C MMIDmaTXMuxMode[1:0] 2x3 Ox0 MMI data write mux swap mode Reg 0 controls the mux select for bits[31:0] Reg 1 controls the mux select for bits[63:32] See Data Mux modes for mode definition WO 2005/120835 PCT/AU2004/000706 572 0x460 MMIDmaRXBottomAdr[21:5] 17 xO00 MMI DMA RX channel bottom 0 address register. A 256 bit aligned address containing the first DRAM address in the DRAM circular buffer to be written with RX data, see Error! Reference source not found. Ox464 MMIDmaRXTopAdr[21:5] 17 0x0000 MMI DMA RX channel top 0 address register. A 256 bit aligned address containing the last DRAM address to be written with RX data before wrapping to MMIDmaRXBottomAdr. Ox468 MMIDmaRXCurrPtr[21:5] 17 OxOOO MMI DMA RX channel current 0 write pointer. (Working register) 0x46C MMIDmaRXIntAdr[21:5] 17 0x0000 MMI DMA RX channel interrupt 0 address register. An interrupt is triggered when MMIDmaRXCurrPtr is >= MMIDmaRXIntAdr. The RX buffer may not yet have completed transfer of data to this DRAM address when the interrupt is being handled by the CPU. Ox470 MMIDmaRXMaxAdr[21:5] 17 0x0000 MMI DMA RX channel max 0 address register. A 256 bit aligned address containing the last DRAM address to be written to with RX data. Ox474-x478 MMIDmaRXMuxMode[1:0] 2x3 Ox0 MMI data write mux swap mode select. Bus 0 controls the mux select for bits[31:0] Bus 1 controls the mux select for bits[63:32] See Data Mux modes for mode definition MMI TX Control 0x500-0x57C MMITXBuf[31:0] 32x32 xO00 MMI TX Buffer write access. 000 Each time the register is accessed the buffer write pointer is incremented. All registers write to the same TX buffer, the address controls how the data is swapped before writing See Data Mux modes, and Valid bytes address offset for modes of operation. (Write only register) 0x580 MMITXBufMode 3 Ox0 TX buffer shift mode. Specifies the data transfer mode for the MMI TX buffer 0 = Serial Mode (1 bit mode) 1 = 8 bit mode 2 = 16 bit mode 3 = 32 bit mode 4 = 64 bit mode Others= Serial Mode WO 2005/120835 PCT/AU2004/000706 573 0x584 MMITXParMode 2 Ox0 TX buffer Parity generation Mode. Specifies the number of bits to use to generate the tx parity output to the MMI engines. 0- 8 bit mode 1-16 bit mode 2-32 bit mode Others- 8 bit mode Ox588 MMITXEmpLevel 4 Ox0 MMI TX Buffer Empty Level. Specifies the buffer level in 32bit words below which the TX Buffer should indicate buffer empty to the MMI engine (via the tx_buf emp signal) - a minimum programmed value of OxO means "activate tx_buff empty when the TX FIFO is completely empty", i.e. there are 0 bits in the FIFO. - a max programmed value of OxF means "activate tx_buff-empty when there is room for 1 x32 bits in the TX FIFO", i.e. there are 15x32 bits in the FIFO. Ox58C MMITXIntEmpLevel 4 Ox0 MMI TX Buffer Empty Interrupt Level. Specifies the buffer level in 32bit words below which the TX Buffer should set the mmi_gpiojrq[0J output and generate an interrupt to the CPU. Ox590 MMITXBufLeveI 10 0x000 Indicates the current TX buffer fill level in bits (Read only Register) MMI RX Control 0x600-0x614 MMIRXBuf[5:0] 6x32 0x0000 MMI RX Buffer read access. 000 Each time the register is accessed the buffer read pointer is incremented. All registers read the same RX buffer, the address controls how the data is swapped before read from the buffer. See Data Mux modes for modes of operation. (Read only Register) 0x620 MMIRXBufMode 3 Ox0 RX buffer shift mode. Specifies the data transfer mode for the MMI RX buffer 0 -Serial Mode (1 bit mode) 1- 8 bit mode 2-16 bit mode 3-32 bit mode 4-64 bit mode Others-defaults to Serial Mode WO 2005/120835 PCT/AU2004/000706 574 0x624 MMIRXParMode 2 Ox0 RX buffer Parity generation Mode. Specifies the number of bits to use to generate the irx.parity output to the MMI engines. 0- 8 bit mode 1-16 bit mode 2-32 bit mode Others-defaults to 8 bit mode Ox628 MMIRXFullLevel 4 OxF MMI RX Buffer Full Level. Specifies the buffer level in 32bit words above which the RX Buffer should indicate buffer full to the MMI engine (via the rxbuffull signal). - a minimum programmed value of Ox0 means "activate ix_bufffull when there are 1 x 32 bits in the RX FIFO". - a max programmed value of OxF means "activate rx_buff_full when the RX FIFO is full", i.e. there are 16x32 bits in the FIFO. Ox62C MMIRXIntFullLevel 4 OxF MMI RX Buffer Full Interrupt Level. Specifies the buffer level in 32bit words above which the RX Buffer should set the mmiLgpiojirq[1] output and generate an interrupt to the CPU. Ox630 MMIRXBufLevel 10 Ox000 Indicates the current RX buffer fill level in bits (Read only Register) Debug 0x640 MMITXState 26 0x000_ Reports the current state of TX 0000 flags, TX byte select, and counters 2 and 0 11:0 - Counter 0 current value 12 - Counter 0 auto count on 14-13 - TX byte select 15 - Unused 23-16 - Count 2 current value 24 - TX parity result 25 - TX compare result (Read only Register) 0x644 MMIRXState 26 x000 Reports the current state of RX 0000 flags, RX byte select, and counters 3 and 1. 11:0 - Counter 1 current value 12 - Counter 1 auto count on 14-13 - RX byte select 15 - Unused 23-16 - Count 3 current value 24 - RX parity result 25 - RX compare result (Read only Register) 0x648 DebugSelect[1 0:2] 9 Ox000 Debug address select. Indicates the address of the register to report on the mmi cpu data bus when it is not otherwise being used.
WO 2005/120835 PCT/AU2004/000706 575 Ox64C MMIBufStatus 4 Ox0 MMI TX & RX buffer status sticky bits used to capture error conditions accessing the RX & TX buffers: 0 - TX Buffer overflow bit 1 - TX Buffer underflow bit 2 - RX Buffer overflow bit 3 - RX Buffer underflow bit (Read only Register) 0x650 MMIBufStatusCir 4 Ox0 MMI TX & RX buffer status clear register, writing a 1 to MMIBufStatusCr[N] clears MMIBufStatus[N]. (Write only Register, reads as 0). Ox654 MMlBufStatuslntEn 4 Ox0 MMI TX & RX buffer status interrupt enable, MMlBufStatusntEn[N] set to 1 enables interrupts on the mmi gpio-irq[1:0] bus as follows: N=O - TX Buffer overflow interrupt enabled on mmi gpioirq[O] N=1 - TX Buffer underflow interrupt enabled on mmi gpiojirq[0) N=2 - RX Buffer overflow interrupt enabled on mmi gpiojirq[1] N=3 - RX Buffer underflow interrupt enabled on mmi-gpiojirq[1) 15.2.2.1 Supervisor and user mode access The configuration registers block examines the CPU access type (cpuacode signal) and determines if the access is allowed to the addressed register (based on the MMIUserModeEnable register). If an access is not 5 allowed the MMI issues a bus error by asserting the mmicpuberr signal. All supervisor and user program mode accesses results in a bus error. Supervisor data mode accesses are always allowed to all registers. User data mode access is allowed to all registers (except MMIUserModeEnable) when the MMIUserModeEnable is set to 1. 10 15.2.3 MMI block partition 15.2.4 MMI Engine The MMI engine consists of 2 separate microcode engines that have their own input and output resources and have some shared resources for communicating between each engine. Both engines operate in exactly the same way. Each engine has an independent 8-bit program counter, 8 15 inputs and 8 output registers bits. In addition there are shared resources between both engines: 8 output WO 2005/120835 PCT/AU2004/000706 576 register bits, 2x12-bit auto counters and 2x8-bit regular counters. It is the responsibility of the program code to ensure that shared resources are allocated correctly, and that both process threads do not interfere with each other. If both process engines attempt to change the same shared resource at the same time, process engine 0 always wins. 5 The 12-bit auto counter can be used to implement a timeout facility where the protocol waits for an acknowledge signal, but the protocol also defines a maximum wait time. The 8-bit regular counter can be used to count the number of bits or bytes sent or received for each transaction. After reset the program counter for each process engine is reset to 0. If the Go bit for a process engine is 0 the program counter will not be allowed to be updated by the engine (although the CPU can update it), and 10 remain at its current value regardless of the instruction at that address. When Go is set to 1 the engine will start executing commands. Note only the CPU can change the Go bit state. The program counter can be read at any time by the CPU, but should only be written to when Go is 0. The program counter for both engines can be accessed through the MMIPCAdr registers. The output registers for each process engine and the shared registers can be accessed by the CPU. They can be 15 accessed at any time, but CPU writes always take priority over MMI process engine writes. The registers can be accessed individually through the MMLOutputControl and MMISharedControl registers, or collectively through the MMIControl register. 15.2.4.1 MMI Instruction decode The MMI instruction decode logic accepts the instruction data (inst data) and decodes the instruction into 20 control signals to the shared logic block and the process engine program counter. The instruction decode block is enabled by the Go bit. If the Go bit is 0 then the program counter is held in its current state and does not update. If the CPU needs to change the program counter it should do so while Go is set to 0. When the Go bit is 1 then program counter is updated after each instruction. For non-branch instructions the 25 program counter increments, but for branch instruction the program counter can be adjusted by an offset. The instruction variable length encoding and bit fields allocations are shown below. Input and output address select allocation Table 81 defines what input is selected or what output is affected for a particular address as used by the BC, LDMULT, and LDBIT instructions. Table 81. IN_SEL/OUTSEL possible values tNELi -es-mae -Test mnods _w [7:0] gpiommi._ctrl Unused gplo mmi ctr[15 Unused [7:0] :8](control inputs) /tmntrnI WO 2005/120835 PCT/AU2004/000706 577 inputs) [15:8] mmi-gpioctrl mmi-gpiosctrl[7:0] mmi_gpioctrl[1 5 mmi-gpio-ctrl[15:8] [7:0] (control outputs) :8](control (control outputs) (control outputs) outputs) [23:16] mmi_ctrlshar mmii_ctrl_shar[7:0] mmi_ctrlshar[7: mmi_ctrl-shar[7:0] [7:0] (shared control outputs) 0] (shared control outputs) (shared (shared control control outputs outputs) [24] txbuf-emp txbufrden tx_buf-emp tx_bufrden (a write of 0 is NOP, a (a write of 0 is NOP, a write of 1 increments the write of 1 increments the TX pointer) TX pointer) [25] rxbuffull rxbufwren rxbuffull rxbufwren (a write of 0 increments (a write of 0 increments the WritePtr only, a write the WritePtr only, a write of 1 increments WritePtr of 1 increments WritePtr and realigns the and realigns the CommitWritePt) CommitWritePt) [26] txjparresult tx.par.gen tx_par_result txpargen (a write of 0 generates (a write of 0 generates odd parity, a write of 1 odd parity, a write of 1 generate even parity) generate even parity) [27] rx-parresult rx-par..gen rx-parjresult rx-par-gen (a write of 0 generates (a write of 0 generates odd parity, a write of 1 odd parity, a write of 1 generates even parity) generates even parity) [31:28] cnt-zero[3:0] cnt dec[3:0] cntzero[3:0] cnt dec[3:0] (a write of 0 is NOP, a (a write of 0 is NOP, a write of 1 decrements the write of 1 decrements the corresponding counter) corresponding counter) The mmigpio ctrl signals are control outputs to the GPIO and gpio mmictrl are control inputs from the GPIO. The mmi-shar-ctrl signals are shared bits between both processes. They are also control outputs to the GPIO block. The MMI control signals connections to the 10 pads are configured in the GPIO. The 5 mii_shar-ctrl signals have added functionality in the GPIO; they can be used to control whether particular pins are input or output, and if in output mode, under what conditions to drive or tri-state that pin. Branch Condition instruction (BC) The branch condition instruction compares the input bit selected by the IN_SEL code to the bit B (see INSEL/OUTSEL possible values for definition of IN SEL bits). If both are equal then the PC is adjusted by 10 the PCOFFSET address specified in the instruction. The PCOFFSET is a 2's complement value which allows negative as well as positive jumps (sign extended before addition). If they are unequal, then the PC increments as normal. BC: INSEL = instdat[12:8] 15 B = instdat[13] PC_OFFSET = instdat[7:0] if ( insel(IN_SEL} == B) then WO 2005/120835 PCT/AU2004/000706 578 pcadr = pc-adr + PC_OFFSET else pc-adr ++ Auto Count instruction (ACNT) 5 The auto count instruction loads the counter specified by bit B with NUMCYCLE and starts the counter decrementing each cycle. When the count reaches zero the cntzero[N] flag (where N is the counter number) is set and the autocount is disabled. ACNT: NUMCYCLES = inst_dat(11:0] 10 B = instdat(12] wr.data[11:0] = NUM_CYCLES // determine which counter to load ld-cnt [B] = 1 auto-en = 1 15 Note that the counter select in the autocount instruction is 1 bit as only counters 0 and 1 have autocount logic associated with them. Load Multiple instruction (LDMULT) The LDMULT instruction performs a bitwise copy of the 8-bit OUT VALUE operand into the process engine's 8-bit output register. In parallel with the 8-bit copy process, the LDMULT instruction also performs 20 a write of 1 to up to 4 particular shared control signals through a mask (the MASK[3:0] operand). Although the 8-bit copy transfers both Is and Os to the output register, the write to the shared control signals from a LDMULT is only ever a write of 1. Thus, when a mask bit is 1, a write of 1 is performed to the appropriate shared control signal for that bit. When a mask bit is 0, a write of 1 is not performed. Thus a mask setting of 0000 has no effect. It is not possible to write a 0 to a shared control signal using the LDMULT 25 command; the LDBIT command must be used instead. The control signals that the mask applies to depend on the setting of the process engine's MMILdMultMode register. When MMILdMultMode is 0, mask bits 0, 1, 2, 3 target OUT SEL addresses 24, 26, 28, 30 respectively (see Table 81). When MMILdMultMode is 1, mask bits 0, 1, 2, 3 target OUTSEL addresses 25, 27, 29, 31 respectively. 30 LDNULT: OUTVALUE = inst-dat[7:0] MASK = inst-dat[11:8] // implement the parallel load wren = 0x0000_FF00 35 wr-data[7:0] = OUTVALUE // adjust based on engine if (mmi_ldmult_mode == RXMODE) then adjust = 1 else 40 adjust = 0 for(i=0,i<4;i++) { if (MASK[i] == 1) then index = i * 2 + 24 + adjust wren[index] = 1 WO 2005/120835 PCT/AU2004/000706 579 wr-data[index] = 1 Compare Nybble instruction (CMPNYBBLE) The compare nybble instruction selects a 4-bit value from the RX or TX buffer, applies a mask (MASK) and 5 compares the result with the instruction value (VALUE). If the result is true then the appropriate compare result (either the RX or TX) will be get set to 1. If the result is false then the result flag will get set to 0. The B2 bit in the instruction selects whether the rx_fifo data or tx ifo data is used for comparison, and also the location of the result. The B1 bit selects the high or low nybble of the byte, which is selected by bytesel[O] or byte sel[1]. 10 The byte from the TX buffer is selected by the bytesel[O] value from the next 32 bits to be read out from the TX buffer, and the byte from the RX buffer is selected by the byte sel[1] value from the last 32bits written into the RX buffer. Note that in the RX case bits only need to be written into the buffer and not necessarily committed to the buffer. The pseudocode is 15 CMPNYBBLE: VALUE = inst_dat(3:0] MASK = instdat[7:4] Bi = inst-dat[8] B2 = inst_dat[9] 20 cmp-byte-en[B2] = 1 wrdata[7:0] = {MASK,VALUE} cmpnybblesel = B1 Compare byte instruction (CMPBYTE) 25 The compare byte instruction has 2 modes of operation: mask enabled mode and direct mode. When the mask enable bit (ME) is 0 it compares the byte selected by the bytesel register which is in turn selected by bit B, with the data value DATAVALUE and puts the result in the appropriate compare result register (either RX or TX) also selected by B. If the ME bit is 1 then an 8-bit counter value (counter 2 or 3) selected by bit B is ANDed with MASK, the data 30 byte (selected as before) is also ANDed with the same MASK, the 2 results are compared for equality and the result is stored in the appropriate compare result register (either RX or TX) also selected by B. CMPBYTE: VALUE = instdata[7:0] Bi = instdata[9] 35 ME = instdata[8] // output control to shared logic wr-data[7:0] = VALUE cmp byte-en(Bl} = 1 cmp_bytemode = ME WO 2005/120835 PCT/AU2004/000706 580 Load Counter instruction (LDCNT) The loads counter instruction loads the NUMCOUNT value into the counter selected by the SEL field. If the counter is one of the 12-bit auto count counters (i.e. counter 0 or 1) and the auto-count is currently active, then the auto count will be disabled. If the instruction is loading an 8-bit NUMCOUNT value into a 12-bit counter 5 the value will be zero filled to 12-bits. A load into a counter overwrites any count that is currently progressing in that counter. LDCNT: NUM_COUNT = inst-dat[7:0] SEL = instdat[9:8] 10 // select to correct load bit ldcnt[SEL] = 1 wr-data[7:0] = NUMCOUNT Branch Condition compare result is I (BCCMP1) The branch condition instruction checks the compare result bit (selected by B) and if equal to 1 then jumps to 15 the relative offset from the current PC address. The PCOFFSET is a 2's complement value which allows negative as well as positive jumps (sign extended before addition). BCCMPl: PCOFFSET = instdat[7:0) B = instdat[8] 20 // select the compare result to check if (B == 0) then cmp-result = txcmpresult else cmp-result = rxcmp-result 25 // do the test if (cmpresult == 1) then pcadr = pc-adr + PCoFFSET else pcadr++ 30 Load Output instruction (LDBIT) The load out instruction loads the value in B into the output selected by OUT SEL. LDBIT: OUT_SEL = inst_dat[4:0] B = instdat[51 35 wren[OUTSEL] = 1 wr-data[OUTSEL) = B Load counter from FIFO (LDCNTFIFO) Loads the counter selected by SEL with data from the RX or TX fifo as selected by bit B. The number of nybbles to load is indicated by NYB field, and values are 0 for 1 nybble load, 1 for 2 nybble loads and 2 for 3 40 nybble load. Note that the 3 nybble loads can only be used with the 12-bit counters. Any unused bits in the counters are loaded with zeros. In all cases a load of a counter from the FIFO will not enable the auto decrement logic.
WO 2005/120835 PCT/AU2004/000706 581 LDCNTFIFO: NYB = instdat[1:0] SEL = instdat[3:2] B = instdat[4] 5 ld_cnt[SEL) = 1 wrdata[2:0] = {B,NYB) ld_cntmode = 1 Load byte select instruction (LDBSEL) The load byte select register loads the value in SEL into the byte select register selected by bit B. If B is 0 the 10 byte sel[0] register is updated if B is 1 the byte sel[J] register is selected. LDBSEL: SEL = inst-dat[1:0] B = inst-dat(3] ld-byte(B] = 1 15 wrdata(1:0] = SEL RX commit (RXCOM) and delete (RXDEL) instructions The RX commit and delete instructions are used to manipulate the RX write pointers. The RX commit command causes the WritePtr value to be assigned to CommitWritePtr, committing any outstanding data to the RX buffer. The RX delete command causes the WritePtr to get set to CommitWritePtr deleting any data 20 written to the FIFO but not yet committed. 15.2.4.2 10 control shared resource logic The shared resource logic controls and arbitrates between the MMI process engines and the MMI output resources. Based on the control signals it receives from each engine it determines how the shared resources should be updated. The same control signals come from each process engine. In the following descriptions the 25 pseudocode is shown for one process engine, but in reality the pseudocode will be repeated for the control inputs of both process engine. Process engine 1 will be checked first then process engine 0, giving process engine 0 the higher priority. The CPU can also write to the shared output registers. Whenever there is contention, process engine 0 always has priority over process engine 1. 30 // update the output and shared bits for (i=0;i<32;i++) ( if (wr-en[i] == 1) then data_bit wr_data[i] case i is 35 15-8 : mmi-pioctrl[i-8] = databit 23-16: mmi-ctrl-shar[i-161 = databit 24 txrd_en = databit 25 rxwr-en = 1; rx-ptr mode = databit 26 tx.par-gen = 1; txparmode = databit 40 27 rx-par-gen = 1; rxpar mode = databit 28 cntdec{0] = 1; 29 : cnt_dec[1] = 1; 30 : cntdec(2] = 1; 31 : cntdec(3] = 1; WO 2005/120835 PCT/AU2004/000706 582 other: endcase 5 // perform CPu write if (mmi_sharwr-en == 1) then mmi-ctrl_shar[7:0] = mmiwrdata[23:16] Shared count logic The count logic controls the CNT[3:0] counters and cntzero[3:0] flags. When an MMI process engine 10 executes an auto count instruction ACNT, a counter is loaded with the auto count value, which automatically counts down to zero. Only counters 0 and 1 can autocount. When the count reaches 0 the cnt zero flag for that counter is set. If the MM engine executes a LDCNT instruction a counter is loaded with the count value in the command. Each time a MMI process engine writes to the cnt_dec[3:0] bits the corresponding counter is decremented. A counter load instruction disables any existing auto count still in progress. Counters 0 and 1 15 are 12-bits wide and can autocount. Counters 2 and 3 are 8-bits wide with no autocount facility. The pseudocode is given by: // implement the count down if (auto-on[N] == 1)OR(cnt-dec(N] == 1) then cnt(N] - 20 // implement the load if (ld-cnt-en[N] == 1) then if (ld-cnt-mode[N] == 1) then // FIFO load mode NYBVALID = wrdata[1:0] // number of nybbles valid B = wrdata[2] // FIFO data select 25 if (B == 0) then fifo-data[11:0] = tx_fifo-data[11:0] else fifo-data[ll:0] = rx-fifo-data[11:0] // create word to load 30 case NYB_VALID 0: cnt[N] = {0x00,fifo-data[3:0]) 1: cnt(N] = {0x0 ,fifodata[7:0]) 2: cnt[N] = fifodata[11:0] end case 35 else cnt(N] = wrdata // check if auto decrement is on and store if (auto-en[N] == 1) autoon[N] = 1 40 else auto~on[N] = 0 // implement the count zero compare if (cnt[N] == 0) then cnt-zero[N] = 1 45 auto-on[N] = 0 The pseudocode is shown for counter N, but similar code exists for all 4 counters. In the case of counters 2 and 3 no auto decrement logic exists.
WO 2005/120835 PCT/AU2004/000706 583 Byte select shared logic In a similar way to the counter the byte select register can be loaded from any process engine. When an MMI process engine executes a load byte select instruction (LDBSEL), the value in the SEL field is loaded in the byte select register selected by the B field. 5 if (ld-byte-en[B] == 1) bytesel[B] = wrdata[l:0] // SEL value from MMI engine else bytesel[B] = bytesel[B] Byte select 0 selects a byte from the TX fifo data 32 bit word, and byte select 1 selects a byte from the RX 10 fifo data 32bit word. Parity/Compare shared logic The parity compare logic block implements the parity generation and compare for both process engines. The results are stored in the rx/tx_parresult and rx/txcmpresult registers which can be read by the BC instruction in the MMI process engines. 15 The pseudo-code for the TX parity generation case is: // implement the parity generation if (txpargen == 1) then txpar-result = tx.parity ^ tx.par mode else 20 tx-par-result = tx-par-result The compare logic has a few possible modes of operation: nybble compare, byte immediate and byte masked compare. In all cases the result is stored in the t'r/x_cmpresult register. The pseudocode shown illustrates the logic for any process engine comparing data from the TX buffer, and 25 setting the t _cmpresult flag. // the nybble compare logic if (cmp-nybble-en[O] == 1) // mux the input byte mask[3:0] = wr-data[7:4] 30 if (cmp-nybble-sel = 1) then // nybble select fifo_data[3:0] = tx_fifo_data[7:4] AND mask[3:0] else fifodata[3:0] = tx-fifo-data[3:0] AND mask[3:0] // do the compare 35 if (wr-data[3:0] == fifo-data[3:0]) then tx-cmp-result = 1 else tx_cmpresult = 0 The byte immediate and byte masked compare logic is also similar to above. In this case the pseudocode is 40 shown for a process engine checking the TX buffer byte data. // byte compare logic if (cmp-byte-en[0] == 1) then // check for mask mode of not if (cmp_byte_mode == 1) then // masked mode WO 2005/120835 PCT/AU2004/000706 584 mask[7:0] = wr-data[7:0) if ((cnt[2][7:0] AND mask[7:0]) == (txfifodata[7:0] AND mask[7:0])) then txcmp-result = 1 5 else txcmpresult = 0 else // immediate mode if (wr-data[7:0] == txfifo-data[7:0]) then tx-cmp-result = 1 10 else txcmpresult = 0 In both pseudocode examples above the code is shown for cmpbyte en [0] and cmp nybble en[O], which compare on TX buffer data (txfifodata), and the counter 2 with the instruction data and the result is stored in the TX compare flag (t _cmpresult). If the compare enable signals were cmpbyte en[1] or 15 cmpnybble en[1], then the command would compare RX buffer data (rxifo data) and counter 3 with the instruction data, and store the result in the RX compare flag (rxcmpresult). 15.2.5 Data Mux Modes The data mux block allows easy swapping of data bus bits and bytes for support of different endianess protocols without the need for CPU or MMI engine processing. 20 The TX and RX buffer blocks each contains instances of a data mux block. The data mux block swaps the bit and byte order of a 32 bit input bus to generate a 32 bit output bus, based on a mode control. It is used on the write side of the TX buffer, and on the read side of the RX buffer. The mode control to the data mux block depends on whether the block is being used by the DMA access controller or the CPU. 25 If the DMA controller is accessing the TX or RX buffer, the data mux operation mode is defined by the MMIDmaRXMuxMode and MMIDmaTX~uxMode registers. The DMAs write or read in 64bits words, so 2 instances of the data mux are required. MMIDma*"tuxMode[0] configures the data mux connected to the lower 32 bits and MMIDma *"uxMode[1j] configures the data mux for the higher 32bits. If the CPU is accessing the RX or TX buffer, the data mux operation mode that is used to do the swapping is 30 derived from the offset of the CPU access from the TX/RX buffer base address. For example if the CPU read was from address RXBUFFERBASE+0x4, (note that addresses are in bytes), the offset is 1, so Mode 1 bit flip mode would be used to re-order the read data. The possible modes of data swap and how they reorder the data bits are shown in Data Mux modes. Table 82. Data Mux modes . "Address..... ........ Ox00 Mode 0 Straight through mode, dout[i] = din[i], where i is 0 to 31 0x04 Mode 1 Bit Flip mode, dout[i] = din[31 -i], where i is 0 to 31 WO 2005/120835 PCT/AU2004/000706 585 Ox08 Mode 2 Bytewise Bit Flip Mode dout[i] = din[7-i], where i is 0 to 7 dout[i] = din[23-i], where i is 8 to 15 dout[i] = din[39-i], where i is 16 to 23 dout[i] = din[55-i], where i is 24 to 31 Ox0C Mode 3 Byte Flip Mode dout[i] = din[i + 24], where i is 0 to 7 dout[i] = din[i + 8], where i is 8 to 15 dout[i] = din[i - 8], where i is 16 to 23 dout[i] = din[i - 24], where i is 24 to 31 0x1 0 Mode 4 16bit word wise bit flip Mode dout[i] = din[15-i], where i is 0to 15 dout[i] = din[47-i], where i is 16 to 31 0x1 4 Mode 5 16bit Word flip Mode dout[i] = din(i + 16], where i is 0 to 15 dout[i] = din[i - 16], where i is 16 to 31 0x1 8 Unused defaults to functionality of Mode 0 Ox1C Unused defaults to functionality of Mode 0 When the CPU writes to the TX buffer it can also indicate the number of valid bytes in a write by choosing a different address offset. See Valid bytes address offset and associated description. In the MMI address map the TX buffer occupies a region of 32 register spaces. If the CPU writes to any one of these locations the TX 5 buffer write pointer will increase, but the order and number of valid bytes written will by dictated by the address used. 15.2.6 RX Buffer The RX buffer accepts data from the GPIO inputs controlled by the MMI engine and transfers data to the CPU or to DRAM using the DMA controller. The RX buffer has several modes of operations configured by 10 the MMIRXBufMode register. The mode of operation controls the number of bits that get written into the RX FIFO, each time a rx wr-en pulse is received from the MMI engine. The RX buffer can be read by the CPU or the DMA controller (selected by the MMIBufferMode register). The CPU always reads 32 bits at a time from the RX buffer. The data the CPU reads from the RX buffer is passed through the data mux block before being placed on the CPU data bus. As a result the data byte and bit 15 order are a function of the CPU address used to access the RX buffer (see Data Mux modes). The DMA controller always transfers 256 bits to DRAM per access, in chunks of 4 double words of 64 bits. The DMA controller passes the data through 2 data muxes, one for the lower 32bits of each double word and one for the upper 32 bits of each double word, before passing the data to DRAM. The mode the data muxes operate in is configured by the MMIDmaRXMuxMode registers. The DMA controller will only request access 20 to DRAM when there is at least 256-bits of data in the RX buffer. The RX buffer maintains a read pointer (ReadPtr) and 2 write pointers CommitWritePtr and WritePtr to keep track of data in the FIFO. The Commit WritePtr is used to determine the fill level committed to the FIFO, and the WritePtr is used to determine where data should be written in the FIFO, but might not get committed.
WO 2005/120835 PCT/AU2004/000706 586 The RX buffer calculates the number of valid bits in the FIFO by comparing the read pointer and the write level pointer, and indicates the level to the CPU via the mmii__rxbufjlevel bus. The RX buffer compares the calculated level with the configured MMIRxFullLevel to determine when the buffer is full, and indicates to the MMI engine via the rx buf full signal. 5 If the buffer is in CPU access mode it compares the calculated fill level with the configured MMIRxIntFullLevel to determine when an mmigpio int[1] interrupt should be generated. If the buffer is in DMA access mode the mmigpio int[J] will be generated when MMIDmaRXCurrPtr = MMIDmaRXintAdr, indicating the DMA has filled the DRAM circular buffer to the configured level. The RX buffer generates parity based on the configured parity mode MMIRxParMode register, and indicates 10 the parity to the MMI engine via the rx_parity signal. The RX buffer always generates odd parity (although the parity can be adjusted to even within the MMI engine). The number of bits over which to generate parity is specified by the parity mode and the exact data used to generate the parity is specified by the WritePtr. For example if the parity mode is 32 bits the parity will be generated on the last 32 bits written into the RX buffer from the WritePtr. 15 The RX buffer maintains 2 write pointers to allow data to be stored in the buffer, and then subsequently removed by the MMI engine if needed. The CommitWritePtr pointer is used to indicate the write data level to the CPU i.e. data that is committed to the RX buffer. The WritePtr is used to indicate the next position in the buffer to write to. If the CommitWritePtr and WritePtr are the same then all data stored in the RX buffer is committed. The MMI engine can control how the pointers are updated via the rxcommit, rx-wren and 20 rxdelete signals. The recommit and rxdelete signals are activated by the RXCOMMIT and the RXDELETE instructions, rxwren is enabled with an LDBIT or LDMULT instruction accessing OUTSEL[25]. If the rx_ wren signal is high and the rx_ptr mode is also high, the WritePtr is incremented (by the mode number of bits) and the Commit WritePtr is set to WritePtr, committing any outstanding data in the RX buffer, 25 and writing a new data word in. If the rxwren signal is high and rx_ptrmode is low then only the WritePtr is incremented, the new data is written into the RX buffer but is not committed, and the CPU side of the buffer is unaware that the data exists in the buffer. The MMI engine can then choose to either commit the data or delete it. If the data is to be deleted (indicated 30 by the rxdelete signal) then WritePtr is set to CommitWritePtr, or if it's to be committed then the Commit WritePtr pointer is set to WritePtr (indicated by the rx commit signal). The RX buffer passes 32 bits of FIFO data (via the rxifodata bus) back to the MMI engine for use in the byte compare, nybble compare and counter load. instructions. The 32bits are the last 32 bits written into the RX buffer from the WritePtr. 35 The RX buffer is 512 bits in total, implemented as an 8 word x 64 bit register array. In the case of a buffer overflow (rxwren active when the buffer is already full) MMIBuJStatus[2] is set to I and mmi_gpioirq[1] is pulsed if the corresponding enable, MMIBujStatusIntEn[2] = 1.
WO 2005/120835 PCT/AU2004/000706 587 In the case of a buffer underflow (CPU read when the buffer is empty) MMIBuJStatus[3] is set to 1 and mmi_gpioirq[1] is pulsed if the corresponding enable, MMIBuJStatuslntEn[3] = 1. MMIBufStatus[3:0] bits are then cleared by the CPU writing 1 to the corresponding MMIBufStatusClr[3:0] register bits. 5 15.2.7 TX Buffer The TX buffer accepts data from the CPU or DRAM for transfer to the GPIO by the MMI engine. The TX buffer has several modes of operation (defined by the MMITXBufMode register). The mode of operation determines the number of data bits to remove from the FIFO each time a tx_rd-en pulse is received from the MMI engine. For example if the mode is set to 32-bit mode, for each tx_rden pulse from the MMI engine the 10 read pointer will increase by 32, and the next 32 bits of data in the FIFO will be presented on the mmitxdata[31:0] bus. The TX buffer can be written to by the CPU or the DMA controller (selected by the MMIBufferMode register). The CPU always writes 32 bits at a time into the TX buffer. The data the CPU writes is passed through the 15 data mux before writing into the TX buffer, so the data byte and bit order is a function of the CPU address used to access the TX buffer (see Data Mux modes). The DMA controller always transfers 256bits from DRAM per access, in chunks of 4 double words of 64 bits. The DMA controller passes the data through 2 data muxes, one for the lower 32bits of each double word and one for the upper 32bits of each double word, before writing data to TX buffer. The mode the data muxes 20 operate in is configured by the MMIDmaTXMuxMode registers. The DMA controller will only request access from DRAM when there is at least 256-bits of data free in the TX buffer. The TX buffer calculates the number of valid bits in the FIFO, and indicates the value to the CPU via the MMITXFillLevel. The TX buffer indicates to the MMI engine when the FIFO fill level has fallen below a configured threshold (MMITXEmpLevel), via x buf empty signal. 25 In CPU access mode the TX buffer also uses the fill level to compare with the configured MMITXntEmpLevel to indicate the level that an interrupt is generated to the CPU (via the mmigpio int[0] signal). This interrupt is optional, and the CPU could manage the TX buffer by polling the MMITXBufLevel register. If the buffer is in DMA access mode the mmipio int[0] will be generated when MM/Dma TXCurrPtr= MMIDmaTXntAdr, indicating the DMA has emptied the DRAM circular buffer to the configured level. 30 TX buffer generates a parity bit (lxparity) for the MMI engine. The parity generation is controlled by the MMITXParMode register which determines how many bits are included in the parity calculation. The parity mode is independent of the TX buffer mode. Parity is always generated on the next N bits in the FIFO to be read out, where the N is derived from the parity mode, e.g. if parity mode is 16-bits, then N is 16. The parity generator always generates odd parity.
WO 2005/120835 PCT/AU2004/000706 588 The TX buffer passes 32 bits of FIFO data (via the tx_fifodata bus) back to the MMI engine for use in the byte compare, nybble compare and counter load instructions. The 32-bits are the next 32 bits to be read from the TX buffer. The TX buffer data mux has additional access modes that allow the CPU to indicate the number of valid bytes 5 per 32-bits word written. The CPU indicates this based on the address used to access TX buffer (as with the data muxing modes). Table 83. Valid bytes address offset Ox000 Straight through mode, byte 0 valid 0x020 Straight through mode, byte 0,1 valid 0x040 Straight through mode, byte 0,1,2 valid 0x060 All 4 bytes are valid (Straight through mode) Each 32 bit entry in the TX buffer has an associated number of valid bytes. When the MMI engine has used all the valid bytes in a 32-bit word the read pointer automatically jumps to the next valid byte. This operation 10 is transparent to the MMI engine. If the TX buffer is operating in DMA mode, all DMA writes (except the last write) to the TX buffer have all bytes valid. The last 256bit access has a configured number of bytes valid as programmed by the MMIDmaTxMaxAdr[4:0] registers. The last fetch is defined as the access to DRAM address MMIDmaTxMaxAdr[21:5]. 15 The TX buffer is 512 bits in total, implemented as a 8 word x 64bit register array. In the case of a buffer overflow (CPU write when the buffer is already full) MMIBuJStatus[0] is set to 1 and mmigpio irq[] is pulsed if the corresponding enable, MMIBuJStatusIntEn[0] = 1. In the case of a buffer underflow (txrden active when the buffer is empty) MMIBuJStatus[1] is set to 1 and mmigpioirq[0] is pulsed if the corresponding enable, MMIBuJStatusIntEn[1] = 1. 20 MMIBuJStatus[3:0] bits are then cleared by the CPU writing 1 to the corresponding MMIBufStatusClr[3:0 register bits. 15.2.8 MicroCode storage The microcode block allows the CPU to program both MMI processes by writing into the program space for each MMI engine. For each clock cycle the MicroCode block returns 2 instruction words of 15 bits each, one 25 for process engine 0 and one for process engine 1. The data words returned are pointed to by the pc adr[0] and pcadr[1] program counters respectively. The microcode block allows for up to 256 words of instructions (each 15 bits wide) to be shared in any ratio between both engines.
WO 2005/120835 PCT/AU2004/000706 589 The CPU can write to the microcode memory at any time, but can only read the microcode memory when both mmi_go bits are zero. This prevents any possible arbitration issues when the CPU and either MMI engine wants to read the memory at the same time. 15.2.9 DMA Controller 5 The RX and TX buffer block each contain a DMA controller. In the RX buffer the DMA controller is responsible for reading data from the RX buffer and transferring data to the DRAM location bounded by the MMIDmaRXTopAdr and MMIDmaRXBottomAdr. In the TX buffer the DMA controller is responsible for data transfer from the DRAM location bounded by the MMIDmaTXopAdr and MMIDmaTXBottomAdr to the TX buffer. Both DMA controllers maintain pointers indicating the state of the circular buffer in DRAM. The 10 operation of the circular buffers in both cases is the same (despite the fact that data is travelling in opposite directions to and from DRAM). The TX DMA channel when enabled (MMIDMAEn[Oj) will always try to read data from DRAM when there is at least 256 bits free in the TX buffer. The RX DMA channel when enabled (MMIDmaEn[1]) will always try to write data to DRAM when there is at least 256bits of data in the RX buffer. 15 The RX circular buffer operation is described below but the TX circular buffer is similar. 15.2.9.1 Circular buffer operation The DMA controller supports the use of circular buffers for each DMA channel. Each circular buffer is controlled by 5 registers: MMIDmaNBottomAdr, MMIDmaNTopAdr, MMIDmaNMaxAdr, MMIDmaNCurrPtr and MMIDmaNIntAdr. The operation of the circular buffers is shown in figure 20 This figure shows two snapshots of the status of a circular buffer with (b) occurring sometime after (a) and some CPU writes to the registers occurring in between (a) and (b). These CPU writes are most likely to be as a result of an interrupt (which frees up buffer space) but could also have occurred in a DMA interrupt service routine resulting from MMIDmaNIntAdr being hit. The DMA manager will continue filling the free buffer space depicted in (a), advancing the MMIDmaNCurrPtr after each write to the DIU. Note that the 25 MMIDmaNCurrPtr register always points to the next address the DMA manager will write to. The DMA manager produces an interrupt pulse whenever MMIDmaNCurrPtr advances to become equal to MMIDmaNIntAdr. The CPU can then, either in an interrupt service routine or at some other appropriate time, change the MMIDmaNIntAdr to the next location of interest. Example uses of the interrupt include: 0 the simple case of informing the CPU that a quantity of data of pre-known size has arrived 30 e informing the CPU that large enough quantity of data (possibly containing several packets) has arrived and is worthy of attention * alerting the CPU to the fact that the MMIDmaNCurrPtr is approaching the MMIDmaMaxAdr (assuming the addresses are set up appropriately) and the CPU should take some action. In the scenario shown in Figure the CPU has determined (most likely as a result of an interrupt) that the filled 35 buffer space in (a) has been freed up and is therefore available to receive more data. The CPU therefore WO 2005/120835 PCT/AU2004/000706 590 moves the MMIDmaNMaxAdr to the end of the section that has been freed up and moves the MMIDmaNIntAdr address to an appropriate offset from the MMIDmaNMaxAdr address. The DMA manager continues to fill the free buffer space and when it reaches the address in MMIDmaNTopAdr it wraps around to the address in MMIDmaNBottomAdr and continues from there. DMA transfers will continue indefinitely in 5 this fashion until the DMA manager completes an access to the address in the MMIDmaNMaxAdr register. When the DMA manager completes an access to the MMIDmaNMaxAdr address the DMA manager will stall and wait for more room to be made available. The CPU interrupt service routine will process data from the buffer (freeing up more space in the buffer) and will update the MMIDmaNMaxAdr address to a new value. When the address is updated it indicates to the DMA manager that more room is available in the buffer, 10 allowing the DMA manager to continue transferring data to the buffer. The circular buffer is initialized by writing the top and bottom addresses to the MMIDmaNTopAdr and MMIDmaNBottomAdr registers, writing the start address (which does not have to be the same as the MMIDmaNBottomAdr even though it usually will be) to the MALDmaNCurrPtr register and appropriate addresses to the MMIDmaNIntAdr and AMIDmaNMaxAdr registers. The DMA operation will not commence 15 until a 1 has been written to the relevant bit of the MMIDmaEn register. While it is possible to modify the MMIDmaNTopAdr and MLDmaNBottomAdr registers after the DMA has started it should be done with caution. The MMIDmaNCurrPtr register should not be written to while the DMA Channel is in operation. DMA operation may be stalled at any time by clearing the appropriate bit of the MMIDmaEn register. 20 16 INTERRUPT CONTROLLER UNIT (ICU) The interrupt controller accepts up to N input interrupt sources, determines their priority, arbitrates based on the highest priority and generates an interrupt request to the CPU. The ICU complies with the interrupt acknowledge protocol of the CPU. Once the CPU accepts an interrupt (i.e. processing of its service routine 25 begins) the interrupt controller will assert the next arbitrated interrupt if one is pending. Each interrupt source has a fixed vector number N, and an associated configuration register, IntReg[N]. The format of the IntReg[N] register is shown in Table 84 below. Table 84. IntReg[N] register format Priority 3:0 Interrupt priority Type 5:4 Determines the triggering conditions for the interrupt 00 - Positive edge 10 - Negative edge 01 - Positive level 11 - Negative level WO 2005/120835 PCT/AU2004/000706 591 Mask 6 Mask bit. 1 - Interrupts from this source are enabled, o - Interrupts from this source are disabled. Note that there may be additional masks in operation at the source of the interrupt. Reserved 31:7 Reserved. Write as 0. Once an interrupt is received the interrupt controller determines the priority and maps the programmed priority to the appropriate CPU priority levels, and then issues an interrupt to the CPU. The programmed interrupt priority maps directly to the LEON CPU interrupt levels. Level 0 is no interrupt. 5 Level 15 is the highest interrupt level. 16.1 INTERRUPT PREEMPTION With standard LEON pre-emption an interrupt can only be pre-empted by an interrupt with a higher priority level. If an interrupt with the same priority level (1 to 14) as the interrupt being serviced becomes pending then it is not acknowledged until the current service routine has completed. 10 Note that the level 15 interrupt is a special case, in that the LEON processor will continue to take level 15 interrupts (i.e re-enter the ISR) as long as level 15 is asserted on the icucpuievel. Level 0 is also a special case, in that LEON consider level 0 interrupts as no interrupt, and will not issue an acknowledge when level 0 is presented on the icu cpu level bus. Thus when pre-emption is required, interrupts should be programmed to different levels as interrupt priorities 15 of the same level have no guaranteed servicing order. Should several interrupt sources be programmed with the same priority level, the lowest value interrupt source will be serviced first and so on in increasing order. The interrupt is directly acknowledged by the CPU and the ICU automatically clears the pending bit of the lowest value pending interrupt source mapped to the acknowledged interrupt level. All interrupt controller registers are only accessible in supervisor data mode. If the user code wishes to mask 20 an interrupt it must request this from the supervisor and the supervisor software will resolve user access levels. 16.2 INTERRUPT SOURCES The mapping of interrupt sources to interrupt vectors (and therefore IntReg[N] registers) is shown in Table 85 below. Please refer to the appropriate section of this specification for more details of the interrupt sources. Table 85. Interrupt sources vector table 0 Timers WatchDog Timer Update request 1 Timers Generic Timer 1 interrupt (timicuirq[0}) WO 2005/120835 PCT/AU2004/000706 592 2 Timers Generic Timer 2 interrupt (timj_icu_irq[1]) 3 PCU PEP Sub-system Interrupt- TE finished band 4 PCU PEP Sub-system Interrupt- LBD finished band 5 PCU PEP Sub-system Interrupt- CDU finished band 6 PCU PEP Sub-system Interrupt- CDU error 7 PCU PEP Sub-system Interrupt- PCU finished band 8 PCU PEP Sub-system Interrupt- PCU Invalid address interrupt 9 PHI PEP Sub-system Interrupt- PHI Line Sync Interrupt 10 PHI PEP Sub-system Interrupt- PHI General Irq 11 UHU USB Host interrupt (uhu_icu_irq[) 12 UDU USB Device interrupt (uduicu_irq[1) 13 LSS LSS interrupt, LSS interface 0 interrupt request (iss_icuirq[0) 14 LSS LSS interrupt, LSS interface 1 interrupt request(issjcujirq[1]) 15 GPIO GPIO general purpose interrupts (gpioicu_irq[) 16 GPIO GPIO general purpose interrupts (gpio_icu_irq[1]) 17 GPIO GPIO general purpose interrupts (gpio_icu_irq[2]) 18 GPIO GPIO general purpose interrupts (gpiojicuirq[3) 19 GPIO GPIO general purpose interrupts (gpio_icu_irq[4}) 20 GPIO GPIO general purpose interrupts (gpio_icu_irq[5]) 21 GPIO GPIO general purpose interrupts (gpioJcu_irq[6) 22 GPIO GPIO general purpose interrupts (gpiojcuirq[7) 23 GPIO GPIO general purpose interrupts (gpioJcuirq[8b) 24 GPIO GPIO general purpose interrupts (gpiojicuirq[9]) 25 GPIO GPIO general purpose interrupts (gpiojicuirq[10J) 26 GPIO GPIO general purpose interrupts (gpioJcujirq[1 1]) 27 GPIO GPIO general purpose interrupts (gpio_icu_irq[12) 28 GPIO GPIO general purpose interrupts (gpiojcujirq[13) 29 GPIO GPIO general purpose interrupts (gpio_icu_irq[14J) 30 GPIO GPIO general purpose interrupts (gpio icuirq[15]) 31 Timers Generic Timer 3 interrupt (timiJcu_irq[2) WO 2005/120835 PCT/AU2004/000706 593 16.3 IMPLEMENTATION 16.3.1 Definitions of 1/0 Table 86. Interrupt Controller Unit I/O definition Clocks and Resets pclk 1 In System Clock prstn 1 In System reset, synchronous active low CPU interface cpu-adr[7:2] 6 In CPU address bus. Only 6 bits are required to decode the address space for the ICU block cpudataout[31:0] 32 In Shared write data bus from the CPU icu-cpu-data[31:0] 32 Out Read data bus to the CPU cpu_rwn 1 In Common read/not-write signal from the CPU cpuicusel 1 In Block select from the CPU. When cpu_icu sel is high both cpuadr and cpudataout are valid icu-cpu-rdy 1 Out Ready signal to the CPU. When icu_cpLrdy is high it indicates the last cycle of the access. For a write cycle this means cpu.dataout has been registered by the ICU block and for a read cycle this means the data on icucptLdata is valid. icu-cpu-ievel[3:0] 4 Out Indicates the priority level of the current active interrupt. cpuiack 1 In Interrupt request acknowledge from the LEON core. cpu-icu-ilevel[3:0] 4 In Interrupt acknowledged level from the LEON core icu-cpu-berr 1 Out Bus error signal to the CPU indicating an invalid access. cpu-acode[1:0] 2 In CPU Access Code signals. These decode as follows: 00 - User program access 01 - User data access 10 - Supervisor program access 11 - Supervisor data access icu-cpu-debug-valid 1 Out Debug Data valid on icu_cpu_data bus. Active high Interrupts timicu-wdjirq 1 In Watchdog timer interrupt signal from the Timers block tim-icu-irq[2:0] 3 In Generic timer interrupt signals from the Timers block gpiojcu-irq[15:0] 16 In GPIO pin interrupts uhu-icu-irq 1 In USB host interrupt udu-icu-irq 1 In USB device interrupt. Iss-icu-irq[1:0] 2 In LSS interface interrupt request WO 2005/120835 PCT/AU2004/000706 594 cdufinishedband 1 In Finished band interrupt request from the CDU cdu-icu-jpegerror 1 In JPEG error interrupt from the CDU Ibdfinishedband 1 In Finished band interrupt request from the LBD te-finishedband 1 In Finished band interrupt request from the TE pcufinishedband 1 In Finished band interrupt request from the PCU pcuicuaddress invalid 1 In Invalid address interrupt request from the PCU phi-icugeneral-irq 1 In PHI general interrupt source. phi-icu_lineirq 1 In Line interrupt request from the PHI 16.3.1 16.3.2 Configuration registers The configuration registers in the ICU are programmed via the CPU interface. Refer to section 11.4 on page 76 for a description of the protocol and timing diagrams for reading and writing registers in the ICU. Note that 5 since addresses in SoPEC are byte aligned and the CPU only supports 32-bit register reads and writes, the lower 2 bits of the CPU address bus are not required to decode the address space for the ICU. When reading a register that is less than 32 bits wide zeros are returned on the upper unused bit(s) of icucpudata. Table 87 lists the configuration registers in the ICU block. The ICU block will only allow supervisor data mode accesses (i.e. cpu_acode[1:0] = SUPER VISORDA TA). 10 All other accesses will result in icu cpuberr being asserted. Table 87. ICU Register Map Ox00 - Ox7C intReg[31:0] 32x7 Ox00 Interrupt vector configuration register See Table 84 for bit field definitions, and Table 85 for interrupt source allocation. O IntClear 32 O0 Interrupt pending clear register. If written with 0_000 a one it clears corresponding interrupt 0 Bits[31:0] - Interrupts sources 31 to 0 (Reads as zero) 0x84 IntPending 32 0x000 Interrupt pending register. (Read Only) 0_000 Bits[31:0]- Interrupts sources 31 to 0 0 Ox88 IntSource 6 Ox3F Indicates the interrupt source of the last acknowledged interrupt. The NoInterrupt value is defined as all bits set to one. (Read Only) x8C DebugSelect[7:2] 6 Ox00 Debug address select. Indicates the address of the register to report on the icu_cpu data bus when it is not otherwise being used.
WO 2005/120835 PCT/AU2004/000706 595 16.3.3 ICU partition 16.3.4 Interrupt detect The ICU contains multiple instances of the interrupt detect block, one per interrupt source. The interrupt detect block examines the interrupt source signal, and determines whether it should generate request pending 5 (intpend) based on the configured interrupt type and the interrupt source conditions. If the interrupt is not masked the interrupt will be reflected to the interrupt arbiter via the int_active signal. Once an interrupt is pending it remains pending until the interrupt is accepted by the CPU or it is level sensitive and gets removed. Masking a pending interrupt has the effect of removing the interrupt from arbitration but the interrupt will still remain pending. 10 When the CPU accepts the interrupt (using the normal ISR mechanism), the interrupt controller automatically generates an interrupt clear for that interrupt source (cpu int clear). Alternatively if the interrupt is masked, the CPU can determine pending interrupts by polling the IntPending registers. Any active pending interrupts can be cleared by the CPU without using an ISR via the IntClear registers. Should an interrupt clear signal (either from the interrupt clear unit or the CPU) and a new interrupt condition 15 happen at the same time, the interrupt will remain pending. In the particular case of a level sensitive interrupt, if the level remains the interrupt will stay active regardless of the clear signal. The logic is shown below: mask = intconfig[6] type = int-config[5:4] 20 int-pend = last-int-pend // the last pending interrupt // update the pending FF // test for interrupt condition if (type == NEGLEVEL) then intpend = NOT(intsrc) 25 elsif (type == POSLEVEL) int-pend = intsrc elsif ((type == POSEDGE) AND (int-src == 1) AND (last_intsrc == 0)) int-pend = 1 elsif ((type == NEGEDGE) AND (intsrc == 0) AND (last_int_src == 1)) 30 int-pend = 1 elsif ((int-clear == 1)OR (cpu_intclear==1)) then intpend = 0 else int-pend = lastint-pend // stay the same as before 35 // mask the pending bit if (mask == 1) then int-active = intpend else int_active = 0 40 // assign the registers lastint-src = int-src lastint-pend = int-pend WO 2005/120835 PCT/AU2004/000706 596 16.3.5 Interrupt arbiter The interrupt arbiter logic arbitrates a winning interrupt request from multiple pending requests based on configured priority. It generates the interrupt to the CPU by setting icucpu_ilevel to a non-zero value. The priority of the interrupt is reflected in the value assigned to icucpu_ilevel, the higher the value the higher the 5 priority, 15 being the highest, and 0 considered no interrupt. // arbitrate with the current winner int_ilevel = 0 for (i=0;i<32;i++) { if (int-active[i] == 1) then 10 if (intconfig[i][3:0] > winint-ilevel[3:0]) then winint_ilevel[3:0] = int-configi][3:0} } 15 // assign the CPU interrupt level int_ilevel = win-int-ilevel[3:0] 16.3.6 Interrupt clear unit The interrupt clear unit is responsible for accepting an interrupt acknowledge from the CPU, determining which interrupt source generated the interrupt, clearing the pending bit for that source and updating the 20 IntSource register. When an interrupt acknowledge is received from the CPU, the interrupt clear unit searches through each interrupt source looking for interrupt sources that match the acknowledged interrupt level (cpu-icu ilevel) and determines the winning interrupt (lower interrupt source numbers have higher priority). When found the interrupt source pending bit is cleared and the IntSource register is updated with the interrupt source number. 25 The LEON interrupt acknowledge mechanism automatically disables all other interrupts temporarily until it has correctly saved state and jumped to the ISR routine. It is the responsibility of the ISR to re-enable the interrupts. To prevent the IntSource register indicating the incorrect source for an interrupt level, the ISR must read and store the IntSource value before re-enabling the interrupts via the Enable Traps (ET) field in the Processor State Register (PSR) of the LEON. 30 See section 11.9 on page 113 for a complete description of the interrupt handling procedure. After reset the state machine remains in Idle state until an interrupt acknowledge is received from the CPU (indicated by cpu jack). When the acknowledge is received the state machine transitions to the Compare state, resetting the source counter (cnt) to the number of interrupt sources. While in the Compare state the state machine cycles through each possible interrupt source in decrementing 35 order. For each active interrupt source the programmed priority (int_priority[cnt[3:0]) is compared with the acknowledged interrupt level from the CPU (cpuicuilevel), if they match then the interrupt is considered the new winner. This implies the last interrupt source checked has the highest priority, e.g interrupt source zero has the highest priority and the first source checked has the lowest priority. After all interrupt sources are WO 2005/120835 PCT/AU2004/000706 597 checked the state machine transitions to the IntClear state, and updates the int_source register on the transition. Should there be no active interrupts for the acknowledged level (e.g. a level sensitive interrupt was removed), the IntSource register will be set to NoInterrupt. NoInterrupt is defined as the highest possible value that 5 IntSource can be set to (in this case Ox3F), and the state machine will return to Idle. The exact number of compares performed per clock cycle is dependent the number of interrupts, and logic area to logic speed trade-off, and is left to the implementer to determine. A comparison of all interrupt sources must complete within 8 clock cycles (determined by the CPU acknowledge hardware). When in the IntClear state the state machine has determined the interrupt source to clear (indicated by the 10 int_source register). It resets the pending bit for that interrupt source, transitions back to the Idle state and waits for the next acknowledge from the CPU. The minimum time between successive interrupt acknowledges from the CPU is 8 cycles. 17 TIMERS BLOCK (TIM) 15 The Timers block contains general purpose timers, a watchdog timer and timing pulse generator for use in other sections of SoPEC. 17.1 TIMING PULSE GENERATOR The timing block contains a timing pulse generator clocked by the system clock, used to generate timing pulses of programmable periods. The period is programmed by accessing the TimerStartValue registers. Each 20 pulse is of one system clock duration and is active high, with the pulse period accurate to the system clock frequency. The periods after reset are set to lus, 100ps and 100 ms. The timing pulses are used internally in the timers block for the watchdog and generic timers, and are exported to the GPIO block for other timing functions. The timing pulse generator also contains a 64-bit free running counter that can be read or reset by accessing 25 the FreeRunCount registers. The free running counter can be used to determine elapsed time between events at system clock accuracy or could be used as an input source in low-security random number generator. 17.2 WATCHDOG TIMER The watchdog timer is a 32 bit counter value which counts down each time a timing pulse is received. The period of the timing pulse is selected by the WatchDogUnitSel register. The value at any time can be read 30 from the WatchDogTimer register and the counter can be reset by writing a non-zero value to the register. When the counter transitions from 1 to 0, a system wide reset will be triggered as if the reset came from a hardware pin. The watchdog timer can be polled by the CPU and reset each time it gets close to 1, or alternatively a threshold (WatchDogIntThres) can be set to trigger an interrupt for the watchdog timer to be serviced by the WO 2005/120835 PCT/AU2004/000706 598 CPU. If the WatchDoglntThres is set to N, then the interrupt will be triggered on the N to N-I transition of the WatchDogTimer. This interrupt can be effectively masked by setting the threshold to zero. The watchdog timer can be disabled, without causing a reset, by writing zero to the WatchDogTimer register. All write accesses to the WatchDogTimer register are protected by the WatchDogKey register. The CPU must 5 write the value OxDEADFIDO to the WatchDogKey register to enable a write access to the WatchDogTimer register. The next access (and only the next access) to the timers address space will be allowed to write to the WatchDogTimer, all subsequent accesses will not be allowed to write to the WatchDogTimer. Any access to any register in the timers address space will clear the write enable key to the WatchDogTimer. An attempt to write to the WatchDogTimer when writes are not enabled will have no effect. 10 17.3 GENERIC TIMERS SoPEC contains 3 programmable generic timing counters, for use by the CPU to time the system. The timers are programmed to a particular value and count down each time a timing pulse is received. When a particular timer decrements from 1 to 0, an interrupt is generated. The counter can be programmed to automatically restart the count, or wait until re-programmed by the CPU. At any time the status of the counter can be read 15 from GenCntValue, or can be reset by writing to GenCntValue register. The auto-restart is activated by setting the GenCntAuto register, when activated the counter restarts at GenCntStart Value. A counter can be stopped or started at any time, without affecting the contents of the GenCntValue register, by writing a 1 or 0 to the relevant GenCntEnable register. 17.4 IMPLEMENTATION 20 17.4.1 Definitions of 1/0 Table 88. Timers block 1/O definition Clocks and Resets pcIk 1 In System Clock prstn 1 In System reset, synchronous active low timpulse[2:0] 3 Out Timers block generated timing pulses, each one pc/k wide 0 - Nominal 1 pas pulse 1 - Nominal 100 ps pulse 2 - Nominal 10ms pulse CPU Interface cpu-adr[6:2] 5 In CPU address bus. Only 5 bits are required to decode the address space for the ICU block cpudataout[31:0] 32 In Shared write data bus from the CPU Tim-cpudata[31:0] 32 Out Read data bus to the CPU WO 2005/120835 PCT/AU2004/000706 599 cpu_rwn 1 In Common read/not-write signal from the CPU cputimsel 1 In Block select from the CPU. When cpu_tim_sel is high both cpuadr and cpu.dataout are valid Tim.cpu-rdy 1 Out Ready signal to the CPU. When timcpurdy is high it indicates the last cycle of the access. For a write cycle this means cpudataout has been registered by the TIM block and for a read cycle this means the data on tim_cpLLdata is valid. Tim_cpuberr 1 Out Bus error signal to the CPU indicating an invalid access. cpu-acode[1:0] 2 In CPU Access Code signals. These decode as follows: 00 - User program access 01 - User data access 10 - Supervisor program access 11 - Supervisor data access Timcpudebugvalid 1 Out Debug Data valid on timcpujdata bus. Active high Miscellaneous Timicuwdirq 1 Out Watchdog timer interrupt signal to the ICU block Tim-icu-irq[2:0] 3 Out Generic timer interrupt signals to the ICU block Timcpr reset-n 1 Out Watch dog timer system reset. 17.4.1 17.4.2 Timers sub-block partition 17.4.3 Watchdog timer The watchdog timer counts down from a pre-programmed value, and generates a system wide reset when 5 equal to one. When the counter passes a pre-programmed threshold (wdogtimthres) value an interrupt is generated (timicuwdirq) requesting the CPU to update the counter. Setting the counter to zero disables the watchdog reset. In supervisor mode the watchdog counter can be written to directly after a valid write of OxDEADFlDO to the WatchDogKey register, it can be read from at any time. In user mode all access (both read and write) is denied. Any accesses in user mode will generate a bus error. 10 The counter logic is given by if (wdogwen == 1) then wdogtim-cnt = writedata // load new data elsif ( wdogtim-cnt == 0) then wdogtim._cnt = wdogtim-cnt // count disabled 15 elsif (cnt-en == 1) then wdog-timcntelse wdogtim-cnt = wdogtim-cnt The timer decode logic is 20 if ((wdog-tincnt == wdog-tim-thres) AND (wdogtim-cnt!= 0) AND (cnt-en == 1)) then tim_icu_wdirq = 1 else timicu-wd_irq = 0 WO 2005/120835 PCT/AU2004/000706 600 // reset generator logic if (wdogtimcnt == 1) AND (cnten == 1) then tirncprreset_n = 0 else 5 tim-cpr_resetn = 1 17.4.4 Generic timers The generic timers block consists of 3 identical counters. A timer is set to a pre-configured value (GenCntStartValue) and counts down once per selected timing pulse (gen unit sel). The timer can be enabled 10 or disabled at any time (gentim en), when disabled the counter is stopped but not cleared. The timer can be set to automatically restart (gentimauto) after it generates an interrupt. In supervisor mode a timer can be written to or read from at any time, in user mode access is determined by the GenCntUserModeEnable register settings. 15 The counter logic is given by if (gen-wen == 1) then gentim-cnt = writedata elsif ((cnt-en == 1) AND (gentinen == 1)) then if (gentimcnt == 1) OR (gentim-cnt == 0) then // counter may need re 20 starting if (gentimauto == 1) then gentim_cnt = gentimcnt-st-value else gentim-cnt = 0 // hold count at zero 25 else gen-tim_cntelse gen-tim-cnt = gentim-cnt The decode logic is 30 if (gen-tim-cnt == 1)AND (cnt-en == 1)AND (gen-tim-en == 1) then timicu_irq = 1 else timicu_irq = 0 17.4.5 Timing pulse generator 35 The timing pulse generator contains a general free running 64-bit timer and 3 timing pulse generators producing timing pulses of one cycle duration with a programmable period. The period is programmed by changed the TimerStartValue registers, but have a nominal starting period of 1Is, 100s and Ims. Note that each timing pulses is generated from the previous timer pulse and so cascade. A change of the timer period 0 will affect the other timer periods. The maximum period for timer 0 is 1.331ps (256 x pclk), timer 1 is 341gs 40 (256 x 1.33 Igs) and timer 2 is 87ms (256 x 341 Is). In supervisor mode the free running timer register can be written to or read from at any time, in user mode access is denied. The status of each of the timers can be read by accessing the PulseTimerStatus registers in supervisor mode. Any accesses in user mode will result in a bus error.
WO 2005/120835 PCT/AU2004/000706 601 17.4.5.1 Free Run Timer The increment logic block increments the timer count on each clock cycle. The counter wraps around to zero and continues incrementing if overflow occurs. When the timing register (FreeRunCount) is written to, the configuration registers block will set thefree_runwen high for a clock cycle and the value on write data will 5 become the new count value. If free_run wen[1] is 1 the higher 32 bits of the counter will be written to, otherwise if freerun wen[0] the lower 32 bits are written to. It is the responsibility of software to handle these writes in a sensible manner. The increment logic is given by if (free-run wen[l] == 1) then 10 free-run-cnt[63:32] = writedata elsif (free-run wen(O] == 1) then free-run-cnt(31:0] = write-data else freerun cnt ++ 15 17.4.5.2 Pulse Timers The pulse timer logic generates timing pulses of I clock cycle length and programmable period. Nominally they generate pulse periods of lIs, 100s and lms. The logic for timer 0 is given by: // Nominal lus generator if (pulse_0_cnt == 0) then 20 pulseOcnt = timerstart-value[0] timpulse[O]= 1 else pulseOcnt tim-pulse[0]= 0 25 The logic for timer 1 is given by: // 100us generator if ((pulse_1_cnt == 0) AND (tim-pulse(O] == 1)) then pulselcnt = timer_startvalue[l] 30 tim-pulse[l]= 1 elsif (timpulse[O] == 1) then pulselcnt timpulse[l]= 0 else 35 pulselcnt = pulse_1_cnt timpulse[l]= 0 The logic for the timer 2 is given by: // lOms generator 40 if ((pulse_2_cnt == 0) AND (tim-pulse[l] == 1)) then pulse_2_cnt = timer.start value[2] timpulse[2]= 1 elsif (tim-pulse[l] == 1) then pulse_2_cnt - 45 timpulse[2]= 0 else WO 2005/120835 PCT/AU2004/000706 602 pulse_2_cnt = pulse_2_cnt timpulse[2]= 0 17.4.6 Configuration registers The configuration registers in the TIM are programmed via the CPU interface. Refer to section 11.4.3 on page 5 77 for a description of the protocol and timing diagrams for reading and writing registers in the TIM. Note that since addresses in SoPEC are byte aligned and the CPU only supports 32-bit register reads and writes, the lower 2 bits of the CPU address bus are not required to decode the address space for the TIM. When reading a register that is less than 32 bits wide zeros are returned on the upper unused bit(s) of tim_pcudata. Table 89 lists the configuration registers in the TIM block. Table 89. Timers Register Map 1 - Nominal 100 js pulse 2 - Nominal 10 ms pulse 3 - pclk 0x04 WatchDogTimer 32 OxFFF Specifies the number of units to FFFF count before watchdog timer ___________ _______________F triggers. Ox08 WatchDoglntThres 32 Ox0000 Specifies the threshold value below 0000 which the watchdog timer issues an interrupt OxOC-Ox10 FreeRunCount[1:0] 2x32 OxOOOO Direct access to the free running 0000 counter register. Bus 0 - Access to bits 31-0 Bus 1 - Access to bits 63-32 Oxi 4 to Ox1 C GenCntStartValue[2:0 3x32 OxOOO Generic timer counter start value, _0000 number of units to count before event Ox20 to 0x28 GenCntValue[2:0] 3x32 OxOOO Direct access to generic timer 0000 counter registers 0x30 WatchDogKey 32 OxOOOO Watchdog Timer write enable key. 0000 A write of OxDEADF1 DO will enable the subsequent access of the timers block to write to the WatchDogTimer register. Any other access will disable WatchDogTimer write access. (Reads as zero) 0x40 to 0x48 GenCntUnitSel[2:0] 3x2 Ox0 Generic counter unit select. Selects the timing units used with corresponding counter: 0 - Nominall gs pulse 1 - Nominal100 ps pulse 2 - Nominal 10 ms pulse ___________3 - pclk WO 2005/120835 PCT/AU2004/000706 603 Ox4C to 0x54 GenCntAuto[2:0] 3x1 Ox0 Generic counter auto re-start select. When high timer automatically restarts, otherwise timer stops. Ox58 to 0x60 GenCntEnable[2:0] 3x1 Ox0 Generic counter enable. 0 - Counter disabled 1 - Counter enabled 0x64 GenCntUserModeEna 3 Ox0 User Mode Access enable to ble generic timer configuration register. When 1 user access is enabled. Bit 0 - Generic timer 0 Bit 1 - Generic timer 1 Bit 2 - Generic timer 2 Ox68 to 0x70 TimerStartValue[2:0] 3x8 OxBF, Timing pulse generator start value. Ox63, Indicates the start value for each 0x63 timing pulse timers. For timer 0 the start value specifies the timer period in pclk cycles - 1. For timer 1 the start value specifies the timer period in timer 0 intervals -1. For timer 2 the start value specifies the timer period in timer 1 intervals -1. Nominally the timers generate pulses at 1us,100us and 1Oms intervals respectively. Ox74 DebugSelect[6:2] 5 Ox00 Debug address select. Indicates the address of the register to report on the timcpu data bus when it is not otherwise being used. Read Only Registers 0x78 PulseTimerStatus 24 Ox00 Current pulse timer values, and pulses 7:0 - Timer 0 count 15:8 - Timer 1 count 23:16 - Timer 2 count 24 - Timer 0 pulse 25 - Timer 1 pulse 26 - Timer 2 pulse 17.4.6.1 Supervisor and user mode access The configuration registers block examines the CPU access type (cpuacode signal) and determines if the access is allowed to that particular register, based on configured user access registers. If an access is not 5 allowed the block will issue a bus error by asserting the tim cpuberr signal. The timers block is fully accessible in supervisor data mode, all registers can written to and read from. In user mode access is denied to all registers in the block except for the generic timer configuration registers that are granted user data access. User data access for a generic timer is granted by setting corresponding bit in the GenCntUserModeEnable register. This can only be changed in supervisor data mode. If a particular timer is 10 granted user data access then all registers for configuring that timer will be accessible. For example if timer 0 WO 2005/120835 PCT/AU2004/000706 604 is granted user data access the GenCntStartValue[O], GenCntUnitSel[O], GenCntAuto[O], GenCntEnable[O] and GenCntValue[O] registers can all be written to and read from without any restriction. Attempts to access a user data mode disabled timer configuration register will result in a bus error. Table 90 details the access modes allowed for registers in the TIM block. In supervisor data mode all registers 5 are accessible. All forbidden accesses will result in a bus error (tim cpu berr asserted). Table 90. TIM supervisor and user access modes Register Realsters ,Access Permission Ox00 WatchDogUnitSel Supervisor data mode only 0x04 WatchDogTimer Supervisor data mode only 0x08 WatchDoglntThres Supervisor data mode only OxOC-Ox1 0 FreeRunCount Supervisor data mode only Ox1 4 GenCntStartValue[0] GenCntUserModeEnable[0] Ox18 GenCntStartValue[1 ] GenCntUserModeEnable[1] OxI C GenCntStartValue[2] GenCntUserModeEnable[2] 0x20 GenCntValue[0] GenCntUserModeEnable0] 0x24 GenCntValue[1] GenCntUserModeEnable[1] 0x28 GenCntValue[2] GenCntUserModeEnable[2] 0x30 WatchDogKey Supervisor data mode only 0x40 GenCntUnitSel[0] GenCntUserModeEnable[0] 0x44 GenCntUnitSel[1] GenCntUserModeEnable[1] Ox48 GenCntUnitSel[2] GenCntUserModeEnable[2] Ox4C GenCntAuto[0] GenCntUserModeEnable[0] 0x50 GenCntAuto[1] GenCntUserModeEnable[1] 0x54 GenCntAuto[2] GenCntUserModeEnable[2] 0x58 GenCntEnable[0] GenCntUserModeEnable[0] Ox5C GenCntEnable[1] GenCntUserModeEnable[1] 0x60 GenCntEnable[2] GenCntUserModeEnable[2] 0x64 GenCntUserModeEnable Supervisor data mode only 0x68-0x70 TimerStattValue[2:0] Supervisor data mode only 0x74 DebugSelect Supervisor data mode only 0x78 PulseTimerStatus Supervisor data mode only WO 2005/120835 PCT/AU2004/000706 605 18 CLOCKING, POWER AND RESET (CPR) The CPR block provides all of the clock, power enable and reset signals to the SoPEC device. 18.1 POWERDOWN MODES 5 The CPR block is capable of powering down certain sections of the SoPEC device. When a section is powered down the clocks to that section are gated in a controlled way to prevent clock glitching. When a section is powered back up the clock is re-enabled without introducing any glitches. Except in the case of the DIU section, all blocks contained in a section will retain their state while powered down. The DIU is unable to retain state as it relies on a refresh circuit to sustain state in DRAM. 10 There are 2 types of powerdown mode, sleep and snooze mode (configured by the SnoozeModeSelect register). In sleep mode when a section is powered down and powered back up again, the CPR automatically resets all the blocks in the section, effectively clearing any retained state. In snooze mode when a section is powered down and back up again the blocks are not automatically reset, and so state is retained. In the case of the PSS state is retained regardless of whether sleep or snooze mode is used to powerdown the 15 block. For the purpose of powerdown the SoPEC device is divided into sections: Table 91. Powerdown sectioning CPU system Section 0 CPU,MMU,ICU,ROM,PSS,LSS PEP Section 1 PCU,CDU,CFU,LBD,SFU,TE,TFUHCUDNC SubSystem ,DWU,LLU,PHI MMI System Section 2 GPIO, MMI,TIM DIU System Section 3 DIU (includes DCU,DAU and DRAM) USB Device Section 4 UDU USB Host Section 5 UHU USB PHY Section 6 USB PHY (common block and all transceivers) Note that the CPR block is not located in any section. All configuration registers in the CPR block are clocked by an ungateable clock and have special reset conditions. 20 18.1.1 Sleep mode Each section can be put into sleep (or snooze) mode by setting the corresponding bit in the SleepModeEnable register. To re-enable the section the sleep mode bit needs to be cleared. Any section re-enabled from sleep WO 2005/120835 PCT/AU2004/000706 606 mode will be automatically reset, those re-enabled from snooze will not. The CPU may choose to reset the section independently at a later stage. Any sections that are reset will need to be re-configured by the CPU. If the CPU system (section 0) is put into sleep mode, the SoPEC device will remain in sleep mode until either a reset or wakeup condition is detected. The reset condition could come from the external reset pin, the 5 power-on detect macro, the brown-out detect macro, or the watchdog timer (if the section 2 was left powered up). The wakeup condition could come from any of the USB PHY ports, the UDU or the GPIO. In the case of the GPIO and UDU they must be left powered on for them to be capable of generating a wakeup condition. The USB PHY can generate a wakeup condition regardless of its powered state. 18.1.2 Sleep/Snooze Mode powerdown procedure 10 When powering down a section, the section will retain its current state (except in the DIU section). It is possible when powering back up a section that inconsistencies between interface state machines could cause incorrect operation. In order to prevent such conditions from happening, all blocks in a section must be disabled before powering down. This will ensure that blocks are restored in a benign state when powered back up. 15 In the case of PEP section units setting the Go bit to zero will disable the block. To correctly powerdown PHI LVDS outputs the CPU must disable the PHI data and clock outputs by setting PhiDataEnable and PhiClkEnable registers to zero. The DRAM subsystem can be effectively disabled by setting the RotationSync bit to zero. The USB host and device sections should be in suspend state, with all DMA channels disabled before 20 powering down. The USB device cannot be put into suspend mode by SoPEC it requires the host to suspend the USB bus. The USB PHY should only be powered down if both the USB host and device are powered down first, requiring that all transceivers are in suspend state. When powering down the MMI section: 25 0 Disable both MMI engines, and both MMI DMA channels e Disable the timing pulse generator, and watchdog timer in the TIM block e Disable all GPIO interrupts To powerdown the CPU section: e Load all the code and data needed to powerdown into the caches 30 e (Optionally) Disable traps (or at least interrupts) e Perform a dummy write to a CPU subsystem location to flush the MMU DRAM write buffer e Write to the SleepModeEnable in the CPR to powerdown the CPU section WO 2005/120835 PCT/AU2004/000706 607 18.2 EXTERNAL RESET SOURCES SoPEC has 3 possible external reset sources, power-on reset (POR), brown-out detect (BOD) and the reset_n pm. The POR macro monitors the device core voltage and keeps its reset active while the voltage is below a 5 threshold (approximately 0.7v-1.05v). The BOD macro monitors the voltage on the Vcomp pad and activates its reset whenever the pad voltage drops below a threshold (also approximately 0.7v-1.05v). It is intended that the Vcomp pad be connected to the power supply unregulated output to allow SoPEC to detect a brownout condition early and take action before the core supply gets removed. Note the Vcomp pad is connected through a resistive divider and not 10 directly to the power supply output. Should there be any operating issues with the POR and BOD macros both can be disabled by setting the por-bo disable pin to 1. The reset n pin allows SoPEC to be reset by an external device. The reset n pin and Vcomp pin are susceptible to glitches that could trigger a system wide reset in SoPEC. As 15 a result the output of the BOD macro and the reset n pin are filtered by an 100us deglitch circuit before triggering a system reset in the device. 18.3 SOFTWARE RESET The CPR provides a mechanism to reset any individual section by accessing the ResetSection register. Like all 20 software resets in SoPEC the ResetSection register is active-low i.e. a 0 should be written to each bit position requiring a reset. The ResetSection register is self-resetting. The CPU can determine if a reset is still in progress by reading the ResetSection register, any bits still 0 indicate a reset in progress. If a section is powered down and the CPU activates a section reset the CPR will automatically re-enable the clock to that section for the duration of the reset. Once the reset is complete the section will be returned to 25 power down mode. Resets of sections 0 to 4 will take approximately 16 pclk cycles, section 5 will take 64 pclk cycles and, section 6 will take approximately lOus. The CPU can also control the external reset pins, resetoutn and phi rst-n[1:0] by accessing the ResetPin register. Values in this register are reflected directly on the external pins (assuming a system reset condition is 30 not active at the time). Bits in this register are not self-resetting, and should be reset by the CPU after the required duration to reset the external device has passed.
WO 2005/120835 PCT/AU2004/000706 608 18.4 RESET SOURCE The SoPEC device can be reset by a number of sources. When a reset from an internal source is initiated the reset source register (ResetSrc) stores the reset source value. This register can then be used by the CPU to determine the type of boot sequence required after reset. 5 18.5 WAKEUP The SoPEC device has a number of sources of wakeup. A wakeup event will power up the CPU and DIU sections and possibly others sections depending on the event type. A wakeup source can be disabled by the CPU before going to sleep by writing to the relevant bit in the WakeUpMask register. When the CPU restarts after up after a wakeup event it can determine the wakeup source that caused the event by reading the 10 ResetSrc register. The CPU can then determine the correct wakeup procedure to follow. Table 92. Section power-on state after wakeup event Wakeup Source CPU DIU PEP MMI UU UDU gpio.cpr..wakeup On On Same On" Same Same Same uduint_wakeup On On Same Same Same On" On" uduwakeup On On Same Same Same On On uhuwakeup On On Same Same On Same On a. Note event could only happen if section was already turned on The UHU wakeup is determine by monitoring the line state signals of the USB PHY ports allocated to the 15 host. UHU wakeup is only enabled when the CPU has powered down the UHU block. A wakeup condition is defined as a high state on any of the line state signals for longer than 63 pclk cycles (approx 4 bit times at 12Mbs). The UHU wakeup condition is intended to detect a device connect on the USB bus and wakeup the system. Others line state events are detected by the UHU itself. The UDU wakeup (resume) is determined by monitoring the suspendm signal from the UDU. A high value of 20 longer than 63 pclk cycles will generate an uduwakeup event. The gpio cprwakeup and the udunt_wakeup are generated by the GPIO and UDU block respectively. Both events can only be generated if the respective blocks are powered on. 18.6 CLOCK RELATIONSHIP The crystal oscillator excites a 32MHz crystal through the xtalin and xtalout pins. The 32M1z output is used 25 by the PLL to derive the master VCO frequency of 1152MHz. The master clock is then divided to produce 192MHz clock (clk a), 288MHz clock (clk-b), and 96MHz (clk-c) clock sources.
WO 2005/120835 PCT/AU2004/000706 609 The default settings of the oscillator in SoPEC allow an input range of 20-60Mhz. The PLL can be configured to generate different clock frequencies and relationships, but the internal PLL VCO frequency must be in the range 850MHz to 1500MHz. Note in order to use the any of the USB system the usbrefclk must be 48Mhz. The phase relationship of each clock from the PLL will be defined. The relationship of internal clocks clka, 5 clk b and clk c to xtalin will be undefined. At the output of the clock block, the skew between each pclk domain (pclk section[5:0] and jclk) should be within skew tolerances of their respective domains (defined as less than the hold time of a D-type flip flop). The phiclk and pclk have no defined phase relationship are treated as asynchronous in the design. The PLL output C (clk_c) is used to generate uhu_48clk (48MHz) and the uhu_12clk (12MHz) clocks for use 10 in the UHU block. Both clocks are treated as synchronous and at the output of the clock block the skew between each both domains should be within the skew tolerances of their respective domains. The usbrefclk is also derived from the PLL output C (clkc) but has no relationship to the other clocks in the system and is considered asynchronous. It is used as a reference clock for the USB PHY PLL. 18.7 OSC AND PLL CONTROL 15 The PLL in SoPEC can be adjusted by programming the PLLRangeA, PLLRangeB, PLLRangeC, PLLTunebits, PLLGenCtrl and PLLMult registers. The oscillator series damping register can be adjusted by programming the OscRDamp register. If these registers are changed by the CPU the values are not updated until the PLL Update register is written to. Writing to the PLL Update register triggers the PLL control state machine to update the PLL configuration in a safe way. When an update is active (as indicated by PLL Update 20 register) the CPU must not change any of the configuration registers, doing so could cause the PLL to lose lock indefinitely, requiring a hardware reset to recover. Configuring the PLL registers in an inconsistent way can also cause the PLL to lose lock, care must taken to keep the PLL configuration within specified parameters. The PLLGenCtrl provides a mechanism for powering down and disabling the output dividers of the PLL. The 25 output dividers are disabled by setting the PLLDivOFF bits in the PLLGenCtrl register. Once a divider is turned all clocks derived from it's output will be disabled. If the pilouta divider is disabled (used to generate pclk) the CPU will be disabled, and the only recovery mechanism, will be a system reset. The VCO and voltage regulator of the PLL can be disabled by setting the VCO power off, and Regulator power off bits of the PLLGenCtrl register. Once either bit is set the PLL will not generate any clock (unless 30 the PLL bypass bit is set) and the only recovery mechanism will be a system reset. The PLL bypass bit can be used to bypass the PLL VCO circuit and feed the refclk input directly to the PLL outputs. The PLL feedback bit selects if internal or external feedback is used in the PLL. The VCO frequency of the PLL is calculated by the number of dividers in the feedback path. The PLL internal VCO output is used as the feedback source. 35 VCOfreq = REFCLK x PLLMult x External divider WO 2005/120835 PCT/AU2004/000706 610 VCOfreq=32 x36x1=1152Mhz. In the default PLL setup, PLLMult is set to Ox8d (or x36), PLLRangeA is set to OxC which corresponds to a divide by 6, PLLRangeB is set to OxE which corresponds to a divide by 4 and PLLRangeC is set to 0x8 which corresponds to a divide by 12. 5 PLLouta = VCOfreq / PLLRangeA = 1152Mhz / 6 = 192 Mhz PLLoutb= VCOfreq / PLLRangeB= 1152Mhz / 4 = 288 Mhz PLLoutc = VCOfreq / PLLRangeC= 1152Mhz / 12 =96 Mhz The PLL selected is PLL8SFLP (low power PLL), and the oscillator is OSCRFBK with integrated parallel feedback resistor. 10 18.8 IMPLEMENTATION 18.8.1 Definitions of 1/0 Table 93. CPR I/O definition CPR miscellaneous control Xtalin 1 In Crystal input, direct from 10 pin. Xtalout 1 Inout Crystal output, direct to 10 pin. Bufoscout 1 Out Buffered version of the output oscillator Jclk-enable 1 In Gating signal for jc/k. When 1 jclk is enabled Clocks pclkcsection[5:0] 6 Out System clocks for each pc/k section Phiclk 1 Out Data out clock (1.5 x pck) for the PHI block Jclk 1 Out Gated version of system clock used to clock the JPEG decoder core in the CDU Usbrefclk 1 Out USB PHY reference clock, nominally at 48 MHz uhu_48clk 1 Out UHU 48MHz USB clock. uhu_12clk 1 Out UHU12MHz USB clock. Synchronous to uhu_48c/k. Reset inputs and wakeup resetn 1 In Reset signal from the resetLn pin. Active low Vcomp 1 In Voltage compare input to the Brown Out detect macro (Analog) por-bo-disable 1 In POR and Brown out macro disable. Active high. tim_cpr~jeset-n 1 In Reset signal from watch dog timer. Active low. gpio-cpr.wakeup 1 In SoPEC wakeup from the GPIO. Active high.
WO 2005/120835 PCT/AU2004/000706 611 udu-icu-irq 1 In USB device interrupt signal to the ICU. Used to detect the a UDU interrupt wakeup condition. phy-line-state[2:0][1:0] 3x2 In The current state of the D+/- receivers of each UHU port of the USB PHY. Used to detect PHY generated wakeup conditions. udu-suspendm 1 In UDU suspend signal to indicate that UHU PHY port should be suspended. Also used to determine a USB resume wakeup event. cpr-phy-suspendm 1 Out CPR PHY suspend mode for UDU PHY port (deglitched version of udu.suspendm) cpr_phypdown 1 Out CPR powerdown control of USB multi-port PHY. Reset (Outputs) prst-n_section[5:0] 6 Out System resets for each section, synchronous active low phirst_n 1 Out Reset for PHI block, synchronous to phiclk active low cprphy_resetn 1 Out Reset for the USB PHY block, synchronous to usbrefclk resetout-n 1 Out Reset Output (direct to 10 pin) to other system devices, active low. phi-rstn[1:0] 2 Out Reset out (direct to 10 pins) to the printhead. Active low CPU Interface cpu-adr[6:2] 5 In CPU address bus. Only 5 bits are required to decode the address space for the CPR block cpu-dataout[31:0] 32 In Shared write data bus from the CPU cpr_cpudata[31:0] 32 Out Read data bus to the CPU cpu_rwn 1 In Common read/not-write signal from the CPU cpu-cpr-sel 1 In Block select from the CPU. When cpcprsel is high both cpu_adr and cpLdataout are valid cpr.cpu-rdy 1 Out Ready signal to the CPU. When cprcpu.rdy is high it indicates the last cycle of the access. For a write cycle this means cpu.dataout has been registered by the block and for a read cycle this means the data on cprcpujdata is valid. cpr.cpu-berr 1 Out Bus error signal to the CPU indicating an invalid access. cpu-acode[1:0] 2 In CPU Access Code signals. These decode as follows: 00 - User program access 01 - User data access 10 - Supervisor program access 11 - Supervisor data access cprcpudebug_valid 1 Out Debug Data valid on cprcpu._data bus. Active high 18.8.2 Configuration registers The configuration registers in the CPR are programmed via the CPU interface. Refer to section 11.4 on page 76 for a description of the protocol and timing diagrams for reading and writing registers in the CPR. Note WO 2005/120835 PCT/AU2004/000706 612 that since addresses in SoPEC are byte aligned and the CPU only supports 32-bit register reads and writes, the lower 2 bits of the CPU address bus are not required to decode the address space for the CPR. When reading a register that is less than 32 bits wide zeros are returned on the upper unused bit(s) of cpr_pcudata. Table 94 lists the configuration registers in the CPR block. 5 The CPR block will only allow supervisor data mode-accesses (i.e. cpuacode[1:0] = SUPER VISORDATA). All other accesses will result in cprcpuberr being asserted. Table 94. CPR Register Map PR as Bitte 4bt Ree Cotrl sctionUBdvc 0x00 SleepModeEnabl 7 0x00 Sleep Mode enable, when high a section of e logic is put into powerdown. Bit 0 - Controls section 0, CPU system Bit 1 - Controls section 1, PEP system Bit 2 - Controls section 2, MMI system Bit 3 - Controls section 3, DIU system Bit 4 - Controls section 4, USB device Bit 5 - Controls section 5, USB host Bit 6 - Controls section 6, USB PHY 0x04 SnoozeModeSel 7 0x00 Selects if a section goes into Sleep or ect Snooze mode when its SleepModeEnable bit is set. One bit per section 0 - Sleep mode 1 - Snooze mode Ox08 ResetSrc 6 0x1 Reset Source register, indicating the source of the last reset Bit 0 - External Reset (includes brownout or POR) Bit 1 - Watchdog timer reset Bit 2 - GPIO wakeup Bit 3 - UDU wakeup (resume condition) Bit 4 - UDU wakeup (interrupt generated wakeup) Bit 5 - UHU wakeup (Read Only Register) 0xI 0 WakeUpMask 4 Ox0 Wakeup mask register, when a bit is 1 the corresponding wakeup is disabled. Bit 0 - GPIO wakeup Bit 1 - UDU wakeup (resume condition) Bit 2 - UDU wakeup (interrupt generated wakeup) Bit 3 - UHU wakeup 0x1 4 ResetSection 7 Ox7F Active-low synchronous reset for each section, self-resetting. Bits 4-0 self reset after 16 pclk cycles, bit 5 after 64 pclk cycles, bit 6 self resets after 10 us. Bit 0 - Controls section 0, CPU system Bit 1 - Controls section 1, PEP system Bit 2 - Controls section 2, MMI system Bit 3 - Controls section 3, DIU system Bit 4 - Controls section 4, USB device Bit 5 - Controls section 5, USB host Bit 6 - Controls section 6, PHY and all transceivers MaInta writinnn n At g hit Will etart a rocat WO 2005/120835 PCT/AU2004/000706 613 sequence, writing a 1 will not terminate the sequence. Ox18 ResetPin 3 Ox0 Software control of external reset pins Bit 0 - Controls resetoutn pin Bit 1 - Controls phi rstn[O] pin Bit 2 - Controls phi rst n[l] pin Ox1C DebugSelect[6:2] 5 Ox00 Debug address select. Indicates the address of the register to report on the cprcputdata bus when it is not otherwise being used. PLL Control Ox20 PLLTuneBits 10 Ox3BC PLL tuning bits 0x24 PLLRangeA 4 OxC PLLOUT A frequency selector (defaults to 192Mhz with 1152Mhz VCO) Ox28 PLLRangeB 4 OxE PLLOUT B frequency selector (defaults to 288Mhz with 1152Mhz VCO) Ox2C PLLRangeC 4 Ox8 PLLOUT C frequency selector (defaults to 96Mhz with 1152Mhz VCO) 0x30 PLLMultiplier 8 Ox8D PLL multiplier selector, defaults to refclk x 36 0x34 PLLGenCtrI 6 0x00 PLL General Control. When 0 the output divider is enabled when 1 the output divider is disabled. Bit 0 -PLL Output Divider A, when 1 divider is disabled Bit 1 -PLL Output Divider B, when 1 divider is disabled Bit 2 -PLL Output Divider C, when 1 divider is disabled Bit 3 - VCO power off, when 1 PLL VCO is disabled. If disabled refclk will be the only clock available in the system. Bit 4 - Regular power off, when 1 PLL voltage regulator is disabled Bit 5 - PLL Bypass, when 1 refclk drives clock outputs directly Bit 6 - PLL Feedback select, when 1 external feedback is selected otherwise internal feedback is selected.
WO 2005/120835 PCT/AU2004/000706 614 0x38 OscRDamp 3 Ox0 Oscillator Damping Resister value. New values written to this register will only get updated to the OSC after a PLLUpdate cycle. 0 - Short 1 - 50 Ohms 2 - 100 Ohms 3 - 150 Ohms 4 - 200 Ohms 5 - 300 Ohms 6 - 400 Ohms 7 - 500 Ohms 0x3C PLLUpdate 1 Ox0 PLL update control. A write (of any value) to this register will cause the PLL to lose lock for -25us. Reading the register indicates the status of the PLL update. 0 - PLL update complete 1 - PLL update active No writes to PLLTuneBits, PLLRangeA, PLLRangeB, PLLRangeC, PLLMultiplier, PIlGenCtrl, OscRDamp or PLLUpdate are allowed while the PLL update is active. a. Reset value depends on reset source. External reset shown. 18.8.3 CPR Sub-block partition 18.8.4 USB Wakeup Detect 5 The USB wakeup block is responsible for detecting a wakeup condition from any of the USB host ports (uhu wakeup) or a wakeup condition from the UDU (udu wakeup). The UDU indicates to the CPR that a resume has happened by setting udu suspendm signal high. The CPR deglitches the udu suspendm for 63 pclk cycles (322ns is approx 4 USB bit times at 12Mbs). After the deglitch time the CPR indicates the wakeup to the reset and sleep logic block (via udu wakeup) and signals 10 the USB PHY to resume via the cprphysuspendm signal. For the UHU wakeup the logic monitors the phyline state signals to determine that a device has connected to one of the host ports. The CPR only monitors the phyline state when the UHU is powered down. When a device connects it pulls one of the phyline state pins high. The CPR monitors all of the line state signals for a high condition of longer than 63 pclk cycles. When detected it signals to the reset and sleep logic that a 15 UHU wakeup condition has occurred. // one loop per input linestate for (i=O;i<6;i++) { if (line-state[i] == 1 AND uhupdown == 0 ) then if (count[i) == 0) then 20 wakeupli] = 1; else count[i] = count[i] - 1 else count[i] = 63 25 // combine all possible wakeup signals together uhuwakeup = OR(wakeup[5:0]) WO 2005/120835 PCT/AU2004/000706 615 18.8.5 Sleep and Reset Logic Reset generator logic The reset generator logic is used to determine which clock domains should be reset, based on configured reset values (reset section n), the deglitched external reset (resetdgn), watchdog timer reset (timcprreset n), 5 the reset sources from the wakeup logic (sleeptrigreset). The external reset could be due to a brownout detect, or a power on reset or from the reset-n pin, and is deglitched and synchronised before passing to the reset logic block. The reset output pins (resetout n and phi rst-n[1:0]) are generated by the reset macro logic. All resets are lengthened to at least 16 pclk cycles (the UHU domain resetdom[5] is lengthened to 64 pclk 10 cycles and the USB PHY reset resetdom[6] is lengthened to 1Ous), regardless of the duration of the input reset. If the clock for a particular section is not running and the CPU resets a section, the CPR will automatically re-enable the clock for the duration of the reset. The external reset sources reset everything including the CPR PLL and the CPR block. The watchdog timer reset resets everything excepts the CPR and CPR PLL. The reset sources triggered by a wakeup from sleep, 15 will cause a reset in their own section only (in snooze mode no reset will occur). The logic is given by if (resetdgn == 0) then reset-dom[6:0] = Ox00 // reset everything reset_src(5:0] = Ox01 20 cpr-resetn 0 elsif (tim-cprresetn == 0) then resetdom[6:0] = Ox00 // reset everything except CPR config resetsrc[5:0] = 0x02 25 cpr_resetn = 1 // CPR config stays the same else // propagate resets from reset section register reset-dom[6:0] = 0x3F // default to no reset cfgreset_n = 1 // CPR cfg registers are not in 30 any section for (i=0;i<7;i++) { if (reset_wr_en == 1 AND reset-section(i] ==0) then reset-dom[i] = 0 if (sleep-trigreset[i] == 1) then 35 reset-dom(i] = 0 The CPU can trigger a reset condition in the CPR for a particular section by writing a 0 to the section bit in the ResetSection register. The CPU cannot terminate a reset prematurely by writing a 1 to the section bit.
WO 2005/120835 PCT/AU2004/000706 616 Sleep logic The sleep logic is used to generate gating signals for each of SoPECs clock domains. The gate enable (gate dom) is generated based on the configured sleepmodeen, wake_up_mask, the internally generated jclkenable and wakeup signals. When a section is being re-enabled again the logic checks the configuration 5 of the snoozemode sel register to determine if it should auto generate a reset for that section. If needed it triggers a section reset by pulsing sleeptrigreset signal. The logic also stores the last wakeup condition (in the ResetSrc register) that was enabled and detected by the CPR. If 2 or more wakeup conditions happen at the same time the ResetSrc register will report the highest number active wakeup event. The logic is given by 10 if (sleep_mode-wren == 1) then // CPU write update the register sleep-mode-enff = sleepmode_en // determine what needs to wakeup when a wakeup condition occurs if (gpiocprwakeup==l AND wakeupmask[O]==O) then 15 sleepmodeen_ff[3,2,1] = 0 // turn on MMI,CPU,DIU reset_src[5:0] = 0x04 if (udu.wakeup==l AND wakeupmask[21==0)then sleepmodeenff[6,4,3,1] = 0 // turn on CPU,DIU,UDU and USB PHY 20 reset-src[5:0] = 0x08 if (udu_icu_irq==l AND wakeupmask[l]==0)then sleepmodeen_ff[6,4,3,1] = 0 // turn on CPU,DIU,UDU and USB PHY resetsrc[5:0} 0x10 25 if (uhu.wakeup==l AND wakeup-mask[3]==0)then sleepmodeenff[6,5,3,1] = 0 // turn on CPU,DIU,UHU and USB PHY resetsrc[5:0] = 0x20 // in all wakeup cases trigger reset if in sleep (no reset in snooze) 30 for (i=0; i<7;i++)( if (negedgedetect (sleepmodeenf [i])==l AND snoozemodesel(i]==0) then sleep-trig-reset[i]= 1 } 35 // assign the outputs (for read back by CPU) sleepmode_stat = sleepmode_ff // map the sections to clock domains gate-dom[5:0] = sleepmodeff[5:0] AND reset_dom[5:0] 40 cpr-phypdown = sleep-modef f[6] AND reset-dom[6] // the jclk can be turned off by CDU signal and is in PEP section if (resetdom(l] == 0) then jclk-dom = 1 elsif (jclk-enable == 0) then 45 jclkjdom = sleep-modef f(1] The clock gating and sleep logic is clocked with the master_pclk clock which is not gated by this logic, but is synchronous to other pclk section andjclk domains.
WO 2005/120835 PCT/AU2004/000706 617 Once a section is in sleep mode it cannot generate a reset to restart the device. For example if section 2 is in sleep mode then the watchdog timer is effectively disabled and cannot trigger a reset. 18.8.6 Reset Macro block The reset macro block contains the reset macros and associated deglitch logic for the generation of the 5 internal and external resets. The power on reset (POR) macro monitors the core voltage and triggers a reset event if the core voltage falls below a specified threshold. The brown out detect macro monitors the voltage on the Vcomp pin and triggers a reset condition when the voltage on the pin drops below a specified threshold. Both macros can be disabled by setting the por bo disable pin high. The external reset pin (reset-n) and the output of the brownout macro 10 (bo-n) are synchronized to the bufrefclk clock domain before being applied to the reset control logic to help prevent metastability issues. The POR circuit is treated differently. It is possible that the por-n signal could go active before the internal oscillator (and consequently bufrefclk) has time to startup. The CPR stores the reset condition by asynchronously clearing synchronizer #1. When bufrefclk does start the synchronizer will be flushed inactive. 15 The output of the synchronizer (#1) is passed through another synchronizer (#2) to prevent the possibility of an asynchronous clear affecting the reset control logic. The resetoutn pin is a general purpose reset that can be used to reset other external devices. The phirst_n pins are external reset pins used to reset the printhead. The phi-rstn and resetout n pins are active whenever an internal SoPEC reset is active (reset int_n). The pins can also be controlled by the CPU programming the 20 ResetPin register. The porasync active-n is used to gate the external reset pins to ensure that external devices are reset even if the internal oscillator in SoPEC is not active. The reset control logic implements a 100us deglitch circuit on the bosyncn and resetsync n inputs signals. It also ensures the reset output (resetint n) is stretched to at least 100us regardless of the duration of the input reset source. 25 If the state machine detects an active brown out reset condition (bosync-n=O) it transitions to the BoDeGlitch state. While in that state if the reset condition remains active for 100us the state machine transitions to the BoExtendRst state. If the reset condition is removed then the machine returns to Idle. In the BoExtendRst the output reset resetint_n will be active. The state machine will remain in the BoExtendRst state while the input reset condition remains (bosync n=0). When the reset condition is released the 30 (bosync n=1) the state machine must extend the reset to at least 100us. It remains in the BoExtendRst state until the reset condition has been inactive for 100us. When true it returns to the Idle state. The external reset deglitch and extend states operate in exactly the same way as the brownout reset. A POR reset condition (porsync n=0) will automatically cause the state machine to generate an interrupt, no deglitching is performed. When detected the state machine transitions to the ExtendRst state from any 35 other state in the state machine. The machine will remain in ExtendRst while porsyncn is active. When WO 2005/120835 PCT/AU2004/000706 618 porsyncn is deactivated the state machine remains in the ExtendRst for 100us before returning to the Idle state. 18.8.7 Clock generator Logic The clock generator block contains the PLL, crystal oscillator, clock dividers and associated control logic. 5 The PLL VCO frequency is at 1152MHz locked to a 32MHz refclk generated by the crystal oscillator. In test mode the xtalin signal can be driven directly by the test clock generator, the test clock will be reflected on the refclk signal to the PLL. 18.8.7.1 PLL control state machine The PLL will go out of lock whenever plLreset goes high (the PLL reset is the only active high reset in the 10 device) or if the configuration bits plLrangea, plirangeb, p1lrangec, pilmult, p/ltune, pll_genctri or osc_rdamp are changed. The PLL control state machine ensures that the rest of the device is protected from glitching clocks while the PLL is being reset or its configuration is being changed. In the case of a hardware reset (the reset is deglitched), the state machine first disables the output clocks (via the clkgate signal), it then holds the PLL in reset while its configuration bits are reset to default values. The 15 state machine then releases the PLL reset and waits approx 25us to allow the PLL to regain lock. Once the lock time has elapsed the state machine re-enables the output clocks and resets the remainder of the device via the resetdgn signal. When the CPU changes any of the configuration registers it must write to the PLL Update register to allow the state machine to update the PLL to the new configuration setup. If a PLL Update is detected the state machine 20 first gates the output clocks. It then holds the PLL in reset while the PLL configuration registers are updated. Once updated the PLL reset is released and the state machine waits approx 25us for the PLL to regain lock before re-enabling the output clocks. Any write to the PLLUpdate register will cause the state machine to perform the update operation regardless of whether the configuration values changed or not. All logic in the clock generator is clocked on bufrefclk which is always an active clock regardless of the state 25 of the PLL. 18.8.8 Clock gate logic The clock gate logic is used to safely gate clocks without generating any glitches on the gated clock. When the enable is high the clock is active otherwise the clock is gated. 18.9 SoPEC CLOCK SYSTEM 30 WO 2005/120835 PCT/AU2004/000706 619 19 ROM BLOCK (ROM) 19.1 OVERVIEW The ROM block interfaces to the CPU bus and contains the SoPEC boot code. The ROM block consists of the CPU bus interface, the ROM macro and the ChipID macro. The address space allocated (by the MMU) to the 5 ROM block is 192Kbytes, although the ROM size is expected to be less than 64 Kbytes. The current ROM size is 16 Kbytes implemented as a 4096x32 macro. Access to the ROM is not cached because the CPU enjoys fast, unarbitrated access to the ROM. Each SoPEC device requires a means of uniquely identifying that SoPEC i.e. a unique ChipID. IBM's 300mm ECID (electronic chip id) macro is used to implement the ChipId, providing 112 bits of laser fuses that are 10 set by blowing fuses at manufacture. IBM controls the content of the 112 bits, but incorporate wafer number, X/Y coordinate on the wafer etc. Of the 112 bits, only 80 are currently guaranteed to be programmed by IBM, with the remainder as undefined. Even so, the 112 bits will form a unique identifier for that SoPEC. In addition, each SoPEC requires a number that can be used to form a key for secure communication with an external QA Device. The number does not need to be unique, just hard for an attacker to guess. The unique 15 ChipId cannot be used to form the key, for although the exact formatting of bits within the 112-bit ID is not published by IBM, a pattern exists, and it is certainly possible to guess valid Chiplds. Therefore SoPEC incorporates a second custom ECID macro that contains an additional 112-bits. The second ECID macro is programmed at manufacture with a completely random number (using a program supplied to IBM by Silverbrook), so that even if an attacker opens a SoPEC package and determines the number for a given chip, 20 the attacker will not be able to determine corresponding numbers for other SoPECs. The way in which the number is used to form a key is a matter for application software, but the ECID macro provides 112-bits of entropy. The ECID macros allow all fuse bits to be read out in parallel, and the ROM block makes the contents of both macros (totalling 224 fuse bits) available to the CPU in the FuseChipfD[N] registers, readable in supervisor 25 mode only. 19.2 BOOT OPERATION The basic function of the SoPEC boot ROM is like any other boot ROM: to load application software and run it at power-up, reset, or upon being woken from sleep mode. On top of this basic function, the SoPEC Boot ROM has an additional security requirement in that it must only run appropriately digitally signed application 30 software. This is to prevent arbitrary software being run on a SoPEC. The security aspects of the SoPEC are discussed in the "SoPEC Security Overview" document. The boot ROM requirements and specification can be found in "SoPEC Boot ROM Design Specification".
WO 2005/120835 PCT/AU2004/000706 620 19.3 IMPLEMENTATION 19.3.1 Definitions of 1/0 Table 95. ROM Block 1/O L Part name Pins I/O Descrito Clocks and Resets prst_n 1 In Global reset. Synchronous to pc/k, active low. pclk 1 -In Global clock CPU Interface cpu-adr[14:2] 13 In CPU address bus. Only 13 bits are required to decode the address space for this block. rom--cpu-data[31 32 Out Read data bus to the CPU :0] cpu-rwn 1 In Common read/not-write signal from the CPU cpu-acode[1:0] 2 In CPU Access Code signals. These decode as follows: 00 - User program access 01 - User data access 10 - Supervisor program access 11 - Supervisor data access cpu-rom-sel 1 In Block select from the CPU. When cpu~rom-sel is high cpu.Ladr is valid rom-cpu-rdy 1 Out Ready signal to the CPU. When rom -cpu~rdy is high it indicates the last cycle of the access. For a read cycle this means the data on rom-cpuk-data is valid. rom-cpu-berr 1 Out ROM bus error signal to the CPU indicating an invalid access. 19.3.1 19.3.2 Configuration registers 5The ROM block only allows read accesses to the FuseChipfID registers and the ROM with supervisor data or program space permissions. Write accesses with the correct permissions has no effect. Any access to the ROM with user mode permissions results in a bus error. The CPU subsystem bus slave interface is described in more detail in section 9.4.3. Table 96. ROM Block Register Map M I~. 011 M *44. 44.I ....... ... 0x00000- ROM[4095:0] 4096x N/A ROM code. Ox03FFC 321 WO 2005/120835 PCT/AU2004/000706 621 Ox2FFEO FuseChipiDO 32 n/a Value of corresponding fuse bits 31 to 0 of the IBM 112-bit ECID macro. (Read only) Ox2FFE4 FuseChipID1 32 n/a Value of corresponding fuse bits 63 to 32 of the IBM 112-bit ECID macro. (Read only) Ox2FFE8 FuseChiplD2 32 n/a Value of corresponding fuse bits 95 to 64 of the IBM 112-bit ECID macro. (Read only) Ox2FFEC FuseChiplD3 16 n/a Value of corresponding fuse bits 111 to 96 of the IBM 112-bit ECID macro. (Read only) Ox2FFFO FuseChiplD4 32 n/a Value of corresponding fuse bits 31 to 0 of the Custom 112-bit ECID macro. (Read only) Ox2FFF4 FuseChipID5 32 n/a Value of corresponding fuse bits 63 to 32 of the Custom 112-bit ECID macro. (Read only) Ox2FFF8 FuseChiplD6 32 n/a Value of corresponding fuse bits 95 to 64 of the Custom 112-bit ECID macro. (Read only) Ox2FFFC FuseChiplD7 16 n/a Value of corresponding fuse bits 111 to 96 of the Custom 112-bit ECID macro. (Read only) Note bits 111-96 of the IBM ECID macro (FuseChiplD3) are not guaranteed to get programmed in all instances of SoPEC, and as a result could produce inconsistent values when read. 19.4 SUB-BLOCK PARTITION 5 IBM offer two variants of their ROM macros; A high performance version (ROMHD) and a low power version (ROMLD). It is likely that the low power version will be used unless some implementation issue requires the high performance version. Both versions offer the same bit density. The sub-block partition diagram below does not include the clocking and test signals for the ROM or ECID macros. The CPU subsystem bus interface is described in more detail in section 11.4.3. 10 19.4.1 Table 97. ROM Block internal signals SPort nael Width DscriptionY Clocks and Resets prstn 1 Global reset. Synchronous to pclk, active low. Pcik 1 Global clock Internal Signals rom-adr[1 1:0] 12 ROM address bus rom-sel 1 Select signal to the ROM macro instructing it to access the location at rom_adr romoe 1 Output enable signal to the ROM block rom_data[31:0] 32 Data bus from the ROM macro to the CPU bus interface WO 2005/120835 PCT/AU2004/000706 622 romdvalid 1 Signal from the ROM macro indicating that the data on rom data is valid for the address on rom_adr fusedata[31:0] 32 Data from the FuseChipD[N] register addressed by fuse-reg adr fusereg-adr[2:O] 3 Indicates which of the FuseChiplD registers is being addressed 19.4.1 Sub-block signal definition WO 2005/120835 PCT/AU2004/000706 623 20 POWER SAFE STORAGE (PSS) 20.1 OVERVIEW The PSS block provides 128 bytes of storage space that will maintain its state when the rest of the SoPEC device is in sleep mode. The PSS is expected to be used primarily for the storage of signature digests 5 associated with downloaded programmed code but it can also be used to store any information that needs to survive sleep mode (e.g. configuration details). Note that the signature digest only needs to be stored in the PSS before entering sleep mode and the PSS can be used for temporary storage of any data at all other times. Prior to entering sleep mode the CPU should store all of the information it will need on exiting sleep mode in the PSS. On emerging from sleep mode the boot code in ROM will read the ResetSrc register in the CPR 10 block to determine which reset source caused the wakeup. The reset and wakeup source information indicates whether or not the PSS contains valid stored data. If for any reason a full power-on boot sequence should be performed (e.g. the printer driver has been updated) then this is simply achieved by initiating a full software reset. Note that a reset or a powerdown (powerdown is implemented by clock gating) of the PSS block will not clear 15 the contents of the 128 bytes of storage. If clearing of the PSS storage is required, then the CPU must write to each location individually. 20.2 IMPLEMENTATION The storage area of the PSS block is implemented as a 128-byte register array. The array is located from PSS_ base through to PSSbase+Ox7F in the address map. The PSS block only allows read or write accesses 20 with supervisor data space permissions (i.e. cpuacode[1:O] = 11). All other accesses result in psscpuberr being asserted. The CPU subsystem bus slave interface is described in more detail in section 11.4.3. 20.2.1 Definitions of I/O Table 98. PSS Block 1/O Clocks and Resets prst_n 1 In Global reset. Synchronous to pclk, active low. pclk 1 In Global clock CPU Interface cpu-adr[6:2] 5 In CPU address bus. Only 5 bits are required to decode the address space for this block. cpu-dataout[31:0 32 In Shared write data bus from the CPU I pss.cpu.data[31: 32 Out Read data bus to the CPU 0] 1 WO 2005/120835 PCT/AU2004/000706 624 cpurwn 1 In Common read/not-write signal from the CPU cpuacode[1:0] 2 In CPU Access Code signals. These decode as follows: 00 - User program access 01 - User data access 10 - Supervisor program access 11 - Supervisor data access cpu-pss-sel 1 In Block select from the CPU. When cpupsssel is high both cpuadr and cpLdataout are valid pss-cpu-rdy 1 Out Ready signal to the CPU. When psscpurdy is high it indicates the last cycle of the access. For a read cycle this means the data on psscpudata is valid. pss-cpu-berr 1 Out PSS bus error signal to the CPU indicating an invalid access. 20.2.1 21 LOW SPEED SERIAL INTERFACE (LSS) 21.1 OVERVIEW 5 The Low Speed Serial Interface (LSS) provides a mechanism for the internal SoPEC CPU to communicate with external QA chips via two independent LSS buses. The LSS communicates through the GPIO block to the QA chips. This allows the QA chip pins to be reused in multi-SoPEC environments. The LSS Master system-level interface is illustrated in Figure 88. Note that multiple QA chips are allowed on each LSS bus. 21.2 QA COMMUNICATION 10 The SoPEC data interface to the QA Chips is a low speed, 2 pin, synchronous serial bus. Data is transferred to the QA chips via the Issdata pin synchronously with the lsselk pin. When the Iss_clk is high the data on issdata is deemed to be valid. Only the LSS master in SoPEC can drive the iss clk pin, this pin is an input only to the QA chips. The LSS block must be able to interface with an open-collector pull-up bus. This means that when the LSS block should transmit a logical zero it will drive 0 on the bus, but when it should transmit a 15 logical 1 it will leave high-impedance on the bus (i.e. it doesn't drive the bus). If all the agents on the LSS bus adhere to this protocol then there will be no issues with bus contention. The LSS block controls all communication to and from the QA chips. The LSS block is the bus master in all cases. The LSS block interprets a command register set by the SoPEC CPU, initiates transactions to the QA chip in question and optionally accepts return data. Any return information is presented through the 20 configuration registers to the SoPEC CPU. The LSS block indicates to the CPU the completion of a command or the occurrence of an error via an interrupt. The LSS protocol can be used to communicate with other LSS slave devices (other than QA chips). However should a LSS slave device hold the clock low (for whatever reason), it will be in violation of the LSS protocol and is not supported. The LSS clock is only ever driven by the LSS master.
WO 2005/120835 PCT/AU2004/000706 625 21.2.1 Start and stop conditions All transmissions on the LSS bus are initiated by the LSS master issuing a START condition and terminated by the LSS master issuing a STOP condition. START and STOP conditions are always generated by the LSS master. As illustrated in Figure 89, a START condition corresponds to a high to low transition on issdata 5 while lss clk is high. A STOP condition corresponds to a low to high transition on Issdata while Iss clk is high. 21.2.2 Data transfer Data is transferred on the LSS bus via a byte orientated protocol. Bytes are transmitted serially. Each byte is sent most significant bit (MSB) first through to least significant bit (LSB) last. One clock pulse is generated 10 for each data bit transferred. Each byte must be followed by an acknowledge bit. The data on the lssdata must be stable during the HIGH period of the lss_clk clock. Data may only change when lss_clk is low. A transmitter outputs data after the falling edge of Iss clk and a receiver inputs the data at the rising edge of Issclk. This data is only considered as a valid data bit at the next Iss_clk falling edge provided a START or STOP is not detected in the period before the next lss_clk falling edge. All clock pulses 15 are generated by the LSS block. The transmitter releases the Issdata line (high) during the acknowledge clock pulse (ninth clock pulse). The receiver must pull down the lssdata line during the acknowledge clock pulse so that it remains stable low during the HIGH period of this clock pulse. Data transfers follow the format shown in Figure 90. The first byte sent by the LSS master after a START condition is a primary id byte, where bits 7-2 form a 6-bit primary id (0 is a global id and will address all QA 20 Chips on a particular LSS bus), bit 1 is an even parity bit for the primary id, and bit 0 forms the read/write sense. Bit 0 is high if the following command is a read to the primary id given or low for a write command to that id. An acknowledge is generated by the QA chip(s) corresponding to the given id (if such a chip exists) by driving the Issdata line low synchronous with the LSS master generated ninth iss_clk. 21.2.3 Write procedure 25 The protocol for a write access to a QA Chip over the LSS bus is illustrated in Figure 92 below. The LSS master in SoPEC initiates the transaction by generating a START condition on the LSS bus. It then transmits the primary id byte with a 0 in bit 0 to indicate that the following command is a write to the primary id. An acknowledge is generated by the QA chip corresponding to the given primary id. The LSS master will clock out M data bytes with the slave QA Chip acknowledging each successful byte written. Once the slave QA 30 chip has acknowledged the M*" data byte the LSS master issues a STOP condition to complete the transfer. The QA chip gathers the M data bytes together and interprets them as a command. See QA Chip Interface Specification for more details on the format of the commands used to communicate with the QA chip. Note that the QA chip is free to not acknowledge any byte transmitted. The LSS master should respond by issuing an interrupt to the CPU to indicate this error. The CPU should then generate a STOP condition on the LSS bus 35 to gracefully complete the transaction on the LSS bus.
WO 2005/120835 PCT/AU2004/000706 626 21.2.4 Read procedure The LSS master in SoPEC initiates the transaction by generating a START condition on the LSS bus. It then transmits the primary id byte with a 1 in bit 0 to indicate that the following command is a read to the primary id. An acknowledge is generated by the QA chip corresponding to the given primary id. The LSS master 5 releases the lssdata bus and proceeds to clock the expected number of bytes from the QA chip with the LSS master acknowledging each successful byte read. The last expected byte is not acknowledged by the LSS master. It then completes the transaction by generating a STOP condition on the LSS bus. See QA Chip Interface Specification for more details on the format of the commands used to communicate with the QA chip. 10 21.3 IMPLEMENTATION A block diagram of the LSS master is given in Figure 93. It consists of a block of configuration registers that are programmed by the CPU and two identical LSS master units that generate the signalling protocols on the two LSS buses as well as interrupts to the CPU. The CPU initiates and terminates transactions on the LSS buses by writing an appropriate command to the command register, writes bytes to be transmitted to a buffer 15 and reads bytes received from a buffer, and checks the sources of interrupts by reading status registers. 21.3.1 Definitions of 10 Table 99. LSS 10 pins definitions Clocks and Resets pclk 1 In System Clock prst-n 1 In System reset, synchronous active low CPU Interface cpu-rwn 1 In Common read/not-write signal from the CPU cpuadr[6:2] 5 In CPU address bus. Only 5 bits are required to decode the address space for this block cpu-dataout[31:0] 32 In Shared write data bus from the CPU cpu-acode[1:0] 2 In CPU access code signals. cpu-acode[0] - Program (0) / Data (1) access cpu-acode[1] - User (0) / Supervisor (1) access cpu-Isssel 1 In Block select from the CPU. When cpujLssLsel is high both cpu.adr and cpuL dataout are valid lss-cpu-rdy 1 Out Ready signal to the CPU. When Iss cpu.rdy is high it indicates the last cycle of the access. For a write cycle this means cpLLdataout has been registered by the LSS block and for a read cycle this means the data on __Isscpu.data is valid.
WO 2005/120835 PCT/AU2004/000706 627 Iss-cpu-berr 1 Out LSS bus error signal to the CPU. Iss-cpu-data[31:0] 32 Out Read data bus to the CPU Issscpudebugvalid 1 Out Active high. Indicates the presence of valid debug data on /ss-cpu data. GPIO for LSS buses Issgpio-dout[1:0] 2 Out LSS bus data output Bit 0 - LSS bus O Bit 1 - LSS bus 1 gpioIss-din[1:0] 2 In LSS bus data input Bit 0 - LSS bus 0 Bit 1 - LSS bus 1 Iss.gpioe[1:0] 2 Out LSS bus data output enable, active high Bit 0 - LSS bus 0 Bit 1 - LSS bus 1 lssgpio-clk[1:0] 2 Out LSS bus clock output Bit 0 - LSS bus 0 Bit 1 - LSS bus 1 ICU interface Issjicu-irq[1:0] 2 Out LSS interrupt requests Bit 0 - interrupt associated with LSS bus 0 Bit 1 - interrupt associated with LSS bus 1 21.3.1 WO 2005/120835 PCT/AU2004/000706 628 21.3.2 Configuration registers The configuration registers in the LSS block are programmed via the CPU interface. Refer to section 11.4 on page 76 for the description of the protocol and timing diagrams for reading and writing registers in the LSS block. Note that since addresses in SoPEC are byte aligned and the CPU only supports 32-bit register reads 5 and writes, the lower 2 bits of the CPU address bus are not required to decode the address space for the LSS block. Table 100 lists the configuration registers in the LSS block. When reading a register that is less than 32 bits wide zeros are returned on the upper unused bit(s) of lss cpudata. The input cpuacode signal indicates whether the current CPU access is supervisor, user, program or data. The configuration registers in the LSS block can only be read or written by a supervisor data access, i.e. when 10 cpuacode equals b 1. If the current access is a supervisor data access then the LSS responds by asserting lss cpurdy for a single clock cycle. If the current access is anything other than a supervisor data access, then the LSS generates a bus error by asserting lss cpuberr for a single clock cycle instead of lss cpu rdy as shown in section 11.4 on page 76. A write access will be ignored, and a read access will return zero. Table 100. LSS Control Registers (LSS-bseRegister #bits Resettn a 'g Aa - NO. 4 Control registers Ox00 Reset 1 Ox1 A write to this register causes a reset of the LSS. Ox04 LssClockHighLow 16 Ox00C Lssclk has a 50:50 duty cycle, this register Duration 8 defines the period of iss_clk by means of specifying the duration (in pclk cycles) that Issclk is low (or high). The reset value specifies transmission over the LSS bus at a nominal rate of 480kHz, corresponding to a low (or high) duration of 200 pclk (192Mhz) cycles. Register should not be set to values less than 8. Ox08 LssClocktoDataH 6 Ox3 Specifies the number of pclk cycles that Data old must remain valid for after the falling edge of Iss clk. Minimum value is 3 cycles, and must to programmed to be less than LssClockHighLowDuration. LSS bus 0 registers WO 2005/120835 PCT/AU2004/000706 629 Ox10 Lss0lntStatus 3 Ox0 LSS bus 0 interrupt status registers Bit 0 - command completed successfully Bit 1 - error during processing of command, not -acknowledge received after transmission of primary id byte on LSS bus 0 Bit 2 - error during processing of command, not -acknowledge received after transmission of data byte on LSS bus 0 All the bits in LssOlntStatus are cleared when the LssOCmd register gets written to. (Read only register) 0x14 LssOCurrentState 4 Ox0 Gives the current state of the LSS bus 0 state machine. (Read only register). (Encoding will be specified upon state machine implementation) 0x18 LssOCmd 21 0x00 Command register defining sequence of events 0000 to perform on LSS bus 0 before interrupting CPU. A write to this register causes all the bits in the LssOlntStatus register to be cleared as well as generating a IssOnew cmd pulse. Ox1C - Ox2C Lss0Buffer[4:0] 5x32 OxOOO LSS Data buffer. Should be filled with transmit 0000 data before transmit command, or read data bytes received after a valid read command. LSS bus 1 registers 0x30 Lssl ntStatus 3 Ox0 LSS bus 1 interrupt status registers Bit 0 - command completed successfully Bit 1 - error during processing of command, not -acknowledge received after transmission of primary id byte on LSS bus 1 Bit 2 - error during processing of command, not -acknowledge received after transmission of data byte on LSS bus 1 All the bits in LssllntStatus are cleared when the Lss1Cmd register gets written to. (Read only register) 0x34 LsslCurrentState 4 Ox0 Gives the current state of the LSS bus 1 state machine. (Read only register) (Encoding will be specified upon state machine implementation) 0x38 LsslCmd 21 Ox00_ Command register defining sequence of events 0000 to perform on LSS bus 1 before interrupting CPU. A write to this register causes all the bits in the LssllntStatus register to be cleared as well as generating a Iss1_newcmd pulse. Ox3C - Ox4C Lssl Buffer[4:0] 5x32 Ox0000 LSS Data buffer. Should be filled with transmit 0000 data before transmit command, or read data bytes received after a valid read command. Debug registers WO 2005/120835 PCT/AU2004/000706 630 0x50 LssDebugSel[6:2] 5 Ox00 Selects register for debug output. This value is used as the input to the register decode logic instead of cpu..adr[6:2] when the LSS block is not being accessed by the CPU, i.e. when cpu_Iss_sel is 0. The output /ss-cpLLdebug valid is asserted to indicate that the data on IsscpuLdata is valid debug data. This data can be mutliplexed onto chip pins during debug mode. 21.3.2.1LSS command registers The LSS command registers define a sequence of events to perform on the respective LSS bus before issuing an interrupt to the CPU. There is a separate command register and interrupt for each LSS bus. The format of 5 the command is given in Table 101. The CPU writes to the command register to initiate a sequence of events on an LSS bus. Once the sequence of events has completed or an error has occurred, an interrupt is sent back to the CPU. Some example commands are: e a single START condition (Start = 1, IdByteEnable = 0, RdWrEnable = 0, Stop = 0) 10 e a single STOP condition (Start = 0, IdByteEnable = 0, RdWrEnable = 0, Stop = 1) * a START condition followed by transmission of the id byte (Start = 1, IdByteEnable = 1, RdWrEnable = 0, Stop = 0, IdByte contains primary id byte) e a write transfer of 20 bytes from the data buffer (Start = 0, IdByteEnable = 0, RdWrEnable = 1, RdWrSense = 0, Stop = 0, TxRxByteCount = 20) 15 e a read transfer of 8 bytes into the data buffer (Start = 0, IdByteEnable = 0, RdWrEnable = 1, RdWrSense = 1, ReadNack = 0, Stop = 0, TxRxByteCount = 8) e a complete read transaction of 16 bytes (Start = 1, IdByteEnable = 1, RdWrEnable = 1, RdWrSense = 1, ReadNack = 1, Stop = 1, IdByte contains primary id byte, TxRxByteCount = 16), etc. The CPU can thus program the number of bytes to be transmitted or received (up to a maximum of 20) on the 20 LSS bus before it gets interrupted. This allows it to insert arbitrary delays in a transfer at a byte boundary. For example the CPU may want to transmit 30 bytes to a QA chip but insert a delay between the 20th and 21" bytes sent. It does this by first writing 20 bytes to the data buffer. It then writes a command to generate a START condition, send the primary id byte and then transmit the 20 bytes from the data buffer. When interrupted by the LSS block to indicate successful completion of the command the CPU can then write the 25 remaining 10 bytes to the data buffer. It can then wait for a defined period of time before writing a command to transmit the 10 bytes from the data buffer and generate a STOP condition to terminate the transaction over the LSS bus. An interrupt to the CPU is generated for one cycle when any bit in LssNIntStatus is set. The CPU can read LssNIntStatus to discover the source of the interrupt. The LssNlntStatus registers are cleared when the CPU 30 writes to the LssNCmd register. A null command write to the LssNCmd register will cause the LssNIntStatus WO 2005/120835 PCT/AU2004/000706 631 registers to clear and no new command to start. A null command is defined as Start, IdbyteEnable, RdWrEnable and Stop all set to zero. Table 101. LSS command register description 0 Start When 1, issue a START condition on the LSS bus. 1 IdByteEnable ID byte transmit enable: 1 - transmit byte in IdByte field 0 - ignore byte in IdByte field 2 RdWrEnable Read/write transfer enable: 0 - ignore settings of RdWrSense, ReadNack and TxRxByteCount 1 - if RdWrSense is 0, then perform a write transfer of TxRxByteCount bytes from the data buffer. if RdWrSense is 1, then perform a read transfer of TxRxByteCount bytes into the data buffer. Each byte should be acknowledged and the last byte received is acknowledged/not-acknowledged according to the setting of ReadNack. 3 RdWrSense Read/write sense indicator: 0 - write 1 - read 4 ReadNack Indicates, for a read transfer, whether to issue an acknowledge or a not acknowledge after the last byte received (indicated by TxRxByteCouno. 0 - issue acknowledge after last byte received 1 - issue not-acknowledge after last byte received. 5 Stop When 1, issue a STOP condition on the LSS bus. 7:6 reserved Must be 0 15:8 IdByte Byte to be transmitted if IdByteEnable is 1. Bit 8 corresponds to the LSB. 20:16 TxRxByteCount Number of bytes to be transmitted from the data buffer or the number of bytes to be received into the data buffer. The maximum value that should be programmed is 20, as the size of the data buffer is 20 bytes. Valid values are 1 to 20, 0 is valid when RdWrEnable = 0, other cases are invalid and undefined. The data buffer is implemented in the LSS master block. When the CPU writes to the LssNBuffer registers the 5 data written is presented to the LSS master block via the lssNbuffer wrdata bus and configuration registers block pulses the IssN bufferwen bit corresponding to the register written. For example if LssNBuffer[2] is written to lssN_buffer wen[2] will be pulsed. When the CPU reads the LssNBuffer registers the configuration registers block reflect the lssN buffer rdata bus back to the CPU. 21.3.3 LSS master unit 10 The LSS master unit is instantiated for both LSS bus 0 and LSS bus 1. It controls transactions on the LSS bus by means of the state machine shown in Figure 96, which interprets the commands that are written by the CPU. It also contains a single 20 byte data buffer used for transmitting and receiving data.
WO 2005/120835 PCT/AU2004/000706 632 The CPU can write data to be transmitted on the LSS bus by writing to the LssNBuffer registers. It can also read data that the LSS master unit receives on the LSS bus by reading the same registers. The LSS master always transmits or receives bytes to or from the data buffer in the same order. For a transmit command, LssNBuffer[0][7:0] gets transmitted first, then LssNBufer[0][15:8], 5 LssNBufer[][23:16], LssNBuffer[0][31:24], LssNBuffer[I][7:0] and so on until TxRxByteCount number of bytes are transmitted. A receive command fills data to the buffer in the same order. For each new command the buffer start point is reset. All state machine outputs, flags and counters are cleared on reset. After a reset the state machine goes to the Reset state and initializes the LSS pins (iss_clk is set to 1, Issdata is tristated and allowed to be pulled up to 10 1). When the reset condition is removed the state machine transitions to the Wait state. It remains in the Wait state until lssnewcmd equals 1. If the Start bit of the command is 0 the state machine proceeds directly to the CheckIdByteEnable state. If the Start bit is 1 it proceeds to the GenerateStart state and issues a START condition on the LSS bus. In the CheckldByteEnable state, if the IdByteEnable bit of the command is 0 the state machine proceeds 15 directly to the CheckRdWrEnable state. If the IdByteEnable bit is 1 the state machine enters the SendIdByte state and the byte in the IdByte field of the command is transmitted on the LSS. The WaitFordAck state is then entered. If the byte is acknowledged, the state machine proceeds to the CheckRdWrEnable state. If the byte is not-acknowledged, the state machine proceeds to the GenerateInterrupt state and issues an interrupt to indicate a not-acknowledge was received after transmission of the primary id byte. 20 In the CheckRdWrEnable state, if the RdWrEnable bit of the command is 0 the state machine proceeds directly to the CheckStop state. If the RdWrEnable bit is 1, count is loaded with the value of the TxRxByteCount field of the command and the state machine enters either the ReceiveByte state if the RdWrSense bit of the command is 1 or the TransmitByte state if the RdWrSense bit is 0. For a write transaction, the state machine keeps transmitting bytes from the data buffer, decrementing count 25 after each byte transmitted, until count is 1. If all the bytes are successfully transmitted the state machine proceeds to the CheckStop state. If the slave QA chip not-acknowledges a transmitted byte, the state machine indicates this error by issuing an interrupt to the CPU and then entering the GenerateInterrupt state. For a read transaction, the state machine keeps receiving bytes into the data buffer, decrementing count after each byte transmitted, until count is 1. After each byte received the LSS master must issue an acknowledge. 30 After the last expected byte (i.e. when count is 1) the state machine checks the ReadNack bit of the command to see whether it must issue an acknowledge or not-acknowledge for that byte. The CheckStop state is then entered. In the CheckStop state, if the Stop bit of the command is 0 the state machine proceeds directly to the GenerateInterrupt state. If the Stop bit is 1 it proceeds to the GenerateStop state and issues a STOP condition 35 on the LSS bus before proceeding to the GenerateInterrupt state. In both cases an interrupt is issued to indicate successful completion of the command.
WO 2005/120835 PCT/AU2004/000706 633 The state machine then enters the Wait state to await the next command. When the state machine reenters the Wait state the output pins (Issdata and iss clk) are not changed, they retain the state of the last command. This allows the possibility of multi-command transactions. The CPU may abort the current transfer at any time by performing a write to the Reset register of the LSS 5 block. 21.3.3.1 START and STOP generation START and STOP conditions, which signal the beginning and end of data transmission, occur when the LSS master generates a falling and rising edge respectively on the data while the clock is high. In the GenerateStart state, /ssgpio clk is held high with lss_gpio_e remaining deasserted (so the data line is 10 pulled high externally) for LssClockHighLowDuration pclk cycles. Then /ssgpio e is asserted and lssgpiodout is pulled low (to drive a 0 on the data line, creating a falling edge) with /ssgpio_c/k remaining high for another LssClockHighLowDuration pclk cycles. In the GenerateStop state, both lssgpio clk and Issgpio dout are pulled low followed by the assertion of lssgpio e to drive a 0 while the clock is low. After LssClockHighLowDuration pclk cycles, /ssgpio c/k is 15 set high. After a further LssClockHighLowDuration pclk cycles, lssgpioe is deasserted to release the data bus and create a rising edge on the data bus during the high period of the clock. If the bus is not in the required state for start and stop generation (iss_clk=1, Iss_data=1 for start, and Iss_clk=1, Issdata=0), the state machine moves the bus to the correct state and proceeds as described above. Figure 95 shows the transition timing from any bus state to start and stop generation 20 21.3.3.2 Clock pulse generation The LSS master holds /ssgpio clk high while the LSS bus is inactive. A clock pulse is generated for each bit transmitted or received over the LSS bus. It is generated by first holding /ssgpio clk low for LssClockHighLowDuration pclk cycles, and then high for LssClockHighLowDuration pclk cycles. 21.3.3.3 Data De-glitching 25 When data is received in the LSS block it is passed to a de-glitching circuit. The de-glitch circuit samples the data 3 times on pelk and compares the samples. If all 3 samples are the same then the data is passed, otherwise the data is ignored. Note that the LSS data input on SoPEC is double registered in the GPIO block before being passed to the LSS. 30 21.3.3.4 Data reception The input data, gpioIssdi, is first synchronised to the pclk domain by means of two flip-flops clocked by pclk (the double register resides in the GPIO block). The LSS master generates a clock pulse for each bit received. The output lss_gpioe is deasserted LssClockToDataHold pclk cycles after the falling edge of WO 2005/120835 PCT/AU2004/000706 634 lssgpio_clk to release the data bus. The value on the synchronised gpio lss di is sampled Tstrobe number of clock cycles after the rising edge of lssgpio_cik (the data is de-glitched over a further 3 stage register to avoid possible glitch detection). See Figure 97 for further timing information. In the ReceiveByte state, the state machine generates 8 clock pulses. At each Tstrobe time after the rising edge 5 of lss_gpio_clk the synchronised gpio lss-di is sampled. The first bit sampled is LssNBuffer[0][7], the second LssNBuffer[0][6], etc to LssNBuffer[0][0]. For each byte received the state machine either sends an NAK or an ACK depending on the command configuration and the number of bytes received. In the SendNack state the state machine generates a single clock pulse. lssgpioe is deasserted and the LSS data line is pulled high externally to issue a not-acknowledge. 10 In the SendAck state the state machine generates a single clock pulse. lssgpio_e is asserted and a 0 driven on Issspiodout after lssgpio_cik falling edge to issue an acknowledge. 21.3.3.5 Data transmission The LSS master generates a clock pulse for each bit transmitted. Data is output on the LSS bus on the falling edge of Issgpio_clk. 15 When the LSS master drives a logical zero on the bus it will assert lssgpio e and drive a 0 on lssgpio_dout after lssgpio_cik falling edge. lssgpio e will remain asserted and lssgpiodout will remain low until the next iss clk falling edge. When the LSS master drives a logical one lssgpio e should be deasserted at lssgpio clk falling edge and remain deasserted at least until the next lssgpio_clk falling edge. This is because the LSS bus will be 20 externally pulled up to logical one via a pull-up resistor. In the SendId byte state, the state machine generates 8 clock pulses to transmit the byte in the IdByte field of the current valid command. On each falling edge of lssgpio clk a bit is driven on the data bus as outlined above. On the first falling edge IdByte[7] is driven on the data bus, on the second falling edge IdByte[6] is driven out, etc. 25 In the TransmitByte state, the state machine generates 8 clock pulses to transmit the byte at the output of the transmit FIFO. On each falling edge of Issgpio clk a bit is driven on the data bus as outlined above. On the first falling edge LssNBuffer[0][7] is driven on the data bus, on the second falling edge LssNBuffer[0][6] is driven out, etc on to LssNBuffer[0][7] bits. In the WaitForAck state, the state machine generates a single clock pulse. At Tstrobe time after the rising edge 30 of Issgpio_clk the synchronized gpio issdi is sampled. A 0 indicates an acknowledge and ackdetect is pulsed, a 1 indicates a not-acknowledge and nackdetect is pulsed. 21.3.3.6 Data rate control The CPU can control the data rate by setting the clock period of the LSS bus clock by programming appropriate value in LssClockHighLowDuration. The default setting for the register is 200 (pclk cycles) which 35 corresponds to transmission rate of 480kHz on the LSS bus (the lss clk is high for LssClockHighLowDuration WO 2005/120835 PCT/AU2004/000706 635 cycles then low for LssClockHighLowDuration cycles). The iss_clk will always have a 50:50 duty cycle. The LssClockHighLowDuration register should not be set to values less than 8. The hold time of Issdata after the falling edge of Iss_clk is programmable by the LssClocktoDataHold register. This register should not be programmed to less than 2 or greater than the LssClockHighLowDuration 5 value. 21.3.3.7 LSS master timing parameters The LSS master timing parameters are shown in Figure 97 and the associated values are shown in Table 102. Table 102. LSS master timing parameters LSS Master Driving Tp LSS clock period divided by 2 8 200 FFFF pclk cycles Tstartdelay Time to start data edge from Tp + LssClocktoDataHold pclk rising clock edge cycles Tstop-delay Time to stop data edge from Tp + LssClocktoDataHold pclk rising clock edge cycles Tdata_setup Time from data setup to rising Tp - 2 - pclk clock edge LssClocktoDataHold cycles Tdatahold Time from falling clock edge to LssClocktoDataHold pclk data hold cycles Tack_setup Time that outgoing (N)Ack is Tp - 2 - pclk setup before Iss~clk rising edge LssClocktoDataHold cycles Tack_hold Time that outgoing (N)Ack is LssClocktoDataHold pclk held after Iss_clk falling edge cycles LSS Master Sampling Tstrobe LSS master strobe point for Tp -2 Tp -2 pclk incoming data and (N)Ack cycles values 10 WO 2005/120835 PCT/AU2004/000706 636 DRAM SUBSYSTEM 22 DRAM INTERFACE UNIT (DIU) 22.1 OVERVIEW 5 Figure 98 shows how the DIU provides the interface between the on-chip 20 Mbit embedded DRAM and the rest of SoPEC. In addition to outlining the functionality of the DIU, this chapter provides a top-level overview of the memory storage and access patterns of SoPEC and the buffering required in the various SoPEC blocks to support those access requirements. The main functionality of the DIU is to arbitrate between requests for access to the embedded DRAM and 10 provide read or write accesses to the requesters. The DIU must also implement the refresh logic for the embedded DRAM. The arbitration scheme uses a fully programmable timeslot mechanism for non-CPU requesters to meet the bandwidth and latency requirements for each unit, with unused slots re-allocated to provide best effort accesses. The CPU is allowed high priority access, giving it minimum latency, but allowing bounds to be 15 placed on its bandwidth consumption. The interface between the DIU and the SoPEC requesters is similar to the interface on PECI i.e. separate control, read data and write data busses. The embedded DRAM is used principally to store: * CPU program code and data. 20 - PEP (re)programming commands. * Compressed pages containing contone, bi-level and raw tag data and header information. * Decompressed contone and bi-level data. " Dotline store during a print. * Print setup information such as tag format structures, dither matrices and dead nozzle information. 25 22.2 IBM Cu-11 EMBEDDED DRAM 22.2.1 Single bank SoPEC will use the 1.5 V core voltage option in IBM's 0.13 l1m class Cu-11 process. The random read/write cycle time and the refresh cycle time is 3 cycles at 192 MHz. An open page access will complete in 1 cycle if the page mode select signal is clocked at 384 MHz or 2 cycles if the page mode 30 select signal is clocked every 192 MHz cycle. The page mode select signal will be clocked at 192 MHz in SoPEC in order to simplify timing closure. The DRAM word size is 256 bits.
WO 2005/120835 PCT/AU2004/000706 637 Most SoPEC requesters will make single 256 bit DRAM accesses (see Section 22.4). These accesses will take 3 cycles as they are random accesses i.e. they will most likely be to a different memory row than the previous access. The entire 20 Mbit DRAM will be implemented as a single memory bank. In Cu-11, the maximum single instance size is 16 Mbit. The first 1 Mbit tile of each instance contains an area 5 overhead so the cheapest solution in terms of area is to have only 2 instances. 16 Mbit and 4Mbit instances would together consume an area of 14.63 mm 2 as would 2 times 10 Mbit instances. 4 times 5 Mbit instances would require 17.2 mm 2 . The instance size will determine the frequency of refresh. Each refresh requires 3 clock cycles. In Cu-I1 each row consists of 8 columns of 256-bit words. This means that 10 Mbit requires 5120 rows. A complete DRAM 10 refresh is required every 3.2 ms. Two times 10 Mbit instances would require a refresh every 120 clock cycles, if the instances are refreshed in parallel. The SoPEC DRAM will be constructed as two 10 Mbit instances implemented as a single memory bank. 22.3 SoPEC MEMORY USAGE REQUIREMENTS The memory usage requirements for the embedded DRAM are shown in Table 103. Table 103. Memory Usage Requirements Compressed page store 2048 Kbytes Compressed data page store for Bi-level and contone data Decompressed Contone 108 Kbyte 13824 lines with scale factor 6 = 2304 Store pixels, store 12 lines, 4 colors = 108 kB 13824 lines with scale factor 5 = 2765 pixels, store 12 lines, 4 colors = 130 kB Spot line store 5.1 Kbyte 13824 dots/line so 3 lines is 5.1 kB Tag Format Structure Typically 12 Kbyte (2.5 mm 55 kB in for 384 dot line tags tags @ 800 dpi) 2.5 mm tags (1/10th inch) @ 1600 dpi require 160 dot lines = 160/384 x55 or 23 kB 2.5 mm tags (1/10th inch) @ 800 dpi require 80/384 x55 = 12 kB Dither Matrix store 4 Kbytes 64x64 dither matrix is 4 kB 128x128 dither matrix is 16 kB 256x256 dither matrix is 64 kB DNC Dead Nozzle Table 1.4 Kbytes Delta encoded, (10 bit delta position + 6 dead nozzle mask) x% Dnozzle 5% dead nozzles requires (10+6)x 692 Dnozzles = 1.4 Kbytes WO 2005/120835 PCT/AU2004/000706 638 Dot-line store 369.6 Kbytes Assume each color row is separated by 5 dot lines on the print head The dot line store will be 0+5+10.. .50+55 = 330 half dot lines + 48 extra half dot lines (4 per dot row) + 60 extra half dot lines estimated to account for printhead misalignment = 438 half dot lines. 438 half dot lines of 6912 dots = 369.6Kbytes PCU Program code 8 Kbytes 1024 commands of 64 bits = 8 kB CPU 64 Kbytes Program code and data TOTAL 2620 Kbytes (12 Kbyte TFS storage) Note: Total storage is fixed to 2560 Kbytes to align to 20 Mbit DRAM. This will mean that less space than noted in Table 103 may be available for the compressed band store. 22.4 SoPEC MEMORY AcCESS PATTERNS 5 Table 104 shows a summary of the blocks on SoPEC requiring access to the embedded DRAM and their individual memory access patterns. Most blocks will access the DRAM in single 256-bit accesses. All accesses must be padded to 256-bits except for 64-bit CDU write accesses and CPU write accesses. Bits which should not be written are masked using the individual DRAM bit write inputs or byte write inputs, depending on the foundry. Using single 256-bit accesses means that the buffering required in the SoPEC 10 DRAM requesters will be minimized. Table 104. Memory access patterns of SoPEC DRAM Requesters CPU R Single 256-bit reads. W Single writes of up to 128 bits in 8-bit multiples. UHU R Single 256-bit reads. W Single 256-bit writes, with byte enables. UDU R Single 256-bit reads. W Single 256-bit writes, with byte enables. MMI R Single 256-bit reads. W Single 256-bit writes. CDU R Single 256-bit reads of the compressed contone data.
WO 2005/120835 PCT/AU2004/000706 639 W Each CDU access is a write to 4 consecutive DRAM words in the same row but only 64 bits of each word are written with the remaining bits write masked. The access time for this 4 word page mode burst is 3 + 2 + 2 +2 = 9 cycles if the page mode select signal is clocked at 192 MHz. CFU R Single 256 bit reads. LBD R Single 256 bit reads. SFU R Separate single 256 bit reads for previous and current line but sharing the same DIU interface W Single 256 bit writes. TE(TD) R Single 256 bit reads. Each read returns 2 times 128 bit tags. TE(TFS) R Single 256 bit reads. TFS is 136 bytes. This means there is unused data in the fifth 256 bit read. A total of 5 reads is required. HCU R Single 256 bit reads. 128 x 128 dither matrix requires 4 reads per line with double buffering. 256 x 256 dither matrix requires 8 reads at the end of the line with single buffering. DNC R Single 256 bit dead nozzle table reads. Each dead nozzle table read contains 16 dead-nozzle tables entries each of 10 delta bits plus 6 dead nozzle mask bits. DWU W Single 256 bit writes since enable/disable DRAM access per color plane. LLU R Single 256 bit reads since enable/disable DRAM access per color plane. PCU R Single 256 bit reads. Each PCU command is 64 bits so each 256 bit word can contain 4 PCU commands. PCU reads from DRAM used for reprogramming PEP should be executed with minimum latency. If this occurs between pages then there will be free bandwidth as most of the other SoPEC Units will not be requesting from DRAM. If this occurs between bands then the LDB, CDU and TE bandwidth will be free. So the PCU should have a high priority to access to any spare bandwidth. Refresh Single refresh.
WO 2005/120835 PCT/AU2004/000706 640 22.5 BUFFERING REQUIRED IN SoPEC DRAM REQUESTERS If each DIU access is a single 256-bit access then we need to provide a 256-bit double buffer in the DRAM requester. If the DRAM requester has a 64-bit interface then this can be implemented as an 8 x 64-bit FIFO. Table 105. Buffer sizes in SoPEC DRAM requesters DRAM Direction Access patterns Buffering required in Requester block CPU R Single 256-bit reads. Cache. W Single writes of up to 128 bits in 8- Single 128-bit buffer. bit multiples. UHU R Single 256-bit reads. Double 256-bit buffer. W Single 256-bit writes, with byte Double 256-bit buffer. enables. UDU R Single 256-bit reads. Double 256-bit buffer. W Single 256-bit writes, with byte Double 256-bit buffer. enables. MMI R Single 256-bit reads. Double 256-bit buffer. W Single 256-bit writes. Double 256-bit buffer. CDU R Single 256-bit reads of the Double 256-bit buffer. compressed contone data. W Each CDU access is a write to 4 Double half JPEG block consecutive DRAM words in the buffer. same row but only 64 bits of each word are written with the remaining bits write masked. CFU R Single 256 bit reads. Triple 256-bit buffer. LBD R Single 256 bit reads. Double 256-bit buffer. SFU R Separate single 256 bit reads for Double 256-bit buffer previous and current line but for each read channel. sharing the same DIU interface W Single 256 bit writes. Double 256-bit buffer. TE(TD) R Single 256 bit reads. Double 256-bit buffer. TE(TFS) R Single 256 bit reads. TFS is 136 Double line-buffer for bytes. This means there is unused 136 bytes implemented data in the fifth 256 bit read. A total in TE. of 5 reads is required. HCU R Single 256 bit reads. 128 x 128 Configurable between dither matrix requires 4 reads per double 128 byte buffer line with double buffering. 256 x and 256 dither matrix requires 8 reads single 256 byte buffer. at the nr4 if tho ling With Cinnila WO 2005/120835 PCT/AU2004/000706 641 buffering. DNC R Single 256 bit reads Double 256-bit buffer. Deeper buffering could be specified to cope with local clusters of dead nozzles. DWU W Single 256 bit writes per enabled Double 256-bit buffer odd/even color plane. per color plane. LLU R Single 256 bit reads per enabled Quad 256-bit buffer per odd/even color plane. color plane. PCU R Single 256 bit reads. Each PCU Single 256-bit buffer. command is 64 bits so each 256 bit DRAM read can contain 4 PCU commands. Requested command is read from DRAM together with the next 3 contiguous 64-bits which are cached to avoid unnecessary DRAM reads. Refresh Single refresh. None WO 2005/120835 PCT/AU2004/000706 642 22.6 SoPEC DIU BANDWIDTH REQUIREMENTS Table 106. SoPEC DIU Bandwidth Requirements % Number of Peak cycles between Bndith 2. sExample Direction 25- M which must be Bandwidthte access in meet sple(bt/ye) timnesntse CPU R W UHU R 102 480 Mbit/s2 2.5 bits/cycle 3 W 102 480 Mbit/s 2.5 bits/cycle 3 UDU R 102 480 Mbit/s 2.5 bits/cycle 3 W 102 480 Mbit/s 2.5 bits/cycle 3 MMI R 102 480 Mbit/s3 2.5 bits/cycle 3 W 102 480 Mbit/s 2.5 bits/cycle 3 CDU R 128 (SF = 4), 288 64/n 2 (SF=n), 32/10*nL (SF=n), 2 (SF=6) (SF = 6), 1:1 1.8 (SF = 6), 0.09 (SF = 6), 4 (SF=4) compression 4 4 (SF = 4) 0.2 (SF = 4) (1:1 (10:1 compression) compression) 5 W For individual 64/n 2 (SF=n), 32/n2 (SF=n) 7 , 2 (SF=6)" accesses: 16 1.8 (SF = 6), 0.9 (SF = 6), 4 (SF=4) cycles (SF = 4), 4 (SF = 4) 2 (SF 4) 36 cycles (SF = 6), n cycles (SF=n). Will be implemented as a page mode burst of 4 accesses every 64 cycles (SF = 4), 144 (SF =6), 4*n (SF =n) cycles 6 CFU R 32 (SF = 4), 48 32/n (SF=n), 32/n (SF=n), 6 (SF=6) (SF = 6)9 5.4 (SF = 6), 5.4 (SF = 6), 8 (SF=4) 8 (SF = 4) 8 (SF = 4) LBD R 256 (1:1 1 (1:1 0.1 (10:1 1 compression)' compression) compression)" SFU R 12812 2 2 2 W 256' 1 1 1 TE(TD) R 25214 1.02 1.02 1 WO 2005/120835 PCT/AU2004/000706 643 TE(TFS) R 5 reads per line' 5 0.093 0.093 0 HCU R 4 reads per line 0.074 0.074 0 for 128 x 128 dither matrix' 6 DNC R 106 (5% dead- 2.4 (clump of 0.8 (equally spaced 3 nozzles 10-bit dead nozzles) dead nozzles) delta encoded) DWU W 6 writes every 6 6 6 256' LLU R 9 reads every 12.86 8.57 9 25619 PCU R 25620 1 1 1 Refresh 12021 2.13 2.13 3(effective) TOTAL SF=6: 34.5 SF = 6: 27.1 SF = 6: 35 SF = 4: 41.9 SF = 4: 31.2 excluding excluding CPU excluding CPU CPU, UHU, UDU, MMI, refresh SF= 4: 41 excluding CPU, UHU, UDU, MMI, refresh Notes: 1: The number of allocated timeslots is based on 64 timeslots each of 1 bit/cycle but broken down to a granularity of 0.25 bit/cycle. Bandwidth is allocated based on peak bandwidth. 2: High-speed USB requires 480 Mbit/s raw bandwidth. Full-speed USB requires 12 Mb/s raw bandwidth. 5 3: Here assume maximum required MMI bandwidth is equivalent to USB high-speed bandwidth. 4: At 1:1 compression CDU must read a 4 color pixel (32 bits) every SF 2 cycles. CDU read bandwidth must match CDU write bandwidth. 5: At 10:1 average compression CDU must read a 4 color pixel (32 bits) every 10*SF 2 cycles. 6: 4 color pixel (32 bits) is required, on average, by the CFU every SF 2 (scale factor) cycles. 10 The time available to write the data is a function of the size of the buffer in DRAM. 1.5 buffering means 4. color pixel (32 bits) must be written every SF 2 / 2 (scale factor) cycles. Therefore, at a scale factor of SF, 64 bits are required every SF 2 cycles. Since 64 valid bits are written per 256-bit write (Figure 152 on page 464) then the DRAM is accessed every SF 2 cycles i.e. at SF4 an access every 16 cycles, at SF6 an access every 36 cycles. 15 If a page mode burst of 4 accesses is used then each access takes (3 + 2 + 2 +2) equals 9 cycles. This means at SF, a set of 4 back-to-back accesses must occur every 4*SF 2 cycles. This assumes the page mode select signal is clocked at 192 MHz. CDU timeslots therefore take 9 cycles. For scale factors lower than 4 double buffering will be used. 7: The peak bandwidth is twice the average bandwidth in the case of 1.5 buffering. 20 8: Each CDU(W) burst takes 9 cycles instead of 4 cycles for other accesses so CDU timeslots are longer.
WO 2005/120835 PCT/AU2004/000706 644 9: 4 color pixel (32 bits) read by CFU every SF cycles. At SF4, 32 bits is required every 4 cycles or 256 bits every 32 cycles. At SF6, 32bits every 6 cycles or 256 bits every 48 cycles. 10: At 1:1 compression require I bit/cycle or 256 bits every 256 cycles. 11: The average bandwidth required at 10:1 compression is 0.1 bits/cycle. 5 12: Two separate reads of 1 bit/cycle. 13: Write at 1 bit/cycle. 14: Each tag can be consumed in at most 126 dot cycles and requires 128 bits. This is a maximum rate of 256 bits every 252 cycles. 15: 17 x 64 bit reads per line in PEC1 is 5 x 256 bit reads per line in SoPEC. Double-line buffered storage. 10 16: 128 bytes read per line is 4 x 256 bit reads per line. Double-line buffered storage. 17: 5% dead nozzles 10-bit delta encoded stored with 6-bit dead nozzle mask requires 0.8 bits/cycle read access or a 256 bit access every 320 cycles. This assumes the dead nozzles are evenly spaced out. In practice dead nozzles are likely to be clumped. Peak bandwidth is estimated as 3 times average bandwidth. 18: 6 bits/cycle requires 6 x 256 bit writes every 256 cycles. 15 19: The LLU requires DIU access of approx 6.43 bits/cycle. This is to keep the PHI fed at an effective rate of 225 Mb/s assuming 12 segments but taking account that only 11 segments can actually be driven. For SegSpan = 640 and SegDotOffset = 0 the LLU will use 256 bits, 256 bits, and then 128 bits of the last DRAM word. Not utilizing the last 128 bits means the average bandwidth required increases by '/3 to 8.57 bits/cycle. The LLU quad buffer will be able to keep the LLU supplied with data if the DIU supplies this average bandwidth. 20 6 bits/192 MHz SoPEC cycle average but will peak at 2 x 6 bits per 128 MHz print head cycle or 8 bits/ SoPEC cycle. The PHI can equalise the DRAM access rate over the line so that the peak rate equals the average rate of 6 bits/cycle. The print head is clocked at an effective speed of 106 MHz. 20: Assume one 256 read per 256 cycles is sufficient i.e. maximum latency of 256 cycles per access is allowable. 21: Refresh must occur every 3.2 ms. Refresh occurs row at a time over 5120 rows of 2 parallel 10 Mbit instances. 25 Refresh must occur every 120 cycles. Each refresh takes 3 cycles. 22: In a printing SoPEC USB host, USB device and MMI connections are unlikely to be simultaneously present. 22.7 DIU BUS TOPOLOGY 22.7.1 Basic topology Table 107. SoPEC DIU Requesters CPU CPU Refresh UHU UHU UDU UDU MMI MMI WO 2005/120835 PCT/AU2004/000706 645 CDU CDU CFU SFU LBD DWU SFU TE(TD) TE(TFS) HCU DNC LLU PCU Table 107 shows the DIU requesters in SoPEC. There are 12 read requesters and 5 write requesters in SoPEC as compared with 8 read requesters and 4 write requesters in PEC 1. Refresh is an additional requester. In PEC 1, the interface between the DIU and the DIU requesters had the following main features: * separate control and address signals per DIU requester multiplexed in the DIU according to the 5 arbitration scheme, e separate 64-bit write data bus for each DRAM write requester multiplexed in the DIU, * common 64-bit read bus from the DIU with separate enables to each DIU read requester. Timing closure for this bussing scheme was straight-forward in PEC1. This suggests that a similar scheme will also achieve timing closure in SoPEC. SoPEC has 5 more DRAM requesters but it will be in a 0.13 um 10 process with more metal layers and SoPEC will run at approximately the same speed as PEC 1. Using 256-bit busses would match the data width of the embedded DRAM but such large busses may result in an increase in size of the DIU and the entire SoPEC chip. The SoPEC requestors would require double 256-bit wide buffers to match the 256-bit busses. These buffers, which must be implemented in flip-flops, are less area efficient than 8-deep 64-bit wide register arrays which can be used with 64-bit busses. SoPEC will 15 therefore use 64-bit data busses. Use of 256-bit busses would however simplify the DIU implementation as local buffering of 256-bit DRAM data would not be required within the DIU. 22.7. 1.1 CPU DRAM access The CPU is the only DIU requestor for which access latency is critical. All DIU write requesters transfer write 20 data to the DIU using separate point-to-point busses. The CPU will use the cpu_diu_wdata[127:O] bus. CPU reads will not be over the shared 64-bit read bus. Instead, CPU reads will use a separate 256-bit read bus. 22.7.2 Making more efficient use of DRAM bandwidth The embedded DRAM is 256-bits wide. The 4 cycles it takes to transfer the 256-bits over the 64-bit data 25 busses of SoPEC means that effectively each access will be at least 4 cycles long. It takes only 3 cycles to actually do a 256-bit random DRAM access in the case of IBM DRAM.
WO 2005/120835 PCT/AU2004/000706 646 22.7.2.1 Common read bus If a common read data bus is used, as in PEC , then during back to back read accesses the next DRAM read cannot start until the read data bus is free. So each DRAM read access can occur only every 4 cycles. This is 5 shown in Figure 99 with the actual DRAM access taking 3 cycles leaving 1 unused cycle per access. 22.7.2.2 Interleaving CPU and non-CPU read accesses The CPU has a separate 256-bit read bus. All other read accesses are 256-bit accesses are over a shared 64-bit read bus. Interleaving CPU and non-CPU read accesses means the effective duration of an interleaved access timeslot is the DRAM access time (3 cycles) rather than 4 cycles. 10 Figure 100 shows interleaved CPU and non-CPU read accesses. 22.7.2.3 Interleaving read and write accesses Having separate write data busses means write accesses can be interleaved with each other and with read accesses. So now the effective duration of an interleaved access timeslot is the DRAM access time (3 cycles) rather than 4 cycles. Interleaving is achieved by ordering the DIU arbitration slot allocation appropriately. 15 Figure 101 shows interleaved read and write accesses. Figure 102 shows interleaved write accesses. 256-bit write data takes 4 cycles to transmit over 64-bit busses so a 256-bit buffer is required in the DIU to gather the write data from the write requester. The exception is CPU write data which is transferred in a single cycle. Figure 102 shows multiple write accesses being interleaved to obtain 3 cycle DRAM access. 20 Since two write accesses can overlap two sets of 256-bit write buffers and multiplexors to connect two write requestors simultaneously to the DIU are required. From Table 106, write requestors only require approximately one third of the total non-CPU bandwidth. This means that a rule can be introduced such that non-CPU write requestors are not allocated adjacent timeslots. This means that a single 256-bit write buffer and multiplexor to connect the one write requestor at a time to 25 the DIU is all that is required. Note that if the rule prohibiting back-to-back non-CPU writes is not adhered to, then the second write slot of any attempted such pair will be disregarded and re-allocated under the unused read round-robin scheme. 30 22.7.3 Bus widths summary Table 108. SoPEC DIU Requesters Data Bus Width CPU 256 (separate) CPU 128 UHU 64 (shared) UHU 64 UDU 64 (shared) UDU 64 WO 2005/120835 PCT/AU2004/000706 647 MMI 64 (shared) MMI 64 CDU 64 (shared) CDU 64 CFU 64 (shared) SFU 64 LBD 64 (shared) DWU 64 SFU 64 (shared) TE(TD) 64 (shared) TE(TFS) 64 (shared) HCU 64 (shared) DNC 64 (shared) LLU 64 (shared) PCU 64 (shared) 22.7.4 Conclusions Timeslots should be programmed to maximise interleaving of shared read bus accesses with other accesses for 3 cycle DRAM access. The interleaving is achieved by ordering the DIU arbitration slot allocation 5 appropriately. CPU arbitration has been designed to maximise interleaving with non-CPU requesters 22.8 SoPEC DRAM ADDRESSING SCHEME The embedded DRAM is composed of 256-bit words. However the CPU-subsystem may need to write individual bytes of DRAM. Therefore it was decided to make the DIU byte addressable. 22 bits are required to byte address 20 Mbit of DRAM. 10 Most blocks read or write 256 bit words of DRAM. Therefore only the top 17 bits i.e. bits 21 to 5 are required to address 256-bit word aligned locations. The exceptions are e CDU which can write 64-bits so only the top 19 address bits i.e. bits 21-3 are required. e CPU writes can be 8, 16 or 32-bits. The cpu_diu_wmask[1:O] pins indicate whether to write 8, 16 15 or 32 bits. All DIU accesses must be within the same 256-bit aligned DRAM word. The exception is the CDU write access which is a write of 64-bits to each of 4 contiguous 256-bit DRAM words. 22.8.1 Write Address Constants Specific to the CDU 20 Note the following conditions which apply to the CDU write address, due to the four masked page-mode writes which occur whenever a CDU write slot is arbitrated. e The CDU address presented to the DIU is cdu_diu_wadr[21:3]. e Bits [4:3] indicate which 64-bit segment out of 256 bits should be written in 4 successive masked 25 page-mode writes.
WO 2005/120835 PCT/AU2004/000706 648 e Each 10-Mbit DRAM macro has an input address port of width [15:0]. Of these bits, [2:0] are the "page address". Page-mode writes, where these LSBs (i.e. the "page" or column address) are varied the rest of the address is kept constant, are faster than random writes. This is taken advantage of for CDU writes. 5 - To guarantee against trying to span a page boundary, the DIU treats "cdudiuwadr[6:5]" as being fixed at "00". * From cdudiuwadr[21:3], a initial address of cdu diuwadr[21:7], concatenated with "00", is used as the starting location for the first CDU write. This address is then auto-incremented a further three times. 10 22.9 DIU PROTOCOLS The DIU protocols are * Pipelined i.e. the following transaction is initiated while the previous transfer is in progress. * Split transaction i.e. the transaction is split into independent address and data transfers. 22.9.1 Read Protocol except CPU 15 The SoPEC read requestors, except for the CPU, perform single 256-bit read accesses with the read data being transferred from the DIU in 4 consecutive cycles over a shared 64-bit read bus, diudata[63:0]. The read address <unit>_diuradr[21:5j is 256-bit aligned. The read protocol is: " <unit> diurreq is asserted along with a valid <unit>_diuradr[21:5]. 20 o The DIU acknowledges the request with diu_<unit>_rack. The request should be deasserted. The minimum number of cycles between <unit>_diurreq being asserted and the DIU generating an diu_<unit>_rack strobe is 2 cycles (1 cycle to register the request, 1 cycle to perform the arbitration - see Section 22.14.10). " The read data is returned on diu data[63:0] and its validity is indicated by diu_<unit>_rvalid. The 25 overall 256 bits of data are transferred over four cycles in the order: [63:0] -> [127:64] -> [191:128] > [255:192]. " When four diu_<unit>_rvalid pulses have been received then if there is a further request <unit>_diurreq should be asserted again. diu_<unit>_rvalid will be always be asserted by the DIU for four consecutive cycles. There is a fixed gap of 2 cycles between diu_<unit>_rack and the first 30 diu_<unit>_rvalid pulse. For more detail on the timing of such reads and the implications for back to-back sequences, see Section 22.14.10. 22.9.2 Read Protocol for CPU The CPU performs single 256-bit read accesses with the read data being transferred from the DIU over a 35 dedicated 256-bit read bus for DRAM data, dram _cpu data[255:0]. The read address cpuadr[21:5] is 256 bit aligned. The CPU DIU read protocol is: WO 2005/120835 PCT/AU2004/000706 649 " cpudiurreq is asserted along with a valid cpuadr[21:5]. * The DIU acknowledges the request with diucpurack. The request should be deasserted. The minimum number of cycles between cpudiurreq being asserted and the DIU generating a cpudiurack strobe is 1 cycle (1 cycle to perform the arbitration - see Section 22.14.10). 5 * The read data is returned on dram cpu data[255:0] and its validity is indicated by diu cpu rvalid. " When the diucpurvalid pulse has been received then if there is a further request cpudiurreq should be asserted again. The diu cpu rvalid pulse has a gap of 1 cycle after diu cpu rack (1 cycle for the read data to be returned from the DRAM - see Section 22.14.10). 10 22.9.3 Write Protocol except CPU and CDU The SoPEC write requestors, except for the CPU and CDU, perform single 256-bit write accesses with the write data being transferred to the DIU in 4 consecutive cycles over dedicated point-to-point 64-bit write data busses. The write address <unit>_diu_wadr[21:5j is 256-bit aligned. The write protocol is: 15 - <unit>_diu wreq is asserted along with a valid <unit>_diu wadr[21:5. e The DIU acknowledges the request with diu_<unit>_wack. The request should be deasserted. The minimum number of cycles between <unit> diu wreq being asserted and the DIU generating an diu_<unit>_wack strobe is 2 cycles (1 cycle to register the request, I cycle to perform the arbitration - see Section 22.14.10). 20 e In the clock cycles following diu_<unit>_wack the SoPEC Unit outputs the <unit>_diudata[63:0], asserting <unit>_diu_wvalid. The first <unit>_diu wvalid pulse must occur the clock cycle after diu_<unit>_wack. <unit>_diu_wvalid remains asserted for the following 3 clock cycles. This allows for reading from an SRAM where new data is available in the clock cycle after the address has changed e.g. the address for the second 64-bits of write data is available the cycle after 25 diu_<unit>_wack meaning the second 64-bits of write data is a further cycle later. The overall 256 bits of data is transferred over four cycles in the order: [63:0] -> [127:64] -> [191:128] -> [255:192]. - Note that for UHU and UDU writes, each 64-bit quarter-word has an 8-bit byte enable mask associated with it. A different mask is used with each quarter-word. The 4 mask values are transferred along with their associated data, as shown in Figure 105. 30 * If four consecutive <unit>_diuwvalid pulses are not provided by the requester^ immediately following the diu_<unit>_wack, then the arbitration logic will disregard the write and re-allocate the slot under the unused read round-robin scheme. e Once all the write data has been output then if there is a further request <unit>_diuwreq should be asserted again. 35 22.9.4 CPU Write Protocol The CPU performs single 128-bit writes to the DIU on a dedicated write bus, cpudiuwdata[127:0]. There is an accompanying write mask, cpu diuwmask[15:0], consisting of 16 byte enables and the CPU also supplies a 128-bit aligned write address on cpudiuwadr[21:4]. Note that writes are posted by the CPU to the DIU WO 2005/120835 PCT/AU2004/000706 650 and stored in a 1-deep buffer. When the DAU subsequently arbitrates in favour of the CPU, the contents of the buffer are written to DRAM. The CPU write protocol, illustrated in Figure 106. , is as follows: The DIU signals to the CPU via diucpuwrite rdy that its write buffer is empty and that the CPU 5 may post a write whenever it wishes. " The CPU asserts cpu_diu_wdatavalid to enable a write into the buffer and to confirm the validity of the write address, data and mask. e The DIU de-asserts diucpuwriterdy in the following cycle. If the CPU address is in range (i.e. does not exceed the maximum legal DRAM address) then the rdy signal is held low to indicate that 10 the write buffer is full and that the posted write is pending execution. However, for out-of-range CPU addresses, diucpuwrite rdy stays low just for one cycle and nothing is loaded into the write buffer. " Note that the check for a legal address for a CPU write is carried out at the time of posting, i.e. while cpudiuwdatavalid is high. If the address is valid, then the buffer is loaded and the write will be executed, regardless of any subsequent reconfiguration of the disableUpperDRAMMacro register. 15 9 When the CPU is awarded a DRAM access by the DAU, the buffer's contents are written to memory. The DIU re-asserts diucpuwrite rdy once the write data has been captured by DRAM, namely in the "MSN1" DCU state. " The CPU can then, if it wishes, asynchronously use the new value of diucpu write rdy to enable a new posted write in the same "MSN1" cycle. 20 22.9.5 CDU Write Protocol The CDU performs four 64-bit word writes to 4 contiguous 256-bit DRAM addresses with the first address specified by cdu diu wadr[21:3j. The write address cdu_diu wadr[21:5] is 256-bit aligned with bits cdu_diu _wadr[4:3j allowing the 64-bit word to be selected. The write protocol is: 25 * cdu_diu_wdata is asserted along with a valid cdu_diu_wadr[21:3]. * The DIU acknowledges the request with diu cduwack. The request should be deasserted. The minimum number of cycles between cdu_diuwreq being asserted and the DIU generating an diu_cdu_wack strobe is 2 cycles (1 cycle to register the request, 1 cycle to perform the arbitration see Section 22.14.10). 30 e In the four clock cycles following diu cdu wack the CDU outputs the cdu_diudata[63:0j, together with asserted cdu_diu_wvalid. The first cdu_diuwvalid pulse must occur the clock cycle after diu_cduwack. cdu_diuwvalid remains asserted for the following 3 clock cycles. This allows for reading from an SRAM where new data is available in the clock cycle after the address has changed e.g. the address for the second 64-bits of write data is available the cycle after diucduwack 35 meaning the second 64-bits of write data is a further cycle later. Data is transferred over the 4-cycle window in an order, such that each successive 64 bits will be written to a monotonically increasing (by 1 location) 256-bit DRAM word.
WO 2005/120835 PCT/AU2004/000706 651 " If four consecutive cdudiu_wvalid pulses are not provided with the data immediately following the write acknowledgment, then the arbitration logic will disregard the write and re-allocate the slot under the unused read round-robin scheme. " Once all the write data has been output then if there is a further request cdudiuwreq should be 5 asserted again WO 2005/120835 PCT/AU2004/000706 652 22.10 DIU ARBITRATION MECHANISM The DIU will arbitrate access to the embedded DRAM. The arbitration scheme is outlined in the next sections. 5 22.10.1 Timesiot based arbitration scheme Table 106 summarised the bandwidth requirements of the SoPEC requestors to DRAM. If the DIU requestors are allocated in terms of peak bandwidth then 35.25 bits/cycle (at SF =6) and 40.75 bits/cycle (at SF = 4) are reuired for all the requestors except the CPU. A timeslot scheme is defined with 64 main timeslots. The number of used main timeslots is programmable 10 between 1 and 64. Since DRAM read requestors, except for the CPU, are connected to the DIU via a 64-bit data bus each 256-bit DRAM access requires 4 pclk cycles to transfer the read data over the shared read bus. The timeslot rotation period for 64 timeslots each of 4 pclk cycles is 256 pclk cycles. Each timeslot represents a 256-bit access every 256 pclk cycles or 1 bit/cycle. This is the granularity of the majority of DIU requestors bandwidth 15 requirements in Table 106. The SoPEC DIU requesters can be represented using 4 bits (Table 129 on page 378). Using 64 timeslots means that to allocate each timeslot to a requester, a total of 64 x 5-bit configuration registers are required for the 64 main timeslots. Timeslot based arbitration works by having a pointer point to the current timeslot. When re-arbitration is 20 signaled the arbitration winner is the current timeslot and the pointer advances to the next timeslot. Each timeslot denotes a single access. The duration of the timeslot depends on the access. Note that advancement through the timeslot rotation is dependent on an enable bit, RotationSync, being set. The consequences of clearing and setting this bit are described in section 22.14.12.2.1 on page 408. If the SoPEC Unit assigned to the current timeslot is not requesting then the unused timeslot arbitration 25 mechanism outlined in Section 22.10.6 is used to select the arbitration winner. Note that there is always an arbitration winner for every slot. This is because the unused read re-allocation scheme includes refresh in its round-robin protocol. If all other blocks are not requesting, an early refresh will act as fall-back for the slot. 22.10.2 Separate read and write arbitration windows 30 For write accesses, except the CPU, 256-bits of write data are transferred from the SoPEC DIU write requestors over 64-bit write busses in 4 clock cycles. This write data transfer latency means that writes accesses, except for CPU writes and also the CDU, must be arbitrated 4 cycles in advance. (The CDU is an exception because CDU writes can start once the first 64-bits of write data have been transferred since each 64-bits is associated with a write to a different 256-bit word).
WO 2005/120835 PCT/AU2004/000706 653 Since write arbitration must occur 4 cycles in advance, and the minimum duration of a timeslot is 3 cycles, the arbitration rules must be modified to initiate write accesses in advance. Accordingly, there is a write timeslot lookahead pointer shown in Figure 109 two timeslots in advance of the current timeslot pointer. The following examples illustrate separate read and write timeslot arbitration with no adjacent write timeslots. 5 (Recall rule on adjacent write timeslots introduced in Section 22.7.2.3 on page 333.) In Figure 110 writes are arbitrated two timeslots in advance. Reads are arbitrated in the same timeslot as they are issued. Writes can be arbitrated in the same timeslot as a read. During arbitration the command address of the arbitrated SoPEC Unit is captured. Other examples are shown in Figure 111 and Figure 112. The actual timeslot order is always the same as the 10 programmed timeslot order i.e. out of order accesses do not occur and data coherency is never an issue. Each write must always incur a latency of two timeslots. Startup latency may vary depending on the position of the first write timeslot. This startup latency is not important. Table 109 shows the 4 scenarios depending on whether the current timeslot and write timeslot lookahead 15 pointers point to read or write accesses. Table 109. Arbitration with separate windows for read and write accesses read write Initiate DRAM read, Initiate write arbitration read read2 Initiate DRAM read. writer write2 Initiate write2 arbitration. Execute DRAM writer. write read Execute DRAM write. If the current timeslot pointer points to a read access then this will be initiated immediately. If the write timeslot lookahead pointer points to a write access then this access is arbitrated immediately, or immediately after the read access associated with the current timeslot pointer is initiated. 20 When a write access is arbitrated the DIU will capture the write address. When the current timeslot pointer advances to the write timeslot then the actual DRAM access will be initiated. Writes will therefore be arbitrated 2 timeslots in advance of the DRAM write occurring. At initialisation, the write lookahead pointer points to the first timeslot. The current timeslot pointer is invalid until the write lookahead pointer advances to the third timeslot when the current timeslot pointer will point to 25 the first timeslot. Then both pointers advance in tandem.
WO 2005/120835 PCT/AU2004/000706 654 CPU write accesses are excepted from the lookahead mechanism. If the selected SoPEC Unit is not requesting then there will be separate read and write selection for unused timeslots. This is described in Section 22.10.6. 22.10.3 Arbitration of CPU accesses 5 What distinguishes the CPU from other SoPEC requestors, is that the CPU requires minimum latency DRAM access i.e. preferably the CPU should get the next available timeslot whenever it requests. The minimum CPU read access latency is estimated in Table 110. This is the time between the CPU making a request to the DIU and receiving the read data back from the DIU. Table 110. Estimated CPU read access latency Ignoring caching Register the read data in CPU 1 cycle CPU MMU logic issues request and 1 cycle DIU arbitration completes Transfer the read address to the I cycle DRAM DRAM read latency 1 cycle DRAM read latency 1 cycle CPU internally completes transaction 1 cycle CPU MMU logic issues request and 1 cycle DIU arbitration completes TOTAL gap between requests 5 cycles 10 If the CPU, as is likely, requests DRAM access again immediately after receiving data from the DIU then the CPU could access every second timeslot if the access latency is 6 cycles. This assumes that interleaving is employed so that timeslots last 3 cycles. If the CPU access latency were 7 cycles, then the CPU would only be able to access every third timeslot. If a cache hit occurs the CPU does not require DRAM access. For its next DIU access it will have to wait for 15 its next assigned DIU slot. Cache hits therefore will reduce the number of DRAM accesses but not speed up any of those accesses. To avoid the CPU having to wait for its next timeslot it is desirable to have a mechanism for ensuring that the CPU always gets the next available timeslot without incurring any latency on the non-CPU timeslots. This can be done by defining each timeslot as consisting of a CPU access preceding a non-CPU access. Each 20 timeslot will last 6 cycles i.e. a CPU access of 3 cycles and a non-CPU access of 3 cycles. This is exactly the interleaving behaviour outlined in Section 22.7.2.2. If the CPU does not require an access, the timeslot will take 3 or 4 and the timeslot rotation will go faster. A summary is given in Table 111.
WO 2005/120835 PCT/AU2004/000706 655 Table 111. Timeslot access times. CPU access + non-CPU 3 + 3 = 6 cycles Interleaved access access non-CPU access 4 cycles Access and preceding access both to shared read bus non-CPU access 3 cycles Access and preceding access not both to shared read bus CDU write access 3+2+2+2 = 9 cycles Page mode select signal is clocked at 192 MHz CDU write accesses require 9 cycles. CDU write accesses preceded by a CPU access require 12 cycles. CDU timeslots therefore take longer than all other DIU requestors timeslots. With a 256 cycle rotation there can be 42 accesses of 6 cycles. 5 For low scale factor applications, it is desirable to have more timeslots available in the same 256 cycle rotation. So two counters of 4-bits each are defined allowing the CPU to get a maximum of (CPUPreAccessTimeslots + 1) pre-accesses for every (CPUTotalTimeslots + 1) main slots. A timeslot counter starts at CPUTotalTimeslots and decrements every timeslot, while another counter starts at CPUPreAccessTimeslots and decrements every timeslot in which the CPU uses its access. When the CPU pre 10 access counter goes to zero before CPUTotalTimeslots, no further CPU accesses are allowed. When the CPUTotalTimeslots counter reaches zero both counters are reset to their respective initial values. The CPU is not included in the list of SoPEC DIU requesters, Table 130, for the main timeslot allocations. The CPU cannot therefore be allocated main timeslots. It relies on pre-accesses in advance of such slots as the sole method for DRAM transfers. 15 CPU access to DRAM can never be fully disabled, since to do so would render SoPEC inoperable. Therefore the CPUPreAccessTimeslots and CPUTotalTimeslots register values are interpreted as follows: In each succeeding window of (CPUTotalTimeslots+ 1) slots, the maximum quota of CPU pre-accesses allowed is (CPUPreAccessTimeslots + 1). The "+ 1" implementations mean that the CPU quota cannot be made zero. The various modes of operation are summarised in Table 112 with a nominal rotation period of 256 cycles. Table 112. CPU timeslot allocation modes with nominal rotation period of 256 cycles CPU Pre-access 6 cycles 42 timeslots Each access is CPU + non-CPU. i.e. If CPU does not use a timeslot then CPUPreAccessTimeslots = rotation is faster. CPUTotalTimeslots Fractional CPU Pre-access 4 or 6 cycles 42-64 Each CPU + non-CPU access i.e. timeslots requires a 6 cycle nt IormA ce-rn~mI*'.* timeslot.
WO 2005/120835 PCT/AU2004/000706 656 CPUPreAccessTimeslots < Individual non-CPU timeslots take 4 CPUTotalTimeslots cycles if current access and preceding access are both to shared read bus. Individual non-CPU timeslots take 3 cycles if current access and preceding access are not both to shared read bus. 22.10.4 CDU accesses As indicated in Section 22.10.3, CDU write accesses require 9 cycles. CDU write accesses preceded by a CPU access require 12 cycles. CDU timeslots therefore take longer than all other DIU requestors timeslots. 5 This means that when a write timeslot is unused it cannot be re-allocated to a CDU write as CDU accesses take 9 cycles. The write accesses which the CDU write could otherwise replace require only 3 or 4 cycles. Unused CDU write accesses can be replaced by any other write access according to 22.10.6.1 Unused write timeslots allocation on page 348. 10 22.10.5 Refresh controller Refresh is not included in the list of SoPEC DIU requesters, Table 130, for the main timeslot allocations. Timeslots cannot therefore be allocated to refresh. The DRAM must be refreshed every 3.2 ms. Refresh occurs row at a time over 5120 rows of 2 parallel 10 Mbit instances. A refresh operation must therefore occur every 120 cycles. The refreshperiod register has a 15 default value of 118. Each refresh takes 3 cycles. Setting refreshperiod to 118 means a refresh occurs every 119 cycles. This allows any delays on issuing the refresh for a particular row due e.g. to CDUW, CPU preaccess to be caught up.] A refresh counter will count down the number of cycles between each refresh. When the down-counter reaches 0, the refresh controller will issue a refresh request and the down-counter is reloaded with the value in 20 refresh_period and the count-down resumes immediately. Allocation of main slots must take into account that a refresh is required at least once every 120 cycles. Refresh is included in the unused read and write timeslot allocation. If unused timeslot allocation results in refresh occurring early by N cycles, then the refresh counter will have counted down to N. In this case, the refresh counter is reset to refresh_period and the count-down recommences. 25 Refresh can be preceded by a CPU access in the same way as any other access. This is controlled by the CPUPreAccessTimeslots and CPUTotalTimeslots configuration registers. Refresh will therefore not affect CPU performance. A sequence of accesses including refresh might therefore be CPU, refresh, CPU, actual timeslot.
WO 2005/120835 PCT/AU2004/000706 657 22.10.6 Allocating unused timeslots Unused slots are re-allocated separately depending on whether the unused access was a read access or a write access. This is best-effort traffic. Only unused non-CPU accesses are re-allocated. 22.10.6.1 Unused write timeslots allocation 5 Unused write timeslots are re-allocated according to affixed priority order shown in Table 113. Table 113. Unused write timeslot priority order UHU(W) 1 UDU(W) 2 SFU(W) 3 DWU 4 MMI(W) 5 Unused read timeslot 6 allocation CDU write accesses cannot be included in the unused timeslot allocation for write as CDU accesses take 9 cycles. The write accesses which the CDU write could otherwise replace require only 3 or 4 cycles. 10 Unused write timeslot allocation occurs two timeslots in advance as noted in Section 22.10.2. If the units at priorities 1-5 are not requesting then the timeslot is re-allocated according to the unused read timeslot allocation scheme described in Section 22.10.6.2. However, the unused read timeslot allocation will occur when the current timeslot pointer of Figure 109 reaches the timeslot i.e. it will not occur in advance. 22.10.6.2 Unused read timeslots allocation 15 Unused read timeslots are re-allocated according to a two level round-robin scheme. The SoPEC Units included in read timeslot re-allocation is shown in Table 131 Table 114. Unused read timeslot allocation UHU(R) UDU(R) CDU(R)
CFU
WO 2005/120835 PCT/AU2004/000706 658 LBD SFU(R) TE(TD) TE(TFS) HCU DNC LLU PCU MMI CPU /Refresh Each SoPEC requestor has an associated bit, ReadRoundRobinLevel, which indicates whether it is in level 1 or level 2 round-robin. Table 115. Read round-robin level selection .............. ReadRoundRobinLevel = 0 Level 1 ReadRoundRobinLevel = 1 Level 2 5 A pointer points to the most recent winner on each of the round-robin levels. Re-allocation is carried out by traversing level I requesters, starting with the one immediately succeeding the last level 1 winner. If a requesting unit is found, then it wins arbitration and the level 1 pointer is shifted to its position. If no level 1 unit wants the slot, then level 2 is similarly examined and its pointer adjusted. 10 Since refresh occupies a (shared) position on one of the two levels and continually requests access, there will always be some round-robin winner for any unused slot. 22.10.5.2.1 Shared CPU / Refresh Round-Robin Position Note that the CPU can conditionally be allowed to take part in the unused read round-robin scheme. Its participation is controlled via the configuration bit EnableCPURoundRobin. When this bit is set, the CPU and 15 refresh share a joint position in the round-robin order, shown in Table 114. When cleared, the position is occupied by refresh alone.
WO 2005/120835 PCT/AU2004/000706 659 If the shared position is next in line to be awarded an unused non-CPU read/write slot, then the CPU will have first option on the slot. Only if the CPU doesn't want the access, will it be granted to refresh. If the CPU is excluded from the round robin, then any awards to the position benefit refresh. 22.11 GUIDELINES FOR PROGRAMMING THE DIU 5 Some guidelines for programming the DIU arbitration scheme are given in this section together with an example. 22.11.1 Circuit Latency Circuit latency is a fixed service delay which is incurred, as and from the acceptance by the DIU arbitration logic of a block's pending read/write request. It is due to the processing time of the request, readying the data, 10 plus the DRAM access time. Latencies differ for read and write requests. See Tables 79 and 80 for respective breakdowns. If a requesting block is currently stalled, then the longest time it will have to wait between issuing a new request for data and actually receiving it would be its timeslot period, plus the circuit latency overhead, along with any intervening non-standard slot durations, such as refresh and CDU(W). In any case, a stalled block 15 will always incur this latency as an additional overhead, when coming out of a stall. In the case where a block starts up or unstalls, it will start processing newly-received data at a time beyond its serviced timeslot equivalent to the circuit latency. If the block's timeslots are evenly spaced apart in time to match its processing rate, (in the hope of minimizing stalls,) then the earliest that the block could restall, if not re-serviced by the DIU, would be the same latency delay beyond its next timeslot occurrence. Put another 20 way, the latency incurred at start-up pushes the potential DIU-induced stall point out by the same fixed delta beyond each successive timeslot allocated to the block. This assumes that a block re-requests access well in advance of its upcoming timeslots. Thus, for a given stall-free run of operation, the circuit latency overhead is only incurred initially when unstalling. While a block can be stalled as a result of how quickly the DIU services its DRAM requests, it is also prone to 25 stalls caused by its upstream or downstream neighbours being able to supply or consume data which is transferred between the blocks directly, (as opposed to via the DIU). Such neighbour-induced stalls, often occurring at events like end of line, will have the effect that a block's DIU read buffer will tend to fill, as the block stops processing read data. Its DIU write buffer will also tend to fill, unable to despatch to DRAM until the downstream block frees up shared-access DRAM locations. This scenario is beneficial, in that when a 30 block unstalls as a result of its neighbour releasing it, then that block's read/write DIU buffers will have a fill state less likely to stall it a second time, as a result of DIU service delays. A block's slots should be scheduled with a service guarantee in mind. This is dictated by the block's processing rate and hence, required access to the DRAM. The rate is expressed in terms of bits per cycle across a processing window, which is typically (though not always) 256 cycles. Slots should be evenly 35 interspersed in this window (or "rotation") so that the DIU can fulfill the block's service needs. The following ground rules apply in calculating the distribution of slots for a given non-CPU block: * The block can, at maximum, suffer a stall once in the rotation, (i.e. unstall and restall) and hence incur the circuit latency described above.
WO 2005/120835 PCT/AU2004/000706 660 This rule is, by definition, always fulfilled by those blocks which have a service requirement of only 1 bit/cycle (equivalent to 1 slot/rotation) or fewer. It can be shown that the rule is also satisfied by those blocks requiring more than 1 bit/cycle. See Section 22.12.4 Slot Distributions and Stall Calculations for Individual Blocks, on page 360. 5 * Within the rotation, enough slots must be subtracted to allow for scheduled refreshes. (See Section 22.11.2 Refresh latencies). * In programming the rotation, account must be taken of the fact that any CDU(W) accesses will consume an extra 6 cycles/access, over and above the norm, in CPU pre-access mode, or 5 cycles/access without pre-access. 10 The total delay overhead due to latency, refreshes and CDU(W) can be factored into the service guarantee for all blocks in the rotation by deleting once, (i.e. reducing the rotation window,) that number of slots which equates to the cumulative duration of these various anomalies. * The use of lower scale factors will imply a more frequent demand for slots by non-CPU blocks. The percentage of slots in the overall rotation which can therefore be designated as CPU pre-access ones 15 should be calculated last, based on what can be accommodated in the light of the non-CPU slot need. Read latency is summarised below in Table 116. Table 116. Read latency non-CPU read requester internally 1 cycle generates DIU request register the non- CPU read request 1 cycle complete the arbitration of the request 1 cycle transfer the read address to the DRAM 1 cycle DRAM read latency 1 cycle register the DRAM read data in DIU 1 cycle register the 1st 64-bits of read data in 1 cycle requester register the 2nd 64-bits of read data in 1 cycle requester register the 3rd 64-bits of read data in 1 cycle requester register the 4th 64-bits of read data in 1 cycle requester TOTAL 10 cycles Write latency is summarised in Table 117.
WO 2005/120835 PCT/AU2004/000706 661 Table 117. Write latency ~N n-GPU w~ilts .~oesfjncy u r tion\ non-CPU write requester internally 1 cycle generates DIU request register the non-CPU write request 1 cycle complete the arbitration of the request 1 cycle transfer the acknowledge to the write 1 cycle requester transfer the 1st 64 bits of write data to the 1 cycle DIU transfer the 2nd 64 bits of write data to the 1 cycle DIU transfer the 3rd 64 bits of write data to the 1 cycle DIU transfer the 4th 64 bits of write data to the 1 cycle DIU Write to DRAM with locally registered write 1 cycle data TOTAL 9 cycles Timeslots removed to allow for read latency will also cover write latency, since the former is the larger of the two. 22.11.2 Refresh latencies 5 The number of allocated timeslots for each requester needs to take into account that a refresh must occur every 120 cycles. This can be achieved by deleting timeslots from the rotation since the number of timeslots is made programmable. This approach takes account of the refresh latencies of blocks which have a service requirement of only 1 bit/cycle (equivalent to 1 slot/rotation) or fewer. It can be shown that the rule is also satisfied by those blocks 10 requiring more than 1 bit/cycle. See Section 22.12.4 Slot Distributions and Stall Calculations for Individual Blocks, on page 360. Refresh is preceded by a CPU access in the same way as any other access. This is controlled by the CPUPreAccessTimeslots and CPUTotalTimeslots configuration registers. Refresh will therefore not affect CPU performance. 15 As an example, in CPU pre-access mode each timeslot will last 6 cycles. If the timeslot rotation has 50 timeslots then the rotation will last 300 cycles. The refresh controller will trigger a refresh every 100 cycles. Up to 47 timeslots can be allocated to the rotation ignoring refresh. Three timeslots deleted from the 50 timeslot rotation will allow for the latency of a refresh every 100 cycles.
WO 2005/120835 PCT/AU2004/000706 662 22.11.3 Ensuring sufficient DNC and PCU access PCU command reads from DRAM are exceptional events and should complete in as short a time as possible. Similarly, sufficient free bandwidth should be provided to account for DNC accesses e.g. when clusters of dead nozzles occur. In Table 106 DNC is allocated 3 times average bandwidth. PCU and DNC can also be 5 allocated to the level 1 round-robin allocation for unused timeslots so that unused timeslot bandwidth is preferentially available to them. 22.11.4 Basing timeslot allocation on peak bandwidths Since the embedded DRAM provides sufficient bandwidth to use 1:1 compression rates for the CDU and 10 LBD, it is possible to simplify the main timeslot allocation by basing the allocation on peak bandwidths. As combined bi-level and tag bandwidth, including the SFU, at 1:1 scaling is only 5 bits/cycle, usually only the contone scale factor will be considered as the variable in determining timeslot allocations. If slot allocation is based on peak bandwidth requirements then DRAM access will be guaranteed to all SoPEC requesters. If slots are not allocated for peak bandwidth requirements then we can also allow for the 15 peaks deterministically by adding some cycles to the print line time. 22.11.5 Adjacent timeslot restrictions 22.11.5.1 Non-CPU write adjacent timeslot restrictions Non-CPU write requestors should not be assigned adjacent timeslots as described in Section 22.7.2.3. This is 20 because adjacent timeslots assigned to non-CPU requestors would require two sets of 256-bit write buffers and multiplexors to connect two write requestors simultaneously to the DIU. Only one 256-bit write buffer and multiplexor is implemented. Recall from section 22.7.2.3 on page 333 that if adjacent non-CPU writes are attempted, that the second write of any such pair will be disregarded and re-allocated under the unused read scheme. 25 22.11.5.2 Same DIU requestor adjacent timeslot restrictions All DIU requesters have state-machines which request and transfer the read or write data before requesting again. From Figure 103 read requests have a minimum separation of 9 cycles. From Figure 105 write requests have a minimum separation of 7 cycles. Therefore adjacent timeslots should not be assigned to a particular DIU requester because the requester will not be able to make use of all these slots. 30 In the case that a CPU access precedes a non-CPU access timeslots last 6 cycles so write and read requesters can only make use of every second timeslot. In the case that timeslots are not preceded by CPU accesses timeslots last 4 cycles so the same write requester can use every second timeslot but the same read requestor can use only every third timeslot. Some DIU requestors may introduce additional pipeline delays before they can request again. Therefore timeslots should be separated by more than the minimum to allow a margin. 35 WO 2005/120835 PCT/AU2004/000706 663 22.11.6 Line margin The SFU must output 1 bit/cycle to the HCU. Since HCUNumDots may not be a multiple of 256 bits the last 256-bit DRAM word on the line can contain extra zeros. In this case, the SFU may not be able to provide 1 bit/cycle to the HCU. This could lead to a stall by the SFU. This stall could then propagate if the margins 5 being used by the HCU are not sufficient to hide it. The maximum stall can be estimated by the calculation: DRAM service period - X scale factor * dots used from last DRAM read for HCU line. Similarly, if the line length is not a multiple of 256-bits then e.g. the LLU could read data from DRAM which contains padded zeros. This could lead to a stall. This stall could then propagate if the page margins cannot hide it. 10 A single addition of 256 cycles to the line time will suffice for all DIU requesters to mask these stalls. Example outline DIU programminG 22.12.1 Full speed USB device, no MMI or UHU connections Table 118. Timeslot allocation based on peak bandwidth with full speed USB device, no MMI or UHU connections and LLU SegSpan = 640, SegSpanStart = 0 BDandwidth Mai __sot Blok Name~ Di.ectio whihmst ~ alocte UDU R 0.0625 1 W 0.0625 1 CDU R 1.8 (SF = 6), 2 (SF = 6) 4(SF=4) 4(SF=4) W 1.8 (SF = 6), 2 (SF = 6) 4(SF=4) 4(SF=4) CFU R 5.4 (SF = 6), 6 (SF = 6) 8(SF=4) 8(SF=4) LBD R 1 1 SFU R 2 2 W 1 1 TE(TD) R 1.02 1 TE(TFS) R 0.093 0 HCU R 0.074 0 DNC R 2.4 3 DWU W 6 6 LLU R 8.57 9 PCU R 1 1 WO 2005/120835 PCT/AU2004/000706 664 UHU R 0 0 W 0 0 MMI R 0 0 W 0 0 TOTAL 1 36 (SF=6) 42 (SF=4) 22.12.1 Table 118 shows an allocation of main timeslots based on the peak bandwidths of Table 106. The bandwidth required for each unit is calculated allowing extra cycles for read and write circuit latency for each access requiring a bandwidth of more than 1 bit/cycle. Fractional bandwidth is supplied via unused read 5 slots. The timeslot rotation is 256 cycles. Timeslots are deleted from the rotation to allow for circuit latencies for accesses of up to 1 bit per cycle i.e. 1 timeslot per rotation. Example 1: Contone scale-factor = 6, bi-level scale factor = 1, USB device full-speed, no MMI or UHU 10 connections, LLU SegSpan = 640, SegSpanStart = 0 Program the MainTimeslot configuration register (Table 129) for peak required bandwidths of SoPEC Units according to the scale factor. Program the read round-robin allocation to share unused read slots. Allocate PCU, DNC, HCU and TFS to level 1 read round-robin. 15 o Assume scale-factor of 6 and peak bandwidths from Table 118. o Assign all DIU requestors except TE(TFS) and HCU to multiples of 1 timeslot, as indicated in Table 118, where each timeslot is 1 bit/cycle. This requires 36 timeslots. o No timeslots are explicitly allocated for the fractional bandwidth requirements of TE(TFS) and HCU accesses. Instead, these units are serviced via unused read slots. 20 - Therefore, 36 scheduled slots are used in the rotation for main timeslots, some or all of which may be able to have a CPU pre-access, provided they fit in the rotation window. e Each of the 2 CDU(W) accesses requires 9 cycles. Per access, this implies an overhead of 6 cycles. Over the rotation the 2 CDU(W) accesses have an overhead of 12 cycles. - Assuming all blocks require a service guarantee of no more than a single stall across 256 bits, allow 25 10 cycles for read latency once in the rotation. o There can be 3 refreshes over the rotation. If each of these refreshes has a pre-access then 3x6 = 18 cycles must be allowed in the rotation. o A total of 12 + 10 +18 = 40 cycles have to be subtracted from the rotation period to allow for CDUW/startup/refresh latency. 30 * Assume a 256 cycle timeslot rotation. * CDU(W), read latency and refresh reduce the number of available cycles in a rotation to: 256 - 40 = 216 cycles.
WO 2005/120835 PCT/AU2004/000706 665 * As a result, 216 cycles available for 36 accesses implies each access can take 216 / 36 = 6 cycles maximum. So, all accesses can have a pre-access. - Therefore the CPU achieves a pre-access ratio of 36 / 36 = 100% of the programmed slots in the rotation. Any refreshes in the rotation can also have pre-accesses. The rotation is speeded up by 10 5 cycles to allow for any startup latencies. The rotation is speeded up by 6 cycles to allow for the extra 6 cycle latency for each of 2 CDUW accesses.CDU(W), read latency and refresh reduce the number of available cycles in a rotation to: 256 - 40 = 216 cycles. Example 2: Contone scale-factor = 4, bi-level scale factor = 1, USB device full-speed, no MMI or UHU 10 connections, LLU SegSpan = 640, SegSpanStart = 0 Program the MainTimeslot configuration register (Table 129) for peak required bandwidths of SoPEC Units according to the scale factor. Program the read round-robin allocation to share unused read slots. Allocate PCU, DNC, HCU and TFS to level 1 read round-robin. e Assume scale-factor of 4 and peak bandwidths from Table 118. 15 e Assign all DIU requestors except TE(TFS) and HCU multiples of 1 timeslot, as indicated in Table 118, where each timeslot is 1 bit/cycle. This requires 42 timeslots. * No timeslots are explicitly allocated for the fractional bandwidth requirements of TE(TFS) and HCU accesses. Instead, these units are serviced via unused read slots. * Therefore, 42 scheduled slots are used in the rotation for main timeslots, some or all of which can 20 have a CPU pre-access, provided they fit in the rotation window. * Each of the 4 CDU(W) accesses requires 9 cycles. Per access, this implies an overhead of 6 cycles. Over the rotation the 4 CDU(W) accesses have an overhead of 24 cycles. * Assuming all blocks require a service guarantee of no more than a single stall across 256 bits, allow 10 cycles for read latency once in the rotation. 25 0 There can be 3 refreshes over the rotation. If each of these refreshes has a pre-access then 3x6 = 18 cycles must be allowed in the rotation. e A total of 24 + 10 +18 = 52 cycles have to be subtracted from the rotation period to allow for CDUW/startup/refresh latency. e Assume a 256 cycle timeslot rotation. 30 - CDU(W), read latency and refresh reduce the number of available cycles in a rotation to: 256 - 52 = 204 cycles. * As a result, between 204 are available for 42 accesses, which implies each access can take 204 / 42 = 4.85 cycles. e Work out how many slots can have a pre-access: For the available 204 cycles, this implies (42 35 n)*6 + n*4 <= 204, where n = number of slots with no pre-access cycle. Solving the equation gives n >= 24. e So 18 slots out of the 42 programmed slots in the rotation can have CPU pre-accesses. * Therefore the CPU achieves a pre-access ratio of 18 / 42 = 42.8% of the programmed slots in the rotation. Any refreshes in the rotation can also have pre-accesses. The rotation is speeded up by 10 WO 2005/120835 PCT/AU2004/000706 666 cycles to allow for any startup latencies. The rotation is speeded up by 6 cycles to allow for the extra 6 cycle latency for each of 4 CDUW accesses. 22.12.2 High Speed USB Host Table 119. Timeslot allocation based on peak bandwidth with high-speed USB host, no MMI or USB device connections and LLU SegSpan = 320, SegSpanStart = 64, 5:1 contone compression Peak andwdth Bloc Nae Drecion which must be MainTimeslots supplied allocated UDU R 0 0 W 0 0 CDU R 1.8/5 (SF = 6), 1 (SF = 6) 4/5 (SF = 4) 1 (SF = 4) W 1.8 (SF = 6), 2 (SF = 6) 4 (SF = 4) 4 (SF = 4) CFU R 5.4 (SF = 6), 6 (SF = 6) 8 (SF = 4) 8 (SF = 4) LBD R 1 1 SFU R 2 2 W 1 1 TE(TD) R 1.02 1 TE(TFS) R 0.093 0 HCU R 0.074 0 DNC R 2.4 3 DWU W 6 6 LLU R 12.86 (average) 13 PCU R 1 1 UHU R 480 Mbit/s 3 W 480 Mbit/s 3 MMI R 0 0 W 0 0 TOTAL 43 (SF=6) 47 (SF=4) 22.12.2 5 Example 3: Contone scale-factor = 6, bi-level scale factor = 1, USB host high-speed, no MMI or USB device connections, LLU SegSpan = 320, SegSpanStart = 64 WO 2005/120835 PCT/AU2004/000706 667 Program the MainTimeslot configuration register (Table 129) for peak required bandwidths of SoPEC Units according to the scale factor. Program the read round-robin allocation to share unused read slots. Allocate PCU, DNC, HCU and TFS to level 1 read round-robin. e Assume scale-factor of 6 and peak bandwidths from Table 119. 5 e Assign all DIU requestors except TE(TFS) and HCU multiples of 1 timeslot, as indicated in Table 119, where each timeslot is 1 bit/cycle. This requires 43 timeslots. * No timeslots are explicitly allocated for the fractional bandwidth requirements of TE(TFS) and HCU accesses. Instead, these units are serviced via unused read slots. * Therefore, 43 scheduled slots are used in the rotation for main timeslots, some or all of which can 10 have a CPU pre-access, provided they fit in the rotation window. e Each of the 2 CDU(W) accesses requires 9 cycles. Per access, this implies an overhead of 6 cycles. Over the rotation the 2 CDU(W) accesses have an overhead of 12 cycles. * Assuming all blocks require a service guarantee of no more than a single stall across 256 bits, allow 10 cycles for read latency once in the rotation. 15 * There can be 3 refreshes over the rotation. If each of these refreshes has a pre-access then 3x6 = 18 cycles must be allowed in the rotation. o A total of 12 + 10 +18 = 40 cycles have to be subtracted from the rotation period to allow for CDUW/startup/refresh latency. a Assume a 256 cycle timeslot rotation. 20 * CDU(W), read latency and refresh reduce the number of available cycles in a rotation to: 256 - 40 = 216 cycles. - As a result, between 216 are available for 44 accesses, which implies each access can take 216 / 43 = 5.02 cycles. * Work out how many slots can have a pre-access: For the available 216 cycles, this implies (43 - n)*6 25 + n*4 <= 216, where n = number of slots with no pre-access cycle. Solving the equation gives n >= 24. Check answer: 22*6 + 21*4 = 216. o So 22 slots out of the 43 programmed slots in the rotation can have CPU pre-accesses. * Therefore the CPU achieves a pre-access ratio of 22 / 43 = 51.1% of the programmed slots in the rotation. Any refreshes in the rotation can also have pre-accesses. The rotation is speeded up by 10 30 cycles to allow for any startup latencies. The rotation is speeded up by 6 cycles to allow for the extra 6 cycle latency for each of 2 CDUW accesses. Example 3: Contone scale-factor = 4, bi-level scale factor = 1, USB host high -speed, no MMI or UHU connections, LLU SegSpan = 320, SegSpanStart = 64 35 Program the MainTimeslot configuration register (Table 129) for peak required bandwidths of SoPEC Units according to the scale factor. Program the read round-robin allocation to share unused read slots. Allocate PCU, DNC, HCU and TFS to level 1 read round-robin. e Assume scale-factor of 4 and peak bandwidths from Table 119. e Assign all DIU requestors except TE(TFS) and HCU multiples of 1 timeslot, as indicated in 40 Table 119, where each timeslot is 1 bit/cycle. This requires 47 timeslots.
WO 2005/120835 PCT/AU2004/000706 668 * No timeslots are explicitly allocated for the fractional bandwidth requirements of TE(TFS) and HCU accesses. Instead, these units are serviced via unused read slots. " Therefore, 47 scheduled slots are used in the rotation for main timeslots, some or all of which can have a CPU pre-access, provided they fit in the rotation window. 5 9 Each of the 4 CDU(W) accesses requires 9 cycles. Per access, this implies an overhead of 6 cycles. Over the rotation the 4 CDU(W) accesses have an overhead of 24 cycles. " Assuming all blocks require a service guarantee of no more than a single stall across 256 bits, allow 10 cycles for read latency once in the rotation. * There can be 3 refreshes over the rotation. If each of these refreshes has a pre-access then 3x6 = 18 10 cycles must be allowed in the rotation. " A total of 24 + 10 +18 = 52 cycles have to be subtracted from the rotation period to allow for CDUW/startup/refresh latency. " Assume a 256 cycle timeslot rotation. " CDU(W), read latency and refresh reduce the number of available cycles in a rotation to: 256 - 52 = 15 204 cycles. " As a result, between 204 are available for 47 accesses, which implies each access can take 204 / 47 = 4.34 cycles. " Work out how many slots can have a pre-access: For the available 204 cycles, this implies (47 - n)*6 + n*4 <= 204, where n = number of slots with no pre-access cycle. Solving the equation gives n >= 20 48. Check answer: 8*6 + 39*4 = 204. " So 8 slots out of the 47 programmed slots in the rotation can have CPU pre-accesses. " Therefore the CPU achieves a pre-access ratio of 8 / 47 = 17% of the programmed slots in the rotation. Any refreshes in the rotation can also have pre-accesses. The rotation is speeded up by 10 cycles to allow for any startup latencies. The rotation is speeded up by 6 cycles to allow for the extra 25 6 cycle latency for each of 4 CDUW accesses. 22.12.3 Communications SoPEC with High Speed USB Host, USB device and MMI connections Table 120. Timeslot allocation based on peak bandwidth with high-speed USB host, high-speed USB device and MMI connections (non printing SoPEC) .-. X px ___ MF~ UDU R 480 Mbit/s 1 W 480 Mbit/s 1 CDU R 0 0 W 0 0 CFU R 0 0 WO 2005/120835 PCT/AU2004/000706 669 LBD R 0 0 SFU R 0 0 W 0 0 TE(TD) R 0 0 TE(TFS) R 0 0 HCU R 0 0 DNC R 0 0 DWU W 0 0 LLU R 0 0 PCU R 0 0 UHU R 480 Mbit/s 1 W 480 Mbit/s 1 MMI R 480 Mbit/s 1 W 480 Mbit/s 1 TOTAL 6 22.12.3 Example 4: High-speed USB host, high-speed USB device and MMI connections (non-printing SoPEC) For this programming example only 6 DIU slots are required. CPU pre-accesses are possible for each slot. The rotation will complete in 6 slots each of 6 cycles or 36 cycles. Each of the 6 slots can transfer 256 bits of 5 DIU data every 36 cycles. So a slot is 256/36 times 192 Mbit/s or 1365 Mbit/s. 22.12.4 Slot Distributions and Stall Calculations for Individual Blocks The following sections show how the slots for blocks with a service requirement greater than 1 bit/cycle should be distributed. Calculations are included to check that such blocks will not suffer more than one stall per rotation due to startup, refresh or CDUW accesses. 10 Therefore the total delay overhead due to latency, refreshes and CDU(W) can be factored into the service guarantee for all blocks in the rotation by deleting once, (i.e. reducing the rotation window) that number of slots which equates to the cumulative duration of these various anomalies. 22.12.4.1 SFU This has 2 bits/cycle on read but this is two separate channels of 1 bit/cycle sharing the same DIU interface so 15 it is effectively 2 channels each of 1 bit/cycle so allowing the same margins as the LBD will work. 22.12.4.2 DWU The DWU has 12 double buffers in each of the 6 colour planes, odd and even. These buffers are filled by the DNC and will request DIU access when double buffers fill. The DNC supplies 6 bits to the DWU every cycle WO 2005/120835 PCT/AU2004/000706 670 (6 odd in one cycle, 6 even in the next cycle). So the service deadline is 512 cycles, given 6 accesses per 256 cycle rotation. 22.12.4.3 CFU The solution for the CFU is to increase its double 256-bit buffer interface to the DIU. The CFU implements a 5 quad-256 bit buffer interface to the DIU. The requirement is that the DIU stall should be less than the time taken for the CFU to consume its extra 512 bits of buffering. The total DIU stall = refresh latency + extra CDU(W) latency + read circuit latency = 3 + 5 (for 4 cycle timeslots) + 10 = 18 cycles. The CFU can consume its data at 8 bits/cycle at SF = 4. An extra 144 bits of buffering i.e. 8 x 18 bits is needed. Therefore the extra 512 bits of buffering is more than enough. 10 Sometimes in slot allocations slots cannot be evenly allocated around the slot rotation. The CFU has an extra 512-144 = 368 bits of buffering to cope with this. This 368 bits will last 46 cycles at SF=4. Therefore the CFU can cope with not exactly evenly spaced slot distributions. 22.12.4.4 LLU 15 The LLU requires DIU access of approx 6.43 bits/cycle. This is to keep the PHI fed at an effective rate of 225 Mb/s assuming 12 segments but taking account that only 11 segments can actually be driven. For SegSpan = 640 and SegDotOffset = 0 the LLU will use 256 bits, 256 bits, and then 128 bits of the last DRAM word. Not utilizing the last 128-bits means the average bandwidth required increases by 1/3 to 8.57 bits/cycle. The LLU quad buffer will be able to keep the LLU supplied with data if the DIU supplies this average bandwidth. 20 Thus each channel requires approximately 1.43 bits/cycle or 1.43 slots per 256 cycle rotation. The allocation of cycles for a startup following a stall will allow for a stall once per rotation. 22.12.4.5 DNC This has a 2.4 bits/cycle bandwidth requirement. Each access will see the DIU stall of 18 cycles. 2.4 bits/cycle 25 corresponds to an access every 106 cycles within a 256 cycle rotation. So to allow for DIU latency, an access is needed every 106 -18 or 88 cycles. This is a bandwidth of 2.9 bits/cycle, requiring 3 timeslots in the rotation. 22.12.4.6 CDU The JPEG decoder produces 8 bits/cycle. Peak CDUR[ead] bandwidth is 4 bits/cycle (SF=4), peak 30 CDUW[rite] bandwidth is 4 bits/cycle (SF=4). both with 1.5 DRAM buffering. The CDU(R) does a DIU read every 64 cycles at scale factor 4 with 1.5 DRAM buffering. The delay in being serviced by the DIU could be read circuit latency (10) + refresh (3) + extra CDU(W) cycles (6) = 19 cycles. The JPEG decoder can consume each 256 bits of DIU-supplied data at 8 bits/cycle, i.e. in 32 cycles. If the DIU is 19 cycles late (due to latency) in supplying the read data then the JPEG decoder will have finished 35 processing the read data 32 + 19 = 49 cycles after the DIU access. This is 64 - 49 = 15 cycles in advance of the next read. This 15 cycles is the upper limit on how much the DIU read service can further be delayed, WO 2005/120835 PCT/AU2004/000706 671 without causing a stall. Given this margin, a stall on the read side will not occur. This margin means that the CDU can cope with not exactly evenly spaced slot distributions. On the write side, for scale factor 4, the access pattern is a DIU writes every 64 cycles with 1.5 DRAM buffering. The JPEG decoder runs at 8 bits cycle and consumes 256 bits in 32 cycles. The CDU will not stall 5 if the JPEG decode time (32) + DIU stall (19) < 64, which is true. The extra margin means that the CDU can cope with not exactly evenly spaced slot distributions. 22.13 CPU DRAM ACCESS PERFORMANCE The CPU's share of the timeslots can be specified in terms of guaranteed bandwidth and average bandwidth allocations. 10 The CPU's access rate to memory depends on " the CPU read access latency i.e. the time between the CPU making a request to the DIU and receiving the read data back from the DIU. " how often it can get access to DIU timeslots. Table 110 estimated the CPU read latency as 5 cycles. 15 How often the CPU can get access to DIU timeslots depends on the access type. This is summarised in Table 121. Table 121. CPU DRAM access performance Accss ne mi CPo DR AMNoe CPU Pre- 6 cycles Lower bound CPU can access every timeslot. access (guaranteed bandwidth) is 192 MHz / 6 = 32 MHz Fractional 4 or 6 Lower bound CPU accesses precede a fraction N of CPU cycles (guaranteed bandwidth) timeslots Pre-access is where N = C/T. (192 MHz * N / P) C = CPUPreAccessTimeslots T = CPUTotalTimeslots P = (6*C + 4*(T-C)) / T In both CPU Pre-access and Fractional CPU Pre-access modes, if the CPU is not requesting the timeslots will have a duration of 3 or 4 cycles depending on whether the current access and preceding access are both to the 20 shared read bus. This will mean that the timeslot rotation will run faster and more bandwidth is available. If the CPU runs out of its instruction cache then instruction fetch performance is only limited by the on-chip bus protocol. If data resides in the data cache then 192 MHz performance is achieved. Accessing memory mapped registers, PSS or ROM with a 3 cycle bus protocol (address cycle + data cycle) gives 64 MHz performance.
WO 2005/120835 PCT/AU2004/000706 672 Due to the action of CPU caching, some bandwidth limiting of the CPU in Fractional CPU Pre-access mode is expected to have little or no impact on the overall CPU performance. 22.14 IMPLEMENTATION The DRAM Interface Unit (DIU) is partitioned into 2 logical blocks to facilitate design and verification. 5 a. The DRAM Arbitration Unit (DAU) which interfaces with the SoPEC DIU requesters. b. The DRAM Controller Unit (DCU) which accesses the embedded DRAM. The basic principle in design of the DIU is to ensure that the eDRAM is accessed at its maximum rate while keeping the CPU read access latency as low as possible. 10 The DCU is designed to interface with single bank 20 Mbit IBM Cu-Il embedded DRAM performing random accesses every 3 cycles. Page mode burst of 4 write accesses, associated with the CDU, are also supported. The DAU is designed to support interleaved accesses allowing the DRAM to be accessed every 3 cycles where back-to-back accesses do not occur over the shared 64-bit read data bus. 15 22.14.1 DIU Partition 22.14.2 Definition of DCU 10 Table 122. DCU Interface W.~~ 'M Clocks and Resets Pclk 1 In SoPEC Functional clock daudcuresetn 1 In Active-low, synchronous reset in pc/k domain. Incorporates DAU hard and soft resets. Inputs from DAU daudcumsn2stall 1 In Signal indicating from DAU Arbitration Logic which when asserted stalls DCU in MSN2 state. dau-dcuadr[21:5] 17 In Signal indicating the address for the DRAM access. This is a 256-bit aligned DRAM address. daudcurwn 1 In Signal indicating the direction for the DRAM access (1=read, O=write). daudcucduwpage 1 In Signal indicating if access is a CDU write page mode access (1=CDU page mode, 0=not CDU page mode). dau-dcu-refresh 1 In Signal indicating that a refresh command is to be issued. If asserted dau_dcu._adr, dau_dcu_rwn and dau_dcu_cduwpage are ignored. dau_dcu_wdata 256 In 256-bit write data to DCU WO 2005/120835 PCT/AU2004/000706 673 daudcuwmask 32 In Byte encoded write data mask for 256-bit dau -dcu wdata to DCU Polarity: A "1" in a bit field of daudcuwmask means that the corresponding byte in the 256-bit dau_dcu_wdata jg written to DRAM. Outputs to DAU dcudauadv 1 Ou Signal indicating to DAU to supply next command to t DCU dcudauwadv 1 Ou Signal indicating to DAU to initiate next non-CPU write t dcudaurefreshcompi 1 Ou Signal indicating that the DCU has completed a ete t refresh. dcudaurdata 256 Ou 256-bit read data from DCU. t dcudaurvalid 1 Ou Signal indicating valid read data on dcu daurdata. t 22.14.2 22.14.3 DRAM access types The DRAM access types used in SoPEC are summarised in Table 123. For a refresh operation the DRAM generates the address internally. Table 123. SoPEC DRAM access types Read Random 256-bit read Write Random 256-bit write with byte write masking Page mode write for burst of 4 256-bit words with byte write masking Refresh Single refresh 5 22.14.4 Constructing the 20 Mbit DRAM from two 10 Mbit instances The 20 Mbit DRAM is constructed from two 10 Mbit instances. The address ranges of the two instances are shown in Table 124. Table 124. Address ranges of the two 10 Mbit instances In the 20 Mbit DRAM r adess-~wrdadrs Instance First word in 00000 0 0000 0000 0000 0000 lower 10 Mbit InstanceO Last word in lower 09FFF 0 1001 1111 1111 1111 10 Mbit WO 2005/120835 PCT/AU2004/000706 674 Instance First word in 0A000 0 1010 0000 0000 0000 upper 10 Mbit Instance Last word in 13FFF 1 0011 1111 1111 1111 upper 10 Mbit There are separate macro select signals, instOMSN and inst1_MSN, for each instance and separate dataout busses instODO and inst1_DO, which are multiplexed in the DCU. Apart from these signals both instances share the DRAM output pins of the DCU. 5 The DRAM Arbitration Unit (DAU) generates a 17 bit address, dau_dcu_adr[21:5], sufficient to address all 256-bit words in the 20 Mbit DRAM. The upper 4 bits are used to select between the two memory instances by gating their MSN pins. If instance is selected then the lower 16-bits are translated to map into the 10 Mbit range of that instance. The multiplexing and address translation rules are shown in Table 125. In the case that the DAU issues a refresh, indicated by dau dcu refresh, then both macros are selected. The 10 other control signals Table 125. Instance selection and address translation 0 it <00Intnce MnSN 1S A[15:0 =Srss _daudu-adr[2__dN _ N dautdcuadr[20:5] >= 0101 Instancel 1 MSN A[15:0] = dau-dcu adr[21:5] hAO00 1 - Instance0 MSN MSN and Instancel daudcu_adr[21:5], daudcurwn and dau dcucduwpage are ignored. The instance selection and address translation logic is shown in Figure 115. 15 The address translation and instance decode logic also increments the address presented to the DRAM in the case of a page mode write. Pseudo code is given below. if risingedge(daudcuvalid) then //capture the address from the DAU 20 next-cmdadr[21:5] = dau-dcu-adr[21:5] elsif pagemodeadr_inc == 1 then //increment the address nextcmdadr[21:5] = cmdadr[21:5] + 1 else 25 nextcmdadr(21:5] = cmdadr[21:5] if risingedge(daudcuvalid) then //capture the address from the DAU adrvar[21:5]:= dau_dcuadr[21:5] 30 else WO 2005/120835 PCT/AU2004/000706 675 adrvar[21:5]:= cmdadr(21:5] if adrvar[21:17] < 01010 then //choose instance 5 instancesel = 0 A[15:0] = adr-var[20:5] else //choose instance instance-sel = 1 10 A[15:0] = adr-var[21:5] - hAO00 Pseudo code for the select logic, SELO, for DRAM Instance0 is given below. instancec0 selected or refresh if instance-sel == 0 OR dau-dcu-refresh == 1 then 15 instOMSN = MSN else inst0_MSN = 1 Pseudo code for the select logic, SEL1, for DRAM Instance 1 is given below. //instancel selected or refresh 20 if instance-sel == 1 OR dau-dcurefresh == 1 then inst1_MSN = MSN else inst1_MSN = 1 During a random read, the read data is returned, on dcudaurdata, after time Tace, the random access time, 25 which varies between 3 and 8 ns (see Table 127). To avoid any metastability issues the read data must be captured by a flip-flop which is enabled 2 pclk cycles or 10.4 ns after the DRAM access has been started. The DCU generates the enable signal dcu_dau_rvalid to capture dcudaurdata. The byte write mask dau_dcuwmask[31:0J must be expanded to the bit write mask bitwritemask[255:0] needed by the DRAM. 30 22.14.5 DAU-DCU interface description The DCU asserts dcu dauadv in the MSN2 state to indicate to the DAU to supply the next command. dcudauadv causes the DAU to perform arbitration in the MSN2 cycle. The resulting command is available to the DCU in the following cycle, the RST state. The timing is shown in Figure 116. The command to the DRAM must be valid in the RST and MSN1 states, or at least meet the hold time requirement to the MSN -35 falling edge at the start of the MSN1 state. Note that the DAU issues a valid arbitration result following every dcudauadv pulse. If no unit is requesting DRAM access, then a fall-back refresh request will be issued. When daudcu refresh is asserted the operation is a refresh and daudcuadr, daudcu rwn and daudcu cduwpage are ignored. The DCU generates a second signal, dcu dauwadv, which is asserted in the RST state. This indicates to the 40 DAU that it can perform arbitration in advance for non-CPU writes. The reason for performing arbitration in advance for non-CPU writes is explained in "Command Multiplexor Sub-block". The DCU state-machine can stall in the MSN2 state when the signal daudcu_msn2stall is asserted by the DAU Arbitration Logic, The states of the DCU state-machine are summarised in Table 126.
WO 2005/120835 PCT/AU2004/000706 676 Table 126. States of the DCU state-machine RST Restore state MSN1 Macro select state 1 MSN2 Macro select state 2 WO 2005/120835 PCT/AU2004/000706 677 22.14.6 DCU state machines The IBM DRAM has a simple SRAM like interface. The DRAM is accessed as a single bank. The state machine to access the DRAM is shown in Figure 117. The signal pagemodeadrinc is exported from the DCU as dcudaucduwaccept. dcu-daucduwaccept tells 5 the DAU to supply the next write data to the DRAM 22.14.7 CU-11 DRAM timing diagrams The IBM Cu-I1 embedded DRAM datasheet Table 127 shows the timing parameters which must be obeyed for the IBM embedded DRAM. Table 127. 1.5 V Cu-1I DRAM a.c. parameters T. Input setup to MVSN/PGN 1 -ns Th Input hold to MSN/PGN 2 - ns T.. Random access time 3 8 ns Ta MSN active time 8 100k ns T. MSN restore time 4 - ns T, Random R/W cycle time 12 - ns T, Refresh cycle time 12 - ns T Page mode access time 1 3.9 ns T, PGN active time 1.6 - ns TP, PGN restore time 1.6 - ns TC PGN cycle time 4 - ns Tm, MSN to PGN restore 6 - ns delay TacP MSN active for page 12 - ns mode Tr Refresh period - 3.2 ms T Page active to MSN 4 - ns restore 10 The IBM DRAM is asynchronous. In SoPEC it interfaces to signals clocked on pclk. The following timing diagrams show how the timing parameters in Table 127 are satisfied in SoPEC.
WO 2005/120835 PCT/AU2004/000706 678 22.14.8 Definition of DAU 10 Table 128. DAU interface Port Name Pis1/0 Description Clocks and Resets Pclk 1 In SoPEC Functional clock prstn 1 In Active-low, synchronous reset in pclk domain daudcureset n 1 Out Active-low, synchronous reset in pc/k domain. This reset signal, exported to the DCU, incorporates the locally captured DAU version of -hard reset (prst n) and the soft reset configuration register bit "Reset'. CPU Interface cpu-adr[21:2] 20 In CPU address bus for DRAM reads and configuration register read/write access. The former uses address bits [21:5], while the latter uses bits [10:2]. DRAM addresses therefore cannot cross a 256-bit word boundary. cpudataout 32 In Data bus from the CPU for configuration register writes. Not used for DRAM accesses. diu-cpu-data 32 Out Configuration, status and debug read data bus to the CPU diu-cpu-debug-valid 1 Out Signal indicating the data on the diucpu_data bus is valid debug data. cpu_rwn 1 In Common read/not-write signal from the CPU cpuacode 2 In CPU access code signals. cpu acode[0] - Program (0) / Data (1) access cpu-acode[1] - User (0) / Supervisor (1) access The DAU will only allow supervisor mode accesses to data space. cpudiusel 1 In Block select from the CPU. When cpudiusel is high, both cpuLadr and cpu_dataout are valid for configuration register accesses.
WO 2005/120835 PCT/AU2004/000706 679 diu-cpu-rdy 1 Out Ready signal to the CPU. When diucpurdy is high it indicates the last cycle of the access. For a write cycle this means cptdataout has been registered by the block and for a read cycle this means the data on diucpu_data is valid. diu.cpu-berr 1 Out Bus error signal to the CPU indicating an invalid access. cpudiuwdatavalid 1 In Write enable for the CPU posted write buffer. Also confirms that the CPU write data, address and mask are valid. diu-cpu-writejrdy 1 Out Flag indicating that the CPU posted write buffer is empty. cpudiuwdata 128 In CPU write data which is loaded into the posted write buffer. cpu diuwadr[21:4] 18 In 128-bit aligned CPU write address for posted write. cpudiuwmask[15:0] 16 In Byte enables for 128-bit CPU posted write. cpu-diu-rreq 1 In Request by the CPU to read from DRAM. When asserted, indicates that cpuadr refers to a DRAM address. DIU Read Interface to SoPEC Units <unit>_diurreq 1 In SoPEC unit requests DRAM read. A read request must be accompanied by a valid read address. <unit>_diu_radr[21:5] 17 In Read address to DIU 17 bits wide (256-bit aligned word). Note: "<unit>" refers to non-CPU requesters only. CPU read addresses are provided via "cpuad'. diu_<unit>_rack 1 Out Acknowledge from DIU that read request has been accepted and new read address can be placed on <unit>_diu radr diudata 64 Out Data from DIU to SoPEC Units except CPU. First 64-bits is bits 63:0 of 256 bit word Second 64-bits is bits 127:64 of 256 bit word Third 64-bits is bits 191:128 of 256 bit word Fourth 64-bits is bits 255:192 of 256 bit word WO 2005/120835 PCT/AU2004/000706 680 dramcpudata 256 Out 256-bit data from DRAM to CPU. diu<unit>frvalid 1 Out Signal from DIU telling SoPEC Unit that valid read data is on the diudata bus DIU Write Interface to SoPEC Units <unit>_diu_wreq 1 In SoPEC unit requests DRAM write. A write request must be accompanied by a valid write address. Note: "<unit>" refers to non-CPU requesters only. <unit>_diu_wadr[21:5] 17 In Write address to DIU except CPU, CDU 17 bits wide (256-bit aligned word) Note: "<unit>" refers to non-CPU requesters, excluding the CDU. uhudiuwmask[7:0] 8 In Byte write enables applicable to a given 64-bit quarter- word transferred from the UHU. Note that different mask values are used with each quarter-word. ududiuwmask[7:0] 8 In Byte write enables applicable to a given 64-bit quarter- word transferred from the UDU. Note that different mask values are used with each quarter-word. cdudiuwadr[21:3] 19 In CDU Write address to DIU 19 bits wide (64-bit aligned word) Addresses cannot cross a 256-bit word DRAM boundary. diu_<unit>_wack 1 Out Acknowledge from DIU that write request has been accepted and new write address can be placed on <unit>_diuwadr <unit>_diu_data[63:0] 64 In Data from SoPEC Unit to DIU except CPU. First 64-bits is bits 63:0 of 256 bit word Second 64-bits is bits 127:64 of 256 bit word Third 64-bits is bits 191:128 of 256 bit word Fourth 64-bits is bits 255:192 of 256 bit word Note: "<unit>" refers to non-CPU requesters only. <unit>_diu_wvalid 1 In Signal from SoPEC Unit indicating that data on <unit>_diudata is valid. Note: "<unit>" refers to non-CPU requesters only.
WO 2005/120835 PCT/AU2004/000706 681 Outputs to DCU daudcumsn2stall 1 Out Signal indicating from DAU Arbitration Logic which when de asserted stalls DCU in MSN2 state. dau-dcu-adr[21:5] 17 Out Signal indicating the address for the DRAM access. This is a 256 bit aligned DRAM address. daudcurwn 1 Out Signal indicating the direction for the DRAM access (1=read, O=write). daudcucduwpage 1 Out Signal indicating if access is a CDU write page mode access (1=CDU page mode, 0=not CDU page mode). daudcurefresh 1 Out Signal indicating that a refresh command is to be issued. If asserted daudcucmdadr, dau_dcurwn and dau dcu cduwpage are ignored. dau_dcu_wdata 256 Out 256-bit write data to DCU dau dcu wmask 32 Out Byte-encoded write data mask for 256-bit daudcuwdata to DCU Polarity: A "1" in a bit field of dau dcu wmask means that the corresponding byte in the 256-bit daudcu wdata ja written to DRAM. dau_dcu_disableupper_dram_m 1 Out Signal which disables all inputs to acro the upper 10 Mbit macro, including refresh. Inputs from DCU dcu dau adv 1 In Signal indicating to DAU to supply next command to DCU dcu dau wadv 1 In Signal indicating to DAU to initiate next non-CPU write dcu_daurefreshcomplete 1 In Signal indicating that the DCU has completed a refresh. dcudaurdata 256 In 256-bit read data from DCU. dcu dau valid 1 In Signal indicating valid read data on dcudaurdata. The CPU subsystem bus interface is described in more detail in Section 11.4.3. The DAU block will only allow supervisor-mode accesses to update its configuration registers (i.e. cpuacode[1:O] = b11). All other accesses will result in diucpuberr being asserted.
WO 2005/120835 PCT/AU2004/000706 682 22.14.9 DAU Configuration Registers Table 129. DAU configuration registers a reset of the DIU. This register can be read to indicate the reset state: 0 - reset in progress 1 - reset not in progress Refresh 0x04 RefreshPeriod 9 0x076 Refresh controller. When set to 0 refresh is off, otherwise the value indicates the number of cycles, less one, between each refresh. [Note that for a system clock frequency of 192 MHz, a value exceeding 0x76 (indicating a 119-cycle refresh period) should n=I be programmed, or the DRAM will malfunction.] [0x76 = d118 or a refresh occurs every 119 cycles. This allows any delays on issuing the the refresh for a particular row due e.g. to CDUW, CPU preaccess to be caught up.] Timeslot allocation and control 0x08 NumMainTimeslots 6 Ox01 Number of main timeslots (1 64) less one Ox0C CPUPreAccessTimeslots 4 Ox0 (CPUPreAccessTimeslots + 1) main slots out of a total of (CPUTotalTimeslots + 1) are preceded by a CPU access. OxI 0 CPUTotalTimeslots 4 Ox0 (CPUPreAccessTimeslots + 1) main slots out of a total of (CPUTotalTimeslots + 1) are preceded by a CPU access. Ox1 00- MainTimeslot[63:0] 64x5 [63:1][3:0] Programmable main timeslots OxIFC = Ox01 (up to 64 main timeslots). [0][3:0] = Ox1 B 0x200 ReadRoundRobinLevel 14 Ox0000 For each read requester plus refresh 0 = level of round-robin 1 = level2 of round-robin The bit order is defined in Table 131.
WO 2005/120835 PCT/AU2004/000706 683 0x204 EnableCPURoundRobin 1 Ox1 Allows the CPU to participate in the unused read round robin scheme. If disabled, the shared CPU/refresh round robin position is dedicated solely to refresh. Ox208 RotationSync 1 0x1 Writing 0, followed by 1 to this bit allows the timeslot rotation to advance on a cycle basis which can be determined by the CPU. Ox2OC minNonCPUReadAdr[21:10] 12 0x200000 12 MSBs of lowest DRAM address which may be read by non-CPU requesters. Ox210 minDWUWriteAdr[21:10] 12 0x200000 12 MSBs of lowest DRAM address which may be written to by the DWU. Ox214 minNonCPUWriteAdr[21:10] 12 0x200000 12 MSBs of lowest DRAM address which may be written to by non-CPU requesters other than the DWU. Ox218 DisableUpperDramMacro 1 Ox0 When asserted, no writes are allowed to the upper DRAM 10 Mbit macro. The macro is not refreshed and reads to its address space return all zeros. Note: Any writes to the upper macro which have been pre arbitrated/posted, but not yet executed in advance of this bit being activated, will be honoured. Ox21 C StickyAdrReset 1 Ox0 When a "1" is written to this address, the stickyinvalid_dram_adt" field of "arbitrationHistory is cleared. The "stickyAdrReser register reads back always as all zeros. Debug WO 2005/120835 PCT/AU2004/000706 684 0x300 debugSelect[1 1:2] 10 0x304 Debug address select. Indicates the address of the register to report on the diLLcpuL..data bus when it is not otherwise being used. When this signal carries debug information the signal diucpudebug-valid will be asserted. Note: For traceability reasons, any registers read using "debugSelect" have the following fields superimposed at their MSB end, provided the bits concerned are not otherwise assigned: Bit 31:27 = arb sel[4:0] ** Bit 26:24 = access-type[2:0 ** NB: A unique identifier code, OxOC, is substituted in this "arbse/' field during the first rotation sync preamble cycle, to allow easy determination of where an arbitration sequence begins. Debug: arbitration and performance Ox304 ArbitrationHistory 26 - Bit 0 = sticky-invalid-dramadr Bit 1 = stickyback2back.noncpu_ write Bit 2 = back2backnon_cpu-write Bit 3 = arb-gnt Bit 4 = pre-arb-gnt Bit 9:5 = arbsel Bit 14:10 = write sel Bit 20:15 = arb-historyimeslot; Bit 23:21 = accesstype Bit 24 = rotation-sync Bit 26:25 = rotationstate See Section 22.14.9.2 DIU Debug for a description of the fields. Read only register.
WO 2005/120835 PCT/AU2004/000706 685 0x308 DIUReadPerformance 22 - Bit 0 = cpu-diu-rreq Bit 1 = uhudiu-rreq Bit 2 = udu_diu_rreq Bit 3 = cdu-diu-rreq Bit 4 = cfu_diu_rreq Bit 5 = lbddiu-rreq Bit 6 = sfu_diu_rreq Bit 7 = tddiurreq Bit 8 = tfs-diu-rreq Bit 9 = hcudiu-rreq Bit 10 = dncdiu-rreq Bit 11 = Ilu_diu-rreq Bit 12 = pcu-diu-rreq Bit 13 = mmii_diu-rreq Bit 18:14 = read-sel[4:0] Bit 19 = readcomplete Bit 20 = refresh-req Bit 21 = dcudaurefreshcomplete See Section 22.14.9.2 DIU Debug for a description of the fields. Read only register. Ox30C DIUWritePerformance - Bit 0 = NOT diu-cpu write..rdy Bit 1 = uhu diuwreq Bit 2 = uhu diu..wreq Bit 3 = cdu diu_wreq Bit 4 = sfudiu_wreq Bit 5 = dwu diu wreq Bit 6 = mmi_diu_wreq Bit 11:7 = write sel[4:0] Bit 12 = write-complete Bit 13 = refreshreq Bit 14 = dcu-dau-refreshcomplete See Section 22.14.9.2 DIU Debug for a description of the fields. Read only register. Debug DIU read requesters interface signals 0x310 CPUReadInterface 25 - Bit 0 = cpu-diu-rreq Bit 20:1 = cpu-adr[21:2] Bit 21 = diuscpurack Bit 22 = diu.cpurvalid Read only register. 0x314 UHUReadinterface 20 - Bit 0 = uhudiu-rreq Bit 17:1 = uhu-diu-radr[21:5] Bit 18 = diuuhurack Bit 19 = diuuhurvalid Read only register. Ox318 UDUReadInterface 20 - Bit 0 = ududiujrreq Bit 17:1 = udu-diu-radr[21:5] Bit 18 = diu udu rack Bit 19 = diuudu-rvalid Read only register. Ox3lC CDUReadInterface 20 - Bit 0 = cdu-diu-rreq Bit 17:1 = cdu diu-radr[21:5] Bit 18 = diu cdu rack Bit 19 = diucdurvalid Read only register.
WO 2005/120835 PCT/AU2004/000706 686 0x320 CFUReadInterface 20 - Bit 0 = cfu-diu-rreq Bit 17:1 = cfu-diu-radr[21:5] Bit 18 = diu-cfurack Bit 19 = diucfurvalid Read only register. Ox324 LBDReadlnterface 20 - Bit 0 = lbd-diu-rreq Bit 17:1 = lbddiu-radr[21:5] Bit 18 = diu_Ibdrack Bit 19 = diuIbd-rvalid Read only register. Ox328 SFUReadInterface 20 - Bit 0 = sfudiu-rreq Bit 17:1 = sfudiu-radr[21:5] Bit 18 = diu sfu rack Bit 19 = diu-sfurvalid Read only register. Ox32C TDReadinterface 20 - Bit 0 = tddiurreq Bit 17:1 = td_diu_radr[21:5] Bit 18 = diu_td_rack Bit 19 = diutdrvalid Read only register. Ox330 TFSReadinterface 20 - Bit 0 = tfsdiu-rreq Bit 17:1 = tfs_diu_radr[21:5] Bit 18 = diutfsrack Bit 19 = diufs_rvalid Read only register. Ox334 HCUReadinterface 20 - Bit 0 = hcudiu-rreq Bit 17:1 = hcu diu-radr[21:5] Bit 18 = diuhcurack Bit 19 = diuhcurvalid Read only register. 0x338 DNCReadlnterface 20 - Bit 0 = dnc_diu_rreq Bit 17:1 = dnc-diu-radr[21:5] Bit 18 = diu_dnc_rack Bit 19 = diudnc-rvalid Read only register. Ox33C LLUReadInterface 20 - Bit 0 = lludiu-rreq Bit 17:1 = lluu-diu-radr[21:5] Bit 18 = diulu-rack Bit 19 = diullurvalid Read only register. Ox340 PCUReadinterface 20 - Bit 0 = pcu-diu-rreq Bit 17:1 = pcu-diu-radr[21:5] Bit 18 = diu-pcurack Bit 19 = diujpcurvalid Read only register. Ox344 MMIReadInterface 20 Bit 0 = mmi_diurreq Bit 17:1 = mmi-diu-radr[21:5] Bit 18 = diummirack Bit 19 = diummirvalid Read only register. Debug DIU write requesters interface signals Ox348 CPUWritelnterface 20 - Bit 0 = cpudiu_wdatavalid Bit 1 = diucpu-writejrdy Bit 19:2 = cpudiu-wadr[21:4] Read only register.
WO 2005/120835 PCT/AU2004/000706 687 0x34C UHUWritelnterface 20 - Bit 0 = uhu_diuwreq Bit 17:1 = uhudiu-wadr[21:5] Bit 18 = diu_uhu_wack Bit 19 = uhu_diu_wvalid Bit 27:20 = uhudiuwmask Read only register. Ox350 UDUWritelnterface 20 - Bit 0 = udu_diuwreq Bit 17:1 = ududiu-wadr[21:5] Bit 18 = diuuduwack Bit 19 = udu diu wvalid Bit 27:20 = ududiuwmask Read only register. Ox354 CDUWritelnterface 22 - Bit 0 = cdudiu-wreq Bit 19:1 = cdu_diu-wadr[21:3] Bit 20 = diu_cdu_wack Bit 21 = cdu diu wvalid Read only register. Ox358 SFUWritelnterface 20 - Bit 0 = sfu-diu wreq Bit 17:1 = sfudiu-wadr[21:5] Bit 18 = diusfuwack Bit 19 = sfu_diu_wvalid Read only register. Ox35C DWUWritelnterface 20 - Bit 0 = dwu_diuwreq Bit 17:1 = dwudiuwadr[21:5] Bit 18 = diudwu_wack Bit 19 = dwu-diuwvalid Read only register. Ox360 MMlWritelnterface 20 - Bit 0 = mmii_diu wreq Bit 17:1 = mmi_diu_wadr[21:5] Bit 18 = diu mmiwack Bit 19 = mmi_diuwvalid Read only register. Debug DAU-DCU interface signals 0x364 DAU-DCUlnterface 25 - Bit 16:0 = daudcu-adr[2l:5] Bit 17 = daudcurwn Bit 18 = dau_dcu_cduwpage Bit 19 = daudcurefresh Bit 20 = dau dcu msn2stall Bit 21 = dcu dau adv Bit 22 = dcu_dau_wadv Bit 23 = dcudaurefreshcomplete Bit 24 = dcudaurvalid Bit 25 = daudcudisable-upper-dra mmacro Read only register. Each main timeslot can be assigned a SoPEC DIU requestor according to Table 130. Table 130. SoPEC DIU requester encoding for main timeslots. UflwNn~ WO 2005/120835 PCT/AU2004/000706 688 Write UHU(W) b0_0000 Ox00 UDU(W) b0_0001 Ox01 CDU(W) b0_0010 0x02 SFU(W) b0_0011 0x03 DWU b0_0100 0x04 MMI(W) b0_0101 0x05 Read UHU(R) b1_0000 0x10 UDU(R) bl_0001 Ox11 CDU(R) bl_001 0x12 CFU b1_0011 0x13 LBD b_0100 0x14 SFU(R) b1_0101 0x15 TE(TD) b1 0110 0x16 TE(TFS) b1_0111 0x17 HCU b1_1000 0x18 DNC b1_1001 0x19 LLU b1_1010 Ox1A PCU b1_1011 Ox1B MMI b1_1100 Ox1C ReadRoundRobinLevel and ReadRoundRobinEnable registers are encoded in the bit order defined in Table 131. Table 131. Read round-robin registers bit order UHU(R) 0 UDU(R) 1 CDU(R) 2 CFU 3 LBD 4 SFU(R) 5 TE(TD) 6 TE(TFS) 7 WO 2005/120835 PCT/AU2004/000706 689 HCU 8 DNC 9 LLU 10 PCU 11 MMI 12 CPU, 13 Refresh 22.14.9.1 22.14.9.1 Configuration register reset state The RefreshPeriod configuration register has a reset value of 0x076 which ensures that a refresh will occur every 119 cycles and the contents of the DRAM will remain valid. 5 The CPUPreAccessTimeslots and CPUTotalTimeslots configuration registers both have a reset value of OxO. Matching values in these two registers means that every slot has a CPU pre-access. NumMainTimeslots is reset to Ox1, so there are just 2 main timeslots in the rotation initially. These slots alternate between UDU writes and PCU reads, as defined by the reset value of MainTimeslot[63:0], thus respecting at reset time the general rule that adjacent non-CPU writes are not permitted. 10 The first access issued by the DIU after reset will be a refresh. 22.14.9.2 DIU Debug External visibility of the DIU must be provided for debug purposes. To facilitate this debug registers are added to the DIU address space. The DIU CPU system data bus diu _cpudata[31:0] returns configuration and status register information to 15 the CPU. When a configuration or status register is not being read by the CPU debug data is returned on diucpudata[31:0] instead. An accompanying active high diucpudebugvalid signal is used to indicate when the data bus contains valid debug data. The DIU features a DebugSelect register that controls a local multiplexor to determine which register is output on diu _cpudata[31:0]. 20 For traceability reasons, any registers read using "debugSelect" have the following fields superimposed at their MSB end, provided the bits concerned are not otherwise assigned: Bit 31:27 = arbsel[4:0] Bit 26:24 = accesstype[2:0] Note that a unique identifier code, "OxOC", is substituted in this "arbsel" field during the first rotation sync 25 preamble cycle, to allow easy determination of where an arbitration sequence begins. Three kinds of debug information are gathered: a. The order and access type of DIU requesters winning arbitration. This information can be obtained by observing the signals in the ArbitrationHistory debug register at 30 DIU Base+0x304 described in Table 132.
WO 2005/120835 PCT/AU2004/000706 690 Table 132. ArbitrationHistory debug register description, DIU_base+0x304 stickyinvaliddramadr 1 Sticky bit which indicates an attempted DRAM access (CPU or non-CPU) with an invalid address. Cleared by reset or by an explicit write of "1" by the CPU to "stickyAdrReset". sticky_back2back-non_cpu-write 1 Sticky version of "back2back_non_cpu-write", cleared on reset. back2back_non_cpu_write 1 Cycle-by-cycle indicator of attempted illegal back-to back non-CPU write. (Recall from section 20.7.2.3 on page 212 that the second write of any such pair is disregarded and re-allocated via the unused read round-robin scheme.) arb-gnt 1 Signal lasting 1 cycle which is asserted in the cycle following a main arbitration. pre-arb-gnt 1 Signal lasting 1 cycle which is asserted in the cycle following a pre-arbitration award. arbsel 5 Signal indicating which requesting SoPEC Unit has won arbitration. Encoding is described in Table 133. Refresh winning arbitration is indicated by access-type. writesel 5 Signal indicating which requesting SoPEC Unit has won pre-arbitration. Only valid when preLarb-gnt is asserted. Encoding is described in Table 133. timeslotnumber 6 Signal indicating which main timeslot is either currently being serviced, or about to be serviced. The latter case applies where a main slot is pre empted by a CPU pre-access or a scheduled refresh. accesstype 3 Signal indicating the origin of the winning arbitration 000 = Standard CPU pre-access. 001 = Scheduled refresh. 010 = Scheduled non-CPU timeslot. 011 = CPU access via unused read slot, re-allocated by round robin. 100 = Non-CPU write via unused write slot, re allocated at pre-arbitration. 101 = Non-CPU read via unused read slot, re allocated by round robin. 110 = Refresh via unused read/write slot, re allocated by round robin. 111 = CPU / Refresh access due to RotationSync = 0. rotation-sync 1 Current value of the RotationSync configuration bit.
WO 2005/120835 PCT/AU2004/000706 691 rotation-state 2 These bits indicate the current status of pre arbitration and main timeslot rotation, as a result of the RotationSync setting. 00 = Pre-arb enabled, rotation enabled. 01 = Pre-arb disabled, rotation enabled. 10 = Pre-arb disabled, rotation disabled. 11 = Pre-arb enabled, rotation disabled. 00 is the normal functional setting when RotationSync is 1. 01 indicates that pre-arbitration has halted at the end of its rotation because of RotationSync having been cleared. However the main arbitration has yet to finish its current rotation. 10 indicates that both pre-arb and the main rotation have halted, due to RotationSync being 0 and that only CPU accesses and refreshes are allowed. 11 indicates that RotationSync has just been changed from 0 to 1 and that pre-arbitration is being given a head start to look ahead for non-CPU writes, in advance of the main rotation starting up again. Table 133. arbsel, read sel and writesel encoding Write UHU(W) b0_0000 0x00 UDU(W) b0_0001 Ox01 CDU(W) b0_0010 0x02 SFU(W) b0_0011 0x03 DWU b0_0100 0x04 MM(W) bO_0101 Ox05 Read UHU(R) b1_0000 Ox10 UDU(R) b1_0001 Ox11 CDU(R) b1_0010 0x12 CFU b1_0011 0x13 LBD b1_0100 0x14 SFU(R) b1_0101 Ox15 TE(TD) b1_0110 0x16 TE(TFS) b1_0111 0x17 HCU b1_1000 Ox18 DNC b1_1001 0x19 WO 2005/120835 PCT/AU2004/000706 692 LLU b1_1010 Ox1A PCU b1_1011 Ox1B MMI(R) b1.1100 Ox1C Refresh Refresh 1_1101 Ox1D CPU CPU(R) b1_1111 Ox1F CPU(W) b0_1111 OxOF The encoding for arbsel is described in Table 133. b. The time between a DIU requester requesting an access and completing the access. 5 This information can be obtained by observing the signals in the DIUPerformance debug register at DIUBase+0x308 described in Table 134. The encoding for readsel and writesel is described in Table 133. The data collected from DIUPerformance can be post-processed to count the number of cycles between a unit requesting DIU access and the access being completed. Table 134. DlUReadPerformance debug register description, DIUbase+0x308 <unit>_diu-rreq 14 Signal indicating that SoPEC unit requests a DRAM read. readsel[4:0] 5 Signal indicating the SoPEC Unit for which the current read transaction is occurring. Encoding is described in Table 117. read-complete 1 Signal indicating that read transaction to SoPEC Unit indicated by readsel is complete i.e. that the last read data has been output by the DIU. refresh-req 1 Signal indicating that refresh has requested a DIU access. dcu.dau-refreshcomplete 1 Signal indicating that refresh has completed. 10 Table 135. DIUWritePerformance debug register description, DIU-base+x3OC Id rfre is ,Dsri o NOT diucpuwrite-rdy 1 Inverse of diu_cpu_writerdy. Indicates that a write has been posted by the CPU and is awaiting execution. <unit>_diu wreq 6 Signal indicating that SoPEC unit requests a DRAM write.
WO 2005/120835 PCT/AU2004/000706 693 write-sel{4:0] 5 Signal indicating the SoPEC Unit for which the current write transaction is occurring. Encoding is described in Table 133. write-complete 1 Signal indicating that write transaction to SoPEC Unit indicated by writesel is complete i.e. that the last write data has been transferred to the DIU. refresh-req 1 Signal indicating that refresh has requested a DIU access. dcudaurefresh-complete 1 Signal indicating that refresh has completed. c. Interface signals to DIU requestors and DAU-DCU interface. C. 5 All interface signals (with the exception of data buses at the interfaces between the DAU and DCU) and DIU write and read requestors can be monitored in debug mode by observing debug registers DIUBase+0x310 to DIU Base+0x360. 22.14.10 DRAM Arbitration Unit (DAU) 10 The DAU is shown in Figure 114. The DAU is composed of the following sub-blocks a. CPU Configuration and Arbitration Logic sub-block. b. Command Multiplexor sub-block. c. Read and Write Data Multiplexor sub-block. 15 The function of the DAU is to supply DRAM commands to the DCU. * The DCU requests a command from the DAU by asserting dcudau_adv. * The DAU Command Multiplexor requests the Arbitration Logic sub-block to arbitrate the next DRAM access. The Command Multiplexor passes dcudauadv as the re_arbitrate signal to the 20 Arbitration Logic sub-block. * If the RotationSync bit has been cleared, then the arbitration logic grants exclusive access to the CPU and scheduled refreshes. If the bit has been set, regular arbitration occurs. A detailed description of RotationSync is given in section 22.14.12.2.1 on page 408. * Until the Arbitration Logic has a valid result it stalls the DCU by asserting daudcu_msn2stall. The 25 Arbitration Logic then returns the selected arbitration winner to the Command Multiplexor which issues the command to the DRAM. The Arbitration Logic could stall for example if it selected a shared read bus access but the Read Multiplexor indicated it was busy by de-asserting read_cmd rdy[1]. * In the case of a read command the read data from the DRAM is multiplexed back to the read 30 requestor by the Read Multiplexor. In the case of a write operation the Write Multiplexor multiplexes the write data from the selected DIU write requestor to the DCU before the write WO 2005/120835 PCT/AU2004/000706 694 command can occur. If the write data is not available then the Command Multiplexor will keep daudcu valid de-asserted. This will stall the DCU until the write command is ready to be issued. * Arbitration for non-CPU writes occurs in advance. The DCU provides a signal dcu dau wadv which the Command Multiplexor issues to the Arbitrate Logic as rearbitrate wadv. If arbitration 5 is blocked by the Write Multiplexor being busy, as indicated by writecmd~rdy[1] being de asserted, then the Arbitration Logic will stall the DCU by asserting daudcu_msn2stall until the Write Multiplexor is ready. 22.14.10 Read Accesses The timing of a non-CPU DIU read access are shown in Figure 122. Note rearbitrate is asserted in the MSN2 10 state of the previous access. Note the fixed timing relationship between the read acknowledgment and the first rvalid for all non-CPU reads. This means that the second and any later reads in a back-to-back non-CPU sequence have their acknowledgments asserted one cycle later, i.e. in the "MSN1" DCU state. 15 The timing of a CPU DIU read access is shown in Figure 123. Note rearbitrate is asserted in the MSN2 state of the previous access. Some points can be noted from Figure 122 and Figure 123. DIU requests: 20 0 For non-CPU accesses the <unit> diu rreq signals are registered before the arbitration can occur. & For CPU accesses the cpudiurreq signal is not registered to reduce CPU DIU access latency. Arbitration occurs when the dcudauadv signal from the DCU is asserted. The DRAM address for the arbitration winner is available in the next cycle, the RST state of the DCU. The DRAM access starts in the MSN1 state of the DCU and completes in the RST state of the DCU. 25 Read data is available: e In the MSN2 cycle where it is output unregistered to the CPU e In the MSN2 cycle and registered in the DAU before being output in the next cycle to all other read requestors in order to ease timing. The DIU protocol is in fact: 30 * Pipelined i.e. the following transaction is initiated while the previous transfer is in progress. e Split transaction i.e. the transaction is split into independent address and data transfers. Some general points should be noted in the case of CPU accesses: e Since the CPU request is not registered in the DIU before arbitration, then the CPU must generate the request, route it to the DAU and complete arbitration all in 1 cycle. To facilitate this CPU 35 access is arbitrated late in the arbitration cycle (see Section 22.14.12.2). " Since the CPU read data is not registered in the DAU and CPU read data is available 8 ns after the start of the access then 2.4 ns are available for routing and any shallow logic before the CPU read data is captured by the CPU (see Section 22.14.4). The phases of CPU DIU read access are shown in Figure 124. This matches the timing shown in Table 110.
WO 2005/120835 PCT/AU2004/000706 695 22.14.10.2 Write Accesses CPU writes are posted into a 1-deep write buffer in the DIU and written to DRAM as shown below in Figure 125. The sequence of events is as follows: 5 e [1] The DIU signals that its buffer for CPU posted writes is empty (and has been for some time in the case shown). * [2] The CPU asserts cpudiu wdatavalid to enable a write to the DIU buffer and presents valid address, data and write mask. The CPU considers the write posted and thus complete in the cycle following [2] in the diagram below. 10 e [3] The DIU stores the address/data/mask in its buffer and indicates to the arbitration logic that a posted write wishes to participate in any upcoming arbitration. * [4] Provided the CPU still has a pre-access entitlement left, or is next in line for a round-robin award, a slot is arbitrated in favour of the posted write. Note that posted CPU writes have higher arbitration priority than simultaneous CPU reads. 15 e [5] The DRAM write occurs. e [6] The earliest that "diu cpuwriterdy" can be re-asserted in the "MSN1" state of the DRAM write. In the same cycle, having seen the re-assertion, the CPU can asynchronously turn around "cpu-diu wdatavalid" and enable a subsequent posted write, should it wish to do so. The timing of a non-CPU/non-CDU DIU write access is shown below in Figure 126. 20 Compared to a read access, write data is only available from the requester 4 cycles after the address. An extra cycle is used to ensure that data is first registered in the DAU, before being despatched to DRAM. As a result, writes are pre-arbitrated 5 cycles in advance of the main arbitration decision to actually write the data to memory. The diagram above shows the following sequence of events: 25 e [1] A non-CPU block signals a write request. * [2] A registered version of this is available to the DAU arbitration logic. e [3] Write pre-arbitration occurs in favour of the requester. * [4] A write acknowledgment is returned by the DIU. e [5] The pre-arbitration will only be upheld if the requester supplies 4 consecutive, write data 30 quarter-words, qualified by an asserted wvalid flag. e [6] Provided this has happened, the main arbitration logic is in a position at [6] to reconfirm the pre-arbitration decision. Note however that such reconfirmation may have to wait a further one or two DRAM accesses, if the write is pre-empted by a CPU pre-access and/or a scheduled refresh. * [7] This is the earliest that the write to DRAM can occur. 35 0 Note that neither the arbitration at [8] nor the pre-arbitration at [9] can award its respective slot to a non-CPU write, due to the ban on back-to-back accesses. The timing of a CDU DIU write access is shown overleaf in Figure 127.
WO 2005/120835 PCT/AU2004/000706 696 This is similar to a regular non-CPU write access, but uses page mode to carry out 4 consecutive DRAM writes to contiguous addresses. As a consequence, subsequent accesses are delayed by 6 cycles, as shown in the diagram. 22.14.10.3 Back-to-back CPU accesses 5 CPU accesses are pre-accesses in front of main timeslots i.e. every CPU access is normally separated by a main timeslot. However, if the EnableCPURoundRobin configuration bit is set then the CPU will win any unused timeslots which would have gone to Refresh. This allows for the possibility of back to back CPU accesses i.e. e unused round-robin CPU access followed by a CPU pre-access 10 * or pairs of unused round-robin CPU accesses. The CPU-DIU protocols described in Section 22.9 and Section 22.14.10 impose a restriction on back-to-back CPU accesses. Section 22.9.2 Read Protocol for CPU indicates that if the CPU is doing a read transaction it cannot issue another request until the read is complete i.e. until it has received a diucpu rvalid pulse. This 15 follows from the single AHIB master interface presented by LEON to the CPU block: a second transaction cannot start until at least the same cycle as the READY signal for the first transaction is received. The CPU block imposes the following restrictions: e The earliest a cpudiurreq can be issued is after a gap of I cycle following diucpurvalid. e The earliest a diu_cpu wdatavalid can be issued is after a gap of I cycle following diucpurvalid. 20 This leads to the following back-to-back CPU access behaviour. e READ-READ: accesses can happen separated by main timeslots - Require 2nd cpudiurreq asserted with maximum 2 cycles gap from 1st diucpu rvalid i.e. by next DIU MSN2 state since CPU reads are arbitrated in the DIU MSN2 state and 25 cpudiu rreq is a combinatorial input to the DAU arbitration logic. - Actual implementation is cpudiurreq can be issued after a gap of I cycle following diucpurvalid (meets requirement). e READ-WRITE: accesses can happen separated by main timeslots - Require cpu diuwdatavalid asserted with maximum 1 cycle gap from diu cpu valid i.e. by 30 next DIU MSN1 as CPU write must be accepted in posted write buffer before it can participate in the arbitration in the DIU MSN2 state. - Actual implementation is a gap of 1 cycle from diucpurvalid assertion to Cpu_diu_wdatavalid assertion (meets requirement). * WRITE-WRITE: accesses can happen in adjacent timeslots 35 - Require 2nd cpudiuwdatavalid asserted combinatorially with diucpu writerdy re assertion i.e. by next DIU MSN1 state as CPU write must be accepted in posted write buffer before it can participate in the arbitration in the DIU MSN2 state. - Actual implementation is identical. e WRITE-READ: accesses can happen in adjacent timeslots WO 2005/120835 PCT/AU2004/000706 697 - Require cpudiurreq asserted with maximum 1 cycle gap from diu cpuwrite rdy assertion i.e. by next DIU MSN2 state since CPU reads are arbitrated in the MSN2 state and cpudiurreq is a combinatorial input to the DAU arbitration logic. The minimum gap from Cpu_diu_wdatavalid assertion to diu_cpu write rdy assertion is 2 cycles. So the requirement 5 translates to a maximum gap of 3 cycles in cpudiurreq assertion from cpudiu wdatavalid assertion. - Actual implementation is a gap of 1 cycle from cpudiurreq assertion from cpu_diu_wdatavalid assertion (meets requirement). 10 22.14.11 Command Multiplexor Sub-block Table 136. Command Multiplexor Sub-block 10 Definition Clocks and Resets pclk 1 In System Clock prst n 1 In System reset, synchronous active low DIU Read Interface to SoPEC Units <unit>_diuradr[21:5] 17 In Read address to DIU 17 bits wide (256-bit aligned word). diu_<unit>_rack 1 Out Acknowledge from DIU that read request has been accepted and new read address can be placed on <unit>_diu radr cpu-adr[21:4] 18 In CPU address for read from DRAM. DIU Write Interface to SoPEC Units <unit>_diu_wadr[21:5] 17 In Write address to DIU except CPU, CDU 17 bits wide (256-bit aligned word) cdudiuwadr[21:3] 19 In CDU Write address to DIU 19 bits wide (64-bit aligned word) Addresses cannot cross a 256-bit word DRAM boundary. diu_<unit>_wack 1 Out Acknowledge from DIU that write request has been accepted and new write address can be placed on <unit>_diu radr Outputs to CPU Interface and Arbitration Logic sub-block rearbitrate 1 Out Signalling telling the arbitration logic to choose the next arbitration winner. re_arbitrate_wadv 1 Out Signal telling the arbitration logic to choose the next arbitration winner for non-CPU writes 2 timeslots in advance Debug Outputs to CPU Configuration and Arbitration Logic Sub-block write-sel 5 Out Signal indicating the SoPEC Unit for which the current write transaction is occurring. Encoding is described in Table 133.
WO 2005/120835 PCT/AU2004/000706 698 write-complete 1 Out Signal indicating that write transaction to SoPEC Unit indicated by write.sel is complete. Inputs from CPU Interface and Arbitration Logic sub-block arb-gnt 1 In Signal lasting 1 cycle which indicates arbitration has occurred and arb_sel is valid. arb~sel 5 In Signal indicating which requesting SoPEC Unit has won arbitration. Encoding is described in Table 133. dir_sel 2 In Signal indicating which sense of access associated with arbsel 00: issue non-CPU write 01: read winner 10: write winner 11: refresh winner Inputs from Read Write Multiplexor Sub-block write-data-valid 2 In Signal indicating that valid write data is available for the current command. 00=not valid 01=CPU write data valid 1 0=non-CPU write data valid 11=both CPU and non-CPU write data valid wdata 256 In 256-bit non-CPU write data wdatamask 32 In Byte mask for non-CPU write data. cpuwdata 128 In 128-bit CPU write data from posted write buffer. cpu-wadr[21:4] 18 In CPU write address [21:4] from posted write buffer. cpuwmask 16 In CPU byte mask from posted write buffer. Outputs to Read Write Multiplexor Sub-block writedataaccept 2 Out Signal indicating the Command Multiplexor has accepted the write data from the write multiplexor 00=not valid 01 =accepts CPU write data 10=accepts non-CPU write data 11 =not valid Inputs from DCU dcudauadv 1 In Signal indicating to DAU to supply next command to DCU dcu-dau-wadv 1 In Signal indicating to DAU to initiate next non-CPU write Outputs to DCU dau-dcu-adr[21:5] 17 Out Signal indicating the address for the DRAM access. This is a 256-bit aligned DRAM address. daudcu-rwn 1 Out Signal indicating the direction for the DRAM access (1 =read, 0=write). daudcucduwpage 1 Out Signal indicating if access is a CDU write page mode access (1=CDU page mode, 0=not CDU page mode). daudcurefresh 1 Out Signal indicating that a refresh command is to be issued. If asserted daudcuLadr, dau_dcurwn and daudcu_cduwpage are ignored.
WO 2005/120835 PCT/AU2004/000706 699 daudcu wdata 256 Out 256-bit write data to DCU daudcuwmask 32 Out Byte encoded write data mask for 256-bit dauLdcu-wdata to DCU 22.14.11.1 Command Multiplexor Sub-block Description The Command Multiplexor sub-block issues read, write or refresh commands to the DCU, according to the SoPEC Unit selected for DRAM access by the Arbitration Logic. The Command Multiplexor signals the 5 Arbitration Logic to perform arbitration to select the next SoPEC Unit for DRAM access. It does this by asserting the re arbitrate signal. rearbitrate is asserted when the DCU indicates on dcudauadv that it needs the next command. The Command Multiplexor is shown in Figure 128. Initially, the issuing of commands is described. Then the additional complexity of handling non-CPU write 10 commands arbitrated in advance is introduced. DAU-DCU interface See Section 22.14.5 for a description of the DAU-DCU interface. Generating re-arbitrate 15 The condition for asserting re arbitrate is that the DCU is looking for another command from the DAU. This is indicated by dcudauadv being asserted. re_arbitrate = dcu_dau_adv 20 Interface to SoPEC DIU requestors When the Command Multiplexor initiates arbitration by asserting re_arbitrate to the Arbitration Logic sub block, the arbitration winner is indicated by the arb-sel[4:0] and dir sel[1:0] signals returned from the Arbitration Logic. The validity of these signals is indicated by arbgnt. The encoding of arbsel[4:0] is shown in Table 133. 25 The value of arbsel[4:0] is used to control the steering multiplexor to select the DIU address of the winning arbitration requestor. The arb_gnt signal is decoded as an acknowledge, diu_<unit>_*ack back to the winning DIU requestor. The timing of these operations is shown in Figure 129. adr[21:0] is the output of the steering multiplexor controlled by arb sel[4:0]. The steering multiplexor can acknowledge DIU requestors in successive cycles. 30 Command Issuing Logic The address presented by the winning SoPEC requestor from the steering multiplexor is presented to the command issuing logic together with arbsel[4:0] and dir sel[1:0]. The command issuing logic translates the winning command into the signals required by the DCU. adr_[21:0], arbsel[4:0] and dir sel[1:0] comes from the steering multiplexor. 35 daudcuadr[21:5] = adr(21:5] WO 2005/120835 PCT/AU2004/000706 700 dau_dcu_rwn = (dir-sel(1:0] == read) daudcucduwpage = (arbsel(4:0] == CDU write) daudcurefresh = (dirsel{1:0]== refresh) 5 dau dcu valid indicates that a valid command is available to the DCU. For a write command, daudcuvalid will not be asserted until there is also valid write data present. This is indicated by the signal write data valid[1:0] from the Read Write Data Multiplexor sub-block. For a write command, the data issued to the DCU on dau_dcu_wdata[255:0] is multiplexed from cpuwdata[127:0] and wdata[255:0] depending on whether the write is a CPU or non-CPU write. The write 10 data from the Write Multiplexor for the CDU is available on wdata[63:0]. This data must be issued to the DCU on dau_dcu_wdata[255:0]. wdata[63:0] is copied to each 64-bit word of dau_dcu_wdata[255:0]. daudcu_wdata[255:0] = OxOOOOOOOO i f (arbLsel [4: 0 ]==CPU wri te) then 15 daudcu_wdata[127:0) = cpuwdata(127:0] daudcuwdata[255:127] = cpuwdata[127:0] elsif (arbsel[4:O]==CDU write)) then daudcuwdata[63:0] = wdata(63:0] daudcuwdata[127:64] = wdata[63:0] 20 daudcuwdata[191:128] = wdata(63:0] daudcuwdata(255:192] = wdata[63:0] else dau-dcuwdata[255:0] = wdata[255:0] 25 CPU write masking The CPU write data bus is only 128 bits wide. cpu wmask[15:0] indicates how many bytes of that 128 bits should be written. The associated address cpuwadr[21:4] is a 128-bit aligned address. The actual DRAM write must be a 256-bit access. The command multiplexor issues the 256-bit DRAM address to the DCU on dau_dcuadr[21:]. cpu_wadr[4] and cpuwmask[15:0] are used jointly to construct a byte write mask 30 dau_dcu_wmask[31:0] for this 256-bit write access. UHU/UDU write masking For UHU/UDU writes, each quarter-word transferred by the requester is accompanied by an independent byte-wide mask <uhu/udu>_diu wmask[7:0]. The cumulative 32-bit mask from the 4 data transfer cycles is 35 used to make up wdata_mask[31:0].This, in turn, is reflected in dau_dcuwmask[31:0] during execution of the actual write. CDU write masking The CPU performs four 64-bit word writes to 4 contiguous 256-bit DRAM addresses with the first address 40 specified by cdudiuwadr[2J:3]. The write address cdu_diuwadr[21:5] is 256-bit aligned with bits cdu_diuwadr[4:3] allowing the 64-bit word to be selected. If these 4 DRAM words lie in the same DRAM row then an efficient access will be obtained.
WO 2005/120835 PCT/AU2004/000706 701 The command multiplexor logic must issue 4 successive accesses to 256-bit DRAM addresses cdu_diuwadr[21:5],+1,+2,+3. dau_dcuwmask[31:0] indicates which 8 bytes (64-bits) of the 256-bit word are to be written. dau_dcuwmask[31:0] is calculated using cdudiuwadr[4:3] i.e. bits 8*cdudiu wadr[4:3] to 5 8*(cdudiuwadr[4:3]+1)-1 of dau_dcu_wmask[3:0]are asserted. Arbitrating non-CPU writes in advance In the case of a non-CPU write commands, the write data must be transferred from the SoPEC requester before the write can occur. Arbitration should occur early to allow for any delay for the write data to be 10 transferred to the DRAM. Figure 126 indicates that write data transfer over 64-bit busses will take a further 4 cycles after the address is transferred. The arbitration must therefore occur 4 cycles in advance of arbitration for read accesses, Figure 122 and Figure 123, or for CPU writes Figure 125. Arbitration of CDU write accesses, Figure 127, should take place 1 cycle in advance of arbitration for read and CPU write accesses. To simplify implementation 15 CDU write accesses are arbitrated 4 cycles in advance, similar to other non-CPU writes. The Command Multiplexor generates another version of rearbitrate called rearbitratewadv based on the signal dcudauwadv from the DCU. In the 3 cycle DRAM access dcudauadv and therefore rearbitrate are asserted in the MSN2 state of the DCU state-machine. dcu dau wadv and therefore re arbitrate wadv will therefore be asserted in the following RST state, see Figure 130. This matches the timing required for 20 non-CPU writes shown in Figure 126 and Figure 127. rearbitratewadv causes the Arbitration Logic to perform an arbitration for non-CPU in advance. re_arbitrate = dcu_dau_adv re_arbitrate_wadv = dcudauwadv 25 If the winner of this arbitration is a non-CPU write then arb_gnt is asserted and the arbitration winner is output on arbsel[4:0] and dir sel[1:0]. Otherwise arb_gnt is not asserted. Since non-CPU write commands are arbitrated early, the non-CPU command is not issued to the DCU immediately but instead written into an advance command register. 30 if (arb-sel(4:0 == non-CPU write) then advancecmd_register[3:0} = arb_sel[4:0] advance_cmd_register[5:4] = dir_sel(1:0] advance_cmd_register(27:6] = adr(21:0] 35 If a DCU command is in progress then the arbitration in advance of a non-CPU write command will overwrite the steering multiplexor input to the command issuing logic. The arbitration in advance happens in the DCU MSNI state. The new command is available at the steering multiplexor in the MSN2 state. The command in progress will have been latched in the DRAM by MSN falling at the start of the MSNI state.
WO 2005/120835 PCT/AU2004/000706 702 Issuing non-CPU write commands The arb-sel[4:0] and dirsel[I:0] values generated by the Arbitration Logic reflect the out of order arbitration sequence. 5 This out of order arbitration sequence is exported to the Read Write Data Multiplexor sub-block. This is so that write data in available in time for the actual write operation to DRAM. Otherwise a latency would be introduced every time a write command is selected. However, the Command Multiplexor must execute the command stream in-order. In-order command execution is achieved by waiting until rearbitrate has advanced to the non-CPU write 10 timeslot from which rearbitratewadv has previously issued a non-CPU write written to the advance command register. If rearbitratewadv arbitrates a non-CPU write in advance then within the Arbitration Logic the timeslot is marked to indicate whether a write was issued. When rearbitrate advances to a write timeslot in the Arbitration Logic then one of two actions can occur 15 depending on whether the slot was marked by rearbitratewadv to indicate whether a write was issued or not. e Non-CPU write arbitrated by re_arbitratewadv If the timeslot has been marked as having issued a write then the arbitration logic responds to rearbitrate by issuing arb sel[4:0], dir_sel[1:0] and asserting arbgnt as for a normal arbitration but selecting a non-CPU 20 write access. Normally, re arbitrate does not issue non-CPU write accesses. Non-CPU writes are arbitrated by rearbitratewadv. dir sel[J:0] == 00 indicates a non-CPU write issued by re_arbitrate. The command multiplexor does not write the command into the advance command register as it has already been placed there earlier by rearbitrate_wadv. Instead, the already present write command in the advance command register is issued when writedata valid[J] = 1. Note, that the value of arb-sel[4:0] issued by 25 rearbitrate could specify a different write than that in the advance command register since time has advanced. It is always the command in the advance command register that is issued. The steering multiplexor in this case must not issue an acknowledge back to SoPEC requester indicated by the value of arb sel[4:0]. if (dir-sel[l:0J == 00) then 30 command_issuing_logic[27:0] == advance_cmd-register(27:0] else command_issuing-logic[27:0} == steering-multiplexor[27:0] ack = arbgnt AND NOT (dirsel[1:0] == 00) 35 - Non-CPU write not arbitrated by re arbitratewadv If the timeslot has been marked as not having issued a write, the rearbitrate will use the un-used read timeslot selection to replace the un-used write timeslot with a read timeslot according to Section 22.10.6.2 Unused read timeslots allocation.
WO 2005/120835 PCT/AU2004/000706 703 The mechanism for write timeslot arbitration selects non-CPU writes in advance. But the selected non-CPU write is stored in the Command Multiplexor and issued when the write data is available. This means that even if this timeslot is overwritten by the CPU reprogramming the timeslot before the write command is actually issued to the DRAM, the originally arbitrated non-CPU write will always be correctly issued. 5 Accepting write commands When a write command is issued then writedataaccept[1:0] is asserted. This tells the Write Multiplexor that the current write data has been accepted by the DRAM and the write multiplexor can receive write data 10 from the next arbitration winner if it is a write. writedata accept[1:0] differentiates between CPU and non CPU writes. A write command is known to have been issued when re arbitrate wadv to decide on the next command is detected. In the case of CDU writes the DCU will generate a signal dcu daucduwaccept which tells the Command Multiplexor to issue a writedata accept[1]. This will result in the Write Multiplexor supplying the next 15 CDU write data to the DRAM. write data accept[0] = RISING EDGE(rearbitratewadv) AND commandjissuinglogic(dir-sel [1]==1) 20 AND commandjissuing-logic(arb~sel[4:0]==CPU) write data accept [1] = (RISING EDGE (rearbitratewadv) AND 25 commandjissuinglogic(dir-sel[1]==1) AND command-issuinglogic(arb-sel[4:01==nonCPU)) OR dcu_daucduwaccept==1 30 Debug logic output to CPU Configuration and Arbitration Logic sub-block writesel[4:0] reflects the value of arbsel[4:0] at the command issuing logic. The signal writecomplete is asserted when every any bit of writedataaccept[1:0] is asserted. write-complete = writedata-accept(O] OR writedata-accept[l] 35 writesel[4:0] and write-complete are CPU readable from the DIUPerformance and WritePerformance status registers. When write-complete is asserted writesel[4:0] will indicate which write access the DAU has issued. 22.14.2 CPU Configuration and Arbitration Logic Sub-block Table 137. CPU Configuration and Arbitration Logic Sub-block 10 Definition j~n M kill~~ Pot nae0% r WO 2005/120835 PCT/AU2004/000706 704 Clocks and Resets PcIk 1 In System Clock prst-n 1 In System reset, synchronous active low CPU Interface data and control signals cpu-adr[10:2] 9 In 9 bits (bits 10:2) are required to decode the configuration register address space. cpudataout 32 In Data bus from the CPU for configuration register writes. diucpudata 32 Out Configuration, status and debug read data bus to the CPU diu-cpu-debugvalid 1 Out Signal indicating the data on the diu_cpudata bus is valid debug data. cpu_rwn 1 In Common read/not-write signal from the CPU cpuacode 2 In CPU access code signals. cpu-acode[0] - Program (0) / Data (1) access cpu-acode[1] - User (0) / Supervisor (1) access The DAU will only allow supervisor mode accesses to data space. cpu-diu-sel 1 In Block select from the CPU. When cpu diuset is high both cpu adr and cpudataout are valid diu-cpu-rdy 1 Out Ready signal to the CPU. When diucpurdy is high it indicates the last cycle of the access. For a write cycle this means cpu.dataout has been registered by the block and for a read cycle this means the data on diucpudata is valid. diucpu-berr 1 Out Bus error signal to the CPU indicating an invalid access. DIU Read Interface to SoPEC Units <unit>_diurreq 11 In SoPEC unit requests DRAM read. DIU Write Interface to SoPEC Units diu-cpu-write-rdy 1 In Indicator that CPU posted write buffer is empty. <unit>_diu_wreq 4 In Non- CPU SoPEC unit requests DRAM write. Inputs from Command Multiplexor sub-block re_arbitrate 1 In Signal telling the arbitration logic to choose the next arbitration winner. rearbitratewadv 1 In Signal telling the arbitration logic to choose the next arbitration winner for non-CPU writes 2 timeslots in advance Outputs to DCU daudcumsn2stall 1 Out Signal indicating from DAU Arbitration Logic which when asserted stalls DCU in MSN2 state. Inputs from Read and Write Multiplexor sub-block WO 2005/120835 PCT/AU2004/000706 705 read cmd-rdy 2 In Signal indicating that read multiplexor is ready for next read read command. 00=not ready 01=ready for CPU read 1O=ready for non-CPU read 11=ready for both CPU and non-CPU reads write-cmd-rdy 2 In Signal indicating that write multiplexor is ready for next write command. 00=not ready 01=ready for CPU write 1 0=ready for non-CPU write 11 =ready for both CPU and non-CPU write Outputs to other DAU sub-block s arb-gnt 1 In Signal lasting 1 cycle which indicates arbitration has occurred and arb_selis valid. arbsel 5 In Signal indicating which requesting SoPEC Unit has won arbitration. Encoding is described in Table 133. dirsel 2 In Signal indicating which sense of access associated with arb sel 00: issue non-CPU write 01: read winner 10: write winner 11: refresh winner Debug Inputs from Read-Write Multiplexor sub-block read-sel 5 In Signal indicating the SoPEC Unit for which the current read transaction is occurring. Encoding is described in Table 133. read-complete 1 In Signal indicating that read transaction to SoPEC Unit indicated by read_sel is complete. Debug Inputs from Command Multiplexor sub-block writesel 5 In Signal indicating the SoPEC Unit for which the current write transaction is occurring. Encoding is described in Table 133. write-complete 1 In Signal indicating that write transaction to SoPEC Unit indicated by writeLsel is complete. Debug Inputs from DCU dcu_dau_refreshcomplete 1 In Signal indicating that the DCU has completed a refresh. Debug Inputs from DAU 10 various n In Various DAU 10 signals which can be monitored in debug mode 22.14.12 The CPU Interface and Arbitration Logic sub-block is shown in Figure 131. 5 22.14.12.1 CPU Interface and Configuration Registers Description The CPU Interface and Configuration Registers sub-block provides for the CPU to access DAU specific registers by reading or writing to the DAU address space.
WO 2005/120835 PCT/AU2004/000706 706 The CPU subsystem bus interface is described in more detail in Section 11.4.3. The DAU block will only allow supervisor mode accesses to data space (i.e. cpuacode[1:0] = b 11). All other accesses will result in diucpu_berr being asserted. The configuration registers described in Section 22.14.9 DAU Configuration Registers are implemented here. 5 22.14.12.2 Arbitration Logic Description Arbitration is triggered by the signal re arbitrate from the Command Multiplexor sub-block with the signal arbgnt indicating that arbitration has occurred and the arbitration winner is indicated by arb sel[4:0]. The encoding of arb sel[4:0] is shown in Table 133. The signal dirsel[1:0] indicates if the arbitration winner is a 10 read, write or refresh. Arbitration should complete within one clock cycle so arbgnt is normally asserted the clock cycle after rearbitrate and stays high for 1 clock cycle. arb sel[4:0] and dir sel[1:0] remain persistent until arbitration occurs again. The arbitration timing is shown in Figure 132. 22.14.12.2.1 Rotation Synchronization A configuration bit, RotationSync, is used to initialize advancement through the timeslot rotation, in order that 15 the CPU will know, on a cycle basis, which timeslot is being arbitrated. This is essential for debug purposes, so that exact arbitration sequences can be reproduced. In general, if RotationSync is set, slots continue to be arbitrated in the regular order specified by the timeslot rotation. When the bit is cleared, the current rotation continues until the slot pointers for pre- and main arbitration reach zero. The arbitration logic then grants DRAM access exclusively to the CPU and refreshes. 20 When the CPU again writes to RotationSync to cause a 0-to-i transition of the bit, the rdy acknowledgment back to the CPU for this write will be exactly coincident with the RST cycle of the initial refresh which heralds the enabling of a new rotation. This refresh, along with the second access which can be either a CPU pre-access or a refresh, (depending on the CPU's request inputs), form a 2-access "preamble" before the first non-CPU requester in the new rotation can be serviced. This preamble is necessary to give the write pre 25 arbitration the necessary head start on the main arbitration, so that write data can be loaded in time. See Figure 105 below. The same preamble procedure is followed when emerging from reset. The alignment of rdy with the commencement of the rotation ensures that the CPU is always able to calculate at any point how far a rotation has progressed. RotationSync has a reset value of 1 to ensure that the default power-up rotation can take place. 30 Note that any CPU writes to the DIU's other configuration registers should only be made when RotationSync is cleared. This ensures that accesses by non-CPU requesters to DRAM are not affected by partial configuration updates which have yet to be completed. 22.14.2.2 Motivation for Rotation Synchronization The motivation for this feature is that communications with SoPEC from external sources are synchronized to 35 the internal clock of our position within a DIU full timeslot rotation. This means that if an external source told SOPEC to start a print 3 separate times, it would likely be at three different points within a full DIU rotation. This difference means that the DIU arbitration for each of the runs would be different, which would manifest WO 2005/120835 PCT/AU2004/000706 707 itself externally as anomalous or inconsistent print performance. The lack of reproducibility is the problem here. However, if in response to the external source saying to start the print, we caused the internal to pass through a known state at a fixed time offset to other internal actions, this would result in reproducible prints. So, the 5 plan is that the software would do a rotation synchronize action, then writes "Go" into various PEP units to cause the prints. This means the DIU state will be the identical with respect to the PEP units state between separate runs. 22.14.12.2.3 Wind-down Protocol when Rotation Synchronization is Initiated When a zero is written to "RotationSync", this initiates a "wind-down protocol" in the DIU, in which any 10 rotation already begun must be fully completed. The protocol implements the following sequence: * The pre-arbitration logic must reach the end of whatever rotation it is on and stop pre-arbitrating. * Only when this has happened, does the main arbitration consider doing likewise with its current rotation. Note that the main arbitration lags the pre-arbitration by at least 2 DRAM accesses, 15 subject to variation by CPU pre-accesses and/or scheduled refreshes, so that the two arbitration processes are sometimes on different rotations. - Once the main arbitration has reached the end of its rotation, rotation synchronization is considered to be fully activated. Arbitration then proceeds as outlined in the next section. 22.14.12.2.4 Arbitration during Rotation Synchronization 20 Note that when RotationSync is'0' and, assuming the terminating rotation has completely drained out, then DRAM arbitration is granted according to the following fixed priority order: Scheduled Refresh -> CPU(W) -> CPU(R) -> Default Refresh. CPU pre-access counters play no part in arbitration during this period. It is only subsequently, when emerging from rotation sync, that they are reloaded with the values of CPUPreAccessTimeslots and CPUTotalTimeslots 25 and normal service resumes. 22.14.12.2.5 Timeslot-based arbitration Timeslot-based arbitration works by having a pointer point to the current timeslot. This is shown in Figure 108 repeated here as Figure 134. When re-arbitration is signaled the arbitration winner is the current timeslot and the pointer advances to the next timeslot. Each timeslot denotes a single access. The duration of the 30 timeslot depends on the access. If the SoPEC Unit assigned to the current timeslot is not requesting then the unused timeslot arbitration mechanism outlined in Section 22.10.6 is used to select the arbitration winner. Note that this unused slot re allocation is guaranteed to produce a result, because of the inclusion of refresh in the round-robin scheme. Pseudo-code to represent arbitration is given below: 35 if re-arbitrate == 1 then arbgnt = 1 if current timeslot requesting then WO 2005/120835 PCT/AU2004/000706 708 choose(arb-sel, dir sel) at current timeslot else // un-used timeslot scheme choose winner according to un-used timeslot allocation of Section 22.10.6 5 arbgnt = 0 22.14.12.3 Arbitrating non-CPU writes in advance In the case of a non-CPU write commands, the write data must be transferred from the SoPEC requester before the write can occur. Arbitration should occur early to allow for any delay for the write data to be transferred to the DRAM. 10 Figure 126 indicates that write data transfer over 64-bit busses will take a further 4 cycles after the address is transferred. The arbitration must therefore occur 4 cycles in advance of arbitration for read accesses, Figure 122 and Figure 123, or for CPU writes Figure 125. Arbitration of CDU write accesses, Figure 127, should take place 1 cycle in advance of arbitration for read and CPU write accesses. To simplify implementation CDU write accesses are arbitrated 4 cycles in advance, similar to other non-CPU writes. 15 The Command Multiplexor generates a second arbitration signal rearbitratewadv which initiates the arbitration in advance of non-CPU write accesses. The timeslot scheme is then modified to have 2 separate pointers: * rearbitrate can arbitrate read, refresh and CPU read and write accesses according to the position 20 of the current timeslot pointer. * rearbitrate wadv can arbitrate only non-CPU write accesses according to the position of the write lookahead pointer. Pseudo-code to represent arbitration is given below: 25 //re-arbitrate if (rearbitrate == 1) AND (current timeslot pointer!= non-CPU write) then arb_gnt = 1 if current timeslot requesting then choose(arbsel, dir-sel) at current timeslot 30 else // un-used read timeslot scheme choose winner according to un-used read timeslot allocation of Section 22.10.6.2 If the SoPEC Unit assigned to the current timeslot is not requesting then the unused read timeslot arbitration mechanism outlined in Section 22.10.6.2 is used to select the arbitration winner. 35 //rearbitrate_wadv if (rearbitrate-wadv == 1) AND (write lookahead timeslot pointer == non-CPU write) then if write lookahead timeslot requesting then 40 choose(arbsel, dirsel) at write lookahead timeslot arbgnt = 1 elsif un-used write timeslot scheme has a requestor choose winner according to un-used write timeslot allocation of Section 22.10.6.1 45 arb-gnt = 1 else //no arbitration winner arb gnt = 0 WO 2005/120835 PCT/AU2004/000706 709 rearbitrate is generated in the MSN2 state of the DCU state-machine, whereas rearbitrate wadv is generated in the RST state. See Figure 116. The write lookahead pointer points two timeslots in advance of the current timeslot pointer. Therefore 5 rearbitratewadv causes the Arbitration Logic to perform an arbitration for non-CPU two timeslots in advance. As noted in Table 111, each timeslot lasts at least 3 cycles. Therefor rearbitratewadv arbitrates at least 4 cycles in advance. At initialisation, the write lookahead pointer points to the first timeslot. The current timeslot pointer is invalid until the write lookahead pointer advances to the third timeslot when the current timeslot pointer will point to 10 the first timeslot. Then both pointers advance in tandem. Some accesses can be preceded by a CPU access as in Table 111. These CPU accesses are not allocated timeslots. If this is the case the timeslot will last 3 (CPU access) + 3 (non-CPU access) = 6 cycles. In that case, a second write lookahead pointer, the CPU pre-access write lookahead pointer, is selected which points only one timeslot in advance. rearbitratewadv will still arbitrate 4 cycles in advance. 15 In the case that the write timeslot lookahead pointers do not advance due to a refresh or a refresh preceeded by a CPU-preaccess then the pre-arbitration is repeated every dcu dau wadv pulse until a requesting non-CPU write requester is found or until the pointers start to advance again. 22.14.12.3.1 Issuing non-CPU write commands Although the Arbitration Logic will arbitrate non-CPU writes in advance, the Command Multiplexor must 20 issue all accesses in the timeslot order. This is achieved as follows: If rearbitratewadv arbitrates a non-CPU write in advance then within the Arbitration Logic the timeslot is marked to indicate whether a write was issued. //rearbitrate_wadv 25 if (rearbitratewadv == 1) AND (write lookahead timeslot pointer == non-CPU write) then if write lookahead timeslot requesting then choose(arb-sel, dirsel) at write lookahead timeslot arb-gnt = 1 30 MARK_timeslot = 1 elsif un-used write timeslot scheme has a requestor choose winner according to un-used write timeslot allocation of Section 22.10.6.1 arbgnt = 1 35 MARKtimeslot = 1 else //no pre-arbitration winner arbgnt = 0 MARK_.timeslot = 0 40 When rearbitrate advances to a write timeslot in the Arbitration Logic then one of two actions can occur depending on whether the slot was marked by rearbitratewadv to indicate whether a write was issued or not. e Non-CPU write arbitrated by re_arbitratewadv WO 2005/120835 PCT/AU2004/000706 710 If the timeslot has been marked as having issued a write then the arbitration logic responds to rearbitrate by issuing arb sel[4:0], dirsel[1:0] and asserting arbgnt as for a normal arbitration but selecting a non-CPU write access. Normally, re arbitrate does not issue non-CPU write accesses. Non-CPU writes are arbitrated by rearbitrate wadv. dir sel[1:0] == 00 indicates a non-CPU write issued by re_arbitrate. 5 0 Non-CPU write not arbitrated by rearbitratewadv If the timeslot has been marked as not having issued a write, the rearbitrate will use the un-used read timeslot selection to replace the un-used write timeslot with a read timeslot according to Section 22.10.6.2 Unused read timeslots allocation. 10 //re-arbitrate except for non-CPU writes if (rearbitrate == 1) AND (current timeslot pointer!= non-CPU write) then arb-gnt = 1 if current timeslot requesting then 15 choose(arbsel, dir-sel) at current timeslot else // un-used read timeslot scheme choose winner according to un-used read timeslot allocation of Section 22.10.6.2 arb-gnt = 1 20 //non-CPU write MARKED as issued elsif (rearbitrate == 1) AND (current timeslot pointer == non-CPU write) AND (MARKtimeslot == 1) then 25 //indicate to Command Multiplexor that non-CPU write has been arbitrated in //advance arb-gnt = 1 dir sel[1:0] == 00 30 //non-CPU write not MARKED as issued elsif (rearbitrate == 1) AND (current timeslot pointer == non-CPU write) AND (MARK_timeslot == 0) then 35 choose winner according to un-used read timeslot allocation of Section 22.10.6.2 arb-gnt = 1 22.14.12.4 Flow control If read commands are to win arbitration, the Read Multiplexor must be ready to accept the read data from the 40 DRAM. This is indicated by the readcmd rdy[J:0] signal. read cmd rdy[1:0] supplies flow control from the Read Multiplexor. read_cmd-rdy(0]==l //Read multiplexor ready for CPU read read_cmd_rdy(l1]==l //Read multiplexor ready for non-CPU read 45 WO 2005/120835 PCT/AU2004/000706 711 The Read Multiplexor will normally always accept CPU reads, see Section 22.14.13.1, so read_cmd rdy[0]==1 should always apply. Similarly, if write commands are to win arbitration, the Write Multiplexor must be ready to accept the write 5 data from the winning SoPEC requestor. This is indicated by the write cmd~rdy[1:0J signal. write_cmd rdy[1:Oj supplies flow control from the Write Multiplexor. write-cmd-rdy[0)==1 //Write multiplexor ready for CPU write write cmd rdy[l]==l //Write multiplexor ready for non-CPU write 10 The Write Multiplexor will normally always accept CPU writes, see Section 22.14.13.2, so write cmd rdy[]==1 should always apply. Non-CPU read flow control 15 If rearbitrate selects an access then the signal dau_dcu_msn2stall is asserted until the Read Write Multiplexor is ready. arbgnt is not asserted until the Read Write Multiplexor is ready. This mechanism will stall the DCU access to the DRAM until the Read Write Multiplexor is ready to accept the next data from the DRAM in the case of a read. 20 //other access flow control dau_dcumsn2stall = (((rearbitrate selects CPU read) AND read~cmdrdy(0]==0) OR (rearbitrate selects non-CPU read) AND 25 read_cmdrdy[l==0)) arb-gnt not asserted until daudcumsn2stall de-asserts 22.14.12.5 Arbitration Hierarchy CPU and refresh are not included in the timeslot allocations defined in the DAU configuration registers of 30 Table 129. The hierarchy of arbitration under normal operation is a. CPU access b. Refresh access c. Timeslot access. 35 This is shown in Figure 137. The first DRAM access issued after reset must be a refresh. As shown in Figure 137, the DIU request signals <unit>_diu_rreq, <unit>_diuwreq are registered at the input of the arbitration block to ease timing. The exceptions are the refreshreq signal, which is generated locally in the sub-block and cpu diurreq. The CPU read request signal is not registered so as to keep CPU DIU read access latency to a minimum. Since CPU writes are posted, cpudiu wreq is registered so that the 40 DAU can process the write at a later juncture. The arbitration logic is coded to perform arbitration of non- WO 2005/120835 PCT/AU2004/000706 712 CPU requests first and then to gate the result with the CPU requests. In this way the CPU can make the requests available late in the arbitration cycle. Note that when RotationSync is set to '0', a modified hierarchy of arbitration is used. This is outlined in section 20.14.12.2.3 on page 280. 5 22.14.12.6 Timeslot access The basic timeslot arbitration is based on the MainTimeslot configuration registers. Arbitration works by the timeslot pointed to by either the current or write lookahead pointer winning arbitration. The pointers then advance to the next timeslot. This was shown in Figure 103. 10 Each main timeslot pointer gets advanced each time it is accessed regardless of whether the slot is used. 22.14.12.7 Unused timeslot allocation If an assigned slot is not used (because its corresponding SoPEC Unit is not requesting) then it is reassigned according to the scheme described in Section 22.10.6. 15 Only used non-CPU accesses are reallocated. CDU write accesses cannot be included in the unused timeslot allocation for write as CDU accesses take 6 cycles. The write accesses which the CDU write could otherwise replace require only 3 or 4 cycles. Unused write accesses are re-allocated according to the fixed priority scheme of Table 113. Unused read timeslots are re-allocated according to the two-level round-robin scheme described in Section 22.10.6.2. 20 A pointer points to the most recently re-allocated unit in each of the round-robin levels. If the unit immediately succeeding the pointer is requesting, then this unit wins the arbitration and the pointer is advanced to reflect the new winner. If this is not the case, then the subsequent units (wrapping back eventually to the pointed unit) in the level 1 round-robin are examined. When a requesting unit is found this unit wins the arbitration and the pointer is adjusted. If no unit is requesting then the pointer does not advance 25 and the second level of round-robin is examined in a similar fashion. In the following pseudo-code the bit indices are for the ReadRoundRobinLevel configuration register described in Table 131. //choose the winning arbitration level 30 level = 0 level2 = 0 for i = 0 to 13 if unit(i) requesting AND ReadRoundRobinLevel(i) = 0 then level = 1 35 if unit(i) requesting AND ReadRoundRobinLevel(i) = 1 then level2 = 1 Round-robin arbitration is effectively a priority assignment with the units assigned a priority according to the round-robin order of Table 131 but starting at the unit currently pointed to. 40 //levelptr is pointer of selected round robin level priority is array 0 to 13 WO 2005/120835 PCT/AU2004/000706 713 //assign decreasing priorities from the current pointer; maximum priority is 13 for i = 1 to 14 priority(levelptr + i) = 14 - i 5 i++ The arbitration winner is the one with the highest priority provided it is requesting and its ReadRoundRobinLevel bit points to the chosen level. The levelptr is advanced to the arbitration winner. The priority comparison can be done in the hierarchical manner shown in Figure 138. 10 22.14.12.8 How CPU and Non-CPU Address Restrictions Affect Arbitration Recall from Table 129, "DAU configuration registers," on page 378 that there are minimum valid DRAM addresses for non-CPU accesses, defined by minNonCPUReadAdr, minDWUWriteAdr and minNonCPUWriteAdr. Similarly, neither the CPU nor non-CPU units may attempt to access a location which exceeds the maximum legal DRAM word address (either OxI_3FFF or, if disableUpperDRAMMacro is set to 15 "1", OxO_9FFF). To ensure compliance with these address restrictions, the following DIU response occurs for any incorrectly addressed non-CPU writes: * Issue a write acknowledgment at pre-arbitration time, to prevent the write requester from hanging. * Disregard the incoming write data and write valids and void the pre-arbitration. 20 * Subsequently re-allocate the write slot at main arbitration time via the round robin. For incorrectly addressed CPU posted write attempts, the DIU response is: * De-assert diucpu write rdy for 1 cycle only, so that the CPU sees a normal response. * Disregard the data, address and mask associated with the incorrect access. Leave the buffer empty for later, legal CPU writes. 25 For any incorrectly addressed CPU or non-CPU reads, the response is: * Arbitrate the slot in favour of the scheduled, misbehaving requester. * Issue the read acknowledgement and rvalid(s) to keep the requester from hanging. * Execute a nominal read of the maximum legal DRAM address (Ox1_3FFF or OxO_9FFF). " Intercept the resultant read data from the DCU and send back all zeros to the requester instead. 30 If an invalidly addressed CPU or non-CPU access is attempted, then a sticky bit, stickyinvaliddramadr, is set in the ArbitrationHistory configuration register. See Table 132 on page 385 for details. 22.14.1.9 Refresh Controller Description The refresh controller implements the functionality described in detail in Section 22.10.5. Refresh is not included in the timeslot allocations. 35 CPU and refresh have priority over other accesses. If the refresh controller is requesting i.e. refreshreq is asserted, then the refresh request will win any arbitration initiated by re arbitrate. When the refresh has won the arbitration refreshreq is de-asserted. The refresh counter is reset to RefreshPeriod[8:0] i.e. the number of cycles between each refresh. Every time this counter decrements to 0, a refresh is issued by asserting refreshreq. The counter immediately reloads 40 with the value in RefreshPeriod[8:0] and continues its countdown. It does not wait for an acknowledgment, WO 2005/120835 PCT/AU2004/000706 714 since the priority of a refresh request supersedes that of any pending non-CPU access and it will be serviced immediately. In this way, a refresh request is guaranteed to occur every (RefreshPeriod[8:0] + 1) cycles. A given refresh request may incur some incidental delay in being serviced, due to alignment with DRAM accesses and the possibility of a higher-priority CPU pre-access. 5 Refresh is also included in the unused read and write timeslot allocation, having second option on awards to a round-robin position shared with the CPU. A refresh issued as a result of an unused timeslot allocation also causes the refresh counter to reload with the value in RefreshPeriod[8:0]. The first access issued by the DAU after reset must be a refresh. This assures that refreshes for all DRAM words fall within the required 3.2ms window. 1.0 //issue a refresh request if counter reaches 0 or at reset or for re allocated slot if RefreshPeriod != 0 AND (refresh cnt == 0 OR diu-softresetn == 0 OR prst-n ==0 OR unusedtimeslot_allocation == 1) then 15 refresh-req = 1 //de-assert refresh request when refresh acked else if refresh_ack == 1 then refreshreq = 0 20 //refresh counter if refresh-cnt == 0 OR diusoftresetn == 0 OR prst n ==0 OR unusedtimeslotallocation == 1 then refreshcnt = RefreshPeriod else 25 refresh_cnt = refreshcnt - 1 Refresh can preceded by a CPU access in the same way as any other access. This is controlled by the CPUPreAccessTimeslots and CPUTotalTimeslots configuration registers. Refresh will therefore not affect 30 CPU performance. A sequence of accesses including refresh might therefore be CPU, refresh, CPU, actual timeslot. 22.14.12.10 CPU Timeslot Controller Description CPU accesses have priority over all other accesses.CPU access is not included in the timeslot allocations. CPU access is controlled by the CPUPreAccessTimeslots and CPUTotalTimeslots configuration registers. 35 To avoid the CPU having to wait for its next timeslot it is desirable to have a mechanism for ensuring that the CPU always gets the next available timeslot without incurring any latency on the non-CPU timeslots. This is be done by defining each timeslot as consisting of a CPU access preceding a non-CPU access. Two counters of 4-bits each are defined allowing the CPU to get a maximum of (CPUPreAccessTimeslots + 1) pre-accesses out of a total of (CPUTotalTimeslots + 1) main slots. A timeslot counter starts at 40 CPUTotalTimeslots and decrements every timeslot, while another counter starts at CPUPreAccessTimeslots and decrements every timeslot in which the CPU uses its access. If the pre-access entitlement is used up before (CPUTotalTimeslots +1) slots, no further CPU accesses are allowed. When the CPUTotalTimeslots counter reaches zero both counters are reset to their respective initial values.
WO 2005/120835 PCT/AU2004/000706 715 When CPUPreAccessTimeslots is set to zero then only one pre-access will occur during every (CPUTotalTimeslots + 1) slots. 22.14.12.10.1 Conserving CPU Pre-Accesses In section 22.10.6.2.1 on page 349, it is described how the CPU can be allowed participate in the unused read 5 round-robin scheme. When enabled by the configuration bit EnableCPURoundRobin, the CPU shares a joint position in the round robin with refresh. In this case, the CPU has priority, ahead of refresh, in availing of any unused slot awarded to this position. Such CPU round-robin accesses do not count towards depleting the CPU's quota of pre-accesses, specified by CPUPreAccessTimeslots. Note that in order to conserve these pre-accesses, the arbitration logic, when faced 10 with the choice of servicing a CPU request either by a pre-access or by an immediately following unused read slot which the CPU is poised to win, will opt for the latter. 22.14.13 Read and Write Data Multiplexor sub-block Table 138. Read and Write Multiplexor Sub-block 10 Definition Clocks and Resets pclk 1 In System Clock prst_n 1 In System reset, synchronous active low DIU Read Interface to SoPEC Units diudata 64 Out Data from DIU to SoPEC Units except CPU. First 64-bits is bits 63:0 of 256 bit word Second 64-bits is bits 127:64 of 256 bit word Third 64-bits is bits 191:128 of 256 bit word Fourth 64-bits is bits 255:192 of 256 bit word dramcpudata 256 Out 256-bit data from DRAM to CPU. diu_<unit>_rvalid 1 Out Signal from DIU telling SoPEC Unit that valid read data is on the diudata bus DIU Write Interface to SoPEC Units <unit>_diu_data 64 In Data from SoPEC Unit to DIU except CPU. First 64-bits is bits 63:0 of 256 bit word Second 64-bits is bits 127:64 of 256 bit word Third 64-bits is bits 191:128 of 256 bit word Fourth 64-bits is bits 255:192 of 256 bit word <unit>_diuwvalid 1 In Signal from SoPEC Unit indicating that data on <unit>_diudata is valid. Note that "unit" refers to non-CPU requesters only. <uhu/udu>_diu_wmask 8 In Byte mask for each quarter-word transferred from the UHU/UDU. cpudiuwdata 128 In Write data from CPU to DIU. Input to the posted write buffer. cpu-diuwadr[21:4] 18 In Write address from the CPU. Input to the posted write buffer.
WO 2005/120835 PCT/AU2004/000706 716 cpu_diuwmask 16 In Byte mask for CPU write. Input to the posted write buffer. cpudiuwdatavalid 1 In Write enable for the CPU posted write buffer. Also confirms the validity of cpu-diu.wdata. diu-cpu-write-rdy 1 Out Indicator that the CPU posted write buffer is empty. Inputs from CPU Configuration and Arbitration Logic Sub-block arb-gnt 1 In Signal lasting 1 cycle which indicates arbitration has occurred and arb_sel is valid. arbsel 5 In Signal indicating which requesting SoPEC Unit has won arbitration. Encoding is described in Table 133. dir_sel 2 In Signal indicating which sense of access associated with arb_sel 00: issue non-CPU write 01: read winner 10: write winner 11: refresh winner Outputs to Command Multiplexor Sub-block write-data-valid 2 Out Signal indicating that valid write data is available for the current command. 00=not valid 01 =CPU write data valid 10=non-CPU write data valid 11 =both CPU and non-CPU write data valid Wdata 256 Out 256-bit non-CPU write data Wdata mask 32 Out Byte mask for non-CPU write data. cpu_wdata 128 Out Posted CPU write data. cpu.wadr[21:4] 18 Out Posted CPU write address. cpu_wmask 16 Out Posted CPU write mask. Inputs from Command Multiplexor Sub-block writedataaccept 2 In Signal indicating the Command Multiplexor has accepted the write data from the write multiplexor 00=not valid 01 =accepts CPU write data 10=accepts non-CPU write data 11 =not valid Inputs from DCU dcu-dau-rdata 256 In 256-bit read data from DCU. dcudau-rvalid 1 In Signal indicating valid read data on dcu_dau_rdata. Outputs to CPU Configuration and Arbitration Logic Sub-block readscmd-rdy 2 Out Signal indicating that read multiplexor is ready for next read read command. 00=not ready 01 =ready for CPU read 1 0=ready for non-CPU read 11=ready for both CPU and non-CPU reads WO 2005/120835 PCT/AU2004/000706 717 write-cmd-rdy 2 Out Signal indicating that write multiplexor is ready for next write command. 00=not ready 01=ready for CPU write 1 O=ready for non-CPU write 11 =ready for both CPU and non-CPU writes Debug Outputs to CPU Configuration and Arbitration Logic Sub-block readsel 5 Out Signal indicating the SoPEC Unit for which the current read transaction is occurring. Encoding is described in Table 133. readcomplete 1 Out Signal indicating that read transaction to SoPEC Unit indicated by readsel is complete.
WO 2005/120835 PCT/AU2004/000706 718 2.14.13 22.14.13.1 Read Multiplexor logic description The Read Multiplexor has 2 read channels a a separate read bus for the CPU, dramcpudata[255:0]. 5 e and a shared read bus for the rest of SoPEC, diudata[63:0]. The validity of data on the data busses is indicated by signals diu_<unit>_rvalid. Timing waveforms for non-CPU and CPU DIU read accesses are shown in Figure 103 and Figure 104, respectively. The Read Multiplexor timing is shown in Figure 140. Figure 140 shows both CPU and non-CPU reads. Both 10 CPU and non-CPU channels are independent i.e. data can be output on the CPU read bus while non-CPU data is being transmitted in 4 cycles over the shared 64-bit read bus. CPU read data, dramcpudata[255:0], is available in the same cycle as output from the DCU. CPU read data needs to be registered immediately on entering the CPU by a flip-flop enabled by the diucpurvalid signal. To ease timing, non-CPU read data from the DCU is first registered in the Read Multiplexor by capturing it in 15 the shared read data buffer of Figure 139 enabled by the dcudaurvalid signal. The data is then partitioned in 64-bit words on diu-data[63:0]. 22.14.13.1.1 Non-CPU Read Data Coherency Note that for data coherency reasons, a non-CPU read will always result in read data being returned to the requester which includes the after-effects of any pending (i.e. pre-arbitrated, but not yet executed) non-CPU 20 write to the same address, which is currently cached in the non-CPU write buffer. This is shown graphically in Figure 139 on page 421. Should the pending write be partially masked, then the read data returned must take account of that mask. Pending, masked writes by the CDU, UHU and UDU, as well as all unmasked non-CPU writes are fully supported. 25 Since CPU writes are dealt with on a dedicated write channel, no attempt is made to implement coherency between posted, unexecuted CPU writes and non-CPU reads to the same address. 22.14.13.1.2 Read multiplexor command queue When the Arbitration Logic sub-block issues a read command the associated value of arb sel[4:0], which indicates which SoPEC Unit has won arbitration, is written into a buffer, the read command queue. 30 write-en = arbgnt AND dirsel[1:0]=="O1" if writeen==l then WRITE arb_sel into read command queue 35 The encoding of arb sel[4:0] is given in Table 133. dir-sel[J:O]=="01" indicates that the operation is a read. The read command queue is shown in Figure 141.
WO 2005/120835 PCT/AU2004/000706 719 The command queue could contain values of arb sel[4:0] for 3 reads at a time. 0 In the scenario of Figure 140 the command queue can contain 2 values of arb sel[4:0] i.e. for the simultaneous CDU and CPU accesses. 5 * In the scenario of Figure 143, the command queue can contain 3 values of arb sel[4:0] i.e. at the time of the second dcudaurvalid pulse the command queue will contain an arb sel[4:0] for the arbitration performed in that cycle, and the two previous arbsel[4:0] values associated with the data for the first two dcudaurvalid pulses, the data associated with the first dcudau_rvalid pulse not having been fully transfered over the shared read data bus. 10 The read command queue is specified as 4 deep so it is never expected to fill. The top of the command queue is a signal read type[4:0] which indicates the destination of the current read data. The encoding of read _ype[4:0] is given in Table 133. 22.14.13.1.3 CPU reads Read data for the CPU goes straight out on dram cpudata[255:0] and dcudau_rvalid is output on 15 diucpu_rvalid. cpureadcomplete(0) is asserted when a CPU read at the top of the read command queue occurs. cpuread complete(0) causes the read command queue to be popped. cpureadcomplete(O) = (read_type[4:0] == CPU read) AND (dcudaurvalid 20 == 1) If the current read command queue location points to a non-CPU access and the second read command queue location points to a CPU access then the next dcudau-rvalid pulse received is associated with a CPU access. This is the scenario illustrated in Figure 140. The dcu dau valid pulse from the DCU must be output to the 25 CPU as diucpurvalid. This is achieved by using cpureadcomplete(l) to multiplex dcu dau_rvalid to diucpurvalid. cpu_read_complete(1) is also used to pop the second from top read command queue location from the read command queue. cpuread~complete(1) = (read-type == non-CPU read) 30 AND SECOND(readtype == CPU read) AND (dcu-dau-rvalid == 1) 22.14.13.1.4 Multiplexing dcudaurvalid readtype[4:0] and cpuread completely) multiplexes the data valid signal, dcudau_-valid, from the DCU, between the CPU and the shared read bus logic. diucpu valid is the read valid signal going to the CPU. 35 noncpu_rvalid is the read valid signal used by the Read Multiplexor control logic to generate read valid signals for non-CPU reads. if read-type[4:0] == CPU-read then //select CPU 40 diu_cpu_rvalid:= 1 WO 2005/120835 PCT/AU2004/000706 720 noncpu-rvalid:= 0 if (readtype[4:0]== non-CPU-read) AND SECOND(read_type(4:0]== CPU read) AND dcu-dau-rvalid == 1 then 5 //select CPU diu-cpurvalid:= 1 noncpu-rvalid:= 0 else //select shared read bus logic 10 diu-cpurvalid:= 0 noncpurvalid:= 1 22.14.13.1.5 Non-CPU reads Read data for the shared read bus is registered in the shared read data buffer using noncpu_rvalid. The shared read buffer has 4 locations of 64 bits with separate read pointer, readptr[:J0], and write pointer, 15 writeyptr[1:0]. if noncpurvalid == 1 then sharedread_databuffer[writeptr] = dcudaudata[63:0] sharedread_databuffer(writeptr+l] = dcu.daudata[127:64] 20 shared_read_data_buffer[writeptr+2] = dcu-dau-data(191:128] sharedreaddata-buffer[write-ptr+3] = dcudaudata[255:192] The data written into the shared read buffer must be output to the correct SoPEC DIU read requestor according to the value of readtype[4:0] at the top of the command queue. The data is output 64 bits at a time on diu_data[63:0] according to a multiplexor controlled by read_ptr[2:0]. 25 diu-data[63:0) = sharedreaddatabuffer[readptr Figure 139 shows how read _ype[4:0] also selects which shared read bus requesters diu_<unit>_rvalid signal is connected to sharedrvalid. Since the data from the DCU is registered in the Read Multiplexor then 30 sharedrvalid is a delayed version of noncpu valid. When the read valid, diu <unit> valid, for the command associated with read type[4:0] has been asserted for 4 cycles then a signal sharedreadcomplete is asserted. This indicates that the read has completed. shared read complete causes the value of readtype[4:0] in the read command queue to be popped. A state machine for shared read bus access is shown in Figure 142. This show the generation of 35 sharedrvalid, sharedread_complete and the shared read data buffer read pointer, read_ptr[2:0], being incremented. Some points to note from Figure 142 are: * sharedrvalid is asserted the cycle after dcudau rvalid associated with a shared read bus access. This matches the cycle delay in capturing dau_dcu_data[255:0] in the shared read data buffer. 40 shared valid remains asserted in the case of back to back shared read bus accesses. " sharedreadcomplete is asserted in the last sharedrvalid cycle of a non-CPU access. sharedread complete causes the shared read data queue to be popped.
WO 2005/120835 PCT/AU2004/000706 721 22.14.13.1.6 Read command queue read pointer logic The read command queue read pointer logic works as follows. if sharedreadcomplete == 1 OR cpureadcomplete(O) == 1 then 5 PoP top of read command queue if cpu-readcomplete(l) == 1 then POP second read command queue location 22.14.13.1.7 Debug signals sharedreadcomplete and cpu_read_complete together define read complete which indicates to the debug 10 logic that a read has completed. The source of the read is indicated on readsel[4:0]. read-complete = sharedread complete OR cpu-read complete(O) OR cpuread_complete (1) if cpureadcomplete(l) == 1 then 15 read_sel:= SECOND(readtype) else read_sel:= read-type 22.14.13.1.8 Flow control There are separate indications that the Read Multiplexor is able to accept CPU and shared read bus commands 20 from the Arbitration Logic. These are indicated by read cmd rdy[1:0]. The Arbitration Logic can always issue CPU reads except if the read command queue fills. The read command queue should be large enough that this should never occur. //Read Multiplexor ready for Arbitration Logic to issue CPU reads 25 readcmdrdy[O] == read command queue not full For the shared read data, the Read Multiplexor deasserts the shared read bus readcmdrdy[1] indication until a space is available in the read command queue. The read command queue should be large enough that this should never occur. read_cmdrdy[1] is also deasserted to provide flow control back to the Arbitration Logic to keep the shared 30 read data bus just full. //Read Multiplexor not ready for Arbitration Logic to issue non-CPU reads read_cmd-rdy[l] = (read command queue not full) AND (flowcontrol = 0) 35 The flow control condition is that DCU read data from the second of two back-to-back shared read bus accesses becomes available. This causes readcmdrdy[1] to de-assert for 1 cycle, resulting in a repeated MSN2 DCU state. The timing is shown in Figure 143. 40 flow-control = (read type[4:0] == non-CPU read) WO 2005/120835 PCT/AU2004/000706 722 AND SECOND(read-type[4:0] == non-CPU read) AND (current DCU state == MSN2) AND (previous DCU state == MSN1). 5 Figure 143 shows a series of back to back transfers over the shared read data bus. The exact timing of the implementation must not introduce any additional latency on shared read bus read transfers i.e. arbitration must be re-enabled just in time to keep back to back shared read bus data full. The following sequence of events is illustrated in Figure 143: * Data from the first DRAM access is written into the shared read data buffer. 10 * Data from the second access is available 3 cycles later, but its transfer into the shared read buffer is delayed by a cycle, due to the MSN2 stall condition. (During this delay, read data for access 2 is maintained at the output of the DRAM.) A similar 1-cycle delay is introduced for every subsequent read access until the back-to-back sequence comes to an end. * Note that arbitration always occurs during the last MSN2 state of any access. So, for the second 15 and later of any back-to-back non-CPU reads, arbitration is delayed by one cycle, i.e. it occurs every fourth cycle instead of the standard every third. This mechanism provides flow control back to the Arbitration Logic sub-block. Using this mechanism means that the access rate will be limited to which ever takes longer - DRAM access or transfer of read data over the shared read data bus. CPU reads are always be accepted by the Read Multiplexor. 20 22.14.13 Write Multiplexor logic description The Write Multiplexor supplies write data to the DCU. There are two separate write channels, one for CPU data on cpudiuwdata[127:O], one for non-CPU data on wdata[255:0]. A signal write-datavalid[1:0] indicates to the Command Multiplexor that the data is valid. The Command Multiplexor then asserts a signal writedataaccept[1:0] indicating that the data has been 25 captured by the DRAM and the appropriate channel in the Write Multiplexor can accept the next write data. Timing waveforms for write accesses are shown in Figure 105 to Figure 107, respectively. There are 3 types of write accesses: * CPU accesses CPU write data on cpudiuwdata[127:0J is output on cpu wdata[127:0]. Since CPU writes are posted, a 30 local buffer is used to store the write data, address and mask until the CPU wins arbitration. This buffer is one position deep. writedatavalid[0], which is synonymous with /diu cpu _write_ rdy, remains asserted until the Command Multiplexor indicates it has been written to the DRAM by asserting write dataaccept[0]. The CPU write buffer can then accept new posted writes. For non-CPU writes, the Write Multiplexor multiplexes the write data from the DIU write requester to the 35 write data buffer and the <unit>_diu_wvalid signal to the write multiplexor control logic. * CDU accesses 64-bits of write data each for a masked write to a separate 256-bit word are transferred to the Write Multiplexor over 4 cycles.
WO 2005/120835 PCT/AU2004/000706 723 When a CDU write is selected the first 64-bits of write data on cdudiuwdata[63:0] are multiplexed to non_cpuwdata[63:0]. writedata valid[1] is asserted to indicate a non-CPU access when cdudiuwvalid is asserted. The data is also written into the first location in the write data buffer. This is so that the data can continue to be output on noncpu wdata[63:0] and writedatavalid[1] remains asserted until the Command 5 Multiplexor indicates it has been written to the DRAM by asserting write data-accept[1]. Data continues to be accepted from the CDU and is written into the other locations in the write data buffer. Successive writedata accept[J] pulses cause the successive 64-bit data words to be output on wdata[63:0] together with writedatavalid[1]. The last writedata accept[1] means the write buffer is empty and new write data can be accepted. 10 * Other write accesses. 256-bits of write data are transferred to the Write Multiplexor over 4 successive cycles. When a write is selected the first 64-bits of write data on <unit>_diu_wdata[63:0] are written into the write data buffer. The next 64-bits of data are written to the buffer in successive cycles. Once the last 64-bit word is available on <unit>_diuwdata[63:0] the entire word is output on non cpuwdata[255:0], write datavalid 15 [1] is asserted to indicate a non-CPU access, and the last 64-bit word is written into the last location in the write data buffer. Data continues to be output on noncpuwdata[255:0] and writedata valid[1] remains asserted until the Command Multiplexor indicates it has been written to the DRAM by asserting writedata accept[J]. New write data can then be written into the write buffer. 20 CPU write multiplexor control logic When the Command Multiplexor has issued the CPU write it asserts writedataaccept[0]. writedata accept[0] causes the write multiplexor to assert writecmd rdy[0]. The signal write cmd rdy[0] tells the Arbitration Logic sub-block that it can issue another CPU write command i.e. the CPU write data buffer is empty. 25 Non-CPU write multiplexor control logic The signal write cmd rdy[1] tells the Arbitration Logic sub-block that the Write Multiplexor is ready to accept another non-CPU write command. When write cmd rdy[J] is asserted the Arbitration Logic can issue a write command to the Write Multiplexor. It does this by writing the value of arb sel[4:0] which indicates 30 which SoPEC Unit has won arbitration into a write command register, writecmd[3:0]. write_en = arb_gnt AND dirsel[1]==1 AND arb_sel = non-CPU if write-en==l then write-cmd = arbsel 35 The encoding of arbsel[4:0] is given in Table 133. dirsel[1]==1 indicates that the operation is a write. arbsel[4:0] is only written to the write command register if the write is a non-CPU write. A rule was introduced in Section 22.7.2.3 Interleaving read and write accesses to the effect that non-CPU write accesses would not be allocated adjacent timeslots. This means that a single write command register is required.
WO 2005/120835 PCT/AU2004/000706 724 The write command register, writecmd[3:0], indicates the source of the write data. write_cmd[3:0] multiplexes the write data <unit>_diu_wdata, and the data valid signal, <unit>_diu_wvalid, from the selected write requestor to the write data buffer. Note, that CPU write data is not included in the multiplex as the CPU has its own write channel. The <unit>_diuwvalid are counted to generate the signal word sel[1:0] which 5 decides which 64-bit word of the write data buffer to store the data from <unit>_diuwdata. //when the Command Multiplexor accepts the write data if write_data_acceptl] = 1 then //reset the word select signal 10 wordsel[1:0]=00 //when wvalid is asserted if wvalid = 1 then //increment the word select signal if wordsel[1:0) 11 then 15 word sel[1:0] == 00 else word-sel[1:0] == wordsel[1:0] + 1 wvalid is the <unit>_diu_wvalid signal multiplexed by write cmd[3:0]. wordsel[J:0 is reset 20 when the Command Multiplexor accepts the write data. This is to ensure that wordsel[1:0] is always starts at 00 for the first wvalid pulse of a 4 cycle write data transfer. The write command register is able to accept the next write when the Command Multiplexor accepts the write data by asserting writedataaccept[1]. Only the last writedata accept[1] pulse associated with a CDU access (there are 4) will cause the write command register to be ready to accept the next write data. 25 Flow control back to the Command Multiplexor write_cmd rdy[0] is asserted when the CPU data buffer is empty. writecmd rdy[1] is asserted when both the write command register and the write data buffer is empty. 30 PEP Subsystem 23 CONTROLLER UNIT (PCU) 23.1 OVERVIEW The PCU has three functions: 35 - The first is to act as a bus bridge between the CPU-bus and the PCU-bus for reading and writing PEP configuration registers. e The second is to support page banding by allowing the PEP blocks to be reprogrammed between bands by retrieving commands from DRAM instead of being programmed directly by the CPU. * The third is to send register debug information to the RDU, within the CPU subsystem, when the 40 PCU is in Debug Mode.
WO 2005/120835 PCT/AU2004/000706 725 23.2 INTERFACES BETWEEN PCU AND OTHER UNITS 23.3 BUS BRIDGE The PCU is a bus-bridge between the CPU-bus and the PCU-bus. The PCU is a slave on the CPU-bus but is the only master on the PCU-bus. See Figure 14 on page 43. 5 23.3.1 CPU accessing PEP All the blocks in the PEP can be addressed by the CPU via the PCU. The MMU in the CPU-subsystem decodes a PCU select signal, cpu_pcusel, for all the PCU mapped addresses (see section 11.4.3 on page 77). Using cpuadr bits 15-12 the PCU decodes individual block selects for each of the blocks within the PEP. The PEP blocks then decode the remaining address bits needed to address their PCU-bus mapped registers. 10 Note: the CPU is only permitted to perform supervisor-mode data-type accesses of the PEP, i.e. cpu _acode = 11. If the PCU is selected by the CPU and any other code is present on the cpuacode bus the access is ignored by the PCU and the pcucpuberr signal is strobed, CPU commands have priority over DRAM commands. When the PCU is executing each set of four commands retrieved from DRAM the CPU can access PCU-bus registers. In the case that DRAM commands 15 are being executed and the CPU resets the CmdSource to zero, the contents of the DRAM CmdFifo is invalidated and no further commands from the fifo are executed. The CmdPending and NextBandCmdEnable work registers are also cleared. When a DRAM command writes to the CmdAdr register it means the next DRAM access will occur at the address written to CmdAdr. Therefore if the JUMP instruction is the first command in a group of four, the 20 other three commands get executed and then the PCU will issue a read request to DRAM at the address specified by the JUMP instruction. If the JUMP instruction is the second command then the following two commands will be executed before the PCU requests from the new DRAM address specified by the JUMP instruction etc. Therefore the PCU will always execute the remaining commands in each four command group before carrying out the JUMP instruction. 25 23.4 PAGE BANDING The PCU can be programmed to associate microcode in DRAM with each finishedband signal. When a finishedband signal is asserted the PCU reads commands from DRAM and executes these commands. These commands are each 64-bits (see Section 23.8.5) and consist of 32-bit address bits and 32 data bits and allow PCU mapped registers to be programmed directly by the PCU. 30 If more than one finishedband signal is received at the same time, or others are received while microcode is already executing, the PCU holds the commands as pending, and executes them at the first opportunity. Each microcode program associated with cdu_finishedband, lbd_finishedband and te_finishedband typically restarts the appropriate unit with new addresses - a total of about 4 or 5 microcode instructions. As well, or alternatively, pcujfinishedband can be used to set up all of the units and therefore involves many more 35 instructions. This minimizes the time that a unit is idle in between bands. The pcu_finishedband control signal WO 2005/120835 PCT/AU2004/000706 726 is issued once the specified combination of CDU, LBD and TE (programmed in BandSelectMask) have finished their processing for a band. 23.5 INTERRUPTS, ADDRESS LEGALITY AND SECURITY 5 Interrupts are generated when the various page expansion units have finished a particular band of data from DRAM. The cdu_finishedband, lbd_finishedband and te_finishedband signals are combined in the PCU into a single interrupt pcujfinishedband which is exported by the PCU to the interrupt controller (ICU). The PCU mapped registers are only accessible from Supervisor Data Mode. The area of DRAM where PCU commands are stored should be a Supervisor Mode only DRAM area, although this is enforced by the MMU 10 and not by the PCU. When the PCU is executing commands from DRAM, any block-address decoded from a command which is not part of the PEP block-address map causes the PCU to ignore the command and strobe the pcuicu_addressinvalid interrupt signal. The CPU can then interrogate the PCU to find the source of the illegal command. The MMU ensures that the CPU cannot address an invalid PEP subsystem block. 15 When the PCU is executing commands from DRAM, any address decoded from a command which is not part of the PEP address map causes the PCU to: * Cease execution of current command and flush all remaining commands already retrieved from DRAM. * Clear CmdPending work-register. 20 e Clear NextBandCmdEnable registers. * Set CmdSource to zero. In addition to cancelling all current and pending DRAM accesses the PCU strobes the pcu icuaddressinvalid interrupt signal. The CPU can then interrogate the PCU to find the source of the illegal command. 25 23.6 DEBUG MODE When there is a need to monitor the (possibly changing) value in any PEP configuration register, the PCU can be placed in Debug Mode. This is done via the CPU setting the DebugSelect register within the PCU. Once in Debug Mode the PCU continually reads the target PEP configuration register and sends the read value to the 30 RDU. Debug Mode has the lowest priority of all PCU functions: if the CPU wishes to perform an access or there are DRAM commands to be executed they will interrupt the Debug access, and the PCU only resumes Debug access once a CPU or DRAM command has completed.
WO 2005/120835 PCT/AU2004/000706 727 23.7 IMPLEMENTATION 23.7.1 Definitions of 1/0 Table 139. PCU Port List Clocks and Resets Pclk 1 In SoPEC functional clock Prst_n 1 In Active-low, synchronous reset in pclk domain End of Band Functionality Cdufinishedband 1 In Finished band signal from CDU Lbdfinishedband 1 In Finished band signal from LBD te_finishedband 1 In Finished band signal from TE Pcufinishedband 1 Out Asserted once the specified combination of CDU, LBD, and TE have finished their processing for a band. PCU address error Pcuicuaddress_invalid I 1 Out Strobed if PCU decodes a non PEP address from commands retrieved from DRAM or CPU. CPU Subsystem Interface Signals Cpu-adr[15:2] 14 In CPU address bus. 14 bits are required to decode the address space for the PEP. Cpu-dataout[31:0] 32 In Shared write data bus from the CPU Pcucpu-data[31:0] 32 Out Read data bus to the CPU Cpu_rwn 1 In Common read/not-write signal from the CPU Cpu-acode[1:0] 2 In CPU Access Code signals. These decode as follows: 00 - User program access 01 - User data access 10 - Supervisor program access 11 - Supervisor data access Cpu-pcu-sel 1 In Block select from the CPU. When cpujpcusel is high both cpuadr and cpu.dataout are valid Pcu-cpu-rdy 1 Out Ready signal to the CPU. When pcLLcpurdy is high it indicates the last cycle of the access. For a write cycle this means cpu._dataout has been registered by the block and for a read cycle this means the data on pcucpudata is valid. Pcu-cpu-berr 1 Out Bus error signal to the CPU indicating an invalid access. Pcu-cpu-debug-valid 1 Out Debug Data valid on pcucpu_data bus. Active high. PCU Interface to PEP blocks WO 2005/120835 PCT/AU2004/000706 728 Pcu-adr[l 1:2] 10 Out PCU address bus. The 10 least significant bits of cpu adr [15:2] allow 1024 32-bit word addressable locations per PEP block. Only the number of bits required to decode the address space are exported to each block. Pcu-dataout[31:0] 32 Out Shared write data bus from the PCU <unit>_pcu-datain[31:0] 32 In Read data bus from each PEP subblock to the PCU Pcurwn 1 Out Common read/not-write signal from the PCU Pcu_<unit>_sel 1 Out Block select for each PEP block from the PCU. Decoded from the 4 most significant bits of cpuadr[15:2]. When pcu_<unit>_sel is high both pcuadr and pcudataout are valid <unit>_pcu-rdy 1 In Ready from each PEP block signal to the PCU. When <unit>_pcuLrdy is high it indicates the last cycle of the access. For a write cycle this means pcudataout has been registered by the block and for a read cycle this means the data on <unit>_pcudatain is valid. DIU Read Interface signals Pcu-diu-rreq 1 Out PCU requests DRAM read. A read request must be accompanied by a valid read address. Pcu-diu-radr[21:5] 17 Out Read address to DIU 17 bits wide (256-bit aligned word). Diu-pcu-rack 1 In Acknowledge from DIU that read request has been accepted and new read address can be placed on pcu diu_radr Diu.data[63:0] 64 In Data from DIU to PCU. First 64-bits is bits 63:0 of 256 bit word Second 64-bits is bits 127:64 of 256 bit word Third 64-bits is bits 191:128 of 256 bit word Fourth 64-bits is bits 255:192 of 256 bit word Diu.pcu-rvalid 1 In Signal from DIU telling PCU that valid read data is on the diu-data bus 23.7.1 23.7.2 Configuration Registers Table 140. PCU Configuration Registers Conrorgsterstr#it etdsrito 0x00 Reset 1 0x1 A write to this register causes a reset of the PCU. This register can be read to indicate the reset state: 0 - reset in progress 1 - reset not in progress WO 2005/120835 PCT/AU2004/000706 729 0x04 CmdAdr[210:5] 17 OxOO The address of the next set of commands to (256-bit aligned DRAM 00 retrieve from DRAM. address) When this register is written to, either by the CPU or DRAM command, 1 is also written to CmdSource to cause the execution of the commands at the specified address. OxO8 BandSelectMask[2:0] 3 Ox0 Selects which input finishedBand flags are to be watched to generate the combined pcu_finishedband signal. BitO - lbd finishedband Bit1 - cdu finishedband Bit2 - tefinishedband OxOC, 0x10, NextBandCmdAdr3:0][2 4x107 OxOOO The address to transfer to CmdAdr as soon Oxi 4, Oxi8 1:5] 00 as possible after the next finishedBand[n] (256-bit aligned DRAM signal has been received as long as address) NextBandCmdEnable[n] is set. A write from the PCU to NextBandCmdAdr[n] with a non-zero value also sets NextBandCmdEnable[n]. A write from the PCU to NextBandCmdAdr[n] with a 0 value clears NextBandCmdEnable[n]. Ox1C NextCmdAdr[21:5] 17 OxOO The address to transfer to CmdAdr when the 00 CPU pending bit (CmdPending[4) get serviced. A write from the PCU to NextCmdAdr[n] with a non-zero value also sets CmdPending[4]. A write from the PCU to NextCmdAdr[n] with a 0 value clears CmdPending[4] 0x20 CmdSource 1 Ox0 0 - commands are taken from the CPU 1 - commands are taken from the-CPU as well as DRAM at CmdAdr. Ox24 DebugSelect[15:2] 14 OxOO Debug address select. Indicates the address 0 of the register to report on the pcu cpudata bus when it is not otherwise being used, and the PEP bus is not being used Bits [15:12] select the unit (see Table 141) Bits [11:2] select the register within the unit Work registers (read only) 0x28 InvalidAddress[21:3] 19 0 DRAM Address of current 64-bit command (64-bit aligned DRAM) attempting to execute. Read only register. Ox2C CmdPending 5 Ox00 For each bit n, where n is 0 to 3 0 -no commands pending for NextBandCmdAdr[n] 1 -commands pending for NextBandCmdAdr[n] For bit 4 0 -no commands pending for NextCmdAdr[n] 1 -commands pending for NextCmdAdr[n] Read only register. Ox34 FinishedSoFar 3 Ox0 The appropriate bit is set whenever the corresponding input finishedBand flag is set and the corresponding bit in the BandSelectMask bit is also set. If all FinishedSoFar bits are set wherever BandSelect bits are also set, all FinishedSoFar bits are cleared and the output pcujfinishedband signal is given. Read only register.
WO 2005/120835 PCT/AU2004/000706 730 Ox38 NextBandCmdEnable 4 Ox0 This register can be written to indirectly (i.e. the bits are set or cleared via writes to NextBandCmdAdr[n]) For each bit: 0 - do nothing at the next finishedBand[n] signal. 1 - Execute instructions at NextBandCmdAdr[n] as soon as possible after receipt of the next finishedBand[n] signal. BitO - lbdfinishedband Bit1 - cdu finishedband Bit2 -tefinishedband Bit3 - pcu_finishedband Read only register. 23.7.2 23.8 DETAILED DESCRIPTION 23.8.1 PEP Blocks Register Map All PEP accesses are 32-bit register accesses. 5 From Table 141 it can be seen that four bits only are necessary to address each of the sub-blocks within the PEP part of SoPEC. Up to 14 bits may be used to address any configurable 32-bit register within PEP. This gives scope for 1024 configurable registers per sub-block. This address comes either from the CPU or from a command stored in DRAM. The bus is assembled as follows: e adr[15:12] = sub-block address 10 e adr[n:2] = 32-bit register address within sub-block, only the number of bits required to decode the registers within each sub-block are used. Table 141. PEP blocks Register Map PCU Ox0 CDU 0x1 CFU Wx LBD Ox3 SFU Ox4 TE Ox5 TFU Ox6 HCU Ox7 DNC Ox8 DWU Ox9 WO 2005/120835 PCT/AU2004/000706 731 LLU OxA PHI OxB Reserved OxC to OxF 23.8.2 Internal PCU PEP protocol The PCU performs PEP configuration register accesses via a select signal, pcu_<block>_sel. The read/write sense of the access is communicated via the pcu rwn signal (1 = read, 0 = write). Write data is clocked out, and read data clocked in upon receipt of the appropriate select-read/write-address combination. 5 Figure 146 shows a write operation followed by a read operation. The read operation is shown with wait states while the PEP block returns the read data. For access to the PEP blocks a simple bus protocol is used. The PCU first determines which particular PEP 10 block is being addressed so. that the appropriate block select signal can be generated. During a write access PCU write data is driven out with the address and block select signals in the first cycle of an access. The addressed PEP block responds by asserting its ready signal indicating that it has registered the write data and the access can complete. The write data bus is common to all PEP blocks. 15 A read access is initiated by driving the address and select signals during the first cycle of an access. The addressed PEP block responds by placing the read data on its bus and asserting its ready signal to indicate to the PCU that the read data is valid. Each block has a separate point-to-point data bus for read accesses to avoid the need for a tri-stateable bus. Consecutive accesses to a PEP block must be separated by at least a single cycle, during which the select 20 signal must be de-asserted. 23.8.3PCU DRAM access requirements The PCU can execute register programming commands stored in DRAM. These commands can be executed at the start of a print run to initialize all the registers of PEP. The PCU can also execute instructions at the 25 start of a page, and between bands. In the inter-band time, it is critical to have the PCU operate as fast as possible. Therefore in the inter-page and inter-band time the PCU needs to get low latency access to DRAM. A typical band change requires on the order of 4 commands to restart each of the CDU, LBD, and TE, followed by a single command to terminate the DRAM command stream. This is on the order of 5 commands per restart component. 30 The PCU does single 256 bit reads from DRAM. Each PCU command is 64 bits so each 256 bit DRAM read can contain 4 PCU commands. The requested command is read from DRAM together with the next 3 contiguous 64-bits which are cached to avoid unnecessary DRAM reads. Writing zero to CmdSource causes the PCU to flush commands and terminate program access from DRAM for that command stream. The PCU requires a 256-bit buffer to the 4 PCU commands read by each 256-bit DRAM access. When the buffer is 35 empty the PCU can request DRAM access again.
WO 2005/120835 PCT/AU2004/000706 732 1024 commands of 64 bits requires 8 Kbytes of DRAM storage. Programs stored in DRAM are referred to as PCU Program Code. 23.8.4 End of band unit The state machine is responsible for watching the various input xxfinishedband signals, setting the 5 FinishedSoFar flags, and outputting the pcufinishedband flags as specified by the BandSelect register. Each cycle, the end of band unit performs the following tasks: pcufinishedband = (FinishedSoFar[Ol == BandSelectMask[0]) AND (FinishedSoFar(l] == BandSelectMask(l]) AND 10 (FinishedSoFar[2] == BandSelectMask(2]) AND (BandSelectMask[O] OR BandSelectMask[l] OR BandSelectMask [2]) if (pcu-finishedband == 1) then FinishedSoFar[O] = 0 15 FinishedSoFar[l] = 0 FinishedSoFar[2] = 0 else FinishedSoFar[0] = (FinishedSoFar[0] OR lbd_finishedband) AND BandSelectMask[0] 20 FinishedSoFar[l] = (FinishedSoFar[l] OR cdu-finishedband) AND BandSelectMask(1] FinishedSoFar[2] = (FinishedSoFar[2] OR tefinishedband) AND BandSelectMask[2] 25 Note that it is the responsibility of the microcode at the start of printing a page to ensure that all 3 FinishedSoFar bits are cleared. It is not necessary to clear them between bands since this happens automatically. If a bit of BandSelectMask is cleared, then the corresponding bit of FinishedSoFar has no impact on the generation ofpcu_finishedband. 30 23.8.5 Executing commands from DRAM Registers in PEP can be programmed by means of simple 64-bit commands fetched from DRAM. The format of the commands is given in Table 142. Register locations can have a data value of up to 32 bits. Commands are PEP register write commands only. Table 142. Register write commands in PEP Register write data zero 32-bit zero word address 35 Due attention must be paid to the endianness of the processor. The LEON processor is a big-endian processor.
WO 2005/120835 PCT/AU2004/000706 733 23.8.6 General Operation Upon a Reset condition, CmdSource is cleared (to 0), which means that all commands are initially sourced only from the CPU bus interface. Registers and can then be written to or read from one location at a time via 5 the CPU bus interface. If CmdSource is 1, commands are sourced from the DRAM at CmdAdr and from the CPU bus. Writing an address to CmdAdr automatically sets CmdSource to 1, and causes a command stream to be retrieved from DRAM. The PCU executes commands from the CPU or from the DRAM command stream, giving higher priority to the CPU always. 10 If CmdSource is 0 the DRAM requestor examines the CmdPending bits to determine if a new DRAM command stream is pending. If any of CmdPending bits are set, then the appropriate NextBandCmdAdr or NextCmdAdr is copied to CmdAdr (causing CmdSource to get set to 1) and a new command DRAM stream is retrieved from DRAM and executed by the PCU. If there are multiple pending commands the DRAM requestor will service the lowest number pending bit first. Note that a new DRAM command stream only gets 15 retrieved when the current command stream is empty. If there are no DRAM commands pending, and no CPU commands the PCU defaults to an idle state. When idle the PCU address bus defaults to the DebugSelect register value (bits 11 to 2 in particular) and the default unit PCU data bus is reflected to the CPU data bus. The default unit is determined by the DebugSelect register bits 15 to 12. 20 In conjunction with this, upon receipt of a finishedBand[n] signal, NextBandCmdEnable[n] is copied to CmdPending[n] and NextBandCmdEnable[n] is cleared. Note, each of the LBD, CDU, and TE (where present) may be re-programmed individually between bands by appropriately setting NextBandCmdAdr[2-0] respectively. However, execution of inter-band commands may be postponed until all blocks specified in the BandSelectMask register have pulsed their finishedband signal. This may be accomplished by only setting 25 NextBandCmdAdr[3] (indirectly causing NextBandCmdEnable[3] to be set) in which case it is the pcu_finishedband signal which causes NextBandCmdEnable[3] to be copied to CmdPending[3]. To conveniently update multiple registers, for example at the start of printing a page, a series of Write Register commands can be stored in DRAM. When the start address of the first Write Register command is written to the CmdAdr register (via the CPU), the CmdSource register is automatically set to 1 to actually start 30 the execution at CmdAdr. Alternatively the CPU can write to NextCmdAdr causing the CmdPending[4] bit to get set, which will then get serviced by the DRAM requestor in the pending bit arbitration order. The final instruction in the command block stored in DRAM must be a register write of 0 to CmdSource so that no more commands are read from DRAM. Subsequent commands will come from pending programs or can be sent via the CPU bus interface. 35 23.8.6.1 Debug Mode Debug mode is implemented by reusing the normal CPU and DRAM access decode logic. When in the Arbitrate state (see state machine A below), the PEP address bus is defaulted to the value in the DebugSelect register. The top bits of the DebugSelect register are used to decode a select to a PEP unit and the remaining WO 2005/120835 PCT/AU2004/000706 734 bits are reflected on the PEP address bus. The selected units read data bus is reflected on the pcucpudata bus to the RDU in the CPU. The pcucpudebugvalid signal indicates to the RDU that the data on the pcucpu_data bus is valid debug data. Normal CPU and DRAM command access requires the PEP bus, and as such causes the debug data to be 5 invalid during the access. This is indicated to the RDU by setting pcucpudebugvalid to zero. The decode logic is: // Default Debug decode if state == Arbitrate then if (cpu.pcu-sel == 1 AND cpu-acode /= SUPERVISOR_DATA_MODE) then 10 pcu-cpudebugvalid = 0 // bus error condition pcucpudata = 0 else <unit> = decode (DebugSelect(15:12]) if (<unit> == PCU) then 15 pcu_cpudata = Internal PCU register else pcucpudata = <uni t>_pcudatain [31 0] pcuadr[11:2] = DebugSelect[ll:2] pcucpu_debug_valid = 1 AFTER 4 clock cycles 20 else pcucpudebug_valid = 0 23.8.7 State Machines DRAM command fetching and general command execution is accomplished using two state machines. State machine A evaluates whether a CPU or DRAM command is being executed, and proceeds to execute the 25 command(s). Since the CPU has priority over the DRAM it is permitted to interrupt the execution of a stream of DRAM commands. Machine B decides which address should be used for DRAM access, fetches commands from DRAM and fills a command fifo which A executes. The reason for separating the two functions is to facilitate the execution of CPU or Debug commands while state machine B is performing DRAM reads and filling the command fifo. In 30 the case where state machine A is ready to execute commands (in its Arbitrate state) and it sees both a full DRAM command fifo and an active cpu_pcu_sel then the DRAM commands are executed last. 23.8.7.1 State Machine A: Arbitration and execution of commands The state-machine enters the Reset state when there is an active strobe on either the reset pin, prst n, or the PCU's soft-reset register. All registers in the PCU are zeroed, unless otherwise specified, on the next rising 35 clock edge. The PCU self-deasserts the soft reset in the pclk cycle after it has been asserted. The state changes from Reset to Arbitrate when prst n = 1 and PCU softreset = 1. The state-machine waits in the Arbitrate state until it detects a request for CPU access to the PEP units (cpu_pcusel = 1 and cpu acode = 11) or a request to execute DRAM commands CmdSource = 1, and DRAM commands are available, CmdFifoFull=l. Note if (cpu_pcuset = 1 and cpuacode!= 11) the CPU 40 is attempting an illegal access. The PCU ignores this command and strobes the cpupcu berr for one cycle. While in the Arbitrate state the machine assigns the DebugSelect register to the PCU unit decode logic and the remaining bits to the PEP address bus. When in this state the debug data returned from the selected PEP unit is reflected on the CPU bus (pcu_ cpudata bus) and the pcucpudebugvalid= 1.
WO 2005/120835 PCT/AU2004/000706 735 If a CPU access request is detected (cpu_pcuse= 1 and cpuacode = 11) then the machine proceeds to the CpuAccess state. In the CpuAccess state the cpu address is decoded and used to determine the PEP unit to select. The remaining address bits are passed through to the PEP address bus. The machine remains in the CpuAccess state until a valid ready from the selected PEP unit is received. When received the machine returns 5 to the arbitrate state, and the ready signal to the CPU is pulsed. // decode the logic pcu_<unit>_sel = decode(cpuadr(15:12]) pcu-adr[11:2] = cpu-adr[11:2] The CPU is prevented (by the MMU) from generating an invalid PEP unit address and so CPU accesses 10 cannot generate an invalid address error. If the state machine detects a request to execute DRAM commands (CmdSource = 1), it waits in the Arbitrate state until commands have been loaded into the command FIFO from DRAM (all controlled by state machine B). When the DRAM commands are available (cmd_fifo full = 1) the state machine proceeds to the DRAMAccess state. 15 When in the DRAMAccess state the commands are executed from the cmdfifo. A command in the cmdfifo consists of 64-bits (or which the FIFO holds 4). The decoding of the 64-bits to commands is given in Table 142. For each command the decode is // DRAM command decode pcu_<unit>_sel = decode( cmd_fifo[cmd-count] (15:12] 20 pcu-adr[11:2] = cmd-fifo[cmd-count][11:2] pcu_dataout = cmdfifo[cmd-count][63:32] When the selected PEP unit returns a ready signal (<unit>_pcu rdy==1) indicating the command has completed, the state machine returns to the Arbitrate state. If more commands exists (cmdcount !=O) the transition decrements the command count. 25 When in the DRAMAccess state, if when decoding the DRAM command address bus (cmd_fifo[cmdcount][15:12]), the address selects a reserved address, the state machine proceeds to the AdrError state, and then back to the Arbitrate state. An address error interrupt is generated and the DRAM command FIFOs are cleared. A CPU access can pre-empt any pending DRAM commands. After each command is completed the state 30 machine returns to the Arbitrate state. If a CPU access is required and DRAM command stream is executing the CPU access always takes priority. If a CPU or DRAM command sets the CmdSource to 0, all subsequent DRAM commands in the command FIFO are cleared. If the CPU sets the CmdSource to 0 the CmdPending and NextBandCmdEnable work registers are also cleared. 23.8.7.2 State Machine B: Fetching DRAM commands 35 A system reset (prst n=0) or a software reset (pcu soft reset n==0) causes the state machine to reset to the Reset state. The state machine remains in the Reset until both reset conditions are removed. When removed the machine proceeds to the Wait state. The state machine waits in the Wait state until it determines that commands are needed from DRAM. Two possible conditions exist that require DRAM access. Either the PCU is processing commands which must be 40 fetched from DRAM (cmd-source=1), and the command FIFO is empty (cmd fifofull=0), or the cmdsource=0 and the command FIFO is empty and there are some commands pending (cmdpending !=0).
WO 2005/120835 PCT/AU2004/000706 736 In either of these conditions the machine proceeds to the Ack state and issues a read request to DRAM (pcudiurreq=l), it calculates the address to read from dependent on the transition condition. In the command pending transition condition, the highest priority NextBandCmdAdr (or NextCmdAdr) that is pending is used for the read address (pcudiuradr) and is also copied to the CmdAdr register. If multiple 5 pending bits are set the lowest pending bits are serviced first. In the normal PCU processing transition the pcu-diuradr is the CmdAdr register. When an acknowledge is received from the DRAM the state machine goes to the FillFifo state. In the FillFifo state the machine waits for the DRAM to respond to the read request and transfer data words. On receipt of the first word of data diu_pcurvalid=1, the machine stores the 64-bit data word in the command FIFO 10 (cmdfifo[3j) and transitions to the Data], Data2, Data3 states each time waiting for a diujpcurvalid==1 and storing the transferred data word to cmdfifo[2], cmdjifo[1] and cmdfifo[0] respectively. When the transfer is complete the machine returns to the Wait state, setting the cmdcount to 3, the cmdfifo_full is set to 1 and the CmdAdr is incremented. If the CPU sets the CmdSource register to 0 while the PCU is in the middle of a DRAM access, the 15 statemachine returns to the Wait state and the DRAM access is aborted. 23.8.7.3 PCU_ICU_AddressInvalid Interrupt When the PCU is executing commands from DRAM, addresses decoded from commands which are not PCU mapped addresses (4-bits only) will cause the current command to be ignored and the 20 pcu-icuaddressinvalid interrupt signal to be strobed. When an invalid command occurs all remaining commands already retrieved from DRAM are flushed from the CmdFifo, and the CmdPending, NextBandCmdEnable and CmdSource registers are cleared to zero. The CPU can then interrogate the PCU to find the source of the illegal DRAM command via the InvalidAddress register. 25 The CPU is prevented by the MMU from generating an invalid address command. 24 CONTONE DECODER UNIT (CDU) 24.1 OVERVIEW The Contone Decoder Unit (CDU) is responsible for performing the optional decompression of the contone 30 data layer. The input to the CDU is up to 4 planes of compressed contone data in JPEG interleaved format. This will typically be 3 planes, representing a CMY contone image, or 4 planes representing a CMYK contone image. The CDU must support a page of A4 length (11.7 inches) and Letter width (8.5 inches) at a resolution of 267 ppi in 4 colors and a print speed of 1 side per 2 seconds. 35 The CDU and the other page expansion units support the notion of page banding. A compressed page is divided into one or more bands, with a number of bands stored in memory. As a band of the page is consumed for printing a new band can be downloaded. The new band may be for the current page or the next page. Band-finish interrupts have been provided to notify the CPU of free buffer space.
WO 2005/120835 PCT/AU2004/000706 737 The compressed contone data is read from the on-chip DRAM. The output of the CDU is the decompressed contone data, separated into planes. The decompressed contone image is written to a circular buffer in DRAM with an expected minimum size of 12 lines and a configurable maximum. The decompressed contone image is subsequently read a line at a time by the CFU, optionally color converted, scaled up to 1600 ppi and then 5 passed on to the HCU for the next stage in the printing pipeline. The CDU also outputs a cdu_finishedband control flag indicating that the CDU has finished reading a band of compressed contone data in DRAM and that area of DRAM is now free. This flag is used by the PCU and is available as an interrupt to the CPU. 24.2 STORAGE REQUIREMENTS FOR DECOMPRESSED CONTONE DATA IN DRAM A single SoPEC must support a page of A4 length (11.7 inches) and Letter width (8.5 inches) at a resolution 10 of 267 ppi in 4 colors and a print speed of 1 side per 2 seconds. The printheads specified in the Linking Printhead Databook have 13824 nozzles per color to provide full bleed printing for A4 and Letter. At 267 ppi, there are 2304 contone pixels per line represented by 288 JPEG blocks per color. However each of these blocks actually stores data for 8 lines, since a single JPEG block is 8 x 8 pixels. The CDU produces contone data for 8 lines in parallel, while the HCU processes data linearly across a line on a line by line basis. The 15 contone data is decoded only once and then buffered in DRAM. This means two sets of 8 buffer-lines are required - one set of 8 buffer lines is being consumed by the CFU while the other set of 8 buffer lines is being generated by the CDU. The buffer requirement can be reduced by using a 1.5 buffering scheme, where the CDU fills 8 lines while the CFU consumes 4 lines. The buffer space required is a minimum of 12 line stores per color, for a total space of 20 108 KBytes. A circular buffer scheme is employed whereby the CDU may only begin to write a line of JPEG blocks (equals 8 lines of contone data) when there are 8-lines free in the buffer. Once the full 8 lines have been written by the CDU, the CFU may now begin to read them on a line by line basis. This reduction in buffering comes with the cost of an increased peak bandwidth requirement for the CDU write access to DRAM. The CDU must be able to write the decompressed contone at twice the rate at which 25 the CFU reads the data. To allow for trade-offs to be made between peak bandwidth and amount of storage, the size of the circular buffer is configurable. For example, if the circular buffer is configured to be 16 lines it behaves like a double-buffer scheme where the peak bandwidth requirements of the CDU and CFU are equal. An increase over 16 lines allows the CDU to write ahead of the CFU and provides it with a margin to cope with very poor local compression ratios in the image. 30 SoPEC should also provide support for A3 printing and printing at resolutions above 267 ppi. This increases the storage requirement for the decompressed contone data (buffer) in DRAM. Table 143 gives the storage requirements for the decompressed contone data at some sample contone resolutions for different page sizes. It assumes 4 color planes of contone data and a 1.5 buffering scheme.
WO 2005/120835 PCT/AU2004/000706 738 Table 143. Storage requirements for decompressed contone data (buffer) .......... .. 9'.1.-. A4/Letterb 267 6 2304 108d 400 4 3456 162 800 2 6912 324 A3c 267 6 3248 152.25 400 4 4872 228.37 800 2 9744 456.75 a. Required for CFU to convert to final output at 1600 dpi b. Linking printhead has 13824 nozzles per color providing full bleed printing for A4/Letter c. Linking printhead has 19488 nozzles per color providing full bleed printing for A3 5 d. 12 lines x 4 colors x 2304 bytes. 24.3 DECOMPRESSION PERFORMANCE REQUIREMENTS The JPEG decoder core can produce a single color pixel every system clock (pclk) cycle, making it capable of decoding at a peak output rate of 8 bits/cycle. SoPEC processes 1 dot (bi-level in 6 colors) per system clock cycle to achieve a print speed of 1 side per 2 seconds for full bleed A4/Letter printing. The CFU replicates 10 pixels a scale factor (SF) number of times in both the horizontal and vertical directions to convert the final output to 1600 ppi. Thus the CFU consumes a 4 color pixel (32 bits) every SF x SF cycles. The 1.5 buffering scheme described in section 24.2 on page 447 means that the CDU must write the data at twice this rate. With support for 4 colors at 267 ppi, the decompression output bandwidth requirement is 1.78 bits/cycle. The JPEG decoder is fed directly from the main memory via the DRAM interface. The amount of 15 compression determines the input bandwidth requirements for the CDU. As the level of compression increases, the bandwidth decreases, but the quality of the final output image can also decrease. Although the average compression ratio for contone data is expected to be 10:1, the average bandwidth allocated to the CDU allows for a local minimum compression ratio of 5:1 over a single line of JPEG blocks. This equates to a peak input bandwidth requirement of 0.36 bits/cycle for 4 colors at 267 ppi, full bleed A4/Letter printing at 20 1 side per 2 seconds. Table 144 gives the decompression output bandwidth requirements for different resolutions of contone data to meet a print speed of 1 side per 2 seconds. Higher resolution requires higher bandwidth and larger storage for decompressed contone data in DRAM. A resolution of 400 ppi contone data in 4 colors requires 4 bits/cycle, which is practical using a 1.5 buffering scheme. However, a resolution of 800 ppi would require a double 25 buffering scheme (16 lines) so the CDU only has to match the CFU consumption rate. In this case the decompression output bandwidth requirement is 8 bits/cycle, the limiting factor being the output rate of the JPEG decoder core.
WO 2005/120835 PCT/AU2004/000706 739 Table 144. CDU performance requirements for full bleed A4/Letter printing at 1 side per 2 seconds. Contone Sae Decompression output resolution fatr bandwidth requirement { ppi) fatr(bits/cycle)" 267 6 1.78 400 4 4 800 2 8 b a. Assumes 4 color pixel contone data and a 12 line buffer. b. Scale factor 2 requires at least a 16 line buffer. 24.4 DATA FLOW 5 Figure 149 shows the general data flow for contone data - compressed contone planes are read from DRAM by the CDU, and the decompressed contone data is written to the 12-line circular buffer in DRAM. The line buffers are subsequently read by the CFU. The CDU allows the contone data to be passed directly on, which will be the case if the color represented by 10 each color plane in the JPEG image is an available ink. For example, the four colors may be C, M, Y, and K, directly represented by CMYK inks. The four colors may represent gold, metallic green etc. for multi- SoPEC printing with exact colors. However JPEG produces better compression ratios for a given visible quality when luminance and chromninance channels are separated. With CM4YK, K can be considered to be luminance, but C, M, and Y 15 each contain luminance information, and so would need to be compressed with appropriate luminance tables. We therefore provide the means by which CMY can be passed to SoPEC as YCrCb. K does not need color conversion. When being JPEG compressed, CMY is typically converted to RGB, then to YCrCb and then finally JPEG compressed. At decompression, the YCrCb data is obtained and written to the decompressed contone store by the CDU. This is read by the CFU where the YCrCb can then be optionally color converted 20 to RGB, and finally back to CMY. The external RIP provides conversion from RGB to YCrCb, specifically to match the actual hardware implementation of the inverse transform within SoPEC, as per CCIR 601-2 except that Y, Cr and Cb are normalized to occupy all 256 levels of an 8-bit binary encoding. The CFU provides the translation to either RGB or CMIY. RGB is included since it is a necessary step to 25 produce CM1Y, and some printers increase their color gamut by including RGB inks as well as CMYK. 24.5 IMPLEMENTATION A block diagram of the CDU is shown in Figure 150.
WO 2005/120835 PCT/AU2004/000706 740 All output signals from the CDU (cdu cfuwradv8line, cdu_finishedband, cduicujpegerror, and control signals to the DIU) must always be valid after reset. If the CDU is not currently decoding, cducfu_wradv8line, cdu_finishedband and cduicujpegerror will always be 0. The read control unit is responsible for keeping the JPEG decoder's input FIFO full by reading compressed 5 contone bytestream from external DRAM via the DIU, and produces the cdu_finishedband signal. The write control unit accepts the output from the JPEG decoder a half JPEG block (32 bytes) at a time, writes it into a double-buffer, and writes the double buffered decompressed half blocks to DRAM via the DIU, interacting with the CFU in order to share DRAM buffers. 24.5.1 Definitions of 1/0 Table 145. CDU port list and description Clocks and reset Pclk 1 In System clock. Jclk 1 In Gated version of system clock used to clock the JPEG decoder core and logic at the output of the core. Allows for stalling of the JPEG core at a pixel sample boundary. jclkenable 1 Out Gating signal for jclk. prstn 1 In System reset, synchronous active low. jrstn 1 In Reset for jclk domain, synchronous active low. PCU interface pcu_cdu_sel 1 In Block select from the PCU. When pcuLcdu..sel is high both pcuadr and pcu.dataout are valid. pcu_rwn 1 In Common read/not-write signal from the PCU. pcu-adr[7:2] 6 In PCU address bus. Only 6 bits are required to decode the address space for this block. pcu-dataout[31:0] 32 In Shared write data bus from the PCU. cdu.pcu-rdy 1 Out Ready signal to the PCU. When cdu.pcu.rdy is high it indicates the last cycle of the access. For a write cycle this means pcu-dataout has been registered by the block and for a read cycle this means the data on cdupcudatain is valid. cdu-pcu-datain[31:0] 32 Out Read data bus to the PCU. DIU read interface cdudiu_rreq 1 Out CDU read request, active high. A read request must be accompanied by a valid read address. Diu_cdu_rack 1 In Acknowledge from DIU, active high. Indicates that a read request has been accepted and the new read address can be placed on the address bus, cdLLdiLradr. cdu-diu-radr[21:5] 17 Out CDU read address. 17 bits wide (256-bit aligned word).
WO 2005/120835 PCT/AU2004/000706 741 Diucdurvalid 1 In Read data valid, active high. Indicates that valid read data is now on the read data bus, diudata. Diu-data[63:0] 64 In Read data from DRAM. DIU write interface cdudiuwreq 1 Out CDU write request, active high. A write request must be accompanied by a valid write address and valid write data. Diucdu_wack 1 In Acknowledge from DIU, active high. Indicates that a write request has been accepted and the new write address can be placed on the address bus, cdu_diu_wadr. cdu_diu wadr[21:3] 19 Out CDU write address. 19 bits wide (64-bit aligned word). cdudiuwvalid 1 Out Write data valid, active high. Indicates that valid data is now on the write data bus, cdu diu_data. cdudiudata[63:0] 64 Out Write data bus. CFU interface cfu_cdu_rdadvline 1 In Read line pulse, active high. Indicates that the CFU has finished reading a line of decompressed contone data to the circular buffer in DRAM and that line of the buffer is now free. cdu_cfu_linestore-rdy 1 Out Indicates if the contone line store has 1 or more lines available to read by the CFU. ICU interface cdufinishedband 1 Out CDU's finishedBand flag, active high. Interrupt to the CPU to indicate that the CDU has finished processing a band of compressed contone data in DRAM and that area of DRAM is now free.This signal goes to both the interrupt controller and the PCU. cdu_icu-jpegerror 1 Out Active high interrupt indicating an error has occurred in the JPEG decoding process and decompression has stopped. A reset of the CDU must be performed to clear this interrupt. 24.5.2 Configuration registers The configuration registers in the CDU are programmed via the PCU interface. Refer to section 23.8.2 on page 439 for the description of the protocol and timing diagrams for reading and writing registers in the CDU. 5 Note that since addresses in SoPEC are byte aligned and the PCU only supports 32-bit register reads and writes, the lower 2 bits of the PCU address bus are not required to decode the address space for the CDU. When reading a register that is less than 32 bits wide zeros are returned on the upper unused bit(s) of cdu_pcudatain. The software reset logic should include a circuit to ensure that both the pclk and jclk domains are reset 10 regardless of the state of the jclkenable when the reset is initiated. The CDU contains the following additional registers: WO 2005/120835 PCT/AU2004/000706 742 Table 146. CDU registers 0x00 Reset 1 Ox1 A write to this register causes a reset of the CDU. This terminates all internal operations within the CS6150. All configuration data previously loaded into the core except for the tables is deleted. Ox04 Go 1 Ox0 Writing 1 to this register starts the CDU. Writing 0 to this register halts the CDU. When Go is deasserted the state machines go to their idle states but all counters and configuration registers keep their values. When Go is asserted all counters are reset, but configuration registers keep their values (i.e. they don't get reset). NextBandEnable is cleared when Go is asserted. The CFU must be started before the CDU is started. Go must remain low for at least 384 jc/k cycles after a hardware reset (prstin = 0) to allow the JPEG core to complete its memory initialisation sequence. This register can be read to determine if the CDU is running (1 running, 0 - stopped). Setup registers OxOC NumLinesAvail 16 OxOOOO The number of image lines of data that there is space available for in the decompressed data buffer in DRAM. If this drops < 8 the CDU will stall. In normal operation this value will start off at NumBuffLines and will be decremented by 8 whenever the CDU writes a line of JPEG blocks (8 lines of data) to DRAM and incremented by 1 whenever the CFU reads a line of data from DRAM. NumLinesA vail can be adjusted by the CPU to prevent the CDU from stalling. When the CPU writes to this register, the NumLinesAvail is incremented by the CPU write value. (Working Register) Ox10 MaxPlane 2 Ox0 Defines the number of contone planes - 1. For example, this will be 0 for K (greyscale printing), 2 for CMY, and 3 for CMYK.
WO 2005/120835 PCT/AU2004/000706 743 0x14 MaxBlock 13 Ox000 Number of JPEG MCUs (or JPEG block equivalents, i.e. 8x8 bytes) in a line - 1. Ox1 8 BuffStartAdr[21:7] 15 OxOOO Points to the start of the decompressed contone circular buffer in DRAM, aligned to a half JPEG block boundary. A half JPEG block consists of 4 words of 256-bits, enough to hold 32 contone pixels in 4 colors, i.e. half a JPEG block. Ox1 C BuffEndAdr[21:7] 15 OxOOO Points to the start of the last half JPEG block at the end of the decompressed contone circular buffer in DRAM, aligned to a half JPEG block boundary. A half JPEG block consists of 4 words of 256-bits, enough to hold 32 contone pixels in 4 colors, i.e. half a JPEG block. Ox20 NumBuffLines[15: 14 Ox000 Defines size of buffer in DRAM in 2] C terms of the number of decompressed contone lines. The size of the buffer should be a multiple of 4 lines with a minimum size of 8 lines. Ox24 BypassJpg 1 Ox0 Determines whether or not the JPEG decoder will be bypassed (and hence pixels are copied directly from input to output) 0 - don't bypass, 1 - bypass Should not be changed between bands. Ox30 NextBandCurrSou 17 0x0_00 The 256-bit aligned word address rceAdr[21:5] 00 containing the start of the next band of compressed contone data in DRAM. This value is copied to CurrSourceAdr when both DoneBand is 1 and NextBandEnable is 1, or when Go transitions from 0 to 1. Ox34 NextBandEndSou 19 OxO_00 The 64-bit aligned word address rceAdr[21:3] 00 containing the last bytes of the next band of compressed contone data in DRAM. This value is copied to EndSourceAdr when both DoneBand is 1 and NextBandEnable is 1, or when Go transitions from 0 to 1. Ox38 NextBandValidByt 3 Ox0 Indicates the number of valid bytes esLastFetch 1 in the last 64-bit fetch of the next band of compressed contone data from DRAM. e.g. 0 implies bits 7:0 are valid, 1 implies bits 15:0 are valid, 7 implies all 63:0 bits are valid etc. This value is copied to ValidBytesLastFetch when both DoneBand is 1 and NextBandEnable ic I nr whfn /rn trancitinne frne n tn WO 2005/120835 PCT/AU2004/000706 744 Ox3C NextBandEnable 1 Ox0 When NextBandEnable is 1 and DoneBand is 1 -NextBandCurrSourceAdr is copied to CurrSourceAdr, -NextBandEndSourceAdr is copied to EndSourceAdr -NextBandValidBytesLastFetch is copied to ValidBytesLastFetch -DoneBand is cleared, -NextBandEnable is cleared. NextBandEnable is cleared when Go is asserted. Note that DoneBand gets cleared regardless of the state of Go. Read-only registers 0x40 DoneBand 1 Ox0 Specifies whether or not the current band has finished loading into the local FIFO. It is cleared to 0 when Go transitions from 0 to 1. When the last of the compressed contone data for the band has been loaded into the local FIFO, the . cdu_finishedband signal is given out and the DoneBand flag is set. If NextBandEnable is 1 at this time then CurrSourceAdr, EndSourceAdr and ValidBytesLastFetch are updated with the values for the next band and DoneBand is cleared. Processing of the next band starts immediately. If NextBandEnable is 0 then the remainder of the CDU will continue to run, decompressing the data already loaded, while the read control unit waits for NextBandEnable to be set before it restarts. Ox44 CurrSourceAdr[21 17 OxO_00 The current 256-bit aligned word :5] 00 address within the current band of compressed contone data in DRAM. Ox48 EndSourceAdr[21: 19 OxO_00 The 64-bit aligned word address 3] 00 containing the last bytes of the current band of compressed contone data in DRAM. Ox4C ValidBytesLastFet 3 Ox00 Indicates the number of valid bytes ch 1 in the last 64-bit fetch of the current band of compressed contone data from DRAM. e.g. 0 implies bits 7:0 are valid, 1 implies bits 15:0 are valid, 7 implies all 63:0 bits are valid etc.
WO 2005/120835 PCT/AU2004/000706 745 JPEG decoder core setup registers 0x50 JpgDecMask 5 0x00 As segments are decoded they can also be output on the DecJpg (JpgDecHdr) port with the user selecting the segments for output by setting bits in the jpgDecMask port as follows: 4 SOF+SOS+DNL 3 COM+APP 2 DRI 1 DQT 0 DHT If any one of the bits of jpgDecMask is asserted then the SOI and E0I markers are also passed to the DecJpg port. Ox54 JpgDecTType 1 Ox0 Test type selector: 0 - DCT coefficients displayed on JpgDecTdata 1 - QDCT coefficient displayed on JpgDecTdata 0x58 JpgDecTestEn 1 Ox0 Signal which causes the memories to be bypassed for test purposes. Ox5C JpgDecPType 4 Ox0 Signal specifying parameters to be placed on port JpgDecPValue (See Table 147). JPEG decoder core read-only status registers 0x60 JpgDecHdr 8 Ox00 Selected header segments from the JPEG stream that is currently being decoded. Segments selected using JpgMask. Ox64 JpgDecTData 13 OxOOO 12 - TSOS output of CS1650, indicates the first output byte of the first 8x8 block of the test data. 11 - TSOB output of CS1650, indicates the first output byte of each 8x8 block of test data. 10-0 - 11-bit output test data port displays DCT coefficients or quantized coefficients depending on value of JpgDecTType. Ox68 JpgDecPValue 16 0x0000 Decoding parameter bus which enables various parameters used by the core to be read. The data available on the PValue port is for information only, and does not contain control signals for the decoder core. Ox6C JpgDecStatus 24 0x00_0 Bit 23 - jpg.rcore stall (if set, 000 indicates that the JPEG core is stalled by gating of jclk as the output JPEG halfblock double-buffers of the CDU are full) Bit 22 - pix.outLvalid (This signal is an output from the JPEG decoder core and is asserted when a pixel is being output Bits 21-16 - fifocontents (Number of huftia in rnmnraadeae rnntnna -Il") WO 2005/120835 PCT/AU2004/000706 746 at the input of CDU which feeds the JPEG decoder core) Bits 15-0 are JPEG decoder status outputs from the CS6150 (see Table 148 for description of bits). Setup registers (remain constant during the processing of multiple bands) 0x80 CduStartOfBandS 17 OxO_00 Points to the 256-bit word that tore[21:5] 00 defines the start of the memory area allocated for CDU page bands. Circular address generation wraps to this start address. Ox84 CduEndOfBandSt 17 Ox1_F Points to the 256-bit word that ore[21:5] FFF defines the last address of the memory area allocated for CDU page bands. If the current read address is from this address, then instead of adding 1 to the current address, the current address will be loaded from the CduStartOfBandStore register. 24.5.3 Typical operation The CDU should only be started after the CFU has been started. For the first band of data, users set up NextBandCurrSourceAdr, NextBandEndSourceAdr, 5 NextBandValidBytesLastFetch, and the various MaxPlane, MaxBlock, Buf]StartBlockAdr, BufjEndBlockAdr and NumBufLines. Users then set the CDU's Go bit to start processing of the band. When the compressed contone data for the band has finished being read in, the cdu_finishedband interrupt will be sent to the PCU and CPU indicating that the memory associated with the first band is now free. Processing can now start on the next band of contone data. 10 In order to process the next band NextBandCurrSourceAdr, NextBandEndSourceAdr and NextBandValidBytesLastFetch need to be updated before finally writing a 1 to NextBandEnable. There are 4 mechanisms for restarting the CDU between bands: a. cdujfinishedband causes an interrupt to the CPU. The CDU will have set its DoneBand bit. The CPU reprograms the NextBandCurrSourceAdr, NextBandEndSourceAdr and 15 NextBandValidBytesLastFetch registers, and sets NextBandEnable to restart the CDU. b. The CPU programs the CDU's NextBandCurrSourceAdr, NextBandCurrEndAdr and NextBandValidBytesLastFetch registers and sets the NextBandEnable bit before the end of the current band. At the end of the current band the CDU sets DoneBand. As NextBandEnable is already 1, the CDU starts processing the next band immediately. 20 c. The PCU is programmed so that cdujfinishedband triggers the PCU to execute commands from DRAM to reprogram the NextBandCurrSourceAdr, NextBandEndSourceAdr and WO 2005/120835 PCT/AU2004/000706 747 NextBandValidBytesLastFetch registers and set the NextBandEnable bit to start the CDU processing the next band. The advantage of this scheme is that the CPU could process band headers in advance and store the band commands in DRAM ready for execution. d. This is a combination of b and c above. The PCU (rather than the CPU in b) programs the CDU's 5 NextBandCurrSourceAdr, NextBandCurrEndAdr and NextBandValidBytesLastFetch registers and sets the NextBandEnable bit before the end of the current band. At the end of the current band the CDU sets DoneBand and pulses cdu_finishedband. As NextBandEnable is already 1, the CDU starts processing the next band immediately. Simultaneously, cdu_finishedband triggers the PCU to fetch commands from DRAM. The CDU will have restarted by the time the PCU has fetched 10 commands from DRAM. The PCU commands program the CDU's next band shadow registers and sets the NextBandEnable bit. If an error occurs in the JPEG stream, the JPEG decoder will suspend its operation, an error bit will be set in the JpgDecStatus register and the core will ignore any input data and await a reset before starting decoding again. An interrupt is sent to the CPU by asserting cduicujpegerror and the CDU should then be reset by 15 means of a write to its Reset register before a new page can be printed. 24.5.4 Read control unit The read control unit is responsible for reading the compressed contone data and passing it to the JPEG decoder via the FIFO. The compressed contone data is read from DRAM in single 256-bit accesses, receiving the data from the DIU over 4 clock cycles (64-bits per cycle). The protocol and timing for read accesses to 20 DRAM is described in section 22.9.1 on page 337. Read accesses to DRAM are implemented by means of the state machine described in Figure 151. All counters and flags should be cleared after reset. When Go transitions from 0 to I all counters and flags should take their initial value. While the Go bit is set, the state machine relies on the DoneBand bit to tell it whether to attempt to read a band of compressed contone data. When DoneBand is set, the state machine does 25 nothing. When DoneBand is clear, the state machine continues to load data into the JPEG input FIFO up to 256-bits at a time while there is space available in the FIFO. Note that the state machine has no knowledge about numbers of blocks or numbers of color planes - it merely keeps the JPEG input FIFO full by consecutive reads from DRAM. The DIU is responsible for ensuring that DRAM requests are satisfied at least at the peak DRAM read bandwidth of 0.36 bits/cycle (see section 24.3 on page 448). 30 A modulo 4 counter, rdcount, is use to count each of the 64-bits received in a 256-bit read access. It is incremented whenever diucdurvalid is asserted. As each 64-bit value is returned, indicated by diucdurvalid being asserted, curr_sourceadr is compared to both endsourceadr and end of bandstore: * If {currsourceadrrdcount) equals end sourceadr, the end ofband control signal sent to the FIFO is 1 (to signify the end of the band), the finishedCDUBand signal is output, and the 35 DoneBand bit is set. The remaining 64-bit values in the burst from the DIU are ignored, i.e. they are not written into the FIFO. e If rdcount equals 3 and {currsourceadrrdcount) does not equal endsourceadr, then currsourceadr is updated to be either start of bandstore or currsourceadr + 1, depending on WO 2005/120835 PCT/AU2004/000706 748 whether curr source adr also equals end of bandstore. The endof band control signal sent to the FIFO is 0. currsourceadr is output to the DIU as cdudiu radr. A count is kept of the number of 64-bit values in the FIFO. When diucdu_ rvalid is 1 and ignore-data is 0, 5 data is written to the FIFO by asserting FifoWr, and fifocontents[3:0] and fifowr_adr[2:0j are both incremented. When fifocontents[3:0] is greater than 0, jpgin _strb is asserted to indicate that there is data available in the FIFO for the JPEG decoder core. The JPEG decoder core asserts jpg in rdy when it is ready to receive data from the FIFO. Note it is also possible to bypass the JPEG decoder core by setting the BypassJpg register to 1. 10 In this case data is sent directly from the FIFO to the half-block double-buffer. While the JPEG decoder is not stalled (jpg_core stall equal 0), and jpg_in rdy (or bypassjpg) and jpg in strb are both 1, a byte of data is consumed by the JPEG decoder core. fifordadr[5:0] is then incremented to select the next byte. The read address is byte aligned, i.e. the upper 3 bits are input as the read address for the FIFO and the lower 3 bits are used to select a byte from the 64 bits. If fifordadr[2:O] = 111 then the next 64-bit value is read from the 15 FIFO by assertingfifo_rd, andfifocontents[3:0] is decremented. 24.5.5 Compressed contone FIFO The compressed contone FIFO conceptually is a 64-bit input, and 8-bit output FIFO to account for the 64-bit data transfers from the DIU, and the 8-bit requirement of the JPEG decoder. In reality, the FIFO is actually 8 entries deep and 65-bits wide (to accommodate two 256-bit accesses), with 20 bits 63-0 carrying data, and bit 64 containing a 1-bit end of band flag. Whenever 64-bit data is written to the FIFO from the DIU, an endof band flag is also passed in from the read control unit. The endof band bit is 1 if this is the last data transfer for the current band, and 0 if it is not the last transfer. When end of band = 1 during an input, the ValidBytesLastFetch register is also copied to an image version of the same. On the JPEG decoder side of the FIFO, the read address is byte aligned, i.e. the upper 3 bits are input as the 25 read address for the FIFO and the lower 3 bits are used to select a byte from the 64 bits (1st byte corresponds to bits 7-0, second byte to bits 15-8 etc.). If bit 64 is set on the read, bits 63-0 contain the end of the bytestream for that band, and only the bytes specified by the image of ValidBytesLastFetch are valid bytes to be read and presented to the JPEG decoder. Note that ValidBytesLastFetch is copied to an image register as it may be possible for the CDU to be 30 reprogrammed for the next band before the previous band's compressed contone data has been read from the FIFO (as an additional effect of this, the CDU has a non-problematic limitation in that each band of contone data must be more than 4 x 64-bits, or 32 bytes, in length). 24.5.6 CS6150 JPEG decoder 35 JPEG decoder functionality is implemented by means of a modified version of the Amphion CS6150 JPEG decoder core. The decoder is run at a nominal clock speed of 160 MHz. (Amphion have stated that the CS6150 JPEG decoder core can run at 185 MHz in 0.13um technology). The core is clocked by jclk which a gated version of the system clock pclk. Gating the clock provides a mechanism for stalling the JPEG decoder on a single color pixel-by-pixel basis. Control of the flow of output data is also provided by the PixOutEnab WO 2005/120835 PCT/AU2004/000706 749 input to the JPEG decoder. However, this only allows stalling of the output at a JPEG block boundary and is insufficient for SoPEC. Thus gating of the clock is employed and PixOutEnab is instead tied high. The CS6150 decoder automatically extracts all relevant parameters from the JPEG bytestream and uses them to control the decoding of the image. The JPEG bytestream contains data for the Huffman tables, quantization 5 tables, restart interval definition and frame and scan headers. The decoder parses and checks the JPEG bytestream automatically detecting and processing all the JPEG marker segments. After identifying the JPEG segments the decoder re-directs the data to the appropriate units to be stored or processed as appropriate. Any errors detected in the bytestream, apart from those in the entropy coded segments, are signalled and, if an error is found, the decoder stops reading the JPEG stream and waits to be reset. 10 JPEG images must have their data stored in interleaved format with no subsampling. Images longer than 65536 lines are allowed: these must have an initial imageHeight of 0. If the image has a Define Number Lines (DNL) marker at the end (normally necessary for standard JPEG, but not necessary for SoPEC's version of the CS6150), it must be equal to the total image height mod 64k or an error will be generated. See the CS6150 Databook for more details on how the core is used, and for timing diagrams of the interfaces. 15 The CS6150 decoder can be bypassed by setting the BypassJpg register. If this register is set, then the data read from DRAM must be in the same format as if it was produced by the JPEG decoder: 8x8 blocks of pixels in the correct color order. The data is uncompressed and is therefore lossless. The following subsections describe the means by which the CS6150 intervals can be made visible. 20 24.5.6.1 JPEG decoder reset The JPEG decoder has 2 possible types of reset, an asynchronous reset and a synchronous clear. In SoPEC the asynchronous reset is connected to the hardware synchronous reset of the CDU and can be activated by any hardware reset to SoPEC (either from external pin or from any of the wake-up sources, e.g. USB activity, Wake-up register timeout) or by resetting the PEP section (ResetSection register in the CPR block). 25 The synchronous clear is connected to the software reset of the CDU and can be activated by the low to high transition of the Go register, or a software reset via the Reset register. The 2 types of reset differ, in that the asynchronous reset, resets the JPEG core and causes the core to enter a memory initialization sequence that takes 384 clock cycles to complete after the reset is deasserted. The synchronous clear resets the core, but leaves the memory as is. This has some implications for programming 30 the CDU. In general the CDU should not be started (i.e. setting Go to 1) until at least 384 cycles after a hardware reset. If the CDU is started before then, the memory initialization sequence will be terminated leaving the JPEG core memory in an unknown state. This is allowed if the memory is to be initialized from the incoming JPEG stream. 35 24.5.6.2 JPEG decoder parameter bus The decoding parameter bus JpgDecPValue is a 16-bit port used to output various parameters extracted from the input data stream and currently used by the core. The 4-bit selector input (JpgDecPType) determines which internal parameters are displayed on the parameter bus as per Table 147. The data available on the PValue port does not contain control signals used by the CS6150.
WO 2005/120835 PCT/AU2004/000706 750 Table 147. Parameter bus definitions . .0 FY[5:0 FYnmbrofle i ame Ox1 FY[15:0] FY: number of lines in frame Oxi FX[i 5:0] FX number of columns in frame Ox2 00_YMCU[1 3:0] YMCU: number of MCUs in Y direction of the current scan Ox3 00_XMCU[13:0] XMCU: number of MCUs in X direction of the current scan Ox4 Cs0[7:0LTq0[1:0]LV0[2:0LHO[2:0] CsO: identifier for the first scan component TqO: quantization table identifier for the first scan component VO: vertical sampling factor for the first scan component. Values = 1-4 HO: horizontal sampling factor for the first scan component. Values = 1-4 Ox5 Cs1[7:OLTq1 [1:OLV1[2:OLH1[2:0] Csi, Tq1, V1 and H1 for the second scan component. V1, H1 undefined if NS<2 Ox6 Cs2[7:OLTq2[1:OLV2[2:OLH2[2:0] Cs2, Tq2, V2 and H2 for the second scan component. V2, H2 undefined if NS<3 Ox7 Cs3[7:OLTq3[1:OLV3[2:OLH3[2:0] Cs3, Tq3, V3 and H3 for the second scan component. V3, H3 undefined if NS<4 x8 CsH[15:0] CsH: no. of rows in current scan Ox9 CsV[1 5:0] CsV: no. of columns in current scan OxA DRI[15:0] DRI: restart interval OxB 000_HMAX[2:OLVMAX[2:OL HMAX: maximal horizontal sampling factor in MCUBLK[3:OLNS[2:0] frame VMAX: maximal vertical sampling factor in frame MCUBLK: number of blocks per MCU of the current scan, from 1 to 10 NS: number of scan components in current scan, 1-4 24.5.6 JPEG decoder status register The status register flags indicate the current state of the CS6150 operation. When an error is detected during the decoding process, the decompression process in the JPEG decoder is suspended and an interrupt is sent to 5 the CPU by asserting cdu icujpegerror (generated from DecError). The CPU can check the source of the error by reading the JpgDecStatus register. The CS6150 waits until a reset process is invoked by asserting the hard reset prst-n or by a soft reset of the CDU. The individual bits of JpgDecStatus are set to zero at reset and active high to indicate an error condition as defined in Table 148.
WO 2005/120835 PCT/AU2004/000706 751 Note: A DecHError will not block the input as the core will try to recover and produce the correct amount of pixel data. The DecHError is cleared automatically at the start of the next image and so no intervention is required from the user. If any of the other errors occur in the decode mode then, following the error cancellation, the core will discard all input data until the next Start Of Image (SOI) without triggering any 5 more errors. The progress of the decoding can be monitored by observing the values of TbiDef, IDctInProg, DecInProg and JpgInProg. Table 148. JPEG decoder status register definitions 15 - 12 TblDef[7:4] Indicates the number of Huffman tables defined, 1bit/table. 11 - 8 TblDef[3:0] Indicates the number of quantization tables defined, 1 bit/table. 7 DecHfError Set when an undefined Huffman table symbol is referenced during decoding. 6 CtlError Set when an invalid SOF parameter or an invalid SOS parameter is detected. Also set when there is a mismatch between the DNL segment input to the core and the number of lines in the input image which have already been decoded. Note that SoPEC's implementation of the CS6150 does not require a final DNL when the initial setting for ImageHeight is 0. This is to allow images longer than 64k lines. 5 HtError Set when an invalid DHT segment is detected. 4 QtError Set when an invalid DQT segment is detected. 3 DecError Set when anything other than a JPEG marker is input. Set when any of DecFlags[6:4] are set. Set when any data other than the SOI marker is detected at the start of a stream. Set when any SOF marker is detected other than SOFO. Set if incomplete Huffman or quantization definition is detected. 2 IDctinProg Set when IDCT starts processing first data of a scan. Cleared when IDCT has processed the last data of a scan. 1 DecInProg For each scan this signal is asserted after the SigSOS (Start of Scan Segment) signal has been output from the core and is de-asserted when the decoding of a scan is complete. It indicates that the core is in the decoding state. 0 JpgInProg Set when core starts to process input data (Jpgln) and de-asserted when decoding has been completed i.e. when the last pixel of last block of the image is output. 24.5.7 Half-block buffer interface 10 Since the CDU writes 256 bits (4 x 64 bits) to memory at a time, it requires a double-buffer of 2 x 256 bits at its output. This is implemented in an 8 x 64 bit FIFO. It is required to be able to stall the JPEG decoder core at its output on a half JPEG block boundary, i.e. after 32 pixels (8 bits per pixel). We provide a mechanism for stalling the JPEG decoder core by gating the clock to the core (with jclk enable) when the FIFO is full. The WO 2005/120835 PCT/AU2004/000706 752 output FIFO is responsible for providing two buffered half JPEG blocks to decouple JPEG decoding (read control unit) from writing those JPEG blocks to DRAM (write control unit). Data coming in is in 8-bit quantities but data going out is in 64-bit quantities for a single color plane. 24.5.8 Write control unit 5 A line of JPEG blocks in 4 colors, or 8 lines of decompressed contone data, is stored in DRAM with the memory arrangement as shown Figure 152. The arrangement is in order to optimize access for reads by writing the data so that 4 color components are stored together in each 256-bit DRAM word. The CDU writes 8 lines of data in parallel but stores the first 4 lines and second 4 lines separately in DRAM. 10 The write sequence for a single line of JPEG 8x8 blocks in 4 colors, as shown in Figure 152, is as follows below and corresponds to the order in which pixels are output from the JPEG decoder core: block 0, color 0, line 0 in word p bits 63-0, line 1 in word p+l bits 63 0, 15 line 2 in word p+2 bits 63-0, line 3 in word p+3 bits 63-0, block 0, color 0, line 4 in word q bits 63-0, line 5 in word q+1 bits 63 0, 20 line 6 in word q+2 bits 63-0, line 7 in word q+3 bits 63-0, block 0, color 1, line 0 in word p bits 127-64, line 1 in word p+l bits 127-64, 25 line 2 in word p+2 bits 127-64, line 3 in word p+3 bits 127-64, block 0, color 1, line 4 in word q bits 127-64, line 5 in word q+l bits 127-64, 30 line 6 in word q+2 bits 127-64, line 7 in word q+3 bits 127-64, repeat for block 0 color 2, block 0 color 3........ 35 block 1, color 0, line 0 in word p+4 bits 63-0, line 1 in word p45 bits 63-0, etc.................................................... 40 block N, color 3, line 4 in word q+4n bits 255-192, line 5 in word q+4n+l bits 255-192, line 6 in word q+4n+2 bits 255-192, line 7 in word q+4n+3 bit 255-192 45 In SoPEC data is written to DRAM 256 bits at a time. The DIU receives a 64-bit aligned address from the CDU, i.e. the lower 2 bits indicate which 64-bits within a 256-bit location are being written to. With that address the DIU also receives half a JPEG block (4 lines) in a single color, 4 x 64 bits over 4 cycles. All accesses to DRAM must be padded to 256 bits or the bits which should not be written are masked using the individual bit write inputs of the DRAM. When writing decompressed contone data from the CDU, only 64 WO 2005/120835 PCT/AU2004/000706 753 bits out of the 256-bit access to DRAM are valid, and the remaining bits of the write are masked by the DIU. This means that the decompressed contone data is written to DRAM in 4 back-to-back 64-bit write masked accesses to 4 consecutive 256-bit DRAM locations/words. Writing of decompressed contone data to DRAM is implemented by the state machine in Figure 153. The 5 CDU writes the decompressed contone data to DRAM half a JPEG block at a time, 4 x 64 bits over 4 cycles. All counters and flags should be cleared after reset. When Go transitions from 0 to 1 all counters and flags should take their initial value. While the Go bit is set, the state machine relies on the halfblock oktoread and linestoreoktowrite flags to tell it whether to attempt to write a half JPEG block to DRAM. Once the half-block buffer interface contains a half JPEG block, the state machine requests a write access to DRAM by 10 asserting cdu__diu wreq and providing the write address, corresponding to the first 64-bit value to be written, on cdudiuwadr (only the address the first 64-bit value in each access of 4x64 bits is issued by the CDU. The DIU can generate the addresses for the second, third and fourth 64-bit values). The state machine then waits to receive an acknowledge from the DIU before initiating a read of 4 64-bit values from the half-block buffer interface by asserting rd_adv for 4 cycles. The output cdu_diu_wvalid is asserted in the cycle after 15 rdadv to indicate to the DIU that valid data is present on the cdudiudata bus and should be written to the specified address in DRAM. A rdadvhalf block pulse is then sent to the half-block buffer interface to indicate that the current read buffer has been read and should now be available to be written to again. The state machine then returns to the request state. The pseudocode below shows how the write address is calculated on a per clock cycle basis. Note counters 20 and flags should be cleared after reset. When Go transitions from 0 to 1 all counters and flags should be cleared and lwrhalfblock adr gets loaded with buffstart-adr and uprhaljblock-adr gets loaded with buff startadr + maxblock + 1. // assign write address output to DRAM 25 cdu-diu-wadr[6:5] = 00 // corresponds to linenumber, only first address is // issued for each DRAM access. Thus line is always 0. // The DIU generates these bits of the address. cdu-diu-wadr[4:3] = color 30 if (half == 1) then cdu_diu-wadr[21:7] = upr_halfblockadr // for lines 4-7 of JPEG block else 35 cdudiu-wadr[21:7] = lwr-halfblock_adr // for lines 0-3 of JPEG block // update half, color, block and addresses after each DRAM write access if (rdadvhalfblock == 1) then 40 if (half == 1) then half = 0 if (color == maxplane) then color = 0 if (block == max_block) then // end of writing a line of JPEG 45 blocks pulse wradv8line block = 0 WO 2005/120835 PCT/AU2004/000706 754 Update half block address for start of next line of JPEG blocks taking Account of address wrapping in circular buffer and 4 5 line offset if (upr~halfblock_adr == buff_entadr) then uprjhalfblock_adr = buff-start-adr + max_block + 1 elsif (uprjialfblock-adr + max_block + 1 buff_endadr) then 10 upr-halfblock-adr = buff-startadr else upr-halfblockadr = upr~halfblockadr + max_block + 2 else block ++ 15 uprhalfblockadr ++ move to address for lines 4 7 for next block else color ++ else 20 half=1 if (color == maxplane) then if (block ==maxblock) then IIend of writing a line of JPEG blocks 25 update half block address for start of next line of JPEG blocks taking // account of address wrapping in circular buffer and 4 line offset if (lwr_halfblock_adr == buff_endadr) then 30 lwr_halfblockadr = buff_start_adr + max-block + 1 elsif (lwrhalfblockadr + max_block + 1 == buffend-adr) then lwr_halfblockadr = buff-startadr else 35 lwrhalfblock adr = lwr halfblockadr + maxblock + 2 else lwr_halfblock_adr ++ // move to address for lines 0 3 for next block 40 24.5.9 Contone line store interface The contone line store interface is responsible for providing the control over the shared resource in DRAM. The CDU writes 8 lines of data in up to 4 color planes, and the CFU reads them line-at-a-time. The contone line store interface provides the mechanism for keeping track of the number of lines stored in DRAM, and 45 provides signals so that a given line cannot be read from until the complete line has been written. The CDU writes 8 lines of data in parallel but writes the first 4 lines and second 4 lines to separate areas in DRAM. Thus, when the CFU has read 4 lines from DRAM that area now becomes free for the CDU to write to. Thus the size of the line store in DRAM should be a multiple of 4 lines. The minimum size of the line store interface is 8 lines, providing a single buffer scheme. Typical sizes are 12 lines for a 1.5 buffer scheme while 50 16 lines provides a double-buffer scheme.
WO 2005/120835 PCT/AU2004/000706 755 The size of the contone line store is defined by num buff lines. A count is kept of the number of lines stored in DRAM that are available to be written to. When Go transitions from 0 to 1, NumLinesAvail is set to the value of num buff_lines. The CDU may only begin to write to DRAM as long as there is space available for 8 lines, indicated when the line store ok to write bit is set. When the CDU has finished writing 8 lines, the 5 write control unit sends an wradv8line pulse to the contone line store interface, and NumLinesAvail is decremented by 8. The write control unit then waits for linestoreoktowrite to be set again. If the contone line store is not empty (has one or more lines available in it), the CDU will indicate to the CFU via the cducfulinestore_rdy signal. The cdu cfu_linestore_rdy signal is generated by comparing the NumLinesAvail with the programmed num bufflines. 10 cducfulinestorerdy = (numnlinesavail != num_buff_lines) AND (cdugo ==1) As the CFU reads a line from the contone line store it will pulse the cfucdu_rdadvline to indicate that it has read a full line from the line store. NumLinesAvail is incremented by 1 on receiving a cfucdurdadvline 15 pulse. To enable running the CDU while the CFU is not running the NumLinesAvail register can also be updated via the configuration register interface. In this scenario the CPU polls the value of the NumLinesAvail register and adjusts it to prevent stalling of the CDU (NumLinesAvail < 8). When the CPU writes to the NumLinesAvail register, it increments the NumLinesA vail register by the CPU write value. 20 If the CPU and the internal logic (via the wradv8line signal) attempt to update NumLinesAvail register together, the register will be updated to old value + the new CPU value - 8. In all CPU update cases the register will be set to OxFFFF if the calculation is greater than OxFFFF. 25 CONTONE FIFO UNIT (CFU) 25 25.1 OVERVIEW The Contone FIFO Unit (CFU) is responsible for reading the decompressed contone data layer from the circular buffer in DRAM, performing optional color conversion from YCrCb to RGB followed by optional color inversion in up to 4 color planes, and then feeding the data on to the HCU. Scaling of data is performed 30 in the horizontal and vertical directions by the CFU so that the output to the HCU matches the printer resolution. Non-integer scaling is supported in both the horizontal and vertical directions. Typically, the scale factor will be the same in both directions but may be programmed to be different. 25.2 BANDWIDTH REQUIREMENTS 35 The CFU must read the contone data from DRAM fast enough to match the rate at which the contone data is consumed by the HCU. Pixels of contone data are replicated a X scale factor (SF) number of times in the X direction and Y scale factor (SF) number of times in the Y direction to convert the final output to 1600 dpi. Replication in the X direction is performed at the output of the CFU on a pixel-by-pixel basis while replication in the Y direction is WO 2005/120835 PCT/AU2004/000706 756 performed by the CFU reading each line a number of times, according to the Y-scale factor, from DRAM. The HCU generates 1 dot (bi-level in 6 colors) per system clock cycle to achieve a print speed of 1 side per 2 seconds for full bleed A4/Letter printing. The CFU output buffer needs to be supplied with a 4 color contone pixel (32 bits) every SF cycles. With support for 4 colors at 267 ppi the CFU must read data from DRAM at 5 5.33 bits/cycle. 25.3 COLOR SPACE CONVERSION The CFU allows the contone data to be passed directly on, which will be the case if the color represented by each color plane in the JPEG image is an available ink. For example, the four colors may be C, M, Y, and K, 10 directly represented by CMYK inks. The four colors may represent gold, metallic green etc. for multi-SoPEC printing with exact colors. JPEG produces better compression ratios for a given visible quality when luminance and chrominance channels are separated. With CMYK, K can be considered to be luminance, but C, M and Y each contain luminance information and so would need to be compressed with appropriate luminance tables. We therefore 15 provide the means by which CMY can be passed to SoPEC as YCrCb. K does not need color conversion. When being JPEG compressed, CMY is typically converted to RGB, then to YCrCb and then finally JPEG compressed. At decompression, the YCrCb data is obtained, then color converted to RGB, and finally back to CMY. 20 The external RIP provides conversion from RGB to YCrCb, specifically to match the actual hardware implementation of the inverse transform within SoPEC, as per CCIR 601-2 except that Y, Cr and Cb are normalized to occupy all 256 levels of an 8-bit binary encoding. The CFU provides the translation to either RGB or CMY. RGB is included since it is a necessary step to produce CMY, and some printers increase their color gamut by including RGB inks as well as CMYK. 25 Consequently the JPEG stream in the color space convertor is one of: 1 color plane, no color space conversion * 2 color planes, no color space conversion e 3 color planes, no color space conversion * 3 color planes YCrCb, conversion to RGB 30 * 4 color planes, no color space conversion * 4 color planes YCrCbX, conversion of YCrCb to RGB, no color conversion of X Note that if the data is non-compressed, there is no specific advantage in performing color conversion (although the CDU and CFU do permit it). 35 25.4 COLOR SPACE INVERSION In addition to performing optional color conversion the CFU also provides for optional bit-wise inversion in up to 4 color planes. This provides the means by which the conversion to CMY may be finalized, or to may be used to provide planar correlation of the dither matrices. The RGB to CMY conversion is given by the relationship: WO 2005/120835 PCT/AU2004/000706 757 S C= 255 - R * M=255-G S Y= 255 - B These relationships require the page RIP to calculate the RGB from CMY as follows: 5 * R=255-C * G=255-M " B=255-Y 25.5 SCALING 10 Scaling of pixel data is performed in the horizontal and vertical directions by the CFU so that the output to the HCU matches the printer resolution. The CFU supports non-integer scaling with the scale factor represented by a numerator and a denominator. Only scaling up of the pixel data is allowed, i.e. the numerator should be greater than or equal to the denominator. For example, to scale up by a factor of two and a half, the numerator is programmed as 5 and the denominator programmed as 2. 15 Scaling is implemented using a counter as described in the pseudocode below. An advance pulse is generated to move to the next dot (x-scaling) or line (y-scaling). if (count + denominator - numerator >= 0) then count = count + denominator - numerator 20 advance = 1 else count = count + denominator advance = 0 25.6 LEAD-IN AND LEAD-OUT CLIPPING 25 The JPEG algorithm encodes data on a block by block basis, each block consists of 64 8-bit pixels (representing 8 rows each of 8 pixels). If the image is not a multiple of 8 pixels in X and Y then padding must be present. This padding (extra pixels) will be present after decoding of the JPEG bytestream. Extra padded lines in the Y direction (which may get scaled up in the CFU) will be ignored in the HCU through the setting of the BottomMargin register. 30 Extra padded pixels in the X direction must also be removed so that the contone layer is clipped to the target page as necessary. In the case of a multi-SoPEC system, 2 SoPECs may be responsible for printing the same side of a page, e.g. SoPEC #1 controls printing of the left side of the page and SoPEC #2 controls printing of the right side of the page and shown in Figure 154. The division of the contone layer between the 2 SoPECs may not fall on a 8 35 pixel (JPEG block) boundary. The JPEG block on the boundary of the 2 SoPECs (JPEG block n below) will be the last JPEG block in the line printed by SoPEC #1 and the first JPEG block in the line printed by SoPEC #2. Pixels in this JPEG block not destined for SoPEC #1 are ignored by appropriately setting the LeadOutClipNum. Pixels in this JPEG block not destined for SoPEC #2 must be ignored at the beginning of WO 2005/120835 PCT/AU2004/000706 758 each line. The number of pixels to be ignored at the start of each line is specified by the LeadInClipNum register. It may also be the case that the CDU writes out more JPEG blocks than is required to be read by the CFU, as shown for SoPEC #2 below. In this case the value of the MaxBlock register in the CDU is set to correspond to 5 JPEG block m but the value for the MaxBlock register in the CFU is set to correspond to JPEG block m-1. Thus JPEG block m is not read in by the CFU. Additional clipping on contone pixels is required when they are scaled up to the printer's resolution. The scaling of the first valid pixel in the line is controlled by setting the XstartCount register. The HcuLineLength 10 register defines the size of the target page for the contone layer at the printer's resolution and controls the scaling of the last valid pixel in a line sent to the HCU. 25.7 IMPLEMENTATION Figure 155 shows a block diagram of the CFU. 25.7.1 Definitions of 1/0 15 Table 149. CFU port list and description Clocks and reset pclk 1 In System clock prst-n 1 In System reset, synchronous active low. PCU interface pcucfusel 1 In Block select from the PCU. When pcucfu.sel is high both pcuadr and pcudataout are valid. pcurwn 1 In Common read/not-write signal from the PCU. pcu-adr[6:2] 5 In PCU address bus. Only 5 bits are required to decode the address space for this block. pcu-dataout[31:0] 32 In Shared write data bus from the PCU. cfu.pcu-rdy 1 Out Ready signal to the PCU. When cfu-pcu.rdy is high it indicates the last cycle of the access. For a write cycle this means pcudataout has been registered by the block and for a read cycle this means the data on cfu.pcu_datain is valid. cfujpcu-datain[31:0] 32 Out Read data bus to the PCU. DIU Interface cfudiu_rreq 1 Out CFU read request, active high. A read request must be accompanied by a valid read address.
WO 2005/120835 PCT/AU2004/000706 759 diu_cfu_rack 1 In Acknowledge from DIU, active high. Indicates that a read request has been accepted and the new read address can be placed on the address bus, cfu diuradr. cfu-diu-radr[21:5] 17 Out CFU read address. 17 bits wide (256-bit aligned word). diucfurvalid 1 In Read data valid, active high. Indicates that valid read data is now on the read data bus, diu-data. diu-data[63:0] 64 In Read data from DRAM. CDU interface cducfulinestore-rdy 1 In When high indicates that the contone line store has 1 or more lines available to be read by the CFU. cfucdurdadvline 1 Out Read line pulse, active high. Indicates that the CFU has finished reading a line of decompressed contone data to the circular buffer in DRAM and that line of the buffer is now free. HCU interface hcu cfu advdot 1 In Informs the CFU that the HCU has captured the pixel data on cfuhcuc[O-3]data lines and the CFU can now place the next pixel on the data lines. cfu hcu avail 1 Out Indicates valid data present on cfu_hcuc[0-3]data lines. cfuhcu_cOdata[7:0] 8 Out Pixel of data in contone plane 0. cfuhcu_cidata[7:0] 8 Out Pixel of data in contone plane 1. cfu_hcu_c2data[7:0] 8 Out Pixel of data in contone plane 2. cfuhcuc3data[7:0] 8 Out Pixel of data in contone plane 3. 25.7.2 Configuration registers The configuration registers in the CFU are programmed via the PCU interface. Refer to section 23.8.2 on page 439 for the description of the protocol and timing diagrams for reading and writing registers in the CFU. Note 5 that since addresses in SoPEC are byte aligned and the PCU only supports 32-bit register reads and writes, the lower 2 bits of the PCU address bus are not required to decode the address space for the CFU. When reading a register that is less than 32 bits wide zeros are returned on the upper unused bit(s) of cfu_pcu datain. The configuration registers of the CFU are listed in Table 150: Table 150. CFU registers Control registers Ox00 Reset 1 Ox1 A write to this register causes a reset of the
CFU.
WO 2005/120835 PCT/AU2004/000706 760 0x04 Go 1 Ox0 Writing 1 to this register starts the CFU. Writing 0 to this register halts the CFU. When Go is reasserted the state-machines go to their idle states but all counters and configuration registers keep their values. When Go is asserted all counters are reset, but configuration registers keep their values (i.e. they don't get reset). The CFU must be started before the CDU is started. This register can be read to determine if the CFU is running (1 - running, 0 - stopped). Setup registers OxI 0 MaxBlock 13 OxOO Number of JPEG MCUs (or JPEG block 0 equivalents, i.e. 8x8 bytes) in a line - 1. Ox1 4 BuffStartAdr[21: 15 OxOO Points to the start of the decompressed contone 7] 0 circular buffer in DRAM, aligned to a half JPEG block boundary. A half JPEG block consists of 4 words of 256 bits, enough to hold 32 contone pixels in 4 colors, i.e. half a JPEG block. Ox18 BuffEndAdr[21: 15 OxOO Points to the end of the decompressed contone 7] 0 circular buffer in DRAM, aligned to a half JPEG block boundary (address is inclusive). A half JPEG block consists of 4 words of 256 bits, enough to hold 32 contone pixels in 4 colors, i.e. half a JPEG block. Ox1C 4LineOffset 13 OxOOO Defines the offset between the start of one 4 line 0 store to the start of the next 4 line store. In Figure 156 on page 476, if BufStartAdr corresponds to line 0 block 0 then BuffStartAdr + 4LineOffset corresponds to line 4 block 0. 4LineOffset is specified in units of128 bytes, e.g. 0 - 128 bytes,1 - 256 bytes etc. This register is required in addition to MaxBlock as the number of JPEG blocks in a line required by the CFU may be different from the number of JPEG blocks in a line written by the CDU. Ox20 YCrCb2RGB 1 Ox0 Set this bit to enable conversion from YCrCb to RGB. Should not be changed between bands. Ox24 InvertColorPlan 4 Ox0 Set these bits to perform bit-wise inversion on a e per color plane basis. bitO - 1 invert color plane 0 - 0 do not convert bit1 - 1 invert color plane 1 - 0 do not convert bit2 - 1 invert color plane 2 - 0 do not convert bit3 - 1 invert color plane 3 - 0 do not convert Should not be changed between bands. Ox28 HcuLineLength 16 OxOOO Number of contone pixels - 1 in a line (after 0 scaling). Equals the number of hcucfudotadv pulses - 1 received from the HCU for each line of contone data. Ox2C LeadinClipNum 3 Ox0 Number of contone pixels to be ignored at the start of a line (from JPEG block 0 in a line). They are not passed to the outout buffer to be scaled WO 2005/120835 PCT/AU2004/000706 761 in the X direction. Ox30 LeadOutClipNu 3 Ox0 Number of contone pixels to be ignored at the m end of a line (from JPEG block MaxBlock in a line). They are not passed to the output buffer to be scaled in the X direction. Ox34 XstartCount 8 Ox00 Value to be loaded at the start of every line into the counter used for scaling in the X direction. Used to control the scaling of the first pixel in a line to be sent to the HCU. This value will typically be zero, except in the case where a number of dots are clipped on the lead in to a line. Ox38 XscaleNum 8 Ox01 Numerator of contone scale factor in X direction. Ox3C XscaleDenom 8 Ox01 Denominator of contone scale factor in X direction. Ox40 YscaleNum 8 Ox01 Numerator of contone scale factor in Y direction. Ox44 YscaleDenom 8 Ox01 Denominator of contone scale factor in Y direction. Ox50 BuffCtrlMode 1 Ox0 Specifies if the contone line buffer logic is controlled externally by interaction between the CFU/CFU or is controlled internally by the CFU. 0 - External Mode (CFU/CDU controlled) 1 - Internal Mode (CFU controlled) When in internal mode the CFU ignores cdu_cfu_linestorerdy and cfucdu_rdadvine is set to 0. Ox54 BuffLinesFilled 16 OxOOO Unused and unchanged in external mode (when 0 BuffCtrlMode is 0). When in internal mode (BuffCtrlMode = 1), BuffLinesFilled is adjusted by the CPU to indicate the number of image lines of data that there is available in the decompressed data buffer in DRAM. When the CPU writes to this register, the BuffLinesFilled is incremented by the CPU write value This value is updated by the CPU and decremented by 1 whenever the CFU reads a line of data from DRAM (used in internal mode only). L_ (Working Register) 25.7.3 Storage of decompressed contone data in DRAM The CFU reads decompressed contone data from DRAM in single 256-bit accesses. JPEG blocks of decompressed contone data are stored in DRAM with the memory arrangement as shown The arrangement is 5 in order to optimize access for reads by writing the data so that 4 color components are stored together in each 256-bit DRAM word. The means that the CFU reads 64-bits in 4 colors from a single line in each 256-bit DRAM access. The CFU reads data line at a time in 4 colors from DRAM. The read sequence, as shown in Figure 156, is as follows: 10 line 0, block 0 in word p of DRAM line 0, block 1 in word p+4 of DRAM WO 2005/120835 PCT/AU2004/000706 762 line 0, block n in word p+4n of DRAM (repeat to read line a number of times according to scale factor) 5 line 1, block 0 in word p+l of DRAM line 1, block 1 in word p+5 of DRAM etc...................................... The CFU reads a complete line in up to 4 colors a Y scale factor number of times from DRAM before it moves on to read the next. When the CFU has finished reading 4 lines of contone data that 4 line store 10 becomes available for the CDU to write to. 25.7.4 Decompressed contone buffer Since the CFU reads 256 bits (4 colors x 64 bits) from memory at a time, it requires storage of at least 2 x 256 bits at its input. To allow for all possible DIU stall conditions the input buffer is increased to 3 x 256 bits to 15 meet the CFU target bandwidth requirements. The CFU receives the data from the DIU over 4 clock cycles (64-bits of a single color per cycle). It is implemented as 4 buffers. Each buffer conceptually is a 64-bit input and 8-bit output buffer to account for the 64-bit data transfers from the DIU, and the 8-bit output per color plane to the color space converter. On the DRAM side, wr buff indicates the current buffer within each triple-buffer that writes are to occur to. 20 wrsel selects which triple-buffer to write the 64 bits of data to when wren is asserted. On the color space converter side, rd buff indicates the current buffer within each triple-buffer that reads are to occur from. When rden is asserted a byte is read from each of the triple-buffers in parallel. rdsel is used to select a byte from the 64 bits (1st byte corresponds to bits 7-0, second byte to bits 15-8 etc.). Due to the limitations of available register arrays in IBM technology, the decompressed contone buffer is 25 implemented as a quadruple buffer. While this offers some benefits for the CFU it is not necessitated by the bandwidth requirements of the CFU. 25.7.5 Y-scaling control unit The Y-scaling control unit is responsible for reading the decompressed contone data and passing it to the color space converter via the decompressed contone buffer. The decompressed contone data is read from 30 DRAM in single 256-bit accesses, receiving the data from the DIU over 4 clock cycles (64-bits per cycle). The protocol and timing for read accesses to DRAM is described in section 22.9.1 on page 337. Read accesses to DRAM are implemented by means of the state machine described in Figure 157. All counters and flags should be cleared after reset. When Go transitions from 0 to 1 all counters and flags should take their initial value. While the Go bit is set, the state machine relies on the line8_oktoread and 35 buff ok_to_write flags to tell it whether to attempt to read a line of compressed contone data from DRAM. When line8_oktoread is 0 the state machine does nothing. When line8_oktoread is 1 the state machine continues to load data into the decompressed contone buffer up to 256-bits at a time while there is space available in the buffer.
WO 2005/120835 PCT/AU2004/000706 763 A bit is kept for the status of each 64-bit buffer: buff avail[O] and buff avail[lf]. It also keeps a single bit (rd~buff) for the current buffer that reads are to occur from, and a single bit (wr buff) for the current buffer that writes are to occur to. buff ok_to_write equals -buff avail[wr buff. When a wradvbuff pulse is received, buff avail[wr buf] is 5 set, and wr buff is inverted. Whenever diucfurvalid is asserted, wren is asserted to write the 64-bits of data from DRAM to the buffer selected by wrsel and wr buff buff ok_to_read equals buff avail[rd bufi]. If there is data available in the buffer and the output double buffer has space available (outbuffoktowrite equals 1) then data is read from the buffer by asserting rd en and rd sel gets incremented to point to the next value. wradv is asserted in the following cycle to write the 10 data to the output double-buffer of the CFU. When finished reading the buffer, rd sel equals b 111 and rden is asserted, buff avail[rd buff] is set, and rd buff is inverted. Each line is read a number of times from DRAM, according to the Y-scale factor, before the CFU moves on to start reading the next line of decompressed contone data. Scaling to the printhead resolution in the Y direction is thus performed. 15 The pseudocode below shows how the read address from DRAM is calculated on a per clock cycle basis. Note all counters and flags should be cleared after reset or when Go is cleared. When a I is written to Go, both curr halfblock and linestart halfblock get loaded with buff start_adr, and yscale count gets loaded with y_scale_denom. Scaling in the Y direction is implemented by line replication by re-reading lines from DRAM. The algorithm for non-integer scaling is described in the pseudocode below. 20 // assign read address output to DRAM cdudiu_wadr[21:7] = curr_halfblock cdu-diu-wadr[6:5) = linell:0] 25 // update block, line, y-scale-count and addresses after each DRAM read access if (wradv-buff == 1) then if (block == max -block) then IIend of reading a line of contone in up to 4 colors block = 0 30 / check whether to advance to next line of contone data in DRAM if (yscalefcount + yscaledenom - yscalenum >= 0) then yscale_count = yscale-count + y-scale-denom - y-scale_num pulse RdAdvline if (line == 3) then // end of reading 4 line store of 35 contone data line = 0 // update half block address for start of next line taking account of // address wrapping in circular buffer and 4 line offset 40 if ((line-start-adr + 4line-offset) > buff-end-adr)) then curr-halfblock = buff-start-adr line-startadr = buff-startadr else curr_halfblock = line_startadr + 4lineoffset 45 line-start-adr = line-startadr + 4lineoffset else line ++ WO 2005/120835 PCT/AU2004/000706 764 curr-halfblock = line-start-adr else // re-read current line from DRAM y-scale-count = yscale_count + y-scale-denom 5 currhalfblock = line_start_adr else block ++ curr halfblock ++ 25.7.6 Contone line store interface 10 The contone line store interface is responsible for providing the control over the shared resource in DRAM. The CDU writes 8 lines of data in up to 4 color planes, and the CFU reads them line-at-a-time. The contone line store interface provides the mechanism for keeping track of the number of lines stored in DRAM, and provides signals so that a given line cannot be read from until the complete line has been written. The contone line store interface has two modes of operation, internal and external as configured by the 15 BuffCtrlMode register. In external mode the CDU indicates to the CFU if data is available in the contone line store buffer (via cducfu_linestore_ rdy signal). When the CFU has completed reading a line of contone data from DRAM, the Y-scaling control unit sends a cfu_cdurdadvline signal to the CDU to free up the line in the buffer in DRAM. The BufiLinesFilled register is ignored, is not automatically updated by the CFU, and can be adjusted by the 20 CPU without interference in external mode In internal mode the cfu cdu rdadvline signal is set to zero and the cdu cfu linestorerdy signal is ignored. The CPU must update the BufiLinesFilled register to indicate to the CFU that data is available in the contone buffer for reading. When the CFU has completed reading a line of contone data from DRAM, the Y-scaling control unit will decrement the BuffLinesFilled register. The CFU will stall if BuffLinesFilled is 0. When the 25 CPU writes to the BuffLinesFilled register, the register value is incremented by the CPU write value and not overwritten. If the CPU attempts to update a new value to the BufiLinesFilled register and the internal CFU tries to decrement the value at exactly the same time, the register will take on the old value + the new CPU write value - 1. For any CPU update of the BuffLinesFilled register, the register is set to OxFFFF if the result of the new value is greater than OxFFFF. 30 25.7.7 Color Space Converter (CSC) The color space converter consists of 2 stages: optional color conversion from YCrCb to RGB followed by optional bit-wise inversion in up to 4 color planes. The convert YCrCb to RGB block takes 3 8-bit inputs defined as Y, Cr, and Cb and outputs either the same data YCrCb or RGB. The YCrCb2RGB parameter is set to enable the conversion step from YCrCb to RGB. If 35 YCrCb2RGB equals 0, the conversion does not take place, and the input pixels are passed to the second stage. The 4th color plane, if present, bypasses the convert YCrCb to RGB block. Note that the latency of the convert YCrCb to RGB block is 1 cycle. This latency should be equalized for the 4th color plane as it bypasses the block.
WO 2005/120835 PCT/AU2004/000706 765 The second stage involves optional bit-wise inversion on a per color plane basis under the control of invertcolor_plane. For example if the input is YCrCbK, then YCrCb2RGB can be set to I to convert YCrCb to RGB, and invert color_plane can be set to 0111 to then convert the RGB to CMY, leaving K unchanged. If YCrCb2RGB equals 0 and invertcolor_plane equals 0000, no color conversion or color inversion will take 5 place, so the output pixels will be the same as the input pixels. Figure 158 shows a block diagram of the color space converter. Although only 10 bits of coefficients are used (1 sign bit, 1 integer bit, 8 fractional bits), full internal accuracy is maintained with 18 bits. The conversion is implemented as follows: e R* = Y + (359/256)(Cr-128) 10 0 G* = Y - (183/256)(Cr-128) - (88/256)(Cb-128) e B* = Y + (454/256)(Cb-128) R*, G* and B* are rounded to the nearest integer and saturated to the range 0-255 to give R, G and B. Note that, while a Reset results in all-zero output, a zero input gives output RGB = [0, 136, 0]. 25.7.8 X-scaling control unit 15 The CFU has a 2 x 32-bit double-buffer at its output between the color space converter and the HCU. The X scaling control unit performs the scaling of the contone data to the printers output resolution, provides the mechanism for keeping track of the current read and write buffers, and ensures that a buffer cannot be read from until it has been written to. A bit is kept for the status of each 32-bit buffer: buffavail[O] and buff avail[1]. It also keeps a single bit 20 (rdbuff) for the current buffer that reads are to occur from, and a single bit (wr buff) for the current buffer that writes are to occur to. The output value outbuff okto write equals -buff avail[wr buff]. Contone pixels are counted as they are received from the Y-scaling control unit, i.e. when wradv is 1. Pixels in the lead-in and lead-out areas are ignored, i.e. they are not written to the output buffer. Lead-in and lead-out clipping of pixels is implemented 25 by the following pseudocode that generates the wr-en pulse for the output buffer. if (wradv == 1) then if (pixel-count == (max-block,bl1l1) then pixel_count = 0 30 else pixel_count ++ - if ((pixel-count < leadin_clipnum) OR (pixel-count > ((maxblockblll - leadoutclipnum))) then 35 wr-en = o else wr-en = 1 When a wr en pulse is sent to the output double-buffer, buff avail[wr buff is set, and wrbuf is inverted.
WO 2005/120835 PCT/AU2004/000706 766 The output cfuhcu avail equals buff avail[rd_buff. When cfu hcu avail equals 1, this indicates to the HCU that data is available to be read from the CFU. The HCU responds by asserting hcucfuadvdot to indicate that the HCU has captured the pixel data on cfuhcuc[-3]data lines and the CFU can now place the next pixel on the data lines. 5 The input pixels from the CSC may be scaled a non-integer number of times in the X direction to produce the output pixels for the HCU at the printhead resolution. Scaling is implemented by pixel replication. The algorithm for non-integer scaling is described in the pseudocode below. Note, xscale_count should be loaded with xstartcount after reset and at the end of each line. This controls the amount by which the first pixel is scaled by. hcu linelength and hcucfu dotadv control the amount by which the last pixel in a line that is sent 10 to the HCU is scaled by. if (hcucfudotadv == 1) then if (xscalecount + x-scale-denom - xscalenum >= 0) then x_scalecount = x_scale-count + xscaledenom - x scale_num 15 rden = 1 else x_scale_count = x scalecount + xscale_denom rden = 0 else 20 xscale_count = x_scale_count rd_en = 0 When a rd en pulse is received, buff avail[rd buff] is cleared, and rd buffs inverted. A 16-bit counter, dotadvcount, is used to keep a count of the number of hcucfu dotadv pulses received from the HCU. If the value of dotadv_count equals hculine_length and a hcu cfu dotadv pulse is received, 25 then a rd-en pulse is genrated to present the next dot at the output of the CFU, dotadv_count is reset to 0 and x_scalecount is loaded with xstartcount. 26 LOSSLESS BI-LEVEL DECODER (LBD) 26.1 OVERVIEW 30 The Lossless Bi-level Decoder (LBD) is responsible for decompressing a single plane of bi-level data. In SoPEC bi-level data is limited to a single spot color (typically black for text and line graphics). The input to the LBD is a single plane of bi-level data, read as a bitstream from DRAM. The LBD is programmed with the start address of the compressed data, the length of the output (decompressed) line, and the number of lines to decompress. Although the requirement for SoPEC is to be able to print text at 10:1 35 compression, the LBD can cope with any compression ratio if the requested DRAM access is available. A pass-through mode is provided for 1:1 compression. Ten-point plain text compresses with a ratio of about 50:1. Lossless bi-level compression across an average page is about 20:1 with 10:1 possible for pages which compress poorly.
WO 2005/120835 PCT/AU2004/000706 767 The output of the LBD is a single plane of decompressed bi-level data. The decompressed bi-level data is output to the SFU (Spot FIFO Unit), and in turn becomes an input to the HCU (Halftoner/Compositor unit) for the next stage in the printing pipeline. The LBD also outputs a lbd_finishedband control flag that is used by the PCU and is available as an interrupt to the CPU. 5 26.2 MAIN FEATURES OF LBD Figure 160 shows a schematic outline of the LBD and SFU. The LBD is required to support compressed images of up to 1600 dpi. The line buffers must therefore be long enough to store a complete line at 1600 dpi. The PEC1 LBD is required to output 2 dots/cycle to the HCU. This throughput capability is retained for 10 SoPEC to minimise changes to the block, although in SoPEC the HCU will only read 1 dot/cycle. The PEC 1 LDB outputs 16 bits in parallel to the PEC 1 spot buffer. This is also retained for SoPEC. Therefore the LBD in SoPEC can run much faster than is required. This is useful for allowing stalls, e.g. due to band processing latency, to be absorbed. The LBD has a pass-through mode to cope with local negative compression. Pass-through mode is activated 15 by a special run-length code. Pass-through mode continues to either end of line or for a pre-programmed number of bits, whichever is shorter. The special run-length code is always executed as a run-length code, followed by pass-through. The LBD outputs decompressed bi-level data to the NextLineFIFO in the Spot FIFO Unit (SFU). This stores the decompressed lines in DRAM, with a typical minimum of 2 lines stored in DRAM, nominally 3 lines up 20 to a programmable number of lines. The SFU's NextLineFIFO can fill while the SFU waits for write access to DRAM. Therefore the LBD must be able to support stalling at its output during a line. The LBD uses the previous line in the decoding process. This is provided by the SFU via its PrevLineFIFO. Decoding can stall in the LBD while this FIFO waits to be filled from DRAM. A signal sfu ldbrdy indicates that both the SFU's NextLineFIFO and PrevLineFIFO are available for writing 25 and reading respectively. A configuration register in the LBD controls whether the first line being decoded at the start of a band uses the previous line read from the SFU or uses an all O's line instead, thereby allowing a band to be compressed independently of its predecessor at the discretion of the RIP. The line length is stored in DRAM must be programmable to a value greater than 128. At 1600dpi, an A4 line 30 of 13824 dots requires 1.7Kbytes of storage and an A3 line of 19488 dots requires 2.4 Kbytes of storage. The compressed spot data can be read at a rate of 1 bit/cycle for pass-through mode 1:1 compression. The LBD finished band signal is exported to the PCU and is additionally available to the CPU as an interrupt.
WO 2005/120835 PCT/AU2004/000706 768 26.2.1 Bi-level Decoding in the LBD The black bi-level layer is losslessly compressed using Silverbrook Modified Group 4 (SMG4) compression which is a version of Group 4 Facsimile compression without Huffman and with simplified run length encodings. The encoding are listed in Table 151 and Table 152 Table 151. Bi-Level group 4 facsimile style compression encodings 1000 Pass Command: a0 +- b2, skip next two edges 1 Vertical(0): aO <- b1, color = !color 110 Vertical(1): a0 <- b1 + 1, color = !color 110000 Vertical(2): a0 <- b1 + 2, color = !color Eo 010000 Vertical(-2): aO <- b1 - 2, color = !color 100000 Vertical(3): aO <- b1 + 3, color = !color .n 0 000000 Vertical(-3): aO <- b1 - 3, color = !color oE - 5, <RL><RL>100 Horizontal: a0 <- a0 + <RL> + <RL> 5. Table 152. Run length (RL) encodings Encodingi Decition RRRRR1 Short Black Runlength (5 bits) RRRRR1 Short White Runlength (5 bits) RRRRRRRRRR10 Medium Black Runlength (10 bits) RRRRRRRR10 Medium White Runlength (8 bits) RRRRRRRRRR10 Medium Black Runlength with RRRRRRRRRR <= 31, Enter pass-through . 8 RRRRRRRR10 Medium White Runlength with RRRRRRRR <= 31, :E 2 Enter pass-through e E RRRRRRRRRRRRRRROO Long Black Runlength (15 bits) RRRRRRRRRRRRRRROO Long White Runlength (15 bits) Since the compression is a bitstream, the encodings are read right (least significant bit) to left (most significant bit). The run lengths given as RRRRR in Table 152 are read in the same way (least significant bit at the right to most significant bit at the left).
WO 2005/120835 PCT/AU2004/000706 769 An additional enhancement to the G4 fax algorithm relates to pass-through mode. It is possible for data to compress negatively using the G4 fax algorithm. On occasions like this it would be easier to pass the data to the LBD as un-compressed data. Pass-through mode is a new feature that was not implemented in the PEC1 version of the LBD. When the LBD is in pass-through mode the least significant bit of the data stream is an 5 un-compressed bit. This bit is used to construct the current line. Therefore SMG4 has a pass-through mode to cope with local negative compression. Pass-through mode is activated by a special run-length code. Pass-through mode continues to either end-of-line or for a pre programmed number of bits, whichever is shorter. The special run-length code is always executed as a run length code, followed by pass-through. 10 To enter pass-through mode the LBD takes advantage of the way run lengths can be written. Usually if one of the runlength pair is less than or equal to 31 it should be encoded as a short runlength. However under the coding scheme of Table 152 it is still legal to write it as a medium or long runlength. The LBD has been designed so that if a short runlength value is detected in a medium runlength, then once the horizontal command containing this runlength is decoded completely this will tell the LBD to enter pass-through mode 15 and the bits following the runlength is un-compressed data. The number of bits to pass-through is either a programmed number of bits or the end of the line which ever comes first. Once the pass-through mode is completed the current color is the same as the color of the last bit of the passed through data. 26.2.2 DRAM Access Requirements The compressed page store for contone, bi-level and raw tag data is programmable, and can be of the order of 20 2 Mbytes. The LBD accesses the compressed page store in single 256-bit DRAM reads. The LBD uses a 256 bit double buffer in its interface to the DIU. At 1600 dpi the LBD's DIU bandwidth requirements are summarized in Table 153 Table 153. DRAM bandwidth requirements Maximum number of Peak Bandwidth Average Bandwidth Direction cycles between each Peak BBandwidth 256-bit DRAM access (bits/cycle) (bits/cycle) Read 256' (1:1 1 (1:1 0.1 (10:1 compression) compression) compression) 1: At 1:1 compression the LBD requires 1 bit/cycle or 256 bits every 256 cycles. 25 26.3 IMPLEMENTATION 26.3.1 Definitions of 10 Table 154. LBD Port List !rt N'an P WO 2005/120835 PCT/AU2004/000706 770 Clocks and Resets PcIk 1 In SoPEC Functional clock. prstn 1 In Global reset signal. Bandstore signals lbdfinishedband 1 Out LBD finished band signal to PCU and Interrupt Controller. DIU Interface signals Ibd-diu-rreq 1 Out LBD requests DRAM read. A read request must be accompanied by a valid read address. lbd-diu-radr[21:5] 17 Out Read address to DIU 17 bits wide (256-bit aligned word). diulbdrack 1 In Acknowledge from DIU that read request has been accepted and new read address can be placed on Ibcdiuradr. diu-data[63:0] 64 In Data from DIU to SoPEC Units. First 64-bits is bits 63:0 of 256 bit word. Second 64-bits is bits 127:64 of 256 bit word. Third 64-bits is bits 191:128 of 256 bit word. Fourth 64-bits is bits 255:192 of 256 bit word. diu_Ibd_rvalid 1 In Signal from DIU telling SoPEC Unit that valid read data is on the diu data bus PCU Interface data and control signals pcu-addr[5:2] 4 In PCU address bus. Only 4 bits are required to decode the address space for this block. pcu-dataout[31:0] 32 In Shared write data bus from the PCU. Ibd-pcu-datain[31:0] 32 Out Read data bus from the LBD to the PCU. pcurwn 1 In Common read/not-write signal from the PCU. pculbdsel 1 In Block select from the PCU. When pcuLbdtsel is high both pcu addr and pcu._dataout are valid. lbd-pcu-rdy 1 Out Ready signal to the PCU. When lbd pcu-rdy is high it indicates the last cycle of the access. For a write cycle this means pcu-dataout has been registered by the block and for a read cycle this means the data on Ibdpcu._datain is valid. SFU Interface data and control signals sfu-lbd-rdy 1 In Ready signal indicating SFU has previous line data available for reading and is also ready to be written to. lbdsfuadvline 1 Out Advance line signal to previous and next line buffers lbd-sfu.pladvword 1 Out Advance word signal for previous line buffer. sfuIbd-pldata[15:0] 16 In Data from the previous line buffer. Ibd_sfuwdata[15:0] 16 Out Write data for next line buffer. lbdsfuwdatavalid 1 Out Write data valid signal for next line buffer data.
WO 2005/120835 PCT/AU2004/000706 771 26.3.1 26.3.2 Configuration Registers Table 155. LBD Configuration Registers Control registers 0x00 Reset 1 Ox1 A write to this register causes a reset of the LBD. This register can be read to indicate the reset state: 0 - reset in progress 1 - reset not in progress 0x04 Go 1 Ox0 Writing 1 to this register starts the LBD. Writing 0 to this register halts the LBD. The Go register is reset to 0 by the LBD when it finishes processing a band. When Go is deasserted the state machines go to their idle states but all counters and configuration registers keep their values. When Go is asserted all counters are reset, but configuration registers keep their values (i.e. they don't get reset). The LBD should only be started after the SFU is started. This register can be read to determine if the LBD is running (1 '- running, 0 - stopped). Setup registers (constant for during processing the page) 0x08 LineLength 16 OxOO Width of expanded bi-level line (in 0 dots) (must be set greater than 128 bits). Ox0C PassThroughEnable 1 Ox1 Writing 1 to this register enables passthrough mode. Writing 0 to this register disables passthrough mode thereby making the LBD compatible with PEC1. Ox10 PassThroughDotLength 16 OxOO This is the dot length - 1 for which 0 pass-through mode will last. If the end of the line is reached first then pass-through will be disabled. The value written to this register must be a non-zero value. Work registers (need to be set up before processing a band) WO 2005/120835 PCT/AU2004/000706 772 Ox1 4 NextBandCurrReadAdr[21:5] 17 OxOQO Shadow register which is copied (256-bit aligned DRAM 00 to CurrReadAdrwhen address) (NextBandEnable == 1 & Go == 0). NextBandCurrReadAdr is the address of the start of the next band of compressed bi-level data in DRAM. Ox1 8 NextBandLinesRemaining 15 OxOO Shadow register which is copied 0 to LinesRemaining when (NextBandEnable == 1 & Go == 0). NextBandLinesRemaining is the number of lines to be decoded in the next band of compressed bi level data. Ox1 C NextBandPrevLineSource 1 Ox0 Shadow register which is copied to PrevLineSource when (NextBandEnable == 1 & Go == 0). 1 - use the previous line read from the SFU for decoding the first line at the start of the next band. 0 - ignore the previous line read from the SFU for decoding the first line at the start of the next band (an all O's line is used instead). Ox20 NextBandEnable 1 Ox0 If (NextBandEnable == 1 & Go == 0) then -NextBandCurrReadAdr is copied to CurrReadAdr, -NextBandLinesRemaining is copied to LinesRemaining, -NextBandPrevLineSource is copied to PrevLineSource, -Go is set, -NextBandEnable is cleared. To start LBD processing NextBandEnable should be set. Setup registers (remain constant during the processing of multiple bands) 0x24 LbdStartOfBandStore[21:5] 17 OxO_0 Points to the 256-bit word that 000 defines the start of the memory area allocated for LBD page bands. Circular address generation wraps to this start address. Ox28 LbdEndOfBandStore[21:5] 17 Ox1_F Points to the 256-bit word that FFF defines the last address of the memory area allocated for LBD page bands. If the current read address is from this address, then instead of adding 1 to the current address, the current address will be loaded from the LbdStartOfBandStore register. Work registers (read only for external access) WO 2005/120835 PCT/AU2004/000706 773 Ox2C CurrReadAdr[21:5] 17 - The current 256-bit aligned read (256-bit aligned DRAM address within the compressed bi address) level image (DRAM address). Read only register. Ox30 LinesRemaining 15 - Count of number of lines remaining to be decoded. The band has finished when this number reaches 0. Read only register. Ox34 PrevLineSource 1 - 1 - uses the previous line read from the SFU for decoding the first line at the start of the next band. 0 - ignores the previous line read from the SFU for decoding the first line at the start of the next band (an all O's line is used instead). Read only register. Ox38 CurrWriteAdr 15 - The current dot position for writing to the SFU. Read only register. Ox3C FirstLineOfBand 1 - Indicates whether the current line is considered to be the first line of the band. Read only register. 26.3.2 26.3.3 Starting the LBD between bands The LBD should be started after the SFU. The LBD is programed with a start address for the compressed bi level data, a decode line length, the source of the previous line and a count of how many lines to decode. The 5 LBD's NextBandEnable bit should then be set (this will set LBD Go). The LBD decodes a single band and then stops, clearing its Go bit and issuing a pulse on lbd_finishedband. The LBD can then be restarted for the next band while the HCU continues to process previously decoded bi-level data from the SFU. There are 4 mechanisms for restarting the LBD between bands: a. lbd_finishedband causes an interrupt to the CPU. The LBD will have stopped and cleared its Go 10 bit. The CPU reprograms the LBD, typically the NextBandCurrReadAdr, NextBandLinesRemaining and NextBandPrevLineSource shadow registers, and sets NextBandEnable to restart the LBD. b. The CPU programs the LBD's NextBandCurrReadAdr, NextBandLinesRemaining, and NextBandPrevLineSource shadow registers and sets the NextBandEnable flag before the end of the 15 current band. At the end of the band the LBD clears Go, NextBandEnable is already set so the LBD restarts immediately. c. The PCU is programmed so that lbdfinishedband triggers the PCU to execute commands from DRAM to reprogram the LBD's NextBandCurrReadAdr, NextBandLinesRemaining, and NextBandPrevLineSource shadow registers and set NextBandEnable to restart the LBD. The 20 advantage of this scheme is that the CPU could process band headers in advance and store the band commands in DRAM ready for execution.
WO 2005/120835 PCT/AU2004/000706 774 d. This is a combination of b and c above. The PCU (rather than the CPU in b) programs the LBD's NextBandCurrReadAdr, NextBandLinesRemaining, and NextBandPrevLineSource shadow registers and sets the NextBandEnable flag before the end of the current band. At the end of the band the LBD clears Go and pulses lbd_finishedband NextBandEnable is already set so the LBD restarts 5 immediately. Simultaneously, lbd_finishedband triggers the PCU to fetch commands from DRAM. The LBD will have restarted by the time the PCU has fetched commands from DRAM. The PCU commands program the LBD's shadow registers and sets NextBandEnable for the next band. 26.3.4 Top-level Description A block diagram of the LBD is shown in Figure 161. 10 The LBD contains the following sub-blocks: Table 156. Functional sub-blocks in the LBD Registers and PCU interface and configuration registers. Also generates the Go Resets and the Reset signals for the rest of the LBD Stream Decoder Accesses the bi-level description from the DRAM through the DIU interface. It decodes the bit stream into a command with arguments, which it then passes to the command controller. Command Interprets the command from the stream decoder and provide Controller the line fill unit with a limit address and color to fill the SFU Next Line Buffer. It also provides the next edge unit starting address to look for the next edge. Next Edge Unit Scans through the Previous Line Buffer using its current address to find the next edge of a color provided by the command controller. The next edge unit outputs this as the next current address back to the command controller and sets a valid bit when this address is at the next edge. Line Fill Unit Fills the SFU Next Line Buffer with a color from its current address up to a limit address. The color and limit are provided by the command controller. In the following description the LBD decodes data for its current decode line but writes this data into the SFU's next line buffer. The LBD is able to stall mid-line should the SFU be unable to supply a previous line or receive a current line 15 frame due to band processing latency. All output control signals from the LBD must always be valid after reset. For example, if the LBD is not currently decoding, lbd sfuadvline (to the SFU) and lbdfinishedband will always be 0.
WO 2005/120835 PCT/AU2004/000706 775 26.3.5 Registers and Resets sub-block description The LBD page band store is defined by the registers LbdStartojBandStore and LbdEndOJBandStore, that enable sequential memory accesses to the page band stores to be circular in nature. The register descriptions for the LBD are listed in Table 155. 5 During initialisation of the LBD, the LineLength and the LinesRemaining configuration values are written to the LBD. The 'Registers and Resets' sub-block supplies these signals to the other sub-blocks in the LBD. In the case of LinesRemaining, this number is decremented for every line that is completed by the LBD. If pass-through is used during a band the PassThroughEnable register needs to be programmed and Pass ThroughDotLength programmed with the length of the compressed bits in pass-through mode. 10 PrevLineSource is programmed during the initialisation of a band, if the previous line supplied for the first line is a valid previous line, a 1 is written to PrevLineSource so that the data is used. If a 0 is written the LBD ignores the previous line information supplied and acts as if it is receiving all zeros for the previous line regardless of what is received from the SFU. The 'Registers and Resets' sub-block also generates the resets used by the rest of the LBD and the Go bit 15 which tells the LBD that it can start requesting data from the DIU and commence decoding of the compressed data stream. 26.3.6 Stream Decoder Sub-block Description The Stream Decoder reads the compressed bi-level image from the DRAM via the DIU (single accesses of 256-bits) into a double 256-bit FIFO. The barrel shift register uses the 64-bit word from the FIFO to fill up the 20 empty space created by the barrel shift register as it is shifting its contents. The bit stream is decoded into a command/arguments pair, which in turn is passed to the command controller. A dataflow block diagram of the stream decoder is shown in Figure 162. 26.3.6.1 DecodeC - Decode Command The DecodeC logic encodes the command from bits 6..0 of the bit stream to output one of three commands: 25 SKIP, VERTICAL and RUNLENGTH. It also provides an output to indicate how many bits were consumed, which feeds back to the barrel shift register. There is a fourth command, PASS_THROUGH, which is not encoded in bits 6..0, instead it is inferred in a special runlength. If the stream decoder detects a short runlength value, i.e. a number less than 31, encoded as a medium runlength this tell the Stream Decoder that once the horizontal command containing this runlength 30 is decoded completely the LBD enters PASSTHROUGH mode. Following the runlength there will be a number of bits that represent un-compressed data. The LBD will stay in PASS_THROUGH mode until all these bits have been decoded successfully. This will occur once a programmed number of bits is reached or the line ends, which ever comes first.
WO 2005/120835 PCT/AU2004/000706 776 26.3.6.2 DecodeD - Decode Delta The DecodeD logic decodes the run length from bits 20..3 of the bit stream. If DecodeC is decoding a vertical command, it will cause DecodeD to put constants of -3 through 3 on its output. The output delta is a 15 bit number, which is generally considered to be positive, but since it needs to only address to 13824 dots for an 5 A4 page and 19488 dots for an A3 page (of 32,768), a 2's complement representation of -3,-2,-1 will work correctly for the data pipeline that follows. This unit also outputs how many bits were consumed. In the case of PASSTHROUGH mode, DecodeD parses the bits that represent the un-compressed data and this is used by the Line Fill Unit to construct the current line frame. DecodeD parses the bits at one bit per clock cycle and passes the bit in the less significant bit location of delta to the line fill unit. 10 DecodeD currently requires to know the color of the run length to decode it correctly as black and white runs are encoded differently. The stream decoder keeps track of the next color based on the current color and the current command. 26.3.6.3 State-machine This state machine continuously fetches consecutive DRAM data whenever there is enough free space in the 15 FIFO, thereby keeping the barrel shift register full so it can continually decode commands for the command controller. Note in Figure 162 that each read cycle curr readaddr is compared to lbdendof_band-store. If the two are equal, currread_addr is loaded with lbd-start ofbandstore (circular memory addressing). Otherwise curr read addr is simply incremented. lbd startof bandstore and lbd_end_of band-store need to be programed so that the distance between them is a multiple of the 256-bit DRAM word size. 20 When the state machine decodes a SKIP command, the state machine provides two SKIP instructions to the command controller. The RUNLENGTH command has two different run lengths. The two run lengths are passed to the command controller as separate RUNLENGTH instructions. In the first instruction fetch, the first run length is passed, and the state machine selects the DecodeD shift value for the barrel shift. In the second instruction fetch from 25 the command controller another RUNLENGTH instruction is generated and the respective shift value is decoded. This is achieved by forcing DecodeC to output a second RUNLENGTH instruction and the respective shift value is decoded. For PASSTHROUGH mode, the PASSTHROUGH command is issued every time the command controller requests a new command. It does this until all the un-compressed bits have been processed. 30 26.3.7 Command Controller Sub-block Description The Command Controller interprets the command from the Stream Decoder and provides the line fill unit with a limit address and color to fill the SFU Next Line Buffer. It provides the next edge unit with a starting address to look for the next edge and is responsible for detecting the end of line and generating the eobcc signal that is passed to the line fill unit.
WO 2005/120835 PCT/AU2004/000706 777 A dataflow block diagram of the command controller is shown in Figure 163. Note that data names such as aO and b1p denote the reference or starting changing element on the coding line and the first changing element on the reference line to the right of aO and of the opposite color to aO respectively. 26.3.7.1 State machine 5 The following is an explanation of all the states that the state machine utilizes. i START This is the state that the Command Controller enters when a hard or soft reset occurs or when Go has been de-asserted. This state cannot be left until the reset has been removed, Go has been asserted and the NEU (Next Edge Unit), the SD (Stream Decoder) and the SFU are ready. 10 ii AWAIT BUFFER The NEU contains a buffer memory for the data it receives from the SFU. When the command controller enters this state the NEU detects this and starts buffering data, the command controller is able to leave this state when the state machine in the NEU has entered the NEU RUNNING state. Once this occurs the command controller can proceed to the PARSE state. 15 iii PAUSECC During the decode of a line it is possible for the FIFO in the stream decoder to get starved of data if the DRAM is not able to supply replacement data fast enough. Additionally the SFU can also stall mid-line due to band processing latency. If either of these cases occurs the LBD needs to pause until the stream decoder gets more of the compressed data stream from the DRAM or the SFU can receive or deliver new 20 frames. All of the remaining states check if sdvalid goes to zero (this denotes a starving of the stream decoder) or if sfu lbd rdy goes to zero and that the LBD needs to pause. PA USECC is the state that the command controller enters to achieve this and it does not leave this state until sdvalid and sfulbdrdy are both asserted and the LBD can recommence decompressing. iv PARSE 25 Once the command controller enters the PARSE state it uses the information that is supplied by the stream decoder. The first clock cycle of the state sees the sdack signal getting asserted informing the stream decoder that the current register information is being used so that it can fetch the next command. When in this state the command controller can receive one of four valid commands: a) Runlength or Horizontal 30 For this command the value given as delta is an integer that denotes the number of bits of the current color that must be added to the current line. Should the current line position, aO, be added to the delta and the result be greater than the final position of the current frame being processed by the Line Fill Unit (only 16 bits at a time), it is necessary for the command controller to wait for the Line Fill Unit (LFU) to process up to that point. 35 The command controller changes into the WAITFOR_R UNLENGTH state while this occurs.
WO 2005/120835 PCT/AU2004/000706 778 When the current line position, aO, and the delta together equal or exceed the LINELENGTH, which is programmed during initialisation, then this denotes that it is the end of the current line. The command controller signals this to the rest of the LBD and then returns to the START state. b) Vertical 5 When this command is received, it tells the command controller that, in the previous line, it needs to find a change from the current color to opposite of the current color, i.e. if the current color is white it looks from the current position in the previous line for the next time where there is a change in color from white to black. It is important to note that if a black to white change occurs first it is ignored. 10 Once this edge has been detected, the delta will denote which of the vertical commands to use, refer to Table 151. The delta will denote where the changing element in the current line is relative to the changing element on the previous line, for a Vertical(2) the new changing element position in the current line will correspond to the two bits extra from changing element position in the previous line. Should the next edge not be detected in the current frame under review in the NEU, then the 15 command controller enters the WAITFORNE state and waits there until the next edge is found. c) Skip A skip follow the same functionality as to Vertical(O) commands but the color in the current line is not changed as it is been filled out. The stream decoder supplies what looks like two separate skip commands that the command controller treats the same a two Vertical(O) commands and has been 20 coded not to change the current color in this case. d) Pass-Through When in pass-through mode the stream decoder supplies one bit per clock cycle that is uses to construct the current frame. Once pass-through mode is completed, which is controlled in the stream decoder, the LBD can recommence normal decompression again. The current color after pass 25 through mode is the same color as the last bit in un-compressed data stream. Pass-through mode does not need an extra state in the command controller as each pass-through command received from the stream decoder can always be processed in one clock cycle. v WAIT FORRUNLENGTH As some RUNLENGTH's can carry over more than one 16-bit frame, this means that the Line Fill Unit 30 needs longer than one clock cycle to write out all the bits represented by the RUNLENGTH. After the first clock cycle the command controller enters into the WAITFORRUNLENGTH state until all the RUNLENGTH data has been consumed. Once finished and provided it is not the end of the line the command controller will return to the PARSE state. vi WAIT FORNE 35 Similar to the RUNLENGTH commands the vertical commands can sometimes not find an edge in the current 16-bit frame. After the first clock cycle the command controller enters the WAITFOR_NE state WO 2005/120835 PCT/AU2004/000706 779 and remains here until the edge is detected. Provided it is not the end of the line the command controller will return to the PARSE state. vii FINISH LINE At the end of a line the command controller needs to hold its data for the SFU before going back to the 5 START state. Command controller remains in the FINISHLINE state for one clock cycle to achieve this. 26.3.8 Next Edge Unit Sub-block Description The Next Edge Unit (NEU) is responsible for detecting color changes, or edges, in the previous line based on the current address and color supplied by the Command Controller. The NEU is the interface to the SFU and it buffers the previous line for detecting an edge. For an edge detect operation the Command Controller supplies 10 the current address, this typically was the location of the last edge, but it could also be the end of a run length. With the current address a color is also supplied and using these two values the NEU will search the previous line for the next edge. If an edge is found the NEU returns this location to the Command Controller as the next address in the current line and it sets a valid bit to tell the Command Controller that the edge has been detected. The Line Fill Unit uses this result to construct the current line. The NEU operates on 16-bit words 15 and it is possible that there is no edge in the current 16 bits in the NEU. In this case the NEU will request more words from the SFU and will keep searching for an edge. It will continue doing this until it finds an edge or reaches the end of the previous line, which is based on the LINELENGTH. A dataflow block diagram of the Next Edge unit is shown in Figure 165. 26.3.8.1 NEU Buffer 20 The algorithm being employed for decompression is based on the whole previous line and is not delineated during the line. However the Next Edge Unit, NEU, can only receive 16 bits at a time from the SFU. This presents a problem for vertical commands if the edge occurs in the successive frame, but refers to a changing element in the current frame. To accommodate this the NEU works on two frames at the same time, the current frame and the first 3 bits 25 from the successive frame. This allows for the information that is needed from the previous line to construct the current frame of the current line. In addition to this buffering there is also buffering right after the data is received from the SFU as the SFU output is not registered. The current implementation of the SFU takes two clock cycles from when a request for a current line is received until it is returned and registered. However when NEU requests a new frame it 30 needs it on the next clock cycle to maintain a decoded rate of 2 bits per clock cycle. A more detailed diagram of the buffer in the NEU is shown in Figure 166. The output of the buffer are two 16-bit vectors, use_prev_line_a and use_prev_lineb, that are used to detect an edge that is relevant to the current line being put together in the Line Fill Unit.
WO 2005/120835 PCT/AU2004/000706 780 26.3.8.2 NEU Edge Detect The NEU Edge Detect block takes the two 16 bit vectors supplied by the buffer and based on the current line position in the current line, aO, and the current color, sdcolor, it will detect if there is an edge relevant to the current frame. If the edge is found it supplies the current line position, b1p, to the command controller and the 5 line fill unit. The configuration of the edge detect is shown in Figure 167. The two vectors from the buffer, use_prev line a and use_prevlineb, pass into two sub-blocks, transition wtob and transition btow. transitionwtob detects if any white to black transitions occur in the 19 bit vector supplied and outputs a 19-bit vector displaying the transitions. transitionwtob is functionally the same as transitionbtow, but it detects white to black transitions. 10 The two 19-bit vectors produced enter into a multiplexer and the output of the multiplexer is controlled by colorneu. colorneu is the current edge transition color that the edge detect is searching for. The output of the multiplexer is masked against a 19-bit vector, the mask is comprised of three parts concatenated together: decode_b_ext, decodeb and FIRSTFLUWRITE. The output of transition wtob (and it complement transitionbtow) are all the transitions in the 16 bit word 15 that is under review. The decodeb is a mask generated from aO. In bit-wise terms all the bits above and including aO are l's and all bits below aO are O's. When they are gated together it means that all the transitions below aO are ignored and the first transition after aO is picked out as the next edge. The decode b block decodes the 4 lsb of the current address (ao) into 16-bit mask bits that control which of the data bits are examined. Table 157 shows the truth table for this block. Table 157. Decodeb truth table 0000 1111111111111111 0001 1111111111111110 0010 1111111111111100 0011 1111111111111000 0100 1111111111110000 0101 1111111111100000 0110 1111111111000000 0111 1111111110000000 1000 1111111100000000 1001 1111111000000000 1010 1111110000000000 1011 1111100000000000 1100 1111000000000000 WO 2005/120835 PCT/AU2004/000706 781 1101 1110000000000000 1110 1100000000000000 1111 1000000000000000 For cases when there is a negative vertical command from the stream decoder it is possible that the edge is in the three lower significant bits of the next frame. The decode_b_ext block supplies the mask so that the necessary bits can be used by the NEU to detect an edge if present, Table 158 shows the truth table for this 5 block. Table 158. Decode_b_ext truth table detta utput Vertical(-3) 111 Vertical(-2) 111 Vertical(-1) 011 OTHERS 001 FIRSTFLU_WRITE is only used in the first frame of the current line. 2.2.5 a) in ANSI/EIA.538 - 1988, Facsimile Coding Schemes and Coding Control Functions for Group 4 Facsimile Equipment, August 1988 refers to "Processing the first picture element", in which it states that "The first starting picture element, aO, 10 on each coding line is imaginarily set at a position just before the first picture element, and is regarded as a white picture element". transition wtob and transitionbtow are set up produce this case for every single frame. However it is only used by the NEU if it is not masked out. This occurs when FIRSTFLU_WRITE is '1' which is only asserted at the beginning of a line. 2.2.5 b) in ANSI/EIA 538 - 1988, Facsimile Coding Schemes and Coding Control Functions for Group 4 15 Facsimile Equipment, August 1988 covers the case of "Processing the last picture element", this case states that "The coding of the coding line continues until the position of the imaginary changing element situated after the last actual element is coded". This means that no matter what the current color is the NEU needs to always find an edge at the end of a line. This feature is used with negative vertical commands. The vector, endframe, is a "one-hot" vector that is asserted during the last frame. It asserts a bit in the end of 20 line position, as determined by LineLength, and this simulates an edge in this location which is ORed with the transition's vector. The output of this, maskeddata, is sent into the encodeBonehot block 26.3.8.3 Encode b one hot The encode_b_one hot block is the first stage of a two stage process that encodes the data to determine the address of the 0 to 1 transition. Table 159 lists the truth table outlining the functionally required by this block.
WO 2005/120835 PCT/AU2004/000706 782 Table 159. Encode_b_one-hot Truth Table -M iiutPPt XXXXXXXXXXXXXXXXXX1 0000000000000000001 XXXXXXXXXXXXXXXXX10 0000000000000000010 XXXXXXXXXXXXXXXX100 0000000000000000100 XXXXXXXXXXXXXXX1000 0000000000000001000 XXXXXXXXXXXXXX1 0000 0000000000000010000 XXXXXXXXXXXXX1 00000 0000000000000100000 XXXXXXXXXXXX1 000000 0000000000001000000 XXXXXXXXXXX10000000 0000000000010000000 XXXXXXXXXX1 00000000 0000000000100000000 XXXXXXXXX1 000000000 0000000001000000000 XXXXXXXX10000000000 0000000010000000000 XXXXXXX1 00000000000 0000000100000000000 XXXXXX1000000000000 0000001000000000000 XXXXX1 0000000000000 0000010000000000000 XXXXi 00000000000000 0000100000000000000 XXX1000000000000000 0001000000000000000 Xx10000000000000000 0010000000000000000 X100000000000000000 0100000000000000000 1000000000000000000 1000000000000000000 0000000000000000000 0000000000000000000 The output of encode_b onehot is a "one-hot" vector that will denote where that edge transition is located. In cases of multiple edges, only the first one will be picked.
WO 2005/120835 PCT/AU2004/000706 783 26.3.8.4 Encode b 4bit Encode_b_4bit is the second stage of the two stage process that encodes the data to determine the address of the 0 to 1 transition. Encode b_4bit receives the "one-hot" vector from encode b one hot and determines the bit location that is 5 asserted. If there is none present this means that there was no edge present in this frame. If there is a bit asserted the bit location in the vector is converted to a number, for example if bit 0 is asserted then the number is one, if bit one is asserted then the number is one, etc. The delta supplied to the NEU determines what vertical command is being processed. The formula that is implemented to return b1p to the command controller is: 10 for V(n) bip = x + n modulus16 where x is the number that was extracted from the "one-hot" vector and n is the vertical command. 26.3.8.5 State machine 15 The following is an explanation of all the states that the NEU state machine utilizes. i NEU START This is the state that NEU enters when a hard or soft reset occurs or when Go has been de-asserted. This state can not left until the reset has been removed, Go has been asserted and it detects that the command controller has entered it's A WAIT BUFF state. When this occurs the NEU enters the NEU FILL-BUFF 20 state. ii NEU FILL BUFF Before any compressed data can be decoded the NEU needs to fill up its buffer with new data from the SFU. The rest of the LBD waits while the NEU retrieves the first four frames from the previous line. Once completed it enters the NEUHOLD state. 25 iii AEU HOLD The NEU waits in this state for one clock cycle while data requested from the SFU on the last access returns. iv NEU RUNNING NEURUNNING controls the requesting of data from the SFU for the remainder of the line by pulsing 30 lbd sfu_pladvword when the LBD needs a new frame from the SFU. When the NEU has received all the word it needs for the current line, as denoted by the LineLength, the NEU enters the NEUEMPTY state. v NEU EMPTY WO 2005/120835 PCT/AU2004/000706 784 NEU waits in this state while the rest of the LBD finishes outputting the completed line to the SFU. The NEU leaves this state when Go gets deasserted. This occurs when the end of line signal is detected from the LBD. 26.3.9 Line Fill Unit sub-block description 5 The Line Fill Unit, LFU, is responsible for filling the next line buffer in the SFU. The SFU receives the data in blocks of sixteen bits. The LFU uses the color and aO provided by the Command Controller and when it has put together a complete 16-bit frame, it is written out to the SFU. The LBD signals to the SFU that the data is valid by strobing the lbd sfu wdatavalid signal. When the LFU is at the end of the line for the current line data it strobes lbd sfuadvline to indicate to the 10 SFU that the end of the line has occurred. A dataflow block diagram of the line fill unit is shown in Figure 167. The dataflow above has the following blocks: 26.3.9.1 State Machine The following is an explanation of all the states that the LFU state machine utilizes. 15 i LFU START This is the state that the LFU enters when a hard or soft reset occurs or when Go has been de-asserted. This state can not left until the reset has been removed, Go has been asserted and it detects that aO is no longer zero, this only occurs once the command controller start processing data from the Next Edge Unit, NEU. 20 ii LFU NEW REG LFU_NEWREG is only entered at the beginning of a new frame. It can remain in this state on subsequent cycles if a whole frame is completed in one clock cycle. If the frame is completed the LFU will output the data to the SFU with the write enable signal. However if a frame is not completed in one clock cycle the state machine will change to the LFUCOMPLETEREG state to complete the remainder of the frame. 25 LFU_NEW_REG handles all the lbdsfu_wdata writes and asserts lbd sfu_wdatavalid as necessary. iii LFU COMPLETEREG LFUCOMPLETE_REG fills out all the remaining parts of the frame that were not completed in the first clock cycle. The command controller supplies the aO value and the color and the state machine uses these to derive the limit and color_sel_J6bitIf which the line_fill data block needs to construct a frame. Limit 30 is the four lower significant bits of aC and colorsel_16bitlfis a 16-bit wide mask of sdcolor. The state WO 2005/120835 PCT/AU2004/000706 785 machine also maintains a check on the upper eleven bits of aO. If these increment from one clock cycle to the next that means that a frame is completed and the data can be written to the SFU. In the case of the LineLength being reached the Line Fill Unit fills out the remaining part of the frame with the color of the last bit in the line that was decoded. 5 26.3.9 line fill data linefilldata takes the limit value and the color selI6bitlf values and constructs the current frame that the command controller and the next edge unit are decoding. The following pseudo code illustrate the logic followed by the linefilldata. work sfuwdata is exported by the LBD to the SFU as lbdsfu wdata. 10 if (lfu-state == LFU_START) OR (lfustate == LFU_NEWREG) then worksfu_wdata = colorsel_16bit_lf else work_sfu_wdata[(l5 - limit) downto limit] = color-sel_16bit-lf[(15 - limit) downto limit] 15 27 SPOT FIFO UNIT (SFU) 27.1 OVERVIEW The Spot FIFO Unit (SFU) provides the means by which data is transferred between the LBD and the HCU. 20 By abstracting the buffering mechanism and controls from both units, the interface is clean between the data user and the data generator. The amount of buffering can also be increased or decreased without affecting either the LBD or HCU. Scaling of data is performed in the horizontal and vertical directions by the SFU so that the output to the HCU matches the printer resolution. Non-integer scaling is supported in both the horizontal and vertical directions. Typically, the scale factor will be the same in both directions but may be 25 programmed to be different. 27.2 MAIN FEATURES OF THE SFU The SFU replaces the Spot Line Buffer Interface (SLBI) in PECL. The spot line store is now located in DRAM. The SFU outputs the previous line to the LBD, stores the next line produced by the LBD and outputs the HCU 30 read line. Each interface to DRAM is via a feeder FIFO. The LBD interfaces to the SFU with a data width of 16 bits. The SFU interfaces to the HCU with a data width of 1 bit. Since the DRAM word width is 256-bits but the LBD line length is a multiple of 16 bits, a capability to flush the last multiples of 16-bits at the end of a line into a 256-bit DRAM word size is required. Therefore, SFU reads of DRAM words at the end of a line, which do not fill the DRAM word, will already be padded.
WO 2005/120835 PCT/AU2004/000706 786 A signal sfu lbd rdy to the LBD indicates that the SFU is available for writing and reading. For the first LBD line after SFU Go has been asserted, previous line data is not supplied until after the first lbd sfu_advline strobe from the LBD (zero data is supplied instead), and sfu lbd rdy to the LBD indicates that the SFU is available for writing. lbd_sfu_advline tells the SFU to advance to the next line. lbd_sfu_pladvword tells the 5 SFU to supply the next 16-bits of previous line data. Until the number of lbd_sfupladvword strobes received is equivalent to the LBD line length, sfujlbd rdy indicates that the SFU is available for both reading and writing. Thereafter it indicates the SFU is available for writing. The LBD should not generate lbdsfuladvword or lbdsfu advline strobes until sfulbdrdy is asserted. A signal sfu hcu avail indicates that the SFU has data to supply to the HCU. Another signal hcusfu_advdot 10 from the HCU, tells the SFU to supply the next dot. The HCU should not generate the hcu sfuadvdot signal until sfuhcuavail is true. The HCU can therefore stall waiting for the sfuhcuavail signal. X and Y non-integer scaling of the bi-level dot data is performed in the SFU. At 1600 dpi the SFU requires 1 dot per cycle for all DRAM channels, 3 dots per cycle in total (read + read + write). Therefore the SFU requires two 256 bit read DRAM access per 256 cycles, 1 write access every 256 15 cycles. A single DIU read interface will be shared for reading the current and previous lines from DRAM. 27.3 BI-LEVEL DRAM MEMORY BUFFER BETWEEN LBD, SFU AND HCU Figure 171 shows a bi-level buffer store in DRAM. Figure 171 (a) shows the LBD previous line address reading after the HCU read line address in DRAM. Figure 171 (b) shows the LBD previous line address reading before the HCU read line address in DRAM. 20 Although the LBD and HCU read and write complete lines of data, the bi-level DRAM buffer is not line based. The buffering between the LBD, SFU and HCU is a FIFO of programmable size. The only line based concept is that the line the HCU is currently reading cannot be over-written because it may need to be re-read for scaling purposes. The SFU interfaces to DRAM via three FIFOs: 25 a. The HCUReadLineFIFO which supplies dot data to the HCU. b. The LBDNextLineFIFO which writes decompressed bi-level data from the LBD. c. The LBDPrevLineFIFO which reads previous decompressed bi-level data for the LBD. There are four address pointers used to manage the bi-level DRAM buffer: a. hcu_readline_rd_adr[21:5] is the read address in DRAM for the HCUReadLineFIFO. 30 b. hcustartreadlineadr[21:5] is the start address in DRAM for the current line being read by the HCUReadLineFIFO. c. lbdnextline_wr_adr[21:5] is the write address in DRAM for the LBDNextLineFIFO. d. lbd_prevline_rd_adr[21:5] is the read address in DRAM for the LBDPrevLineFIFO. The address pointers must obey certain rules which indicate whether they are valid: WO 2005/120835 PCT/AU2004/000706 787 a. hcureadlinerdadr is only valid if it is reading earlier in the line than lbd_nextlinewradr is writing i.e. the fifo is not empty b. The SFU (lbdnextline wradr) cannot overwrite the current line that the HCU is reading from (hcu.startreadline_adr) i.e. the fifo is not full, when compared with the HCU read line pointer 5 c. The LBDNextLineFIFO (lbdnextline_wr_adr) must be writing earlier in the line than LBDPrevLineFIFO (lbd_prevline rd adr) is reading and must not overwrite the current line that the HCU is reading from i.e. the fifo is not full when compared to the PrevLineFifo read pointer d. The LBDPrevLineFIFO (lbd_previnerdadr) can read right up to the address that LBDNextLineFIFO (lbdnextlinewradr) is writing i.e the fifo is not empty. 10 e. At startup i.e. when sfu_go is asserted, the pointers are reset to start_sfuadr[21:5]. f. The address pointers can wrap around the SFU bi-level store area in DRAM. As a guideline, the typical FIFO size should be a minimum of 2 lines stored in DRAM, nominally 3 lines, up to a programmable number of lines. A larger buffer allows lines to be decompressed in advance. This can be useful for absorbing local complexities in compressed bi-level images. 15 27.4 DRAM ACCESS REQUIREMENTS The SFU has 1 read interface to the DIU and 1 write interface. The read interface is shared between the previous and current line read FIFOs. The spot line store requires 5.1 Kbytes of DRAM to store 3 A4 lines. The SFU will read and write the spot line store in single 256-bit DRAM accesses. The SFU will need 256-bit double buffers for each of its 20 previous, current and next line interfaces. The SFU's DIU bandwidth requirements are summarized in Table 160. Table 160. DRAM bandwidth requirements _VW --- a wk Pea adwidth f ' N Maximum number of required to be Average Direction cycles between each supported by Bandwidth 10 256-bit DR AM access DIU (bits/cycle) ~J'A Read 128' 2 2 Write 2562 1 1 1: Two separate reads of 1 bit/cycle. 2: Write at I bit/cycle. 27.5 SCALING 25 Scaling of bi-level data is performed in both the horizontal and vertical directions by the SFU so that the output to the HCU matches the printer resolution. The SFU supports non-integer scaling with the scale factor represented by a numerator and a denominator. Only scaling up of the bi-level data is allowed, i.e. the WO 2005/120835 PCT/AU2004/000706 788 numerator should be greater than or equal to the denominator. Scaling is implemented using a counter as described in the pseudocode below. An advance pulse is generated to move to the next dot (x-scaling) or line (y-scaling). 5 if (count + denominator >= numerator) then count = (count + denominator) - numerator advance = 1 else count = count + denominator 10 advance = 0 X scaling controls whether the SFU supplies the next dot or a copy of the current dot when the HCU asserts hcusfu_advdot. The SFU counts the number of hcu_sfu advdot signals from the HCU. When the SFU has supplied an entire HCU line of data, the SFU will either re-read the current line from DRAM or advance to 15 the next line of HCU read data depending on the programmed Y scale factor. An example of scaling for numerator = 7 and denominator = 3 is given in Table 161. The signal advance if asserted causes the next input dot to be output on the next cycle, otherwise the same input dot is output Table 161. Non-integer scaling example for scaleNum = 7, scaleDenom = 3 0 0 1 3 0 1 6 1 1 2 0 2 5 1 2 1 0 3 4 1 3 0 0 4 3 0 4 6 1 4 2 0 5 27.6 LEAD-IN AND LEAD-OUT CLIPPING 20 To account for the case where there may be two SoPEC devices, each generating its own portion of a dot-line, the first dot in a line may not be replicated the total scale-factor number of times by an individual SoPEC. The dot will ultimately be scaled-up correctly with both devices doing part of the scaling, one on its lead-out and the other on its lead in. Scaled up dots on the lead-out, i.e. which go beyond the HCU linelength, will be WO 2005/120835 PCT/AU2004/000706 789 ignored. Scaling on the lead-in, i.e. of the first valid dot in the line, is controlled by setting the XstartCount register. At the start of each line count in the pseudo-code above is set to XstartCount. If there is no lead-in, XstartCount is set to 0 i.e. the first value of count in Table 161. If there is lead-in then XstartCount needs to 5 be set to the appropriate value of count in the sequence above. 27.7 INTERFACES BETWEEN LDB, SFU AND HCU 27.7.1 LDB-SFU Interfaces The LBD has two interfaces to the SFU. The LBD writes the next line to the SFU and reads the previous line from the SFU. 10 27.7.1.1 LBDNextLineFIFO Interface The LBDNextLineFIFO interface from the LBD to the SFU comprises the following signals: " lbd sfu wdata, 16-bit write data. e lbd~sfuwdatavalid, write data valid. * lbdsfuadvline, signal indicating LDB has advanced to the next line. 15 The LBD should not write to the SFU until sfujlbd~rdy is true. The LBD can therefore stall waiting for the sfulbd rdy signal. 27.7.1.2 LBDPrevLineFIFO Interface The LBDPrevLineFIFO interface from the SFU to the LBD comprises the following signals: e sfulbd_pidata, 16-bit data. 20 The previous line read buffer interface from the LBD to the SDU comprises the following signals: * lbd sfupladvword, signal indicating to the SFU to supply the next 16-bit word. e lbdsfuadvine, signal indicating LDB has advanced to the next line. Previous line data is not supplied until after the first lbd sfu _advline strobe from the LBD (zero data is supplied instead). The LBD should not assert lbd sfu_pladvword unless sfu lbd rdy is asserted. 25 27.7.1.3 Common Control Signals sflbdrdy indicates to the LBD that the SFU is available for writing. After the first lbdsfu advline and before the number of lbd _sfu_pladvword strobes received is equivalent to the LBD line length, sfulbdrdy indicates that the SFU is available for both reading and writing. Thereafter it indicates the SFU is available for writing. 30 The LBD should not generate lbd sfujpladvword or lbd sfuadvline strobes until sfu lbd~rdy is asserted.
WO 2005/120835 PCT/AU2004/000706 790 27.7.2 SFU-HCU Current Line FIFO Interface The interface from the SFU to the HCU comprises the following signals: * sfuhcusdata, 1-bit data. * sfuhcu avail, data valid signal indicating that there is data available in the SFU 5 HCUReadLineFIFO. The interface from HCU to SFU comprises the following signals: * hcusfuadvdot, indicating to the SFU to supply the next dot. The HCU should not generate the hcu sfuadvdot signal until sfuhcu_avail is true. The HCU can therefore stall waiting for the sfu hcu avail signal. 10 27.8 IMPLEMENTATION 27.8.1 Definitions of 10 Table 162. SFU Port List Clocks and Resets Pclk 1 In SoPEC Functional clock. prstn 1 In Global reset signal. DIU Read Interface signals sfu-diu-rreq 1 Out SFU requests DRAM read. A read request must be accompanied by a valid read address. sfu-diu-radr[21:5] 17 Out Read address to DIU 17 bits wide (256-bit aligned word). diusfurack 1 In Acknowledge from DIU that read request has been accepted and new read address can be placed on sfu_diu_radr. diu-data[63:0] 64 In Data from DIU to SoPEC Units. First 64-bits are bits 63:0 of 256 bit word. Second 64-bits are bits 127:64 of 256 bit word. Third 64-bits are bits 191:128 of 256 bit word. Fourth 64-bits are bits 255:192 of 256 bit word. diusfu_rvalid 1 In Signal from DIU telling SoPEC Unit that valid read data is on the diu_data bus. DIU Write Interface signals sfudiuwreq 1 Out SFU requests DRAM write. A write request must be accompanied by a valid write address together with valid write data and a write valid. sfu-diuwadr[21:5] 17 Out Write address to DIU 17 bits wide (256-bit aligned word).
WO 2005/120835 PCT/AU2004/000706 791 diu-sfu-wack 1 In Acknowledge from DIU that write request has been accepted and new write address can be placed on sfu_diuwadr. sfu-diu-data[63:0] 64 Out Data from SFU to DIU. First 64-bits are bits 63:0 of 256 bit word. Second 64-bits are bits 127:64 of 256 bit word. Third 64-bits are bits 191:128 of 256 bit word. Fourth 64-bits are bits 255:192 of 256 bit word. sfudiuwvalid 1 Out Signal from PEP Unit indicating that data on sfu_diu_data is valid. PCU Interface data and control signals pcu-adr[6:2] 5 In PCU address bus. Only 5 bits are required to decode the address space for this block pcu.dataout[31:01 32 In Shared write data bus from the PCU sfupcu.datain[31:0] 32 Out Read data bus from the SFU to the PCU pcurwn 1 In Common read/not-write signal from the PCU pcusfu_sel 1 In Block select from the PCU. When pcu_sfusel is high both pcuadr and pcu_dataout are valid sfu.pcu-rdy 1 Out Ready signal to the PCU. When sfu~pcurdy is high it indicates the last cycle of the access. For a write cycle this means pcu dataout has been registered by the block and for a read cycle this means the data on sfu pcLdatain is valid. LBD Interface Data and Control Signals sfuIbd-rdy 1 Out Signal indication that SFU has previous line data available and is ready to be written to. Ibdsfuadvline 1 In Line advance signal for both next and previous lines. lbd-sfu-pladvword 1 In Advance word signal for previous line buffer. sfulbd-pldata[15:0] 16 Out Data from the previous line buffer. lbd_sfu_wdata[15:0] 16 In Write data for next line buffer. lbd_sfuwdatavalid 1 In Write data valid signal for next line buffer data. HCU Interface Data and Control Signals hcusfuadvdot 1 In Signal indicating to the SFU that the HCU is ready to accept the next dot of data from SFU. sfuhcusdata 1 Out Bi-level dot data. sfuhcuavail 1 Out Signal indicating valid bi-level dot data on sfu_hcu_sdata.
WO 2005/120835 PCT/AU2004/000706 792 27.8.1 27.8.2 Configuration Registers Table 163. SFU Configuration Registers (SFU se+ register name #bits vae description Control registers Ox00 Reset 1 Ox1 A write to this register causes a reset of the SFU. This register can be read to indicate the reset state: 0 - reset in progress 1 - reset not in progress 0x04 Go 1 Ox0 Writing 1 to this register starts the SFU. Writing 0 to this register halts the SFU. When Go is deasserted the state-machines go to their idle states but all counters and configuration registers keep their values. When Go is asserted all counters are reset, but configuration registers keep their values (i.e. they don't get reset). The SFU must be started before the LBD is started. This register can be read to determine if the SFU is running (1 - running, 0 - stopped). Setup registers (constant for during processing the page) 0x08 HCUNumDots 16 Ox0000 Width of HCU line (in dots). Ox0C HCUDRAMWords 8 Ox00 Number of 256-bit DRAM words in a HCU line - 1. Ox1 0 LBDDRAMWords 8 Ox00 Number of 256-bit words in a LBD line - 1. (LBD line length must be at least 128 bits). Ox1 4 StartSfuAdr[21:5] 17 OxO000 First SFU location in memory. (256-bit aligned DRAM address) Ox18 EndSfuAdr[21:5] 17 0x00000 Last SFU location in memory. (256-bit aligned DRAM address) WO 2005/120835 PCT/AU2004/000706 793 Ox1 C XstartCount 8 Ox00 Value to be loaded at the start of every line into the counter used for scaling in the X direction. Used to control the scaling of the first dot in a line. This value will typically equal zero, except in the case where a number of dots are clipped on the lead in to a line. XstartCount must be programmed to be less than the XscaleNum value. Ox20 XscaleNum 8 Ox01 Numerator of spot data scale factor in X direction. Ox24 XscaleDenom 8 Ox01 Denominator of spot data scale factor in X direction. Ox28 YscaleNum 8 Ox01 Numerator of spot data scale factor in Y direction. Ox2C YscaleDenom 8 Ox01 Denominator of spot data scale factor in Y direction. Work registers 0x30 HCUReadLinePtr[31:5] 18 Ox00000 Current address pointer for the (256-bit aligned DRAM HCU read data address) 31 - hcu_readine_rd_wrap FIFO wrap flag 30:22 - Unused, read as zero 21:5 - hcureadline_rd_adr HCU read data DRAM address. Read only register. Ox34 HCUStartReadLinePtr[3 18 Ox00000 Start address pointer of a line 1:5] being read by HCU buffer (256-bit aligned DRAM 31 - hcu_startreadinewrap address) FIFO wrap flag 30:22 - Unused, read as zero 21:5 - hcu_startreadline_adr HCU line start DRAM address. Read only register. 0x38 LBDNextLinePtr[31 :5] 18 Ox00000 Current address pointer for the (256-bit aligned DRAM LBD next line write data address) 31 - Ibdnextlinewrwrap FIFO wrap flag 30:22 - Unused, read as zero 21:5 - Ibdnextine_wr_adr LBD next line write data DRAM address. Register can be written to by CPU. (Working Register) Ox3C LBDPrevLinePtr[31:5] 18 Ox00000 Current address pointer for the (256-bit aligned DRAM LBD previous line read data address) 31 - Ibd previne..rd-wrap FIFO wrap flag 30:22 - Unused, read as zero 21:5 -Ibdprevine_rd_adr LBD previous line read data DRAM address. Read only register WO 2005/120835 PCT/AU2004/000706 794 0x40 FIFOStatus 5 0x19 SFU FIFO status debug register. 0 - plLn/flfifo-emp, previous line and next line FIFO empty signal 1 - piLn/fififojfull, previous line and next line FIFO full signal 2 - ni_hrffifofull, next line and HCU read FIFO full signal 3 - hrf_niffifoemp, HCU read and next line FIFO empty signal 4 - starthrf_niffifoemp, HCU line start read FIFO and next line FIFO empty signal See section 27.8.10.4 on page 534 for exact definition of how the signals are derived. Read only register 27.8.2 27.8.3 SFU sub-block partition The SFU contains a number of sub-blocks: PCU Interface PCU interface, configuration and status registers. Also generates the Go and the Reset signals for the rest of the SFU LBD Previous Line FIFO Contains FIFO which is read by the LBD previous line interface. LBD Next Line FIFO Contains FIFO which is written by the LBD next line interface. HCU Read Line FIFO Contains FIFO which is read by the HCU interface. DIU Interface and Contains DIU read interface and DIU write interface. Manages Address Generator the address pointers for the bi-level DRAM buffer. Contains X and Y scaling logic. 5 The various FIFO sub-blocks have no knowledge of where in DRAM their read or write data is stored. In this sense the FIFO sub-blocks are completely de-coupled from the bi-level DRAM buffer. All DRAM address management is centralised in the DIU Interface and Address Generation sub-block. DRAM access is pre emptive i.e. after a FIFO unit has made an access then as soon as the FIFO has space to read or data to write a DIU access will be requested immediately. This ensures there are no unnecessary stalls introduced e.g. at the 10 end of an LBD or HCU line. There now follows a description of the SFU sub-blocks.
WO 2005/120835 PCT/AU2004/000706 795 27.8.4 PCU Interface Sub-block The PCU interface sub-block provides for the CPU to access SFU specific registers by reading or writing to the SFU address space. 27.8.5 LBDPrevLineFIFO sub-block Table 164. LBDPrevLineFIFO Additional 10 Definitions Internal Output plfrdy 1 Out Signal indicating LBDPrevLineF/FO is ready to be read from. Until the first Ibdsfu_advine for a band has been received and after the number of reads from DRAM for a line is received is equal to LBDDRAMWords, plLrdy is always asserted. During the second and subsequent lines plrdy is reasserted whenever the LBDPrevLineF/FO has one word left in the FIFO. DIU and Address Generation sub-block Signals plfdiurreq 1 Out Signal indicating the LBDPrevLineF/FO has 256-bits of data free. plfdiurack 1 In Acknowledge that read request has been accepted and pldiurreq should be de-asserted. plfdiurdata 1 In Data from the DIU to LBDPrevLineFFO. First 64-bits are bits 63:0 of 256 bit word. Second 64-bits are bits 127:64 of 256 bit word. Third 64-bits are bits 191:128 of 256 bit word. Fourth 64-bits is are 255:192 of 256 bit word. plfdiurrvalid 1 In Signal indicating data on p/Ldiurdata is valid. Plf_diuidle 1 Out Signal indicating DIU state-machine is in the IDLE state. 5 27.8.5 27.8.5. 1General Description The LBDPrevLineFIFO sub-block comprises a double 256-bit buffer between the LBD and the DIU Interface and Address Generator sub-block. The FIFO is implemented as 8 times 64-bit words. The FIFO is written by the DIU Interface and Address Generator sub-block and read by the LBD. 10 Whenever 4 locations in the FIFO are free the FIFO will request 256-bits of data from the DIU Interface and Address Generation sub-block by asserting plf diurreq. A signal plfdiurack indicates that the request has been accepted and plf diurreq should be de-asserted. The data is written to the FIFO as 64-bits on pif diurdata[63:0] over 4 clock cycles. The signal plfdiurvalid indicates that the data returned on pif diurdata[63:0] is valid. pifdiurvalid is used to generate the FIFO write WO 2005/120835 PCT/AU2004/000706 796 enable, writeen, and to increment the FIFO write address, writeadr[2:0J. If the LBDPrevLineFIFO still has 256-bits free then plfdiurreq should be asserted again. The DIU Interface and Address Generation sub-block handles all address pointer management and DIU interfacing and decides whether to acknowledge a request for data from the FIFO. 5 The state diagram of the LBDPrevLineFIFO DIU Interface is shown in Figure 176. If sfu_go is deasserted then the state-machine returns to its idle state. The LBD reads 16-bit wide data from the LBDPrevLineFIFO on sfu lbd_pldata[15:0]. lbd sfufpladvword from the LBD tells the LBDPrevLineFIFO to supply the next 16-bit word. The FIFO control logic generates a signal wordselect which selects the next 16-bits of the 64-bit FIFO word to output on sfulbd pldata[15:0]. 10 When the entire current 64-bit FIFO word has been read by the LBD lbd sfu_pladvword will cause the next word to be popped from the FIFO. Previous line data is not supplied until after the first lbd sfuadvline strobe from the LBD after sfu_go is asserted (zero data is supplied instead). Until the first lbd sfuadvline strobe after sfugo lbd sfupladvword strobes are ignored. 15 The LBDPrevLineFIFO control logic uses a counter, plcount[7:0], to counts the number of DRAM read accesses for the line. When the p1 count counter is equal to the LBDDRAMWords, a complete line of data has been read by the LBD the plfrdy is set high, and the counter is reset. It remains high until the next lbdsfu_advline strobe from the LBD. On receipt of the lbd sfu advline strobe the remaining data in the 256 bit word in the FIFO is ignored, and the FIFO readadr is rounded up if required. 20 The LBDPrevLineFIFO generates a signal plf rdy to indicate that it has data available. Until the first lbd sfu_advline for a band has been received and after the number of DRAM reads for a line is equal to LBDDRAMWords, plf rdy is always asserted. During the second and subsequent lines plf rdy is deasserted whenever the LBDPrevLineFIFO has one word left. The last 256-bit word for a line read from DRAM can contain extra padding which should not be output to the 25 LBD. This is because the number of 16-bit words per line may not fit exactly into a 256-bit DRAM word. When the count of the number of DRAM reads for a line is equal to lbddramwords the LBDPrevLineFIFO must adjust the FIFO write address to point to the next 256-bit word boundary in the FIFO for the next line of data. At the end of a line the read address must round up the nearest 256-bit word boundary and ignore the remaining 16-bit words. This can be achieved by considering the FIFO read address, read adr[2:0], will 30 require 3 bits to address 8 locations of 64-bits. The next 256-bit aligned address is calculated by inverting the MSB of the readadr and setting all other bits to 0. if (read-adr(1:0] /= bOO AND lbdsfu_advline == 1)then read-adr[1:01 = bOO 35 readadr[2] = -read_adr[2] WO 2005/120835 PCT/AU2004/000706 797 27.8.6 LBDNextLineFIFO sub-block Table 165. LBDNextLineFIFO Additional 10 Definition Pot amd Pinsrfl 1/0 De ~ cn2ti LBDNextLineFIFO Interface Signals nlf rdy 1 Out Signal indicating LBDNextLineF/FO is ready to be written to i.e. there is space in the FIFO. DIU and Address Generation sub-block Signals nif diuwreq 1 Out Signal indicating the LBDNextLineF/FO has 256-bits of data for writing to the DIU. nif diuwack 1 In Acknowledge from DIU that write request has been accepted and write data can be output on nifdiuwdata together with nif diuwvalid. nlf_diuwdata 1 Out Data from LBDNextLineF/FO to DIU Interface. First 64-bits is bits 63:0 of 256 bit word Second 64-bits is bits 127:64 of 256 bit word Third 64-bits is bits 191:128 of 256 bit word Fourth 64-bits is bits 255:192 of 256 bit word nf_diuwvalid 1 In Signal indicating that data on wif diuwdata is valid. 27.8.6 27.8.6.1 General Description The LBDNextLineFIFO sub-block comprises a double 256-bit buffer between the LBD and the DIU Interface 5 and Address Generator sub-block. The FIFO is implemented as 8 times 64-bit words. The FIFO is written by the LBD and read by the DIU Interface and Address Generator. Whenever 4 locations in the FIFO are full the FIFO will request 256-bits of data to be written to the DIU Interface and Address Generator by asserting nif diuwreq. A signal nif diuwack indicates that the request has been accepted and nlf diuwreq should be de-asserted. On receipt of nif diuwack, the data is sent to the DIU 10 Interface as 64-bits on nif diuwdata[63:0] over 4 clock cycles. The signal nifdiuwvalid indicates that the data on nlfdiuwdata[63:0] is valid. nlfdiuwvalid should be asserted with the smallest -latency after nlf diuwack. If the LBDNextLineFIFO still has 256-bits more to transfer then nf diuwreq should be asserted again. The state diagram of the LBDNextLineFIFO DIU Interface is shown in Figure 179. If sfugo is deasserted 15 then the state-machine returns to its Idle state. The signal nif rdy indicates that the LBDNextLineFIFO has space for writing by the LBD. The LBD writes 16-bit wide data supplied on lbd_ sfuwdata[15:0]. lbd sfuwvalid indicates that the data is valid. The LBDNextLineFIFO control logic counts the number of lbdsfu wvalid signals and is used to correctly address into the next line FIFO. The lbd_sfuwvalid counter is rounded up to the nearest 256-bit word when a WO 2005/120835 PCT/AU2004/000706 798 lbdsfu_advline strobe is received from the LBD. Any data remaining in the FIFO is flushed to DRAM with padding being added to fill a complete 256-bit word. 27.8.7 sfu_Ibd_rdy Generation The signal sfu lbd rdy is generated by ANDing pif rdy from the LBDPrevLineFIFO and nifrdy from the 5 LBDNextLineFIFO. sfulbdrdy indicates to the LBD that the SFU is available for writing i.e. there is space available in the LBDNextLineFIFO. After the first lbd_sfuadvline and before the number of lbd~sfuladvword strobes received is equivalent to the line length, sfu lbd rdy indicates that the SFU is available for both reading, i.e. there is data in the LBDPrevLineFIFO, and writing. Thereafter it indicates the SFU is available for writing. 10 27.8.8 LBD-SFU Interfaces Timing Waveform Description In Figure 180 and Figure 181, shows the timing of the data valid and ready signals between the SFU and LBD. A diagram and pseudocode is given for both read and write interfaces between the SFU and LBD. 27.8.8.1 LBD-SFU write interface timing The main points to note from Figure 180 are: 15 e In clock cycle 1 sfu lbd~rdy detects that it has only space to receive 2 more 16 bit words from the LBD after the current clock cycle. * The data on lbd~sfuwdata is valid and this is indicated by lbd sfu wdatavalid being asserted. * In clock cycle 2 sfu lbd~rdy is deasserted however the LBD can not react to this signal until clock cycle 3. So in clock cycle 3 there is also valid data from the LBD which consumes the last available 20 location available in the FIFO in the SFU (FIFO free level is zero). * In clock cycle 4 and 5 the FIFO is read and 2 words become free in the FIFO. * In cycle 4 the SFU determines that the FIFO has more room and asserts the ready signal on the next cycle. * The LBD has entered a pause mode and waits for sfujlbd rdy to be asserted again, in cycle 5 the 25 LBD sees the asserted ready signal and responds by writing one unit into the FIFO, in cycle 6. * The SFU detects it has 2 spaces left in the FIFO and the current cycle is an active write (same as in cycle 1), and deasserts the ready on the next cycle. * In cycle 7 the LBD did not have data to write into the FIFO, and so the FIFO remains with one space left 30 0 The SFU toggles the ready signal every second cycle, this allows the LBD to write one unit at a time to the FIFO. " In cycle 9 the LBD responds to the single ready pulse by writing into the FIFO and consuming the last remaining unit free. The write interface pseudocode for generating the ready is.
WO 2005/120835 PCT/AU2004/000706 799 // ready generation pseudocode if (fifo-free-level > 2)then nlf-rdy = 1 elsif (fifo-free-level == 2) then 5 if (lbd_sfuwdatavalid == 1)then nlf_rdy = 0 else nlfrdy = 1 elsif (fifo-free-level == 1) then 10 if (lbdsfu_wdatavalid == 1)then nlfrdy = 0 else nlfrdy = NOT(sfulbdrdy) else 15 nlf-rdy = 0 sfulbdrdy = (nlf-rdy AND plf_rdy) 27.8.8.2 SFU-LBD read interface The read interface is similar to the write interface except that read data (sfu lbd_pldata) takes an extra cycle to respond to the data advance signal (lbd sfu_pladvword signal). 20 It is not possible to read the FIFO totally empty during the processing of a line, one word must always remain in the FIFO. At the end of a line the fifo can be read to totally empty. This functionality is controlled by the SFU with the generation of the p/frdy signal. There is an apparent corner case on the read side which should be highlighted. On examination this turns out to not be an issue. 25 Scenario 1: sfulbdrdy will go low when there is still is still 2 pieces of data in the FIFO. If there is a lbdsfuladvword pulse in the next cycle the data will appear on sfulbdpldata[15:0]. Scenario 2: sfulbdrdy will go low when there is still 2 pieces of data in the FIFO. If there is no lbdsfuj_pladvword 30 pulse in the next cycle and it is not the end of the page then the SFU will read the data for the next line from DRAM and the read FIFO will fill more, sfu_lbd_rdy will assert again, and so the data will appear on sfu_lbd_pldata[15:0]. If it happens that the next line of data is not available yet the sfu lbd_pldata bus will go invalid until the next lines data is available. The LBD does not sample the sfu lbdldata bus at this time (i.e. after the end of a line) and it is safe to have invalid data on the bus. 35 Scenario 3: sfulbdrdy will go low when there is still 2 pieces of data in the FIFO. If there is no lbdsfuladvword pulse in the next cycle and it is the end of the page then the SFU will do no more reads from DRAM, sfulbd_ rdy will remain de-asserted, and the data will not be read out from the FIFO. However last line of WO 2005/120835 PCT/AU2004/000706 800 data on the page is not needed for decoding in the LBD and will not be read by the LBD. So scenario 3 will never apply. The pseudocode for the read FIFO ready generation // ready generation pseudocode 5 if (plcount == lbd_dramn_words) then plfrdy = 1 elsif (fifo-fill-level > 3)then plf_rdy = 1 elsif (fifo-filllevel == 3) then 10 if (lbd_sfupladvword == 1)then plf-rdy = 0 else plfrdy = 1 elsif (fifo fill-level == 2) then 15 if (lbdsfu_pladvword == 1)then plf-rdy = 0 else plf-rdy = NOT(sfulbd-rdy) else 20 plf-rdy = 0 sfulbdrdy = (plfrdy AND nlf-rdy) 27.8.9 HCUReadLineFIFO sub-block Table 166. HCUReadLineFIFO Additional 10 Definition DIU and Address Generation sub-block Signals hrf-xadvance 1 In Signal from horizontal scaling unit 1 - supply the next dot 1 - supply the current dot hrfhcu_endofline 1 Out Signal lasting 1 cycle indicating then end of the HCU read line. hrf.diurreq 1 Out Signal indicating the HCUReadLineFIFO has space for 256-bits of DIU data. hrf_diurack 1 In Acknowledge that read request has been accepted and hrf_diurreq should be de-asserted. hrfdiurdata 1 In Data from HCUReadLineFIFO to DIU. First 64-bits are bits 63:0 of 256 bit word. Second 64-bits are bits 127:64 of 256 bit word. Third 64-bits are bits 191:128 of 256 bit word. Fourth 64-bits are bits 255:192 of 256 bit word. hrfdiurvalid 1 In Signal indicating data on hrf diurdata is valid. hifdiuidle 1 Out Signal indicating DIU state-machine is in the IDLE state.
WO 2005/120835 PCT/AU2004/000706 801 27.8.9 27.8.9.1 General Description The HCUReadLineFIFO sub-block comprises a double 256-bit buffer between the HCU and the DIU Interface and Address Generator sub-block. The FIFO is implemented as 8 times 64-bit words. The FIFO is 5 written by the DIU Interface and Address Generator sub-block and read by the HCU. The DIU Interface and Address Generation (DAG) sub-block interface of the HCUReadLineFIFO is identical to the LBDPrevLineFIFO DIU interface. Whenever 4 locations in the FIFO are free the FIFO will request 256-bits of data from the DAG sub-block by asserting hrfdiurreq. A signal hrf diurack indicates that the request has been accepted and hrf diurreq 10 should be de-asserted. The data is written to the FIFO as 64-bits on hrfdiurdata[63:0] over 4 clock cycles. The signal hrfdiurvalid indicates that the data returned on hrf diurdata[63:0] is valid. hrf diurvalid is used to generate the FIFO write enable, writeen, and to increment the FIFO write address, write adr[2:0]. If the HCUReadLineFIFO still has 256-bits free then hrfdiurreq should be asserted again. 15 The HCUReadLineFIFO generates a signal sfuhcu avail to indicate that it has data available for the HCU. The HCU reads single-bit data supplied on sfu_hcusdata. The FIFO control logic generates a signal bit select which selects the next bit of the 64-bit FIFO word to output on sfuhcusdata. The signal hcu sfu_advdot tells the HCUReadLineFIFO to supply the next dot (hrfxadvance = 1) or the current dot (hrfxadvance = 0) on sfuhcusdata according to the hrf xadvance signal from the scaling control unit in the 20 DAG sub-block. The HCU should not generate the hcu sfuadvdot signal until sfu hcu avail is true. The HCU can therefore stall waiting for the sfu_hcuavail signal. When the entire current 64-bit FIFO word has been read by the HCU hcu sfuadvdot will cause the next word to be popped from the FIFO. The last 256-bit word for a line read from DRAM and written into the HCUReadLineFIFO can contain dots 25 or extra padding which should not be output to the HCU. A counter in the HCUReadLineFIFO, hcuadvdot count[15:0], counts the number of hcu_sfuadvdot strobes received from the HCU. When the count equals hcu num dots[15:0] the HCUReadLineFIFO must adjust the FIFO read address to point to the next 256-bit word boundary in the FIFO. This can be achieved by considering the FIFO read address, read_adr[2:O], will require 3 bits to address 8 locations of 64-bits. The next 256-bit aligned address is 30 calculated by inverting the MSB of the readadr and setting all other bits to 0. If (hcuadvdot-count == hcu_nun_dots) then read.adr[1:0] = bOO read adr[2] = -read adr[2] 35 WO 2005/120835 PCT/AU2004/000706 802 The DIU Interface and Address Generator sub-block scaling unit also needs to know when hcuadvdotcount equals hcunumdots. This condition is exported from the HCUReadLineFIFO as the signal hrfhcuendofline. When the hrfhcu endofline is asserted the scaling unit will decide based on vertical scaling whether to go back to the start of the current line or go onto the next line. 5 27.8.9.2 DRAM Access Limitation The SFU must output 1 bit/cycle to the HCU. Since HCUNumDots may not be a multiple of 256 bits the last 256-bit DRAM word on the line can contain extra zeros. In this case, the SFU may not be able to provide 1 bit/cycle to the HCU. This could lead to a stall by the SFU. This stall could then propagate if the margins being used by the HCU are not sufficient to hide it. The maximum stall can be estimated by the calculation: 10 DRAM service period - X scale factor * dots used from last DRAM read for HCU line. 27.8.10 DIU Interface and Address Generator Sub-block Table 167. DIU Interface and Address Generator Additional 10 Description Internal LBDPrevLineFIFO Inputs plf-diurreq 1 In Signal indicating the LBDPrevLineFFO has 256-bits of data free. plf-diurack 1 Out Acknowledge that read request has been accepted and plLdiurreq should be de-asserted. plf_diurdata 1 Out Data from the DIU to LBDPrevLineFFO. First 64-bits are bits 63:0 of 256 bit word Second 64-bits are bits 127:64 of 256 bit word Third 64-bits are bits 191:128 of 256 bit word Fourth 64-bits are bits 255:192 of 256 bit word plf_diurrvalid 1 Out Signal indicating data on p/Ldiurdata is valid. plf_diuidle 1 In Signal indicating DIU state-machine is in the IDLE state. Internal LBDNextLineFIFO Inputs nifdiuwreq 1 In Signal indicating the LBDNextLineF/FO has 256-bits of data for writing to the DIU. nif_diuwack 1 Out Acknowledge from DIU that write request has been accepted and write data can be output on nifdiuwdata together with nif_diuwvalid. nlf_diuwdata 1 In Data from LBDNextLineF/FOto DIU Interface. First 64-bits are bits 63:0 of 256 bit word Second 64-bits are bits 127:64 of 256 bit word Third 64-bits are bits 191:128 of 256 bit word Fourth 64-bits are bits 255:192 of 256 bit word nif-diuwvalid 1 In Signal indicating that data on wifdiuwdata is valid. Internal HCUReadLineFIFO Inputs hrf_hcuendofline 1 In Signal lasting 1 cycle indicating then end of the HCU read line.
WO 2005/120835 PCT/AU2004/000706 803 hrf-xadvance 1 Out Signal from horizontal scaling unit 1 - supply the next dot 1 - supply the current dot hrf-diurreq 1 In Signal indicating the HCUReadLineFFO has space for 256-bits of DIU data. hrfdiurack 1 Out Acknowledge that read request has been accepted and hrf-diurreq should be de-asserted. hrf-diurdata 1 Out Data from HCUReadLineFIFO to DIU. First 64-bits are bits 63:0 of 256 bit word Second 64-bits are bits 127:64 of 256 bit word Third 64-bits are bits 191:128 of 256 bit word Fourth 64-bits are bits 255:192 of 256 bit word hrf-diurvalid 1 Out Signal indicating data on p/Ldiurdata is valid. hrf-diuidle 1 In Signal indicating DIU state-machine is in the IDLE state.
WO 2005/120835 PCT/AU2004/000706 804 27.8.10 27.8.10.1 General Description The DIU Interface and Address Generator (DAG) sub-block manages the bi-level buffer in DRAM. It has a DIU Write Interface for the LBDNextLineFIFO and a DIU Read Interface shared between the 5 HCUReadLineFIFO and LBDPrevLineFIFO. All DRAM address management is centralised in the DAG. DRAM access is pre-emptive i.e. after a FIFO unit has made an access then as soon as the FIFO has space to read or data to write a DIU access will be requested immediately. This ensures there are no unnecessary stalls introduced e.g. at the end of an LBD or HCU line. The control logic for horizontal and vertical non-integer scaling logic is completely contained in the DAG 10 sub-block. The scaling control unit exports the h/f xadvance signal to the HCUReadLineFIFO which indicates whether to replicate the current dot or supply the next dot for horizontal scaling. 27.8.10.2 DIU Write Interface The LBDNextLineFIFO generates all the DIU write interface signals directly except for sfudiuwadr[21:5] which is generated by the Address Generation logic 15 The DIU request from the LBDNextLineFIFO will be negated if its respective address pointer in DRAM is invalid i.e. nlfadrvalid = 0. The implementation must ensure that no erroneous requests occur on sfudiuwreq. 27.8.10.3 DIU Read Interface Both HCUReadLineFIFO and LBDPrevLineFIFO share the read interface. If both sources request 20 simultaneously, then the arbitration logic implements a round-robin sharing of read accesses between the HCUReadLineFIFO and LBDPrevLineFIFO. The DIU read request arbitration logic generates a signal, select_hrfpjif which indicates whether the DIU access is from the HCUReadLineFIFO or LBDPrevLineFIFO (0=HCUReadLineFIFO, 1 = LBDPrevLineFIFO). Figure 184 shows selecthrfp/f multiplexing the returned DIU acknowledge and read 25 data to either the HCUReadLineFIFO or LBDPrevLineFIFO. The DIU read request arbitration logic is shown in Figure 185. The arbitration logic will select a DIU read request on hrf diurreq or p/f diurreq and assert sfu_ diurreq which goes to the DIU. The accompanying DIU read address is generated by the Address Generation Logic. The select signal selecthrfp/f will be set according to the arbitration winner (0=HCUReadLineFIFO, 1=LBDPrevLineFIFO). sfudiu rreq is cleared 30 when the DIU acknowledges the request on diu sfu rack. Arbitration cannot take place again until the DIU state-machine of the arbitration winner is in the idle state, indicated by diu idle. This is necessary to ensure that the DIU read data is multiplexed back to the FIFO that requested it.
WO 2005/120835 PCT/AU2004/000706 805 The DIU read requests from the HCUReadLineFIFO and LBDPrevLineFIFO will be negated if their respective addresses in DRAM are invalid, hrf adrvalid = 0 or pif adrvalid = 0. The implementation must ensure that no erroneous requests occur on sfudiurreq. If the HCUReadLineFIFO and LBDPrevLineFIFO request simultaneously, then if the request is not following 5 immediately another DIU read port access, the arbitration logic will choose the HCUReadLineFIFO by default If there are back to back requests to the DIU read port then the arbitration logic implements a round robin sharing of read accesses between the HCUReadLineFIFO and LBDPrevLineFIFO. A pseudo-code description of the DIU read arbitration is given below. 10 // history is of type (none, hrf, plf}, hrf is HCUReadLineFIFO, plf is LBDPrevLineFIFO // initialisation on reset select-hrfplf = 0 // default choose hrf history = none // no DIU read access immediately preceding 15 // state-machine is busy between asserting sfudiurreq and diu-idle = 1 // if DIU read requester state-machine is in idle state then de-assert busy if (diu-idle == 1) then 20 busy = 0 //if acknowledge received from DIU then de-assert DIU request if (diu-sfu_rack == 1) then //de-assert request in response to acknowledge 25 sfudiurreq = 0 // if not busy then arbitrate between incoming requests // if request detected then assert busy if (busy == 0) then 30 //if there is no request if (hrf-diurreq == 0) AND (plfdiurreq == 0) then sfudiurreq = 0 history = none // else there is a request 35 else { // assert busy and request DIU read access busy = 1 sfu-diurreq = 1 // arbitrate in round-robin fashion between the requestors 40 // if only HCUReadLineFIFO requesting choose HCUReadLineFIFO if (hrf-diurreq == 1) AND (plf-diurreq == 0) then history = hrf select_hrfplf = 0 // if only LBDPrevLineFIFO requesting choose LBDPrevLineFIFO 45 if (hrf-diurreq == 0) AND (plf-diurreq == 1) then history = plf select_hrfplf = 1 //if both HCUReadLineFIFO and LBDPrevLineFIFO requesting if (hrfdiurreq == 1) AND (plf-diurreq == 1) then 50 // no immediately preceding request choose HCUReadLineFIFO if (history == none) then WO 2005/120835 PCT/AU2004/000706 806 history = hrf select-hrfplf = 0 // if previous winner was HCUReadLineFIFO choose LBDPrevLineFIFO elsif (history == hrf) then 5 history = plf selecthrfplf = 1 // if previous winner was LBDPrevLineFIFO choose HCUReadLineFIFO elsif (history == plf) then history = hrf 10 selecthrfplf = 0 // end there is a request } 27.8.10.4 Address Generation Logic The DIU interface generates the DRAM addresses of data read and written by the SFU's FIFOs. 15 A write request from the LBDNextLineFIFO on nlf diuwreq causes a write request from the DIU Write Interface. The Address Generator supplies the DRAM write address on sfudiu-wadr[21:5]. A winning read request from the DIU read request arbitration logic causes a read request from the DIU Read Interface. The Address Generator supplies the DRAM read address on sfudiuradr[21:5]. The address generator is configured with the number of DRAM words to read in a HCU line, 20 hcudramwords, the first DRAM address of the SFU area, start_ sfu adr[21 5], and the last DRAM address of the SFU area, endsfu_adr[21:5]. Note hcudramwords configuration register specifies the number of DRAM words consumed per line in the HCU, while lbddramwords specifies the number of DRAM words generated per line by the LBD. These values are not required to be the same. 25 For example the LBD may store 10 DRAM words per line (lbddramwords = 10), but the HCU may consume 5 DRAM words per line. In such case the hcu dram words would be set to 5 and the HCU Read Line FIFO would trigger a new line after it had consumed 5 DRAM words (via hrf hcu-endofline). Address Generation 30 There are four address pointers used to manage the bi-level DRAM buffer: a. hcu readline rd adr is the read address in DRAM for the HCUReadLineFIFO. b. hcustartreadlineadr is the start address in DRAM for the current line being read by the HCUReadLineFIFO. c. lbd nextline wr adr is the write address in DRAM for the LBDNextLineFIFO. 35 d. lbd_prevlinerdadr is the read address in DRAM for the LBDPrevLineFIFO. The current value of these address pointers are readable by the CPU. Four corresponding address valid flags are required to indicate whether the address pointers are valid, based on whether the FIFOs are full or empty.
WO 2005/120835 PCT/AU2004/000706 807 a. hif adrvalid, derived from hrf nlffifo emp b. hif startadrvalid, derived from start_hrfnlffifoemp c. nlfadrvalid. derived from nlfplffifo full and nif hrffifo full d. plfadrvalid. derived from plfnIffifoemp 5 DRAM requests from the FIFOs will not be issued to the DIU until the appropriate address flag is valid. Once a request has been acknowledged, the address generation logic can calculate the address of the next 256 bit word in DRAM, ready for the next request. Rules for address pointers The address pointers must obey certain rules which indicate whether they are valid: 10 a. hcureadlinerdadr is only valid if it is reading earlier in the line than lbd_nextline_wr_adr is writing i.e. the fifo is not empty b. The SFU (lbd nextlinewradr) cannot overwrite the current line that the HCU is reading from (hcu-startreadine_adr) i.e. the fifo is not full, when compared with the HCU read line pointer c. The LBDNextLineFIFO (lbd nextline_wr_adr) must be writing earlier in the line than 15 LBDPrevLineFIFO (lbdfprevline rd adr) is reading and must not overwrite the current line that the HCU is reading from i.e. the fifo is not full when compared to the PrevLineFifo read pointer d. The LBDPrevLineFIFO (lbdprevinerdadr) can read right up to the address that LBDNextLineFIFO (lbdnextlinewr adr) is writing i.e the fifo is not empty. e. At startup i.e. when sfugo is asserted, the pointers are reset to start_sfu_adr[21:5]. 20 f. The address pointers can wrap around the SFU bi-level store area in DRAM. Address generator pseudo-code: Initialization: if (sfugo rising edge) then { // initialise address pointers to start of SFU address space 25 lbd_prevlinerdadr = start_sfu_adr[21:5] lbdnextlinewradr = start_sfu_adr[21:5] hcu-readline-rd-adr = startsfuadr[21:5] hcustartreadline-adr = startsfuadr[21:5] lbd~nextlinewr_wrap = 0 30 lbd-prevline-rd-wrap = 0 hcu~startreadline-wrap = 0 hcu~readline_rd_wrap = 0 Determine FIFO fill and empty status: 35 // calculate which FIFOs are full and empty plfnlffifoemp = (lbd_prevlinerdadr == lbdnextline-wr-adr) AND (lbdprevlinerd~wrap == lbdnextline-wr_wrap) nlf_plf_fifofull = (lbdnextline_wr_adr == lbd-prevline-rdadr) AND (lbd_prevline_rd_wrap = lbdnextline-wrwrap) 40 nlfhrf-fifo-full = (lbdnextline_wr_adr == hcu-startreadlineadr ) AND (hcustartreadlinewrap lbdnextline-wrwrap // hcu start address can jump addresses and so needs comparitor if (hcu-startreadlinewrap == lbd_nextline_wr_wrap) then starthrf~nlffifoemp = (hcu_startreadline adr >=lbd_nextlinewr~adr) WO 2005/120835 PCT/AU2004/000706 808 else starthrf_nlffifoemp = NOT(hcustartreadlineadr >=lbd-nextlinewradr) // hcu read address can jump addresses and so needs comparitor if (hcureadlinerd_wrap == lbd_nextlinewrwrap) then 5 hrf_nlf_fifo-emp = (hcureadlinerdadr >=lbdnextlinewradr) else hrfnlf_fifoemp = NOT(hcureadline_rdadr >=lbd_nextline-wradr) Address pointer updating: 10 LBD Next line FIFO // if DIU write acknowledge and LBDNextLineFIFO is not full with reference to PLF and HRF if (lbd-nextline-wr-en == 1) then lbd_nextline-wradr = cpuwrdata[21:5] lbdnextline-wrwrap = cpuwr_data[31] 15 elsif (diu-sfu-wack == 1 AND nlfplffifo_full != 1 AND nlf_hrf_fifofull !=1 ) then if (lbd-nextline-wr-adr == endsfuadr) then // if end of SFU address range lbd-nextline-wr-adr = startsfuadr // go to start of SFU address range 20 lbd-nextline-wr-wrap= NOT (lbd_nextlinewrwrap) // invert the wrap bit else lbdnextline_wr_adr++ // increment address pointer // LBD PrevLine FIFO 25 //if DIU read acknowledge and LBDPrevLineFIFO is not empty if (diusfurack == 1 AND selecthrfplf == 1 AND plf.nlf_fifoemp !=1) then if (lbd-prevlinerdadr == endsfuadr) then lbd_prevline_rdadr = start-sfuadr // go to start of SFU address range 30 lbd-prevlinerdwrap= NOT (lbdtprevlinerd wrap) // invert the wrap bit else lbd_prevlinerdadr++ // increment address pointer // HCU ReadLine FIFO 35 // if DIU read acknowledge and HCUReadLineFIFO fifo is not empty if (diu-sfu-rack == 1 AND select-hrfplf == 0 AND hrf-nlffifoemp = 1) then // going to update hcu read line address if (hrf-hcu-endofline == 1) AND (hrfyadvance == 1) then ( // read the next line from DRAM 40 // advance to start of next HCU line in DRAM hcu_startreadlineadr = hcustartreadlineadr + lbd_dram..words offset = hcu-startreadlineadr - endsfuadr - 1 // allow for address wraparound if (offset >= 0) then 45 hcu_startreadlineadr = startsfuadr + offset hcustartreadline_wrap= NOT(hcu-startreadlinewrap) hcureadline_rdadr = hcu-startreadline-adr hcu-readline-rd-wrap= hcu-startreadlinewrap 50 elsif (hrfhcuendofline == 1) AND (hrf-yadvance == 0) then hcu.readline-rd~adr = hcustartreadlineadr // restart and re-use the same line hcu-readline-rdwrap= hcu_startreadline-wrap elsif (hcureadline-rdadr == end sfu adr) then // check if the FIFO needs 55 to wrap space hcureadlinerdadr = startsfu_adr // go to start of SFU address space hcu-readline-rd-wrap= NOT (hcu-readlinerdwrap) else 60 hcu-readline-rd_adr ++ // increment address pointer WO 2005/120835 PCT/AU2004/000706 809 The CPU can update the lbd nextline wr adr address and lbd_nextline-wr-wrap by writing to the LBDNextLinePtr register. The CPU access mechanism should only be used when LBD is disabled to avoid conflicting LBD and CPU updates to the next line FIFO address. The CPU access always has higher priority than the internal logic update to the lbdnextline_wradr register. When updating the lbd_nextlinewradr 5 address register the CPU must ensure that the new address does not jump the hcustartreadlineadr address, failure to do may cause the SFU to stall indefinitely. 27.8.10.4.1 X scaling of data for HCUReadLineFIFO The signal hcusfuadvdot tells the HCUReadLineFIFO to supply the next dot or the current dot on 10 sfuhcusdata according to the hrfxadvance signal from the scaling control unit. When hrfxadvance is 1 the HCUReadLineFIFO should supply the next dot. When hrfxadvance is 0 the HCUReadLineFIFO should supply the current dot. The algorithm for non-integer scaling is described in the pseudocode below. Note, xscale_count should be loaded with xstartcount after reset and at the end of each line. The end of the line is indicated by 15 hrfhcuendofline from the HCUReadLineFIFO. if (hcusfuadvdot == 1) then if (x_scalecount + x-scaledenom - xscalenum >= 0) then x_scalecount = x_scale-count + xscaledenom - x-scale num 20 hrfxadvance = 1 else x_scalecount = xscalecount + xscaledenom hrf xadvance = 0 else 25 x scale-count = x_scalecount hrfxadvance = 0 27.8.10.4.2 Y scaling of data for HCUReadLineFIFO The HCUReadLineFIFO counts the number of hcu_sfuadvdot strobes received from the HCU. When the count equals hcu-numdots the HCUReadLineFIFO will assert hrf hcuendofline for a cycle. 30 The algorithm for non-integer scaling is described in the pseudocode below. Note, yscalecount should be loaded with zero after reset. if (hrf-hcuendofline == 1) then if (yscale_count + yscaledenom - y-scalenum >= 0) then 35 y-scalecount = y-scale_count + y-scaledenom - yscalenum hrfyadvance = 1 else y_scalecount = yscalecount + y-scale-denom hrf-yadvance = 0 40 else y-scalecount = yscale-count hrf-yadvance = 0 WO 2005/120835 PCT/AU2004/000706 810 When the hrfhcuendofline is asserted the Y scaling unit will decide whether to go back to the start of the current line, by setting hrfyadvance = 0, or go onto the next line, by setting hrfyadvance = 1. Figure 189 shows an overview of X and Y scaling for HCU data. 5 28 TAG ENCODER (TE) 28.1 OVERVIEW The Tag Encoder (TE) provides functionality for Netpage-enabled applications, and typically requires the presence of IR ink (although K ink can be used for tags in limited circumstances). 10 The TE encodes fixed data for the page being printed, together with specific tag data values into an error correctable encoded tag which is subsequently printed in infrared or black ink on the page. The TE places tags on a triangular grid, and can be programmed for both landscape and portrait orientations. Basic tag structures are normally rendered at 1600 dpi, while tag data is encoded into an arbitrary number of printed dots. The TE supports integer scaling in the Y-direction while the TFU supports integer scaling in the 15 X-direction. Thus, the TE can render tags at resolutions less than 1600 dpi which can be subsequently scaled up to 1600 dpi. The output from the TE is buffered in the Tag FIFO Unit (TFU) which is in turn used as input by the HCU. In addition, a te_finishedband signal is output to the end of band unit once the input tag data has been loaded from DRAM. The high level data path is shown by the block diagram in Figure 190. 20 After passing through the HCU, the tag plane is subsequently printed with an infrared-absorptive ink that can be read by a Netpage sensing device. Since black ink can be IR absorptive, limited functionality can be provided on offset-printed pages using black ink on otherwise blank areas of the page - for example to encode buttons. Alternatively an invisible infrared ink can be used to print the position tags over the top of a regular page. However, if invisible IR ink is used, care must be taken to ensure that any other printed information on 25 the page is printed in infrared-transparent CMY ink, as black ink will obscure the infrared tags. The monochromatic scheme was chosen to maximize dynamic range in blurry reading environments. When multiple SoPEC chips are used for printing the same side of a page, it is possible that a single tag will be produced by two SoPEC chips. This implies that the TE must be able to print partial tags. The throughput requirement for the SoPEC TE is to produce tags at half the rate of the PEC 1 TE. Since the 30 TE is reused from PEC 1, the SoPEC TE over-produces by a factor of 2. In PEC1, in order to keep up with the HCU which processes 2 dots per cycle, the tag data interface has been designed to be capable of encoding a tag in 63 cycles. This is actually accomplished in either 52 cycles or 36 cycles approximately, depending on the type of encoding used. If the SoPEC TE were to be modified from two dots production per cycle to a nominal one dot per cycle it should not lose the 63/52 cycle performance 35 edge attained in the PEC1 TE.
WO 2005/120835 PCT/AU2004/000706 811 28.2 WHAT ARE TAGS? The first barcode was described in the late 1940's by Woodland and Silver, and finally patented in 1952 (US Patent 2,612,994) when electronic parts were scarce and very expensive. Now however, with the advent of cheap and readily available computer technology, nearly every item purchased from a shop contains a barcode 5 of some description on the packaging. From books to CDs, to grocery items, the barcode provides a convenient way of identifying an object by a product number. The exact interpretation of the product number depends on the type of barcode. Warehouse inventory tracking systems let users define their own product number ranges, while inventory in shops must be more universally encoded so that products from one company don't overlap with products from another company. Universal Product Codes (UPC) were 10 introduced in the mid 1970's at the request of the National Association of Food Chains for this very reason. Barcodes themselves have been specified in a large number of formats. The older barcode formats contain characters that are displayed in the form of lines. The combination of black and white lines describe the information the barcodes contains. Often there are two types of lines to form the complete barcode: the characters (the information itself) and lines to separate blocks for better optical recognition. While the 15 information may change from barcode to barcode, the lines to separate blocks stays constant. The lines to separate blocks can therefore be thought of as part of the constant structural components of the barcode. Barcodes are read with specialized reading devices that then pass the extracted data onto the computer for further processing. For example, a point-of-sale scanning device allows the sales assistant to add the scanned item to the current sale, places the name of the item and the price on a display device for verification etc. 20 Light-pens, gun readers, scanners, slot readers, and cameras are among the many devices used to read the barcodes. To help ensure that the data extracted was read correctly, checksums were introduced as a crude form of error detection. More recent barcode formats, such as the Aztec 2D barcode developed by Andy Longacre in 1995 (US patent number US5591956), but now released to the public domain, use redundancy encoding schemes 25 such as Reed-Solomon. Very often the degree of redundancy encoding is user selectable. More recently there has also been a move from the simple one dimensional barcodes (line based) to two dimensional barcodes. Instead of storing the information as a series of lines, where the data can be extracted from a single dimension, the information is encoded in two dimensions. Just as with the original barcodes, the 2D barcode contains both information and structural components for better optical recognition. Figure 191 30 shows an example of a QR Code (Quick Response Code), developed by Denso of Japan (US patent number US5726435). Note the barcode cell is comprised of two areas: a data area (depends on the data being stored in the barcode), and a constant position detection pattern. The constant position detection pattern is used by the reader to help locate the cell itself, then to locate the cell boundaries, to allow the reader to determine the original orientation of the cell (orientation can be determined by the fact that there is no 4th corner pattern). 35 The number of barcode encoding schemes grows daily. Yet very often the hardware for producing these barcodes is specific to the particular barcode format. As printers become more and more embedded, there is an increasing desire for real-time printing of these barcodes. In particular, Netpage enabled applications WO 2005/120835 PCT/AU2004/000706 812 require the printing of 2D barcodes (or tags) over the page, preferably in infra-red ink. The tag encoder in SoPEC uses a generic barcode format encoding scheme which is particularly suited to real-time printing. Since the barcode encoding format is generic, the same rendering hardware engine can be used to produce a wide variety of barcode formats. 5 Unfortunately the term "barcode" is interpreted in different ways by different people. Sometimes it refers only to the data area component, and does not include the constant position detection pattern. In other cases it refers to both data and constant position detection pattern. We therefore use the term tag to refer to the combination of data and any other components (such as position detection pattern, blank space etc. surround) that must be rendered to help hold or locate/read the data. A tag 10 therefore contains the following components: * data area(s). The data area is the whole reason that the tag exists. The tag data area(s) contains the encoded data (optionally redundancy-encoded, perhaps simply checksummed) where the bits of the data are placed within the data area at locations specified by the tag encoding scheme. * constant background patterns, which typically includes a constant position detection pattern. These 15 help the tag reader to locate the tag. They include components that are easy to locate and may contain orientation and perspective information in the case of 2D tags. Constant background patterns may also include such patterns as a blank area surrounding the data area or position detection pattern. These blank patterns can aid in the decoding of the data by ensuring that there is no interference between tags or data areas. 20 In most tag encoding schemes there is at least some constant background pattern, but it is not necessarily required by all. For example, if the tag data area is enclosed by a physical space and the reading means uses a non-optical location mechanism (e.g. physical alignment of surface to data reader) then a position detection pattern is not required. Different tag encoding schemes have different sized tags, and have different allocation of physical tag area to 25 constant position detection pattern and data area. For example, the QR code has 3 fixed blocks at the edges of the tag for position detection pattern (see Figure 191) and a data area in the remainder. By contrast, the Netpage tag structure (see Figures 192 and 193) contains a circular locator component, an orientation feature, and several data areas. Figure 192(a) shows the Netpage tag constant background pattern in a resolution independent form. Figure 192(b) is the same as Figure 192(a), but with the addition of the data areas to the 30 Netpage tag. Figure 193 is an example of dot placement and rendering to 1600 dpi for a Netpage tag. Note that in Figure 193 a single bit of data is represented by many physical output dots to form a block within the data area. 28.2.1 Contents of the data area The data area contains the data for the tag. 35 Depending on the tag's encoding format, a single bit of data may be represented by a number of physical printed dots. The exact number of dots will depend on the output resolution and the target reading/scanning resolution. For example, in the QR code (see Figure 191), a single bit is represented by a dark module or a WO 2005/120835 PCT/AU2004/000706 813 light module, where the exact number of dots in the dark module or light module depends on the rendering resolution and target reading/scanning resolution. For example, a dark module may be represented by a square block of printed dots (all on for binary 1, or all off for binary 0), as shown in Figure 194. The point to note here is that a single bit of data may be represented in the printed tag by an arbitrary printed 5 shape. The smallest shape is a single printed dot, while the largest shape is theoretically the whole tag itself, for example a giant macrodot comprised of many printed dots in both dimensions. An ideal generic tag definition structure allows the generation of an arbitrary printed shape from each bit of data. 28.2.2 What do the bits represent? 10 Given an original number of bits of data, and the desire to place those bits into a printed tag for subsequent retrieval via a reading/scanning mechanism, the original number of bits can either be placed directly into the tag, or they can be redundancy-encoded in some way. The exact form of redundancy encoding will depend on the tag format. The placement of data bits within the data area of the tag is directly related to the redundancy mechanism 15 employed in the encoding scheme. The idea is generally to place data bits together in 2D so that burst errors are averaged out over the tag data, thus typically being correctable. For example, all the bits of Reed-Solomon codeword would be spread out over the entire tag data area so to minimize being affected by a burst error. Since the data encoding scheme and shape and size of the tag data area are closely linked, it is desirable to have a generic tag format structure. This allows the same data structure and rendering embodiment to be used 20 to render a variety of tag formats. 28.2.2.1 Fixed and variable data components In many cases, the tag data can be reasonably divided into fixed and variable components. For example, if a tag holds N bits of data, some of these bits may be fixed for all tags while some may vary from tag to tag. For example, the Universal product code allows a country code and a company code. Since these bits don't 25 change from tag to tag, these bits can be defamed as fixed, and don't need to be provided to the tag encoder each time, thereby reducing the bandwidth when producing many tags. Another example is Netpage tags. A single printed page contains a number of Netpage tags. The page-id will be constant across all the tags, even though the remainder of the data within each tag may be different for each tag. By reducing the amount of variable data being passed to SoPEC's tag encoder for each tag, the 30 overall bandwidth can be reduced. Depending on the embodiment of the tag encoder, these parameters will be either implicit or explicit, and may limit the size of tags renderable by the system. For example, a software tag encoder may be completely variable, while a hardware tag encoder such as SoPEC's tag encoder may have a maximum number of tag data bits.
WO 2005/120835 PCT/AU2004/000706 814 28.2.2.2 Redundancy-encode the tag data within the tag encoder Instead of accepting the complete number of TagData bits encoded by an external encoder, the tag encoder accepts the basic non-redundancy-encoded data bits and encodes them as required for each tag. This leads to significant savings of bandwidth and on-chip storage. 5 In SoPEC's case for Netpage tags, only 120 bits of original data are provided per tag, and the tag encoder encodes these 120 bits into 360 bits. By having the redundancy encoder on board the tag encoder the effective bandwidth and internal storage required is reduced to only 33% of what would be required if the encoded data was read directly. 28.3 PLACEMENT OF TAGS ON A PAGE 10 The TE places tags on the page in a triangular grid arrangement as shown in Figure 195. The triangular mesh of tags combined with the restriction of no overlap of columns or rows of tags means that the process of tag placement is greatly simplified. For a given line of dots, all the tags on that line correspond to the same part of the general tag structure. The triangular placement can be considered as alternative lines of tags, where one line of tags is inset by one amount in the dot dimension, and the other line of dots is inset by a 15 different amount. The dot inter-tag gap is the same in both lines of tag, and is different from the line inter-tag gap. Note also that as long as the tags themselves can be rotated, portrait and landscape printing are essentially the same - the placement parameters of line and dot are swapped, but the placement mechanism is the same. The general case for placement of tags therefore relies on a number of parameters, as shown in Figure 196. 20 The parameters are more formally described in Table 168. Note that these are placement parameters and not registers. Table 168. Tag placement parameters Tag height 7 The number of dot lines in a tag's bounding minimum 1 box Tag width The number of dots in a single line of the minimum 1 tag's bounding box. The number of dots in the tag itself may vary depending on the shape of the tag, but the number of dots in the bounding box will be constant (by definition). Dot inter-tag gap The number of dots from the edge of one minimum = 0 tag's bounding box to the start of the next tag's bounding box, in the dot direction. Line inter-tag gap The number of dot lines from the edge of minimum = 0 one tag's bounding box to the start of the next tag's bounding box, in the line direction.
WO 2005/120835 PCT/AU2004/000706 815 Start Position Defines the status of the top left dot on the page - is an offset in dot & row within the tag or the inter-tag gap. AltTagLinePosition Defines the status for the start of the alternate row of tags. Is an offset in dot within the tag or within the dot inter-tag gap (the row position is always 0). 28.4 BASIC TAG ENCODING PARAMETERS SoPEC 's tag encoder imposes range restrictions on tag encoding parameters as a direct result of on-chip buffer sizes. Table 169 lists the basic encoding parameters as well as range restrictions where appropriate. 5 Although the restrictions were chosen to take the most likely encoding scenarios into account, it is a simple matter to adjust the buffer sizes and corresponding addressing to allow arbitrary encoding parameters in future implementations. Table 169. Encoding parameters W page width 2 14 dotpairs or 20.48 inches at 1600 dpi S tag size typical tag size is 2mm x 2mm maximum tag size is 384 dots x 384 dots before scaling i.e. 6 mm x 6 mm at 1600 dpi N number of dots in each dimension of 384 dots before scaling the tag E redundancy encoding for tag data Reed-Solomon GF(2 4 ) at 5:10 or 7:8 DF size of fixed data (unencoded) 40 or 56 bits RF size of redundancy-encoded fixed data 120 bits D, size of variable data (unencoded) 120 or 112 bits R, size of redundancy-encoded variable 360 or 240 bits data T tags per page width 256 The fixed data for the tags on a page need only be supplied to the TE once. It can be supplied as 40 or 56 bits 10 of unencoded data and encoded within the TE as described in Section 28.4.1. Alternatively it can be supplied as 120 bits of pre-encoded data (encoded arbitrarily). The variable data for the tags on a page are those 112 or 120 data bits that are variable for each tag. Variable tag data is supplied as part of the band data, and is always encoded by the TE as described in Section 28.4.1, but may itself be arbitrarily pre-encoded.
WO 2005/120835 PCT/AU2004/000706 816 28.4.1 Redundancy encoding The mapping of data bits (both fixed and variable) to redundancy encoded bits relies heavily on the method of redundancy encoding employed. Reed-Solomon encoding was chosen for its ability to deal with burst errors and effectively detect and correct errors using a minimum of redundancy. 5 In this implementation of the TE, Reed-Solomon encoding over the Galois Field GF(2 4 ) is used. Symbol size is 4 bits. Each codeword contains 15 4-bit symbols for a codeword length of 60 bits. The primitive polynomial is p(x) =.x4 + x + 1, and the generator polynomial is g(x) = (x+ax)(x+a 2 ) ...(x+c?), where t = the number of symbols that can be corrected. Of the 15 symbols, there are two possibilities for encoding: 10 e RS(15, 5): 5 symbols original data (20 bits), and 10 redundancy symbols (40 bits). The 10 redundancy symbols mean that up to 5 symbols in error can be correct. The generator polynomial is therefore g(x) = (x+a)(x+a 2 ).. .(x+x' 0 ). * RS(15, 7): 7 symbols original data (28 bits), and 8 redundancy symbols (32 bits). The 8 redundancy symbols mean that up to 4 symbols in error can be corrected. The generator polynomial is g(x) = 15 (x+a)(x+ 2 )...(x+0). In the first case, with 5 symbols of original data, the total amount of original data per tag is 160 bits (40 fixed, 120 variable). This is redundancy encoded to give a total amount of 480 bits (120 fixed, 360 variable) as follows: " Each tag contains up to 40 bits of fixed original data. Therefore 2 codewords are required for the 20 fixed data, giving a total encoded data size of 120 bits. Note that this fixed data only needs to be encoded once per page. - Each tag contains up to 120 bits of variable original data. Therefore 6 codewords are required for the variable data, giving a total encoded data size of 360 bits. In the second case, with 7 symbols of original data, the total amount of original data per tag is 168 bits (56 25 fixed, 112 variable). This is redundancy encoded to give a total amount of 360 bits (120 fixed, 240 variable) as follows: - Each tag contains up to 56 bits of fixed original data. Therefore 2 codewords are required for the fixed data, giving a total encoded data size of 120 bits. Note that this fixed data only needs to be encoded once per page. 30 - Each tag contains up to 112 bits of variable original data. Therefore 4 codewords are required for the variable data, giving a total encoded data size of 240 bits. The choice of data to redundancy ratio depends on the application. The TE takes approximately 52 cycles to encode a tag using RS(15,5) and approximately 36 cycles using RS(15,7).
WO 2005/120835 PCT/AU2004/000706 817 28.5 DATA STRUCTURES USED BY TAG ENCODER 28.5.1 Tag Format Structure The Tag Format Structure (TFS) is the template used to render tags, optimized so that the tag can be rendered in real time. The TFS contains an entry for each dot position within the tag's bounding box. Each entry 5 specifies whether the dot is part of the constant background pattern or part of the tag's data component (both fixed and variable). The TFS is very similar to a bitmap in that it contains one entry for each dot position of the tag's bounding box. The TFS therefore has TagHeight x TagWidth entries, where TagHeight matches the height of the bounding box for the tag in the line dimension, and TagWidth matches the width of the bounding box for the 10 tag in the dot dimension. A single line of TFS entries for a tag is known as a tag line structure. The TFS consists of TagHeight number of tag line structures, one for each 1600 dpi line in the tag's bounding box. Each tag line structure contains three contiguous tables, known as tables A, B, and C. Table A contains 384 2-bit entries, one entry for each of the maximum number of dots in a single line of a tag (see Table 169). The actual number of entries used should match the size of the bounding box for the tag in the dot dimension, 15 but all 384 entries must be present. Table B contains 32 9-bit data addresses that refer to (in order of appearance) the data dots present in the particular line. All 32 entries must be present, even if fewer are used. Table C contains two 5-bit pointers into table B, and therefore comprises 10 bits. Padding of 214 bits is added. The total length of each tag line structure is therefore 5 x 256-bit DRAM words. Thus a TFS containing TagHeight tag line structures requires a TagHeight * 160 bytes. The structure of a TFS is shown in Figure 20 197. A full description of the interpretation and usage of Tables A, B and C is given in section 28.8.3 on page 593. 28.5.1.1 Scaling a tag If the size of the printed dots is too small, then the tag can be scaled in one of several ways. Either the tag itself can be scaled by N dots in each dimension, which increases the number of entries in the TFS. As an 25 alternative, the output from the TE can be scaled up by pixel replication via a scale factor greater than 1 in the both the TE and TFU. For example, if the original TFS was 21 x 21 entries, and the scaling were a simple 2 x 2 dots for each of the original dots, we could increase the TFS to be 42 x 42. To generate the new TFS from the old, we would repeat each entry across each line of the TFS, and then we would repeat each line of the TFS. The net number 30 of entries in the TFS would be increased fourfold (2 x 2). The TFS allows the creation of macrodots instead of simple scaling. Looking at Figure 198 for a simple example of a 3 x 3 dot tag, we may want to produce a physically large printed form of the tag, where each of the original dots was represented by 7 x 7 printed dots. If we simply performed replication by 7 in each dimension of the original TFS, either by increasing the size of the TFS by 7 in each dimension or putting a WO 2005/120835 PCT/AU2004/000706 818 scale-up on the output of the tag generator output, then we would have 9 sets of 7 x 7 square blocks. Instead, we can replace each of the original dots in the TFS by a 7 x 7 dot definition of a rounded dot. Figure 199 shows the results. Consequently, the higher the resolution of the TFS the more printed dots can be printed for each macrodot, 5 where a macrodot represents a single data bit of the tag. The more dots that are available to produce a macrodot, the more complex the pattern of the macrodot can be. As an example, Figure 193 on page 542 shows the Netpage tag structure rendered such that the data' bits are represented by an average of 8 dots x 8 dots (at 1600 dpi), but the actual shape structure of a dot is not square. This allows the printed Netpage tag to be subsequently read at any orientation. 10 28.5.2 Raw tag data The TE requires a band of unencoded variable tag data if variable data is to be included in the tag bit-plane. A band of unencoded variable tag data is a set of contiguous unencoded tag data records, in order of encounter top left of printed band from top left to lower right. An unencoded tag data record is 128 bits arranged as follows: bits 0-111 or 0-119 are the bits of raw tag data, 15 bit 120 is a flag used by the TE (TagIsPrinted), and the remaining 7 bits are reserved (and should be 0). Having a record size of 128 bits simplifies the tag data access since the data of two tags fits into a 256-bit DRAM word. It also means that the flags can be stored apart from the tag data, thus keeping the raw tag data completely unrestricted. If there is an odd number of tags in line then the last DRAM read will contain a tag in the first 128 bits and padding in the final 128 bits. 20 The TagIsPrinted flag allows the effective specification of a tag resolution mask over the page. For each tag position the TagIsPrinted flag determines whether any of the tag is printed or not. This allows arbitrary placement of tags on the page. For example, tags may only be printed over particular active areas of a page. The TagIsPrinted flag allows only those tags to be printed. TagIsPrinted is a 1 bit flag with values as shown in Table 170. Table 170. TagisPrinted values 0 Don't print the tag in this tag position. Output 0 for each dot within the tag bounding box. 1 Pnnt the tag as specified by the various tag structures. 25 28.5.3 DRAM storage requirements The total DRAM storage required by a single band of raw tag data depends on the number of tags present in that band. Each tag requires 128 bits. Consequently if there are N tags in the band, the size in DRAM is 16N bytes.
WO 2005/120835 PCT/AU2004/000706 819 The maximum size of a line of tags is 163 x 128 bits. When maximally packed, a row of tags contains 163 tags (see Table 169) and extends over a minimum of 126 print lines. This equates to 282 KBytes over a Letter page. The total DRAM storage required by a single TFS is TagHeight/7 KBytes (including padding). Since the 5 likely maximum value for TagHeight is 384 (given that SoPEC restricts TagWidth to 384), the maximum size in DRAM for a TFS is 55 KBytes. 28.5.4 DRAM access requirements The TE has two separate read interfaces to DRAM for raw tag data, TD, and tag format structure, TFS. The memory usage requirements are shown in Table 171. Raw tag data is stored in the compressed page store Table 171. Memory usage requirements Compressed page 2048 Kbytes Compressed data page store for Bi-level, contone store and raw tag data. Tag Format Structure 55 Kbyte (384 dot line 55 kB in PEC1 for 384 dot line tags (the benchmark) tags @ 1600 dpi) at 1600 dpi 2.5 mm tags (1/10th inch) @ 1600 dpi require 160 dot lines = 160/384 x55 or 23 kB 2.5 mm tags @ 800 dpi require 80/384 x55 = 12 kB 10 The TD interface will read 256-bits from DRAM at a time. Each 256-bit read returns 2 times 128-bit tags. The TD interface to the DIU will be a 256-bit double buffer. If there is an odd number of tags in line then the last DRAM read will contain a tag in the first 128 bits and padding in the final 128 bits. The TFS interface will also read 256-bits from DRAM at a time. The TFS required for a line is 136 bytes. A 15 total of 5 times 256-bit DRAM reads is required to read the TFS for a line with 192 unused bits in the fifth 256-bit word. A 136-byte double-line buffer will be implemented to store the TFS data. The TE's DIU bandwidth requirements are summarized in Table 172. Table 172. DRAM bandwidth requirements Maximum number of Peak Bandwidth Average Block Name Direction cycles between each lBandwidth 256bit DRAM access bicyclec) iscce TD Read Single 256 bit reads'. 1.02 1.02 TFS Read Single 256 bit reads 2 . 0.093 0.093 TFS is 136 bytes. This means there is unused data in the fifth 256 bit read. A total of 5 reads is required. 1: Each 2mm tag lasts 126 dot cycles and requires 128 bits. This is a rate of 256 bits every 252 cycles.
WO 2005/120835 PCT/AU2004/000706 820 2: 17 x 64 bit reads per line in PECI is 5 x 256 bit reads per line in SoPEC with unused bits in the last 256-bit read. 28.5.5 TD and TFS Bandstore wrapping Both TD and TFS storage in DRAM can wrap around the bandstore area. The bounds of the band store are 5 defined by the TeStartofBandStore and TeEndofBandStore registers in Table 174. The TD and TFS DRAM interfaces therefore support bandstore wrapping. If the TD or TFS DRAM interface increments an address it is checked to see if it matches the end of bandstore address. If so, then the address is mapped to the start of the bandstore. 28.5.6 Tag sizes 10 SoPEC allows for tags to be between 0 to 384 dots. A typical 2 mm tag requires 126 dots. Short tags do not change the internal bandwidth or throughput behaviours at all. Tag height is specified so as to allow the DRAM storage for raw tag data to be specified. Minimum tag width is a condition imposed by throughput limitations, so if the width is too small TE cannot consistently produce 2 dots per cycle across several tags (also there are raw tag data bandwidth implications). Thinner tags still work, they just take longer and/or need 15 scaling. 28.6 IMPLEMENTATION 28.6.1 Tag Encoder Architecture A block diagram of the TE can be seen below. The TE writes lines of bi-level tag plane data to the TFU for later reading by the HCU. The TE is responsible 20 for merging the encoded tag data with the tag structure (interpreted from the TFS). Y-integer scaling of tags is performed in the TE with X-integer scaling of the tags performed in the TFU. The encoded tag layer is generated 2 bits at a time and output to the TFU at this rate. The HCU however only consumes 1 bit per cycle from the TFU. The TE must provide support for 126dot Tags (2mm densely packed) with 108 Tags per line with 128bits per tag. 25 The tag encoder consists of a TFS interface that loads and decodes TFS entries, a tag data interface that loads tag raw data, encodes it, and provides bit values on request, and a state machine to generate appropriate addressing and control signals. The TE has two separate read interfaces to DRAM for raw tag data, TD, and tag format structure, TFS. 28.6.2 Y-Scaling output lines 30 In order to support scaling in the Y direction the following modifications to the PEC 1 TE are made to the Tag Data Interface, Tag Format Structure Interface and TE Top Level: WO 2005/120835 PCT/AU2004/000706 821 e for Tag Data Interface: program the configuration registers of Table 174, firstTagLineHeight and tagMaxLine with true value i.e. not multiplied up by the scale factor YScale. Within the Tag Data interface there are two counters, countx and county that have a direct bearing on the rawTagDataAddr generation. countx decrements as tags are read from DRAM. It is reset to 5 NumTags[RtdTagSense] at start of each line of tags. county is decremented as each line of tags is completely read from DRAM i.e. countx = 0. Scaling may be performed by counting the number of times countx reaches zero and only decrementing county when this number reaches YScale. This will cause the TagData Interface to read each line of tag data NumTags[RtdTagSense] * YScale times. 10 e for Tag Format Structure Interface: The implication of Y-scaling for the TFS is that each Tag Line Structure is used YScale times. This may be accomplished in the following way: * Fetch each TagLineStructure YScale times. This solution involves controlling the activity of currTfsAddr with YScale. 15 In SoPEC the TFS must supply five addresses to the DIU to read each individual Tag Line Structure. The DIU returns 4*64-bit words for each of the 5 accesses. This is different from the behaviour in PEC1, where one address is given and 17 data-words were returned by the DIU. Since the behaviour of the currTfsAddr must be changed to meet the requirements of the SoPEC DIU it makes sense to include the Y-Scaling into this change i.e. a count of the number of 20 completed sets of 5 accesses to the DIU is compared to YScale. Only when this count equals YScale can currTfsAddr be loaded with the base address of the next lines Tag Line Structure in DRAM, otherwise it is re-loaded with the base address of the current lines Tag Line Structure in DRAM. 25 * For Top Level: The Top Level of the TE has a counter, LinePos, which is used to count the number of completed output lines when in a tag gap or in a line of tags. At the start (i.e. top-left hand dot pair) of a gap or tag LinePos is loaded with either TagGapLine or TagMaxLine. The value of LinePos is decremented at last dot-pair in line. Y-Scaling may be accomplished by gating the decrement of LinePos based on YScale value 30 28.6.3 TE Physical Hierarchy Figure 201 above illustrates the structural hierarchy of the TE. The top level contains the Tag Data Interface (TDI), Tag Format Structure (TFS), and an FSM to control the generation of dot pairs along with a block to carry out the PCU read/write decoding. There is also some additional logic for muxing the output data and generating other control signals. 35 At the highest level, the TE state machine processes the output lines of a page one line at a time, with the starting position either in an inter-tag gap or in a tag (a SoPEC may be only printing part of a tag due to multiple SoPECs printing a single line).
WO 2005/120835 PCT/AU2004/000706 822 If the current position is within an inter-tag gap, an output of 0 is generated. If the current position is within a tag, the tag format structure is used to determine the value of the output dot, using the appropriate encoded data bit from the fixed or variable data buffers as necessary. The TE then advances along the line of dots, moving through tags and inter-tag gaps according to the tag placement parameters. 5 There are three stalling mechanisms that can halt the dot pipeline: " futeoktowrite is deasserted (stalling back from the TFU block); e tfsvalid is deasserted whilst processing a tag (stalling from the TFS DRAM interface); " tdvalid is deasserted whilst processing a tag (stalling from the TD DRAM interface). If any of these three stalling events occurs the dot pipeline is completely stalled and will only start up again 10 when all three signals are active (high). 28.6.4 10 Definitions Table 173. TE Port List Clocks and Resets pclk 1 In SoPEC Functional clock. prst_n 1 In Global reset signal. Bandstore Signals te_finishedband 1 Out TE finished band signal to PCU and ICU. PCU Interface data and control signals pcu-addr[8:2] 7 In PCU address bus. 7 bits are required to decode the address space for this block. pcu-dataout[31:0] 32 In Shared write data bus from the PCU. te.pcu-datain[31:0] 32 Out Read data bus from the TE to the PCU. pcurwn 1 In Common read/not-write signal from the PCU. pcutesel 1 In Block select from the PCU. When pcujtesel is high both pcuaddr and pcu_dataout are valid. tepcu-rdy 1 Out Ready signal to the PCU. When tepcurdy is high it indicates the last cycle of the access. For a write cycle this means pcudataout has been registered by the block and for a read cycle this means the data on te_pcu.datain is valid. TD (raw Tag Data) DIU Read Interface signals tddiu-rreq 1 Out TD requests DRAM read. A read request must be accompanied by a valid read address. tddiu-radr[21:5] 17 Out TD read address to DIU. 17 bits wide (256-bit aligned word).
WO 2005/120835 PCT/AU2004/000706 823 diu td rack 1 In Acknowledge from DIU that TD read request has been accepted and new read address can be placed on tediu radr. diu-data[63:0] 64 In Data from DIU to TE. First 64-bits are bits 63:0 of 256 bit word; Second 64-bits are bits 127:64 of 256 bit word; Third 64-bits are bits 191:128 of 256 bit word; Fourth 64-bits are bits 255:192 of 256 bit word. diu td rvalid 1 In Signal from DIU telling TD that valid read data is on the diu,_data bus. TFS (Tag Format Structure) DIU Read Interface signals tfs-diu-rreq 1 Out TFS requests DRAM read. A read request must be accompanied by a valid read address. tfs.diu-radr[21:5] 17 Out TFS Read address to DIU 17 bits wide (256-bit aligned word). diu_tfs_rack 1 In Acknowledge from DIU that TFS read request has been accepted and new read address can be placed on fs diu radr. diu-data[63:0] 64 In Data from DIU to TE. First 64-bits are bits 63:0 of 256 bit word; Second 64-bits are bits 127:64 of 256 bit word; Third 64-bits are bits 191:128 of 256 bit word; Fourth 64-bits are bits 255:192 of 256 bit word. diutfsrvalid 1 In Signal from DIU telling TFS that valid read data is on the diudata bus. TFU Interface data and control signals tfu_te_oktowrite 1 In Ready signal indicating TFU has space available and is ready to be written to. Also asserted from the point that the TFU has received its expected number of bytes for a line until the next te_tfu wradvine te_tfuwdata[7:0] 8 Out Write data for TFU. te tfu wdatavalid 1 Out Write data valid signal. This signal remains high whenever there is valid output data on te_tfuwdata te tfu wradvline 1 Out Advance line signal strobed when the last byte in a line is placed on te_tfu_wdata 28.6.4 28.6.5Configuration Registers The configuration registers in the TE are programmed via the PCU interface.Refer to section 23.8.2 on page 439 for the description of the protocol and timing diagrams for reading and writing registers in the TE.Note 5 that since addresses in SoPEC are byte aligned and the PCU only supports 32-bit register reads and writes the lower 2 bits of the PCU address bus are not required to decode the address space for the TE.Table 174 lists the configuration registers in the TE. Registers which address DRAM are 256-bit word aligned.
WO 2005/120835 PCT/AU2004/000706 824 Table 174. TE Configuration Registers TE-base register name #bits e on description Control registers Ox000 Reset 1 1 A write to this register causes a reset of the TE. This register can be read to indicate the reset state: 0 - reset in progress 1 - reset not in progress 0x004 Go 1 0 Writing 1 to this register starts the TE. Writing 0 to this register halts the TE. When Go is deasserted the state-machines go to their idle states but all counters and configuration registers keep their values. When Go is asserted all counters are reset, but configuration registers keep their values (i.e. they don't get reset). NextBandEnable is cleared when Go is asserted. The TFU must be started before the TE is started. This register can be read to determine if the TE is running (1 = running, 0 = stopped). Setup registers (constant for processing of a page) 0x040 TfsStartAdr[21:5] 17 0 Points to the first word of the (256-bit aligned DRAM first TFS line in DRAM. address) 0x044 TfsEndAdr[21:5] 17 0 Points to the last word of the (256-bit aligned DRAM last TFS line in DRAM. address) 0x048 TfsFirstLineAdr[21:5] 17 0 Points to the first word of the (256-bit aligned DRAM first TFS line to be address) encountered on the page. If the start of the page is in an inter-tag gap, then this value will be the same as TFSStartAdr since the first tag line reached will be the top line of a tag. Ox04C DataRedun 1 0 Defines the data to redundancy ratio for the Reed Solomon encoder. Symbol size is always 4 bits, Codeword size is always 15 symbols (60 bits). 0 - 5 data symbols (20 bits), 10 redundancy symbols (40 bits) 1 -7 data symbols (28 bits), 8 redundancy symbols (32 bits) WO 2005/120835 PCT/AU2004/000706 825 0x050 Decode2Den 1 0 Determines whether or not the data bits are to be 2D decoded rather than redundancy encoded (each 2 bits of the data bits becomes 4 output data bits). 0 = redundancy encode data 1 = decode each 2 bits of data into 4 bits 0x054 VariableDataPresent 1 0 Defines whether or not there is variable data in the tags. If there is none, no attempt is made to read tag data, and tag encoding should only reference fixed tag data. Ox058 EncodeFixed 1 0 Determines whether or not the lower 40 (or 56) bits of fixed data should be encoded into 120 bits or simply used as is. Ox05C TagMaxDotpairs 8 0 The width of a tag in dot-pairs, minus 1. Minimum 0, Maximum=191. Ox060 TagMaxLine 9 0 The number of lines in a tag, minus 1. Minimum 0, Maximum = 383. Ox064 TagGapDot 14 0 The number of dot pairs between tags in the dot dimension minus 1. Only valid if TagGapPresen4bit 0] = 1. Ox068 TagGapLine 14 0 Defines the number of dotlines between tags in the line dimension minus 1. Only valid if TagGapPresenfbitl] = 1. Ox06C DotPairsPerLine 14 0 Number of output dot pairs to generate per tag line. Ox070 DotStartTagSense 2 0 Determines for the first/even (bit 0) and second/odd (bit 1) rows of tags whether or not the first dot position of the line is in a tag. 1 = in a tag, 0 = in an inter-tag gap. Ox074 TagGapPresent 2 0 Bit 0 is 1 if there is an inter-tag gap in the dot dimension, and 0 if tags are tightly packed. Bit 1 is 1 if there is an inter-tag gap in the line dimension, and 0 if tags are tightly packed. Ox078 Yscale 8 1 Tag scale factor in Y direction. Output lines to the TFU will be generated YScale times. Ox080 to DotStartPos[1:0] 2x14 0 Determines for the first/even Ox084 (0) and second/odd (1) rows of tags the number of dotpairs remaining minus 1, in either tho tan nr intar-tan non ot thm WO 2005/120835 PCT/AU2004/000706 826 start of the line. Ox088 to NumTags[1:0] 2x8 0 Determines for the first/even OxO8C and second/odd rows of tags how many tags are present in a line (equals number of tags minus 1). Setup band related registers OxOCO NextBandStartTagDataAdr[2 17 0 Holds the value of 1:5] StartTagDataAdr for the next (256-bit aligned DRAM band. This value is copied to address) StartTagDataAdr when DoneBand is 1 and NextBandEnable is 1, or when Go transitions from 0 to 1. OxOC4 NextBandEndOfTagData[21: 17 0 Holds the value of 5] EndOffagData for the next (256-bit aligned DRAM band. This value is copied to address) EndOfTagData when DoneBand is 1 and NextBandEnable is 1, or when Go transitions from 0 to 1. OxOC8 NextBandFirstTagLineHeight 9 0 Holds the value of FirstTagLineHeight for the next band. This value is copied to FirstTagLineHeight when DoneBand gets is 1 and NextBandEnable is 1, or when Go transitions from 0 to 1. OxOCC NextBandEnable 1 0 When NextBandEnable is 1 and DoneBand is 1, then when te_finishedband is set at the end of a band: -NextBandStartTagDataAdr is copied to StartTagDataAdr -NextBandEndOfTagData is copied to EndOfTagData -NextBandFirstTagLineHeight is copied to FirstTagLineHeight -DoneBand is cleared -NextBandEnable is cleared. NextBandEnable is cleared when Go is asserted. Read-only band related registers OxODO DoneBand 1 0 Specifies whether the tag data interface has finished loading all the tag data for the band. It is cleared to 0 when Go transitions from 0 to 1. When the tag data interface has finished loading all the tag data for the band, the te_finishedband signal is given out and the DoneBand flag is set. If Alavt anr knhn i nt thick WO 2005/120835 PCT/AU2004/000706 827 time then startTagDataAdr, endOfTagData and firstTaglineHeight are updated with the values for the next band and DoneBand is cleared. Processing of the next band starts immediately. If NextBandEnable is 0 then the remainder of the TE will continue to run, while the read control unit waits for NextBandEnable to be set before it restarts. Read only. OxOD4 StartTagDataAdr21 :5] 17 0 The start address of the (256-bit aligned DRAM current row of raw tag data. address) This is initially points to the first word of the band's tag data. Read only. OxOD8 EndOfTagData[21:5] 17 0 Points to the address of the (256-bit aligned DRAM final tag for the band. When address) all the tag data up to and including address endOfTagData has been read in, the te -finishedband signal is given and the doneBand flag is set. Read only. OxODC FirstTagLineHeight 9 0 The number of lines minus 1 in the first tag encountered in this band. This will be equal to TagMaxLine if the band starts at a tag boundary. Read only. Setup registers (remain constant during the processing of multiple bands) OxOEO TeStartOfBandStore[21:5] 17 OxO_ Points to the 256-bit word that 0000 defines the start of the memory area allocated for TE page bands. Circular address generation wraps to this start address. OxOE4 TeEndOfBandStore[21:5] 17 Ox1_ Points to the 256-bit word that FFFF defines the last address of the memory area allocated for TE page bands. If the current read address is from this address, then instead of adding 1 to the current address, the current address will be loaded from the TeStartOfBandStore register. Work registers (set before starting the TE and must not be touched between bands) Ox1 00 LinelnTag 1 0 Determines whether or not the first line of the page is in a line of tags or in an inter-tag gap. 1 - in a tag, 0 - in an inter-tag gap.
WO 2005/120835 PCT/AU2004/000706 828 Ox1 04 LinePos 14 0 The number of lines remaining minus 1, in either the tag or the inter-tag gap in at the start of the page. OxI 10 to TagData[3:0] 4x32 0 This 128 bit register must be Ox11C set up initially with the fixed data record for the page. This is either the lower 40 (or 56) bits (and the encodeFixed register should be set), or the lower 120 bits (and encodedFixed should be clear). The tagData[0] register contains the lower 32 bits and the tagData[3] register contains the upper 32 bits. This register is used throughout the tag encoding process to hold the next tag's variable data. Work registers (set internally) Read-only from the point of view of PCU register access 0x1 40 DotPos 14 0 Defines the number of dotpairs remaining in either the tag or inter-tag gap. Does not need to be setup. Ox144 CurrTagPlaneAdr 14 0 The dot-pair number being generated. Ox148 DotsinTag 1 0 Determines whether the current dot pair is in a tag or not 1 - in a tag, 0 - in an inter-tag gap. Ox14C TagAltSense 1 0 Determines whether the production of output dots is for the first (and subsequent even) or second (and subsequent odd) row of tags. Ox154 CurrTFSAdr[21:5 (256-bit 17 0 Points to the next 256 bit word aligned DRAM address) of the TFS to be read in. Ox15C CountX 8 0 The number of tags read by the raw tag data interface for the current line. Ox160 CountY 9 0 The number of times (minus 1) the tag data for the current line of tags needs to be read in by the raw tag data interface. Ox164 RtdTagSense 1 0 Determines whether the raw tag data interface is currently reading even rows of tags (=0) or odd rows of tags (=1) with respect to the start of the page. Note that this can be different from tagAltSense since the raw tag data interface is reading ahead of the production of dots.
WO 2005/120835 PCT/AU2004/000706 829 0x168 RawTagDataAdr[21:5] 17 0 The current read address (256-bit aligned DRAM within the unencoded raw tag address) data. 28.6.5.1 Starting the TE and restarting the TE between bands The TE must be started after the TFU. For the first band of data, users set up NextBandStartTagDataAdr, NextBandEndTagData and 5 NextBandFirstTagLineHeight as well as other TE configuration registers. Users then set the TE's Go bit to start processing of the band. When the tag data for the band has finished being decoded, the te_finishedband interrupt will be sent to the PCU and ICU indicating that the memory associated with the first band is now free. Processing can now start on the next band of tag data. In order to process the next band NextBandStartTagDataAdr, NextBandEndTagData and 10 NextBandFirstTagLineHeight need to be updated before writing a 1 to NextBandEnable. There are 4 mechanisms for restarting the TE between bands: a. tefinishedband causes an interrupt to the CPU. The TE will have set its DoneBand bit. The CPU reprograms the NextBandStartTagDataAdr, NextBandEndTagData and NextBandFirstTagLineHeight registers, and sets NextBandEnable to restart the TE. 15 b. The CPU programs the TE's NextBandStartTagDataAdr, NextBandEndTagData and NextBandFirstTagLineHeight registers and sets the NextBandEnable flag before the end of the current band. At the end of the current band the TE sets DoneBand. As NextBandEnable is already 1, the TE starts processing the next band immediately. c. The PCU is programmed so that te_finishedband triggers the PCU to execute commands from 20 DRAM to reprogram the NextBandStartTagDataAdr, NextBandEndTagData and NextBandFirstTagLineHeight registers and set the NextBandEnable bit to start the TE processing the next band. The advantage of this scheme is that the CPU could process band headers in advance and store the band commands in DRAM ready for execution. d. This is a combination of b and c above. The PCU (rather than the CPU in b) programs the TE's 25 NextBandStartTagDataAdr, NextBandEndTagData and NextBandFirstTagLineHeight registers and sets the NextBandEnable bit before the end of the current band. At the end of the current band the TE sets DoneBand and pulses tefinishedband As NextBandEnable is already 1, the TE starts processing the next band immediately. Simultaneously, tejfinishedband triggers the PCU to fetch commands from DRAM. The TE will have restarted by the time the PCU has fetched commands 30 from DRAM. The PCU commands program the TE next band shadow registers and sets the NextBandEnable bit. After the first tag on the page, all bands have their first tag start at the top i.e. NextBandFirstTagLineHeight = TagMaxLine. Therefore the same value of NextBandFirstTagLineHeight will normally be used for all bands. Certainly, NextBandFirstTagLineHeight should not need to change after the second time it is programmed.
WO 2005/120835 PCT/AU2004/000706 830 28.6.6 TE Top Level FSM The following diagram illustrates the states in the FSM. At the highest level, the TE state machine steps through the output lines of a page one line at a time, with the starting position either in an inter-tag gap (signal dotsintag = 0) or in a tag (signals tfsvalid and tdvalid and 5 lineintag = 1) (a SoPEC may be only printing part of a tag due to multiple SoPECs printing a single line). If the current position is within an inter-tag gap, an output of 0 is generated. If the current position is within a tag, the tag format structure is used to determine the value of the output dot, using the appropriate encoded data bit from the fixed or variable data buffers as necessary. The TE then advances along the line of dots, moving through tags and inter-tag gaps according to the tag placement parameters. 10 Table 175 highlights the signals used within the FSM. Table 175. Signals used within TE top level FSM AML_ I %*~f.t**~ --- , pclk Sync clock used to register all data within the FSM prstn, te_reset Reset signals advtagline 1 cycles pulse indicating to TDI and TFS sub-blocks to move onto the next line of Tag data currdotlineadr[13:0] Address counter starting 2 pclk ahead of currtagplaneadr to generate the correct dotpair for the current line dotpos Counter to identify how many dotpairs wide the tag/gap is dotsintag Signal identifying whether the dotpair are in a tag(1)/gap(0) lineintagjemp Identical to lineintag but generated 1 pclk earlier linepos-shadow Shadow register for linepos due to linepos being written to by 2 different processes tagaltsense Flag which alternates between tag/gap lines testate FSM state variable Teplanebuf 6-bit shift register used to format dotpairs into a byte for the TFU Wradvline Advance line signal strobed when the last byte in a line is placed on te_tfu_wdata The tagdot line state can be broken down into 3 different stages. Stage1:- The state tagdot line is entered due to the go signal becoming active. This state controls the writing of dotbytes to the TFU. As long as the tag line buffer address is not equal to the dotpairsperline register value 15 and tfu_te_oktowrite is active, and there is valid TFS and TD available or taggaps, dotpairs are buffered into bytes and written to the TFU. The tag line buffer address is used internally but not supplied to the TFU since the TFU is a FIFO rather than the line store used in PEC 1.
WO 2005/120835 PCT/AU2004/000706 831 While generating the dotline of a tag/gap line (lineintag flag = 1) the dot position counter dotpos is decremented/reloaded (with tagmaxdotpairs or taggapdot) as the TE moves between tags/gaps. The dotsintag flag is toggled between tags/gaps (0 for a gap, 1 for a tag). This pattern continues until the end of a dotline approaches (currdotlineadr = dotpairsperline). 5 Stage2:- At this point the end of a dot line is reached so it is time to decrement the linepos counter if still in a tag/gap row or reload the linepos register, dotpos counter and reprogram the dotsintag flag if going onto another tag/gap or pure gap row.When dotpos = 0 the end of a tag/gap has been reached, when linepos = 0 the end of a tag row is reached. Stage3:- This stage implements the writing of dotpairs to the correct part of the 6-bit shift register based on 10 the LSBs of currtagplaneadr and also implements the counter for the currtagplaneadr. The currtagplaneadr is reset on reaching currtagplaneadr = (dotpairsperline - 1). 28.6.7 Combinational Logic The TDI is responsible for providing the information data for a tag while the TFSI is responsible for deciding whether a particular dot on the tag should be printed as background pattern or tag information. Every dot 15 within a tag's boundary is either an information dot or part of the background pattern. The resulting lines of dots are stored in the TFU. The TFSI reads one Tag Line Structure (TLS) from the DIU for every dot line of tags. Depending on the current printing position within the tag (indicated by the signal tagdotnum), the TFS interface outputs dot information for two dots and if necessary the corresponding read addresses for encoded tag data. The read 20 address are supplied to the TDI which outputs the corresponding data values. These data values (tdietdO and tdietd1) are then combined with the dot information (tfsitadotO and tfsitadot1) to produce the dot values that will actually be printed on the page (dots), see Figure 203. The signal lastdotintag is generated by checking that the dots are in a tag (dotsintag = 1) and that the dotposition counter dotpos is equal to zero. It is also used by the TFS to load the index address register with 25 zeros at the end of a tag as this is always the starting index when going from one tag to the next. lastdotintag is also used in the TDi FSM (etdswitch state) to pulse the etdadvtag signal hence switching buffers in the ETDi for the next tag. The dotposvalid signal is created based on being in a tag line (lineintag1 = 1), dots being in a tag (dotsintag = 1), having a valid tag format structure available (tfsvalid = 1) and having encoded tag data available (tdvalidl 30 = 1). The dotposvalid signal is used as an enable to load the Table C address register with the next index into Table B which in turn provides the 2 addresses to make 2 dots available. The signal te tfuwdatavalid can only be active if in a taggap or if valid tag data is available (tdvalid and tfsvalid) and the currtagpplaneadr(1:0) equal 11 i.e. a byte of data has been generated by combining four dotpairs.
WO 2005/120835 PCT/AU2004/000706 832 The signal tagdotnum tells the TFS how many dotpairs remain in a tag/gap. It is calculated by subtracting the value in the dotpos counter from the value programmed in the tagmaxdotpairs register. 28.7 TAG DATA INTERFACE (TDi) 28.7.1 1/0 Specification Table 176. TDI Port List Clocks and Resets PcIk In SoPEC system clock prstn In Active-low, synchronous reset in pclk domain. DIU Read Interface Signals diudata[63:0] In Data from DRAM. tddiu-rreq Out Data request to DRAM. tddiu-radr[21:5] Out Read address to DRAM. diu_td_rack In Data acknowledge from DRAM. diu td rvalid In Data valid signal from DRAM. PCU Interface Data, Control Signals and pcu-dataout[31:0] In PCU writes this data. pcu-addr[8:2] In PCU accesses this address. pcurwn In Global read/write-not signal from PCU. pcu_te_sel In PCU selects TE for r/w access. pcutereset In PCU reset. td te doneband Out PCU readable registers. td_te_dataredun td te decode2den td_te_variabledatapresent td_te_encodefixed td_tenumtagsO td_tenumtagsl td_testarttagdataadr tdte.rawtagdataadr tdje-endoftagdata tdte-firsttaglineheight td_tetagdataO tdjte_tagdatal tdtejagdata2 td_te.tagdata3 tdte_countx td_tecounty td_te_rtdtagsense td te readsremaining TFS (Tag Format Structure) WO 2005/120835 PCT/AU2004/000706 833 tfsi-adrO[8:0] In Read address for dotO tfsi-adrl [8:0] In Read address for dot1 Bandstore Signals teendofbandstore[21:5] In Address of the end of the current band of data. 256-bit word aligned DRAM address. testartofbandstore[21:5] In Address of the start of the current band of data. 256-bit word aligned DRAM address. tefinishedband Out Tag encoder band finished 28.7.1 28.7.2 Introduction The tag data interface is responsible for obtaining the raw tag data and encoding it as required by the tag encoder. The smallest typical tag placement is 2mm x 2mm, which means a tag is at least 126 1600 dpi dots 5 wide. In PEC 1, in order to keep up with the HCU which processes 2 dots per cycle, the tag data interface has been designed to be capable of encoding a tag in 63 cycles. This is actually accomplished in either approximately 52 cycles or 36 cycles within PECI depending on the encoding method. For SoPEC the TE need only produce one dot per cycle; it should be able to produce tags in no more than twice the time taken by the PEC TE. 10 Moreover, any change in implementation from two dots to one dot per cycle should not lose the 63/52 cycle performance edge attained in the PECl TE. As shown in Figure 209, the tag data interface contains a raw tag data interface FSM that fetches tag data from DRAM, two symbol-at-a-time GF(2 4 ) Reed-Solomon encoders, an encoded data interface and a state machine for controlling the encoding process. It also contains a tagData register that needs to be set up to 15 hold the fixed tag data for the page. The type of encoding used depends on the registers TE encodefixed, TE dataredun and TE decode2den the options being, e (15,5) RS coding, where every 5 input symbols are used to produce 15 output symbols, so the output is 3 times the size of the input. This can be performed on fixed and variable tag data. 20 e (15,7) RS coding, where every 7 input symbols are used to produce 15 output symbols, so for the same number of input symbols, the output is not as large as the (15,5) code (for more details see section 28.7.6 on page 580). This can be performed on fixed and variable tag data. * 2D decoding, where each 2 input bits are used to produce 4 output bits. This can be performed on fixed and variable tag data. 25 e no coding, where the data is simply passed into the Encoded Data Interface. This can be performed on fixed data only. Each tag is made up of fixed tag data (i.e. this data is the same for each tag on the page) and variable tag data (i.e. different for each tag on the page).
WO 2005/120835 PCT/AU2004/000706 834 Fixed tag data is either stored in DRAM as 120-bits when it is already coded (or no coding is required), 40 bits when (15,5) coding is required or 56-bits when (15,7) coding is required. Once the fixed tag data is coded it is 120-bits long. It is then stored in the Encoded Tag Data Interface. The variable tag data is stored in the DRAM in uncoded form. When (15,5) coding is required, the 120-bits 5 stored in DRAM are encoded into 360-bits. When (15,7) coding is required, the 112-bits stored in DRAM are encoded into 240-bits. When 2D decoding is required, if DataRedun = 0, the 120-bits stored in DRAM are converted into 240-bits, if DataRedun = 112-bits stored in DRAM are converted to 224. In each case the encoded bits are stored in the Encoded Tag Data Interface. The encoded fixed and variable tag data are eventually used to print the tag. 10 The fixed tag data is loaded in once from the DRAM at the start of a page. It is encoded as necessary and is then stored in one of the 8x15-bits registers/RAMs in the Encoded Tag Data Interface. This data remains unchanged in the registers/RAMs until the next page is ready to be processed. The 120-bits of unencoded variable tag data for each tag is stored in four 32-bit words. The TE re-reads the variable tag data, for a particular tag from DRAM, every time it produces that tag. The variable tag data 15 FIFO which reads from DRAM has enough space to store 4 tags. 28.7.2.1 Bandstore wrapping Both TD and TFS storage in DRAM can wrap around the bandstore area. The bounds of the band store are described by inputs from the CDU shown in Table 190. The TD and TFS DRAM interfaces therefore support bandstore wrapping. If the TD or TFS DRAM interface increments an address it is checked to see if it 20 matches the end of bandstore address. If so, then the address is mapped to the start of the bandstore. 28.7.3Data Flow An overview of the dataflow through the TDI can be seen in Figure 209 below. The TD interface consists of the following main sections: * the Raw Tag Data Interface - fetches tag data from DRAM; 25 e the tag data register; * 2 Reed Solomon encoders - each encodes one 4-bit symbol at a time; * the Encoded Tag Data Interface - supplies encoded tag data for output; * Two 2D decoders. The main performance specification for PEC 1 is that the TE must be able to output data at a continuous rate 30 of 2 dots per cycle. 28.7.4 Raw tag data interface The raw tag data interface (RTDI) provides a simple means of accessing raw tag data in DRAM. The RTDI passes tag data into a FIFO where it can be subsequently read as required. The 64-bit output from the FIFO WO 2005/120835 PCT/AU2004/000706 835 can be read directly, with the value of the wrrdcounter being used to set/reset as the enable signal (rtdAvail). The FIFO is clocked out with receipt of an rtdRd signal from the TS FSM. Figure 210 shows a block diagram of the raw tag data interface. 28.7.4.1 RTDI FSM 5 The RTDI state machine is responsible for keeping the raw tag FIFO full. The state machine reads the line of tag data once for each printline that uses the tag. This means a given line of tag data will be read TagHeight times. Typically this will be 126 times or more, based on an approximately 2mm tag. Note that the first line of tag data may be read fewer times since the start of the page may be within a tag. In addition odd and even rows of tags may contain different numbers of tags. 10 Section 28.6.5.1 outlines how to start the TE and restart it between bands. Users must set the NextBandStartTagDataAdr, NextBandEndOjTagData, NextBandFirstTagLineHeight and numTags[0], numTags[1] registers before starting the TE by asserting Go. To restart the tag encoder for second and subsequent bands of a page, the NextBandStartTagDataAdr, NextBandEndOfTagData and NextBandFirstTagLineHeight registers need to be updated (typically 15 numTags[O] and numTags[1] will be the same if the previous band contains an even number of tag rows) and NextBandEnable set. See Section 28.6.5.1 for a full description of the four ways of reprogramming the TE between bands. The tag data is read once for every printline containing tags. When maximally packed, a row of tags contains 163 tags (see Table 169 on page 546). 20 The RTDI State Flow diagram is shown in Figure 211. An explanation of the states follows: idle state:- Stay in the idle state if there is no variable data present. If there is variable data present and there are at least 4 spaces left in the FIFO then request a burst of 2 tags from the DRAM (1 * 256bits). Counter county is assigned the number of tags in a even/odd line which depends on the value of register rtdtagsense. Down-counter county is assigned the number of dot lines high a tag will be (min 126). Initially it must be set 25 the firsttaglineheight value as the TE may be between pages (i.e. a partial tag). For normal tag generation county will take the value of tagmaxline register. diu access:- The diu access state will generate a request to the DRAM if there are at least 4 spaces in the FIFO. This is indicated by the counter wr rdcounter which is incremented/decremented on writes/reads of 30 the FIFO. As long as wrrdcounter is less than 4 (FIFO is 8 high) there must be 4 locations free. A control signal called tddiuradrvalid is generated for the duration of the DRAM burst access. Addresses are sent in bursts of 1. If there is an odd number of tags in line then the last DRAM read will contain a tag in the first 128 bits and padding in the final 128 bits.
WO 2005/120835 PCT/AU2004/000706 836 fifoload:- This state controls the addressing to the DRAM. Counters countx and county are used to monitor whether the TE is processing a line of dots within a row of tags. When countx is zero it means all tag dots for this row are complete. When county is zero it means the TE is on the last line of dots (prior to Y scaling) for this row of tags. When a row of tags is complete the sense of rtdtagsense is inverted (odd/even). The 5 rawtagdataadr is compared to the teendoftagdata address. If rawtagdataadr = endoftagdata the doneband signal is set, thefinishedband signal is pulsed, and the FSM enters the rtdstall state until the doneband signal is reset to zero by the PCU by which time the rawtagdata, endoftagedata and frsttaglineheight registers are setup with new values to restart the TE. This state is used to count the 64-bit reads from the DIU. Each time diutdrvalid is high rtd datacount is incremented by 1. The compare of rtddatacount = rtdnum is 10 necessary to find out when either all 4*64-bit data has been received or n*64-bit data (depending on a match of rawtagdataadr = endoftagdata in the middle of a set of 4*64-bit values being returned by the DIU. rtdstall:- This state waits for the doneband signal to be reset (see page 560 for a description of how this occurs). Once reset the FSM returns to the idle state. This states also performs the same count on the diudata 15 read as above in the case where diutdrvalid has not gone high by the time the addressing is complete and the end of band data has been reached i.e. rawtagdataadr = endoftagdata 28.7.5 TDI state machine The tag data state machine has two processing phases. The first processing phase is to encode the fixed tag data stored in the 128-bit (2 x 64-bit) tag data register. The second is to encode tag data as it is required by the 20 tag encoder. When the Tag Encoder is started up, the fixed tag data is already preloaded in the 128 bit tag data record. If encodeFixed is set, then the 2 codewords stored in the lower bits of the tag data record need to be encoded: 40 bits if dataRedun = 0, and 56 bits if dataRedun = 1. If encodeFixed is clear, then the lower 120 bits of the tag data record must be passed to the encoded tag data interface without being encoded. 25 When encodeFixed is set, the symbols derived from codeword 0 are written to codeword 6 and the symbols derived from codeword 1 are written to codeword 7. The data symbols are stored first and then the remaining redundancy symbols are stored afterwards, for a total of 15 symbols. Thus, when dataRedun = 0, the 5 symbols derived from bits 0-19 are written to symbols 0-4, and the redundancy symbols are written to symbols 5-14. When dataRedun = 1, the 7 symbols derived from bits 0-27 are written to symbols 0-6, and the 30 redundancy symbols are written to symbols 7-14. When encodeFixed is clear, the 120 bits of fixed data is copied directly to codewords 6 and 7. The TDI State Flow diagram is shown in Figure 213. An explanation of the states follows. idle:- In the idle state wait for the tag encoder go signal - topgo = 1. The first task is to either store or encode the Fixed data. Once the Fixed data is stored or encoded/stored the donefixed flag is set. If there is no variable 35 data the FSM returns to the idle state hence the reason to check the donefixed flag before advancing i.e. only store/encode the fixed data once.
WO 2005/120835 PCT/AU2004/000706 837 fixeddata:- In the fixeddata state the FSM must decode whether to directly store the fixed data in the ETDi or if the fixed data needs to be either (15:5) (40-bits) or (15:7) (56-bits) RS encoded or 2D decoded. The values stored in registers encodefixed and dataredun and decode2den determine what the next state should be. bypass_to_etdi:- The bypass-to_etdi takes 120-bits of fixed data(pre-encoded) from the tagdata(127:0) .5 register and stores it in the 15*8 (by 2 for simultaneous reads) buffers. The data is passed from the tagdata register through 3 levels of muxing levell, level2, level3) where it enters the RSO/RS1 encoders (which are now in a straight through mode (i.e. control and control_7 are zero hence the data passes straight from the input to the output). The MSBs of the etdwradr must be high to store this data as codewords 6,7. etdbuf switch:- This state is used to set the tdvalid signal and pulse the etd advtag signal which in turn is 10 used to switch the read write sense of the ETDi buffers (wrsb0). The firsttime signal is used to identify the first time a tag is encoded. If zero it means read the tag data from the RTDi FIFO and encode. Once encoded and stored the FSM returns to this state where it evaluates the sense of tdvalid. First time around it will be zero so this sets tdvalid and returns to the readtagdata state to fill the 2nd ETDi buffer. After this the FSM returns to this state and waits for the lastdotintag signal to arrive. In between tags when the lastdotingtag 15 signal is received the etd_adv_tag is pulsed and the FSM goes to the readtagdata state. readtagdata:- The readtagdata state waits to receive a rtdavail signal from the raw tag data interface which indicates there is raw tag data available. The tagdata register is 128-bits so it takes 2 pulses of the rtdrd signal to get the 2*64-bits into the tagdata register. If the rtdavail signal is set rtdrd is pulsed for 1 cycle and the FSM steps onto the loadtagdata state. Initially the flag first64bits will be zero. The 64-bits of rtd are 20 assigned to the tagdata[63:0] and the flag first64bits is set to indicate the first raw tag data read is complete. The FSM then steps back to the readtagdata state where it generates the second rtdrd pulse. The FSM then steps onto the loadtagdata state for where the second 64-bits of rawtag data are assigned to tagdata[128:64]. loadtagdata:- The loadtagdata state writes the raw tag data into the tagdata register from the RTDi FIFO. The first64bits flag is reset to zero as the tagdata register now contains 120/112 bits of variable data. A 25 decode of whether to (15:5) or (15:7) RS encode or 2D decode this data decides the next state. rs_15_5:- The rs_15_5 (Reed Solomon (15:5) mode) state either encodes 40-bit Fixed data or 120-bit Variable data and provides the encoded tag data write address and write enable (etdwradr and etdwe respectively). Once the fixed tag data is encoded the donefixed flag is set as this only needs to be done once per page. The variabledatapresent register is then polled to see if there is variable data in the tags. If there is 30 variable data present then this data must be read from the RTDi and loaded into the tagdata register. Else the tdvalid flag must be set and FSM returns to the idle state. control_5 is a control bit for the RS Encoder and controls feedforward and feedback muxes that enable (15:5) encoding. The rs_15_5 state also generates the control signals for passing 120-bits of variable tag data to the RS encoder in 4-bit symbols per clock cycle. rscounter is used both to control the levellmux and act as the 15-cycle 35 counter of the RS Encoder. This logic cycles for a total of 3*15 cycles to encode the 120-bits. rs 15 7:- The rs_15_7 state is similar to the rs_15_5 state except the levellmux has to select 7 4-bit symbols instead of 5.
WO 2005/120835 PCT/AU2004/000706 838 decode_2d_15_5, decode_2d 15 7:- The decode_2d states provides the control signals for passing the 120-bit variable data to the 2D decoder. The 2 lsbs are decoded to create 4 bits. The 4 bits from each decoder are combined and stored in the ETDi. Next the 2 MSBs are decoded to create 4 bits. Again the 4 bits from each decoder are combined and stored in the ETDi. 5 As can be seen from Figure 208 on page 566 there are 3 stages of muxing between the Tag Data register and the RS encoders or 2D decoders. Levels 1-2 are controlled by* level 1mux and level2_mux which are generated within the TDi FSM as is the write address to the ETDi buffers (etd wradr) Figures 214 through 219 illustrate the mappings used to store the encoded fixed and variable tag data in the ETDI buffers. 10 28.7.6 Reed Solomon (RS) Encoder 28.7.7 Introduction A Reed Solomon code is a non binary, block code. If a symbol consists of m bits then there are q = 2' possible symbols defining the code alphabet. In the TE, m = 4 so the number of possible symbols is q = 16. An (n,k) RS code is a block code with k information symbols and n code-word symbols. RS codes have the 15 property that the code word n is limited to at most q+1 symbols in length. In the case of the TE, both (15,5) and (15,7) RS codes can be used. This means that up to 5 and 4 symbols respectively can be corrected. Only one type of RS coder is used at any particular time. The RS coder to be used is determined by the registers TEdataredun and TEdecode2den: 20 e TEdataredun = 0 and TEdecode2den = 0, then use the (15,5) RS coder e TEdataredun = 1 and TEdecode2den = 0, then use the (15,7) RS coder For a (15,k) RS code with m = 4, k 4-bit information symbols applied to the coder produce 15 4-bit codeword symbols at the output. In the TE, the code is systematic so the first k codeword symbols are the same the as the k input information symbols. 25 A simple block diagram can be seen in. 28.7.8 1/0 Specification A I/O diagram of the RS encoder can be seen in. 28.7.9 Proposed implementation In the case of the TE, (15,5) and (15,7) codes are to be used with 4-bits per symbol. 30 The primitive polynomial is p(x) = x 4 + x + 1 In the case of the (15,5) code, this gives a generator polynomial of g(x) = (x+a)(x+a 2 )(x+a 3 )(x+a 4 )(x+a5)(x+a6)(x+a 7 )(x+a')(x+a')(x+aO') WO 2005/120835 PCT/AU2004/000706 839 g(x)= xl+ a2 9 + a3x + a'x' + ax + a 4xI+ ax + ax + ax + ax + al g(x) = x 0 + g 9 x 9 + g 8 X + g 7
X
7 + g 6 x 6 + g 5 x' + g 4
X
4 + g 3 x 3 + g 2 x 2 + gjx + go In the case of the (15,7) code, this gives a generator polynomial of h(x) = (x+a)(x+a 2 )(x+a 3 )(x+a 4 )(x+a 5 )(x+a 6 )(x+a 7 )(x+a 8 ) 5 h(x)= x+ a 4 x 7 + a 2
X
6 + a 4 x 5 + a 2
X
4 + a' 3
X
3 + a 5 x 2 + aix + a 6 h(x) = x 8 + hyx 7 + h 6 x 6 + h 5 x 5 + h 4 x 4 + h 3 x 3 + h 2 x 2 + hix + ho The output code words are produced by dividing the generator polynomial into a polynomial made up from the input symbols. This division is accomplished using the circuit shown in Figure 222. 10 The data in the circuit are Galois Field elements so addition and multiplication are performed using special circuitry. These are explained in the next sections. The RS coder can operate either in (15,5) or (15,7) mode. The selection is made by the registers TE dataredun and TE decode2den. When operating in (15,5) mode control_7 is always zero and when operating in (15,7) mode control is 15 always zero. Firstly consider (15,5) mode i.e. TEdataredun is set to zero. For each new set of 5 input symbols, processing is as follows: The 4-bits of the first symbol do are fed to the input port rsdatain(3:0) and control_5 is set to 0. mux2 is set so as to use the output as feedback. control is zero so mux4 selects the input (rsdatain) as the output 20 (rsdataout). Once the data has settled (<< 1 cycle), the shift registers are clocked. The next symbol d, is then applied to the input, and again after the data has settled the shift registers are clocked again. This is repeated for the next 3 symbols d 2 , d 3 and d 4 . As a result, the first 5 outputs are the same as the inputs. After 5 cycles, the shift registers now contain the next 10 required outputs. control is set to 1 for the next 10 cycles so that zeros are fed back by mux2 and the shift register values are fed to the output by mux3 and mux4 by 25 simply clocking the registers. A timing diagram is shown below. Secondly consider (15,7) mode i.e. TEdataredun is set to one. In this case processing is similar to above except that control_7 stays low while 7 symbols (do, d, ... d) are fed in. As well as being fed back into the circuit, these symbols are fed to the output. After these 7 cycles, 30 control_7 is set to 1 and the contents of the shift registers are fed to the output. A timing diagram is shown below. The enable signal can be used to start/reset the counter and the shift registers.
WO 2005/120835 PCT/AU2004/000706 840 The RS encoders can be designed so that encoding starts on a rising enable edge. After 15 symbols have been output, the encoder stops until a rising enable edge is detected. As a result there will be a delay between each codeword. Alternatively, once the enable goes high the shift registers are reset and encoding will proceed until it is told 5 to stop. rs_data in must be supplied at the correct time. Using this method, data can be continuously output at a rate of 1 symbol per cycle, even over a few codewords. Alternatively, the RS encoder can request data as it requires. The performance criterion that must be met is that the following must be carried out within 63 cycles e load one tag's raw data into TEtagdata 10 0 encode the raw tag data e store the encoded tag data in the Encoded Tag Data Interface In the case of the raw fixed tag data at the start of a page, there is no definite performance criterion except that it should be encoded and stored as fast as possible. 28.7.10 Galois Field elements and their representation 15 A Galois Field is a set of elements in which we can do addition, subtraction, multiplication and division without leaving the set. The TE uses RS encoding over the Galois Field GF(2 4 ). There are 24 elements in GF(2 4 ) and they are generated using the primitive polynomial p(x) = x 4 + x + 1. The 16 elements of GF(2 4 ) can be represented in a number of different ways. Table shows three possible 20 representations - the power, polynomial and 4-tuple representation. Table 177. GF(2 4 ) representations POwe Polynomia 4-tuple reprsenatin Reresntaion representation 0 0 (0000) 1 1 (1 0 00) a x (0 1 0 0) a 2 , (0010) a 3 x3 (0001) a4 1 + x (1 1 00) c' x+x 2 (0 1 1 0) ' x 2 + x 3 (00 1 1) a' 1 +x +xx 3 (1 1 0 1) a! 1 + x 2 (1 0 1 0) WO 2005/120835 PCT/AU2004/000706 841 a' X+ x 3 (0101) a* 1 +x+x 2 (1 1 10) a"l X + x 2 + x 3 (01 1 1) a 2 1 +x+x 2 +x 3 (1 1 1 1) (X11 + x 2 + x 3 (1011) a 4 1+ 3 (100 1) 28.7.11 Multiplication of GF(2 4 ) elements The multiplication of two field elements aa and ab is defined as -X c =a czb = a(a+b)modulo 15 Thus 5 al.2= a3 5 10 15 cx a =ct 6 12 3 Cx.al =a So if the elements are available in exponential form, multiplication is simply a matter of modulo 15 addition. If the elements are in polynomial/tuple form, the polynomials must be multiplied and reduced mod x 4 + x + 1. 10 Suppose we wish to multiply the two field elements in GF(2 4 ): ca = a 3 x3 + a 2 x 2 + ajx1 + ao ox = b 3 x 3 + b 2 x 2 + bix' + bo where aj, bi are in the field (0,1) (i.e. modulo 2 arithmetic) Multiplying these out and using x 4 + x + 1 = 0 we get: 15 a*b = [(aob 3 + aib 2 + a 2 b, + a 3 bo) + a 3 b 3 ]x 3 + [(aob 2 + alb, + a 2 bo) + a 3 b 3 + (a 3 b 2 + a2b3x2 + [(aobi + albo) + (a 3 b 2 + a 2 b 3 ) + (aib 3 + a 2 b 2 + a 3 b,)]x + [(aobo + ajb 3 + a 2 b 2 + a 3 b,)] aa+b= [aob 3 + ajb 2 + a 2 b, + a 3 (bo + b 3 )]x 3 20 + [aob 2 + alb, + a 2 (bo + b 3 ) + a 3 (b 2 + b 3 )]x 2 + [aobi + a 1 (bo + b 3 ) + a 2 (b2 + b 3 ) + as(b + b2)X + [aobo + ajb 3 + a 2 b 2 + a 3 bi] If we wish to multiply an arbitrary field element by a fixed field element we get a more simple form. Suppose we wish to multiply co by a 3 . 25 In this case a 3 = x 3 so (aO al a2 a3) = (0 0 0 1). Substituting this into the above equation gives WO 2005/120835 PCT/AU2004/000706 842 ac = (bo + b 3 )x 3 + (b 2 + b 3 )x 2 + (b, + b 2 )x + bi This can be implemented using simple XOR gates as shown in Figure 225. 28.7.12 Addition of GF(2 4 ) elements If the elements are in their polynomial/tuple form, polynomials are simply added. 5 Suppose we wish to add the two field elements in GF(2 4 ): aa = a3x 3 + a2x 2 + aix + ao ax= b 3 x 3 + b 2 x 2 + bjx + bo where a 1 , bi are in the field (0,1) (i.e. modulo 2 arithmetic) ac a + ab= (a + b 3 )x 3 + (a 2 + b 2 )x 2 + (ai + bi)x + (ao + bo) 10 Again this can be implemented using simple XOR gates as shown in Figure 226. 28.7.13 Reed Solomon Implementation The designer can decide to create the relevant addition and multiplication circuits and instantiate them where necessary. Alternatively the feedback multiplications can be combined as follows. Consider the multiplication 15 aa.Cb =C or in terms of polynomials (a 3 x 3 + a 2 x 2 + aix + ao).(b 3 x 3 + b 2 x 2 + bix + bo) = (c 3 x 3 + c 2 x 2 + cix + co) If we substitute all of the possible field elements in for aa and express d' in terms of c , we get the table of results shown in Table 178. Table 178. a* multiplied by all field elements, expressed in terms of ab 1 (1000) b 0 b b 2 b 3 a (0100) ba ba+b, b, b 2 2 (0010) b b+b b 0 +bb 1 (100 b2 bb2b a 3 (0100) b3b ,b,+b, a' (0 0 0 1) b, b,+b2 b2+b3 b,+b, a' (11 0 0) b,+b 3 bo+b,+b 3 b,+b2 b 2 +b d (01 10) b 2 +b 3 b,+b 2 bo+b,+b 3 WO 2005/120835 PCT/AU2004/000706 843 a 8 (001 1) b,+b 2 b,+b, b +b b,+b,+b, a7 (1 101) b 0 +b,+b, bo+b 2 +b, b,+b, b,+b 2 (1 01 0) b,+b 2 b,+b 2 +b 3 b.+b2+b, b,+b, (0 1 0 1) b 1 +b, b.+b,+b 2 +b, b,+b 2 +b, b,+b 2 +b 3 a'* (1 1 1 0) b,+b 2 +b, b 0 +b,+b 2 b,+b,+b 2 +b 3 b,+b 2 +b 3 a" (0 1 11) b,+b 2 +b 3 b, +b, bo+b,+b 2 b,+b,+b 2 +b 3 a1 2 (1 1 1 1) b,+b,+b 2 +b 3 b 0 bo+b, b,+b,+b 2 a' 3 (1011) bo+b,+b 2 b3 b bo+b, a 4 (1 001) b,+b, b 2 b 3 b 0 the following signals are required: * bo, bI, b 2 , b 3 , * (b o +bl), (bo+b 2 ), (bo+b), (b 1 +b 2 ), (bl+bA), (b 2 +b 3 ), * (bo+bi+b 2 ), (bo+bi+b), (bo+b 2 +b 3 ), (bi+b 2 +b 3 ), 5 - (bo+bl+b 2 +b 3 ) The implementation of the circuit can be seen in Figure . The main components are XOR gates, 4-bit shift registers and multiplexers. The RS encoder has 4 input lines labelled 0,1,2 & 3 and 4 output lines labelled 0,1,2 & 3. This labelling corresponds to the subscripts of the polynomial/4-tuple representation. The mapping of 4-bit symbols from 10 the TE tagdata register into the RS is as follows: - the LSB in the TE tagdata is fed into lineO - the next most significant LSB is fed into line 1 - the next most significant LSB is fed into line2 - the MSB is fed into line3 15 The RS output mapping to the Encoded tag data interface is similar. Two encoded symbols are stored in an 8 bit address. Within these 8 bits: - line is fed into the LSB (bit 0/4) - line is fed into the next most significant LSB (bit 1/5) - line2 is fed into the next most significant LSB (bit 2/6) 20 - line3 is fed into the MSB (bit 3/7) 28.7.14 2D Decoder The 2D decoder is selected when TEdecode2den = 1. It operates on variable tag data only. its function is to convert 2-bits into 4-bits according to Table 179.
WO 2005/120835 PCT/AU2004/000706 844 Table 179. Operation of 2D decoder iput u.Li 0 0 0001 01 0010 10 0100 11 1000 28.7.15 Encoded tag data interface The encoded tag data interface contains an encoded fixed tag data store interface and an encoded variable tag data store interface, as shown in Figure 228. The two reord units simply reorder the 9 input bits to map low-order codewords into the bit selection 5 component of the address as shown in Table 180. Reordering of write addresses is not necessary since the addresses are already in the correct format. Table 180. Reord unit 8 A A select 1 of 4 codeword t B select 1 of 8 codewords B tables 6 C D ---- -- _ select 1 of 15 symbols 4 E F select 1 of 15 symbols 3 F G 2 G C H H select 1 of 8 bits select 1 of 4 bits The encoded fixed and variable data are stored in a 112 x 8 bit dual port reg array. The MSB for the reg. array's write address is the inverted wrsbO signal which switches selecting either the lower or upper half of 10 the reg. array to write variable data. The fixed data is stored in the top of the lower half of the reg. array (from address 0110000 to 100000) and is written in by adding an offset to the reg. array write address.
WO 2005/120835 PCT/AU2004/000706 845 28.8 TAG FORMAT STRUCTURE (TFS) INTERFACE 28.8.1 Introduction The TFS specifies the contents of every dot position within a tags border i.e.: e is the dot part of the background? 5 e is the dot part of the data? The TFS is broken up into Tag Line Structures (TLS) which specify the contents of every dot position in a particular line of a tag. Each TLS consists of three tables - A, B and C (see Figure 229). For a given line of dots, all the tags on that line correspond to the same tag line structure. Consequently, for a given line of output dots, a single tag line structure is required, and not the entire TFS. Double buffering 10 allows the next tag line structure to be fetched from the TFS in DRAM while the existing tag line structure is used to render the current tag line. The TFS interface is responsible for loading the appropriate line of the tag format structure as the tag encoder advances through the page. It is also responsible for producing table A and table B outputs for two consecutive dot positions in the current tag line. 15 - There is a TLS for every dot line of a tag. - All tags that are on the same line have the exact same TLS. * A tag can be up to 384 dots wide, so each of these 384 dots must be specified in the TLS. e The TLS information is stored in DRAM and one TLS must be read into the TFS Interface for each line of dots that are outputted to the Tag Plane Line Buffers. 20 0 Each TLS is read from DRAM as 5 times 256-bit words with 214 padded bits in the last 256-bit DRAM read. 28.8.2 1/0 Specification Table 181. Tag Format Structure Interface Port List signal name s description I.I.......7 'A . ...... type~ I r_.. . Pclk In SoPEC system clock prst n In Active-low, synchronous reset in pclk domain top-go In Go signal from TE top level DRAM diu-data[63:0] In Data from DRAM diu_tfs_rack In Data acknowledge from DRAM diutfsrvalid In Data valid from DRAM tfsdiu-rreq Out Read request to DRAM WO 2005/120835 PCT/AU2004/000706 846 tfsdiu-radr[21:5] Out Read address to DRAM tag encoder top level top.advtagline In Pulsed after the last line of a row of tags top-tagaltsense In For even tag rows = 0 i.e. 0,2,4.. For odd tag rows = 1 i.e. 1,3,5... topjlastdotintag In Last dot in tag is currently being processed top-dotposvalid In Current dot position is a tag dot and its structure data and tag data is available top-jagdotnum[7:0] In Counts from zero up to TEjtagmaxdotpairs (min. =1, max. = 192) tfsivalid Out TLS tables A, B and C, ready for use tfsita-dotO[1:0] Out Even entry from Table A corresponding to top-jagdotnum tfsi_ta-dotl [1:0] Out Odd entry from Table A corresponding to top-jagdotnum tag encoder top level (PCU read decoder) tfs-te_tfsstartadr[23:0] Out TFS tfsstartadr register tfstejtfsendadr[23:0] Out TFS tfsendadr register ifstetfsfirstlineadr[23:0] Out TFS tfsfirstlineadr register ifstecurrtfsadr[23:0] Out TFS currtfsadr register TDI tfsi_tdi-adr0[8:0] Out Read address for dotO (even dot) ifsitdi-adr1 [8:0] Out Read address for dot1 (odd dot) 28.8.2 28.8.2.1 State machine The state machine is responsible for generating control signals for the various TFS table units, and to load the appropriate line from the TFS. The states are explained below. 5 idle:- Wait for topgo to become active. Pulse advtfs_line for 1 cycle to reset tawradr and tbwradr registers. Pulsing advtfs line will switch the read/write sense of Table B so switching Table A here as well to keep things the same i.e. wrtaO = NOT(wrtaO). diu access:- In the diuaccess state a request is sent to the DIU. Once an ack signal is received Table A write enable is asserted and the FSM moves to the ils load state. 10 tls_load:- The DRAM access is a burst of 5 256-bit accesses, ultimately returned by the DIU as 5*(4*64bit) words. There will be 192 padded bits in the last 256-bit DRAM word. The first 12 64-bit words reads are for Table A, words 12 to 15 and some of 16 are for Table B while part of read 16 data is for Table C. The counter readnum is used to identify which data goes to which table. The table B data is stored temporarily in a 288 bit register until the tlsupdate state hence tbwe does not become active until readnum = 16). 15 e The DIU data goes directly into Table A (12 * 64).
WO 2005/120835 PCT/AU2004/000706 847 - The DIU data for Table B is loaded into a 288-bit register. * The DIU data goes directly into Table C. tls update:- The 288-bits in Table B need to written to a 32*9 buffer. The tls update state takes care of this 5 using the readnum counter. tls_next:- This state checks the logic level of tfsvalid and switches the read/write senses of Table A (wrtaO) and Table B a cycle later (using the advtfs line pulse). The reason for switching Table A a cycle early is to make sure the top_level address via tagdotnum is pointing to the correct buffer. Keep in mind the top_level is working a cycle ahead of Table A and 2 cycles ahead of Table B. 10 If tfsValid is 1, the state machine waits until the advTagLine signal is received. When it is received, the state machine pulses advTFSLine (to switch read/write sense in tables A, B, C), and starts reading the next line of the TFS from currTFSAdr. If tfsValid is 0, the state machine pulses advTFSLine (to switch read/write sense in tables A, B, C) and then jumps to the tlstfsvalidset state where the signal tfsValid is set to 1 (allowing the tag encoder to start, or to 15 continue if it had been stalled). The state machine can then start reading the next line of the TFS from currTFSAdr. tlstfsvalid next:- Simply sets the tfsvalid signal and returns the FSM to the diuaccess state. If an advTagLine signal is received before the next line of the TFS has been read in, tfsValid is cleared to 0 20 and processing continues as outlined above. 28.8.2.2 Bandstore wrapping Both TD and TFS storage in DRAM can wrap around the bandstore area. The bounds of the band store are described by inputs from the CDU shown in Table 190. The TD and TFS DRAM interfaces therefore support bandstore wrapping. If the TD or TFS DRAM interface increments an address it is checked to see if it 25 matches the end of bandstore address. If so, then the address is mapped to the start of the bandstore. The TFS state flow diagram is shown in below. 28.8.3 Generating a tag from Tables A, B and C The TFS contains an entry for each dot position within the tag's bounding box. Each entry specifies whether 30 the dot is part of the constant background pattern or part of the tag's data component (both fixed and variable).
WO 2005/120835 PCT/AU2004/000706 848 The TFS therefore has TagHeight x TagWidth entries, where TagHeight is the height of the tag in dot-lines and TagWidth is the width of the tag in dots. The TFS entries that specify a single dot-line of a tag are known as a Tag Line Structure. The TFS contains a TLS for each of the 1600 dpi lines in the tag's bounding box. Each TLS contains three 5 contiguous tables, known as tables A, B and C. Table A contains 384 2-bit entries i.e. one entry for each dot in a single line of a tag up to the maximum width of a tag. The actual number of entries used should match the size of the bounding box for the tag in the dot dimension, but all 384 entries must be present. Table B contains 32 9-bit data address that refer to (in order of appearance) the data dots present in the 10 particular line. Again, all 32 entries must be present, even if fewer are used. Table C contains two 5-bit pointers into table B and is followed by 22 unused bits. The total length of each TLS is therefore 34 32-bit words. Each output dot value is generated as follows: Each entry in Table A consists of 2-bits - bitO and bit1. These 2-bits are interpreted according to Table , Table and Table . 15 Table 182. Interpretation of bitO from entry in Table A 0 the output bit comes directly from bit1 (see Table). 1 the output bit comes from a data bit. Bit1 is used in conjunction with Tag Line Structure Table B to determine which data bit will be output. Table 183. Interpretation of bit1 from entry in table A when bitO = 0 0 output 0 1 output 1 Table 184. Interpretation of bit1 from entry in table A when bitO = 1 0 output data bit pointed to by current index into Table B. 1 output data bit pointed to by current index into Table B, and advance index by 1. If bitO 0 then the output dot for this entry is part of the constant background pattern. The dot value itself comes from bitl i.e. if bitl = 0 then the output is 0 and if bitl = 1 then the output is 1.
WO 2005/120835 PCT/AU2004/000706 849 If bitO = 1 then the output dot for this entry comes from the variable or fixed tag data. Bitl is used in conjunction with Tables B and C to determine data bits to use. To understand the interpretation of bitl when bitO = 1 we need to know what is stored in Table B. Table B contains the addresses of all the data bits that are used in the particular line of a tag in order of appearance. 5 Therefore, up to 32 different data bits can appear in a line of a tag. The address of the first data dot in a tag will be given by the address stored in entry 0 of Table B. As we advance along the various data dots we will advance through the various Table B entries. Each Table B entry is 9-bits long and each points to a specific variable or fixed data bit for the tag. Each tag contains a maximum of 120 fixed and 360 variable data bits, for a total of 480 data bits. To aid address 10 decoding, the addresses are based on the RS encoded tag data. Table lists the interpretation of the 9-bit addresses. Table 185. Interpretation of 9-bit tag data address in Table B . ........ CodeWordSelect Select 1 of 8 codewords. Codewords 0, 1, 2, 3, 4, 5 are variable data. Codewords 6, 7 are fixed data. 6 5 SymbolSelect Select 1 of 15 symbols (1111 invalid) 3 2 61- BitSelect Select 1 of 4 bits from the selected symbols If the fixed data is supplied to the TE in an unencoded form, the symbols derived from codeword 0 of fixed data are written to codeword 6 and the symbols derived from fixed data codeword 1 are written to codeword 15 7. The data symbols are stored first and then the remaining redundancy symbols are stored afterwards, for a total of 15 symbols. Thus, when 5 data symbols are used, the 5 symbols derived from bits 0-19 are written to symbols 0-4, and the redundancy symbols are written to symbols 5-14. When 7 data symbols are used, the 7 symbols derived from bits 0-27 are written to symbols 0-6, and the redundancy symbols are written to symbols 7-14 20 However, if the fixed data is supplied to the TE in a pre-encoded form, the encoding could theoretically be anything. Consequently the 120 bits of fixed data is copied to codewords 6 and 7 as shown in Table 186.
WO 2005/120835 PCT/AU2004/000706 850 Table 186. Mapping of fixed data to codeword/symbols when no redundancy encoding input bits output output symbol range codeword 0-19 0-4 6 20-39 0-4 7 40-59 5-9 6 60-79 5-9 7 80-99 10-14 6 100-119 10-14 7 It is important to note that the interpretation of bitI from Table A (when bitO = 1) is relative. A 5-bit index is used to cycle through the data address in Table B. Since the first tag on a particular line may or may not start at the first dot in the tag, an initial value for the index into Table B is needed. Subsequent tags on the same 5 line will always start with an index of 0, and any partial tag at the end of a line will simply finish before the entire tag has been rendered. The initial index required due to the rendering of a partial tag at the start of a line is supplied by Table C. The initial index will be different for each TLS and there are two possible initial indexes since there are effectively two types of rows of tags in terms of initial offsets. Table C provides the appropriate start index into Table B (2 5-bit indices). When rendering even rows of tags, 10 entry 0 is used as the initial index into Table B, and when rendering odd rows of tags, entry 1 is used as the initial index into Table B. The second and subsequent tags start at the left most dots position within the tag, so can use an initial index of 0. 28.8.4 Architecture A block diagram of the Tag Format Structure Interface can be seen in Figure 231. 15 28.8.4.1 Table A interface The implementation of table A is a 32 x 64-bit reg. array with a small amount of control logic. Each time an AdvTFSLine pulse is received, the sense of which half of the reg. array is being read from or written to changes. This is accomplished by a 1-bit flag called wrtaO. Although the initial state of wrtaO is irrelevant, it must invert upon receipt of an AdvTFSLine pulse. A 4-bit counter called taWrAdr keeps the write 20 address for the 12 writes that occur after the start of each line (specified by the AdvTFSLine control input). The tawe (table A write enable) input is set whenever the data in is to be written to table A. The taWrAdr address counter automatically increments with each write to table A. Address generation for tawe and taWrAdr is shown in Table 232.
WO 2005/120835 PCT/AU2004/000706 851 28.8.4.2 Table C interface A block diagram of the table C interface is shown below in Figure 233. The address generator for table C contains a 5 bit address register adr that is set to a new address at the start of processing the tag (either of the two table C initial values based on tagAltSense at the start of the line, and 0 5 for subsequent tags on the same line). Each cycle two addresses into table B are generated based on the two 2 bit inputs (inO and inl). As shown in Section 187, the output address tbRdAdrO is always adr and tbRdAdr1 is one of adr and adr+1, and at the end of the cycle adr takes on one of adr, adr+1, and adr+2. Table 187. AdrGen lookup table 00 00 X X adr 00 01 X adr adr 00 10 X X adr 00 11 X adr adr+1 01 00 adr X adr 01 01 adr adr adr 01 10 adr X adr 01 11 adr adr adr+1 10 00 X X adr 10 01 X adr adr 10 10 X X adr 10 11 X adr adr+1 11 00 adr X adr+1 11 01 adr adr+1 adr+1 11 10 adr X adr+1 11 11 adr adr+1 adr+2 28.8.4.3 Table B interface 10 The table B interface implementation generates two encoded tag data addresses (tfsi adrO, tfsi adr1) based on two table B input addresses (tbRdAdrO, tbRdAdr1). A block diagram of table B can be seen in Figure 234.
WO 2005/120835 PCT/AU2004/000706 852 Table B data is initially loaded into the 288-bit table B temporary register via the TFS FSM. Once all 288-bit entries have been loaded from DRAM, the data is written in 9-bit chunks to the 64*9 dual port register array based on tbwradr. Each time an AdvTFSLine pulse is received, the sense of which sub buffer is being read from or written to 5 changes. This is accomplished by a 1-bit flag called wrtbO. Although the initial state of wrtbO is irrelevant, it must invert upon receipt of an AdvTFSLine pulse. 29 TAG FIFO UNIT (TFU) 29.1 OVERVIEW 10 The Tag FIFO Unit (TFU) provides the means by which data is transferred between the Tag Encoder (TE) and the HCU. By abstracting the buffering mechanism and controls from both units, the interface is clean between the data user and the data generator. The TFU is a simple FIFO interface to the HCU. The Tag Encoder will provide support for arbitrary Y integer scaling up to 1600 dpi. X integer scaling of the tag dot data is performed at the output of the FIFO in the TFU. 15 There is feedback to the TE from the TFU to allow stalling of the TE during a line. The TE interfaces to the TFU with a data width of 8 bits. The TFU interfaces to the HCU with a data width of 1 bit. The depth of the TFU FIFO is chosen as 16 bytes so that the FIFO can store a single 126 dot tag. 29.1.1 Interfaces between TE, TFU and HCU 29.1.1.1 TE-TFU Interface 20 The interface from the TE to the TFU comprises the following signals: e te_tfuwdata, 8-bit write data. e te_tfuwdatavalid, write data valid. e te tfuwradvline, accompanies the last valid 8-bit write data in a line. The interface from the TFU to TE comprises the following signal: 25 - tfu _teoktowrite, indicating to the TE that there is space available in the TFU FIFO. The TE writes data to the TFU FIFO as long as the TFU's tfuteoktowrite output bit is set. The TE write will not occur unless data is accompanied by a data valid signal. 29.1.1.2 TFU-HCU Interface The interface from the TFU to the HCU comprises the following signals: 30 e tfuhcutdata, 1-bit data. e tfuhcuavail, data valid signal indicating that there is data available in the TFU FIFO.
WO 2005/120835 PCT/AU2004/000706 853 The interface from HCU to TFU comprises the following signal: e hcutfuadvdot, indicating to the TFU to supply the next dot. 29.1.1.2.1 X scaling Tag data is replicated a scale factor (SF) number of times in the X direction to convert the final output to 1600 5 dpi. Unlike both the CFU and SFU, which support non-integer scaling, the scaling is integer only. Replication in the X direction is performed at the output of the TFU FIFO on a dot-by-dot basis. To account for the case where there may be two SoPEC devices, each generating its own portion of a dot-line, the first dot in a line may not be replicated the total scale-factor number of times by an individual TFU. The dot will ultimately be scaled-up correctly with both devices doing part of the scaling, one on its lead-out and 10 the other on its lead in. Note two SoPEC TEs may be involved in producing the same byte of output tag data straddling the printhead boundary. The HCU of the left SoPEC will accept from its TE the correct amount of dots, ignoring any dots in the last byte that do not apply to its printhead. The TE of the right SoPEC will be programmed the correct number of dots into the tag and its output will be byte aligned with the left edge of the printhead. 15 29.2 DEFINITIONS OF 1/0 Table 188. TFU Port List Clocks and Resets Pclk 1 In SoPEC Functional clock. prst_n 1 In Global reset signal. PCU Interface data and control signals pcu-adr[4:2] 3 In PCU address bus. Only 3 bits are required to decode the address space for this block. pcudataout[31:0] 32 In Shared write data bus from the PCU. tfu.pcu-datain[31:0] 32 Out Read data bus from the TFU to the PCU. pcurwn 1 In Common read/not-write signal from the PCU. pcu_tfu_sel 1 In Block select from the PCU. When pcutfuselis high both pcuadr and pcudataout are valid. tfu-pcu-rdy 1 Out Ready signal to the PCU. When tfupcu.rdy is high it indicates the last cycle of the access. For a write cycle this means pcLdataout has been registered by the block and for a read cycle this means the data on ffupcudatain is valid. TE Interface data and control signals te_tfuwdata[7:0] 8 In Write data for TFU FIFO. tefu_wdatavaid 1 In Write data valid signal.
WO 2005/120835 PCT/AU2004/000706 854 tetfuwradvline 1 In Advance line signal strobed when the last byte in a line is placed on te_tfuwdata tfu_te_oktowrite 1 Out Ready signal indicating TFU has space available in it's FIFO and is ready to be written to. HCU Interface data and control signals hcu_tfu_advdot 1 In Signal indicating to the TFU that the HCU is ready to accept the next dot of data from TFU. tfu-hcu-jdata 1 Out Data from the TFU FIFO. tfu_hcu_avail 1 Out Signal indicating valid data available from TFU FIFO. 29.2 29.3 CONFIGURATION REGISTERS Table 189. TFU Configuration Registers Control registers Ox00 Reset 1 1 A write to this register causes a reset of the TFU. This register can be read to indicate the reset state: 0 - reset in progress 1 - reset not in progress. Ox04 Go 1 see Writing 1 to this register starts the text TFU. Writing 0 to this register halts the TFU. When Go is deasserted the state machines go to their idle states but all counters and configuration registers keep their values. When Go is asserted all counters are reset, but configuration registers keep their values (i.e. they don't get reset). The TFU must be started before the TE is started. This register can be read to determine if the TFU is running (1 = running, 0 = stopped). Setup registers (constant during processing of page) 0x08 XScale 8 1 Tag scale factor in X direction. Ox0C XFracScale 8 1 Tag scale factor in X direction for the first dot in a line (must be programmed to be less than or equal to XScale) WO 2005/120835 PCT/AU2004/000706 855 0xI 0 TEByteCount 12 0 The number of bytes to be accepted from the TE per line. Once this number of bytes have been received subsequent bytes are ignored until there is a strobe on the te_tfu wradvine 0x14 HCUDotCount 16 0 The number of (optionally) x scaled dots per line to be supplied to the HCU. Once this number has been reached the remainder of the current FIFO byte is ignored. 29.3 29.4 DETAILED DESCRIPTION The FIFO is a simple 16-byte store with read and write pointers, and a contents store, Figure 236. 16 bytes is sufficient to store a single 126 dot tag. 5 Each line a total of TEByteCount bytes is read into the FIFO. All subsequent bytes are ignored until there is a strobe on the tetfu_wradvline signal, whereupon bytes for the next line are stored. On the HCU side, a total of HCUDotCount dots are produced at the output. Once this count is reached any more dots in the FIFO byte currently being processed are ignored. For the first dot in the next line the start of line scale factor, XFracScale, is used. 10 The behaviour of these signals and the control signals between the TFU and the TE and HCU is detailed below. // Concurrently Executed Code: // TE always allowed to write when there's either (a) room or (b) no room and all 15 // bytes for that line have been received. if ((FifoCntnts != FifoMax) OR (FifoCntnts == FifoMax and ByteToRx == 0)) then tfu_te_oktowrite = 1 else 20 tfuteoktowrite = 0 // Data presented to HCU when there is (a) data in FIFO and (b) the HCU has not // received all dots for a line 25 if (FifoCntnts != 0) AND (BitToTx != O)then tfuhcuavail = 1 else tfuhcuavail = 0 30 // Output mux of FIFO data tfu_hcu_tdata = Fifo[FifoRdPnt] [RdBit] // Sequentially Executed Code: if (te-tfu-wdatavalid == 1) AND (FifoCntnts != FifoMax) AND 35 (ByteToRx != 0) then WO 2005/120835 PCT/AU2004/000706 856 Fifo[FifoWrPnt] = te-tfuwdata FifoWrPnt ++ FifoContents ++ ByteToRx - 5 if (te-tfuwradvline == 1) then ByteToRx = TEByteCount if (hcutfuadvdot == 1 and FifoCntnts != 0) then 10 BitToTx ++ if (RepFrac == 1) then RepFrac = Xscale if (RdBit = 7) then RdBit = 0 15 FifoRdPnt ++ FifoContents else RdBit++ else 20 RepFracif(BitToTx == 1) then RepFrac = XFracScale RdBit = 0 FifoRdPnt ++ 25 FifoContents- BitToTx = HCUDotCount } What is not detailed above is the fact that, since this is a circular buffer, both the fifo read and write-pointers 30 wrap-around to zero after they reach two. Also not detailed is the fact that if there is a change of both the read and write-pointer in the same cycle, the fifo contents counter remains unchanged. 30 HALFTONER COMPOSITOR UNIT (HCU) 30.1 OVERVIEW 35 The Halftoner Compositor Unit (HCU) produces dots for each nozzle in the destination printhead taking account of the page dimensions (including margins). The spot data and tag data are received in bi-level form while the pixel contone data received from the CFU must be dithered to a bi-level representation. The resultant 6 bi-level planes for each dot position on the page are then remapped to 6 output planes and output one dot at a time (6 bits) to the next stage in the printing pipeline, namely the dead nozzle compensator 40 (DNC).
WO 2005/120835 PCT/AU2004/000706 857 30.2 DATA FLOW Figure 237 shows a simple dot data flow high level block diagram of the HCU. The HCU reads contone data from the CFU, bi-level spot data from the SFU, and bi-level tag data from the TFU. Dither matrices are read from the DRAM via the DIU. The calculated output dot (6 bits) is read by the DNO. 5 The HCU is given the page dimensions (including margins), and is only started once for the page. It does not need to be programmed in between bands or restarted for each band. The HCU stalls appropriately if its input buffers are starved. At the end of the page the HCU continues to produce 0 for all dots as long as data is requested by the units further down the pipeline (this allows later units to conveniently flush pipelined data). The HCU performs a linear processing of dots, calculating the 6-bit output of a dot in each cycle. The 10 mapping of 6 calculated bits to 6 output bits for each dot allows for such example mappings as compositing of the spotO layer over the appropriate contone layer (typically black), the merging of CMY into K (if K is present in the printhead), the splitting of K into CMY dots if there is no K in the printhead, and the generation of a fixative output bitstream if required. 30.3 DRAM STORAGE REQUIREMENTS 15 SoPEC allows for a number of different dither matrix configurations up to 256 bytes wide. The dither matrix is stored in DRAM. Using either a single or double-buffer scheme a line of the dither matrix must be read in by the HCU over a SoPEC line time. SoPEC must produce 13824 dots per line for A4/Letter printing which takes 13824 cycles. The following give the storage and bandwidths requirements for some of the possible configurations of the 20 dither matrix. * 4 Kbyte DRAM storage required for one 64x64 (preferred) byte dither matrix e 6.25 Kbyte DRAM storage required for one 80x80 byte dither matrix * 16 Kbyte DRAM storage required for four 64x64 byte dither matrices e 64 Kbyte DRAM storage required for one 256x256 byte dither matrix 25 It takes 4 or 8 read accesses to load a line of dither matrix into the dither matrix buffer, depending on whether a single or double buffer is used (configured by DoubleLineBuffregister). 30.4IMPLEMENTATION A block diagram of the HCU is given in Figure 238..
WO 2005/120835 PCT/AU2004/000706 858 30.4.1 Definition of 1/0 Table 190. HCU port list and description Clocks and reset pclk 1 In System clock. prst_n 1 In System reset, synchronous active low. PCU Interface pcuhcusel 1 In Block select from the PCU. When pcu-hcu-sel is high both pcu-adr and pcu.dataout are valid. pcurwn 1 In Common read/not-write signal from the PCU. pcu-adr[7:2] 6 In PCU address bus. Only 6 bits are required to decode the address space for this block. pcu.dataout[31:0] 32 In Shared write data bus from the PCU. hcu-pcu-rdy 1 Out Ready signal to the PCU. When hcupcurdy is high it indicates the last cycle of the access. For a write cycle this means pcudataout has been registered by the block and for a read cycle this means the data on hcu-pcu-datain is valid. hcu.pcu-datain[31:0] 32 Out Read data bus to the PCU. DIU interface hcu-diu-rreq 1 Out HCU read request, active high. A read request must be accompanied by a valid read address. diuhcurack 1 In Acknowledge from DIU, active high. Indicates that a read request has been accepted and the new read address can be placed on the address bus, hcu_diu_radr. hcu-diu-radr[21:5] 17 Out HCU read address. 17 bits wide (256-bit aligned word). diuhcurvalid 1 In Read data valid, active high. Indicates that valid read data is now on the read data bus, diu.data. diu.data[63:0] 64 In Read data from DIU. CFU Interface cfu hcu avail 1 In Indicates valid data present on cfuhcuc[3-0]data lines. cfuhcu_cOdata[7:0] 8 In Pixel of data in contone plane 0. cfuhcu_cidata[7:0] 8 In Pixel of data in contone plane 1. cfuhcuc2data[7:0] 8 In Pixel of data in contone plane 2. cfu_hcu_c3data[7:0] 8 In Pixel of data in contone plane 3. hcucfuadvdot 1 Out Informs the CFU that the HCU has captured the pixel data on cfu_hcu_c[3-0]data lines and the CFU can now place the next pixel on the data lines. SFU interface WO 2005/120835 PCT/AU2004/000706 859 sfuhcuavail 1 In Indicates valid data present on sfuLhcusdata. sfuhcusdata 1 In Bi-level dot data. hcusfuadvdot 1 Out Informs the SFU that the HCU has captured the dot data on sfuhcusdata and the SFU can now place the next dot on the data line. TFU interface tfuhcuavail 1 In Indicates valid data present on tfu_hcutdata. tfuhcutdata 1 In Tag dot data. hcu tfu advdot 1 Out Informs the TFU that the HCU has captured the dot data on tfu_hcu_tdata and the TFU can now place the next dot on the data line. DNC Interface dnchcuready 1 In Indicates that DNC is ready to accept data from the HCU. hcudncavail 1 Out Indicates valid data present on hcudncdata. hcudncdata[5:0] 6 Out Output bi-level dot data in 6 ink planes. 30.4.1 30.4.2 Configuration Registers The configuration registers in the HCU are programmed via the PCU interface. Refer to section 23.8.2 on page 439 for the description of the protocol and timing diagrams for reading and writing registers in the HCU. 5 Note that since addresses in SoPEC are byte aligned and the PCU only supports 32-bit register reads and writes, the lower 2 bits of the PCU address bus are not required to decode the address space for the HCU. When reading a register that is less than 32 bits wide zeros are returned on the upper unused bit(s) of hcu_pcudatain. The configuration registers of the HCU are listed in Table 191. Table 191. HCU Registers (HUb" RegisterNae #R oDscitn Control registers 0x00 Reset 1 Ox1 A write to this register causes a reset of the
HCU.
WO 2005/120835 PCT/AU2004/000706 860 0x04 Go 1 Ox0 Writing 1 to this register starts the HCU. Writing 0 to this register halts the HCU. When Go is asserted all counters, flags etc. are cleared or given their initial value, but configuration registers keep their values. When Go is deasserted the state-machines go to their idle states but all counters and configuration registers keep their values. The HCU should be started after the CFU, SFU, TFU, and DNC. This register can be read to determine if the HCU is running (1 = running, 0 = stopped). Setup registers (constant for during processing) OxI 0 AvailMask 4 Ox0 Mask used to determine which of the dotgen units etc. are to be checked before a dot is generated by the HCU within the specified margins for the specified color plane. If the specified dotgen unit is stalled, then the HCU will also stall. See Table 192 for bit allocation and definition. Ox14 TMMask 4 Ox0 Same as AvailMask, but used in the top margin area before the appropriate target page is reached. Ox18 PageMarginY 32 0x0000 The first line considered to be off the page. 0000 Ox1C MaxDot 16 OxOOO This is the maximum dot number - 1 present across a page. For example if a page contains 13824 dots, then MaxDot will be 13823. Ox20 TopMargin 32 0x0000 The first line on a page to be considered within 0000 the target page for contone and spot data. (0 = first printed line of page) 0x24 BottomMargin 32 OxO00 The first line in the target bottom margin for 0000 contone and spot data (i.e. first line after target page). Ox28 LeftMargin 16 OxOOOO The first dot on a line within the target page for contone and spot data. Ox2C RightMargin 16 OxFFFF The first dot on a line within the target right margin for contone and spot data. Ox30 TagTopMargin 32 OxOOOO The first line on a page to be considered within 0000 the target page for tag data. (0 = first printed line of page) 0x34 TagBottomMarg 32 OxOOOO The first line in the target bottom margin for tag in 0000 data (i.e. first line after target page). Ox38 TagLeftMargin 16 OxOOOO The first dot on a line within the target page for tag data. Ox3C TagRightMargin 16 OxFFFF The first dot on a line within the target right margin for tag data. Ox44 StartDMAdr[21: 17 OxO_ Points to the first 256-bit word of the first line of 5] 0000 the dither matrix in DRAM. Ox48 EndDMAdr[21:5 17 0x0_ Points to the last address of the group of four 0000 256-bit reads (or 8 if single buffering) that reads in the last line of the dither matrix.
WO 2005/120835 PCT/AU2004/000706 861 Ox4C LineIncrement 5 0x2 The number of 256-bit words in DRAM from the start of one line of the dither matrix and the start of the next line, i.e. the value by which the DRAM address is incremented at the start of a line so that it points to the start of the next line of the dither matrix. Ox50 DMInitIndexCO 8 Ox00 If using the single-buffer scheme this register represents the initial index within 256-byte dither matrix line buffer for contone plane 0. If using double-buffer scheme, only the 7 Isbs are used. Ox54 DMLwrIndexCO 8 Ox00 If using the single-buffer scheme this register represents the lower index within 256-byte dither matrix line buffer for contone plane 0. If using double-buffer scheme, only the 7 Isbs are used. Ox58 DMUprIndexCO 8 Ox3F If using the single-buffer scheme this register represents the upper index within 256-byte dither matrix line buffer for contone plane 0. After reading the data at this location the index wraps to DMLwrlndexCO. If using double-buffer scheme, only the 7 Isbs are used. Ox5C DMInitIndexC1 8 Ox00 If using the single-buffer scheme this register represents the initial index within 256-byte dither matrix line buffer for contone plane 1. If using double-buffer scheme, only the 7 Isbs are used. Ox60 DMLwrIndexC1 8 Ox00 If using the single-buffer scheme this register represents the lower index within 256-byte dither matrix line buffer for contone plane 1. If using double-buffer scheme, only the 7 Isbs are used. Ox64 DMUprindexC1 8 Ox3F If using the single-buffer scheme this register represents the upper index within 256-byte. dither matrix line buffer for contone plane 1. After reading the data at this location the index wraps to DMLwrIndexCl. If using double-buffer scheme, only the 7 Isbs are used. Ox68 DMInitIndexC2 8 Ox00 If using the single-buffer scheme this register represents the initial index within 256-byte dither matrix line buffer for contone plane 2. If using double-buffer scheme, only the 7 Isbs are used. Ox6C DMLwrIndexC2 8 Ox00 If using the single-buffer scheme this register represents the lower index within 256-byte dither matrix line buffer for contone plane 2. If using double-buffer scheme, only the 7 Isbs are used. Ox70 DMUprindexC2 8 Ox3F If using the single-buffer scheme this register represents the upper index within 256-byte dither matrix line buffer for contone plane 2. After reading the data at this location the index wraps to DMLwrIndexC2. If using double-buffer scheme, only the 7 Isbs are used. Ox74 DMinitIndexC3 8 Ox00 If using the single-buffer scheme this register represents the initial index within 256-byte dither matrix line buffer for contone plane 3. If using double-buffer scheme, only the 7 Isbs are used.
WO 2005/120835 PCT/AU2004/000706 862 0x78 DMLwrlndexC3 8 Ox00 If using the single-buffer scheme this register represents the lower index within 256-byte dither matrix line buffer for contone plane 3. If using double-buffer scheme, only the 7 Isbs are used. Ox7C DMUprlndexC3 8 Ox3F If using the single-buffer scheme this register represents the upper index within 256-byte dither matrix line buffer for contone plane 3. After reading the data at this location the index wraps to DMLwrlndexC3. If using double-buffer scheme, only the 7 Isbs are used. Ox80 DoubleLineBuf 1 Ox1 Selects the dither line buffer mode to be single or double buffer. 0 - single line buffer mode 1 - double line buffer mode Ox84 to 0x98 IOMappingLo 6x3 OxOOO The dot reorg mapping for output inks 0 to 5. 2 0000 For each ink's 64-bit IOMapping value, /OMappingLo represents the low order 32 bits. Ox9C to IOMappingHi 6x3 OxOOO The dot reorg mapping for output inks 0 to 5. OxBO 2 0000 For each ink's 64-bit IOMapping value, IOMappingHi represents the high order 32 bits. OxB4 to cpConstant 4x8 Ox00 The constant contone value to output for OxCO contone plane N when printing in the margin areas of the page. This value will typically be 0. OxC4 sConstant 1 Ox0 The constant bi-level value to output for spot when printing in the margin areas of the page. This value will typically be 0. OxC8 tConstant 1 Ox0 The constant bi-level value to output for tag data when printing in the margin areas of the page. This value will typically be 0. OxCC DitherConstant 8 OxFF The constant value to use for dither matrix when the dither matrix is not available, i.e. when the signal dm_avail is 0. This value will typically be OxFF so that cpConstant can easily be OxOO or OxFF without requiring a dither matrix (DitherConstant is primarily used for threshold dithering in the margin areas). Debug registers (read only) OxDO HcuPortsDebug 14 N/A Bit 13 = tfu~hcu~avail Bit 12 = hcHgt1Nadvdot Bit 13 = sfu_hcuavail Bit 10 = hcu_sfu_advdot Bit 9 = cfu_hcuavail Bit 8 = hcu_cfu_advdot Bit 7 = dnchcuready Bit 6 = hcu_dncavail Bits 5-0 = hcu_dncdata OxD4 HcuDotgenDeb 15 N/A Bit 14 = aftertop-margin ug Bit 13 = injtag-target page Bit 12 = injtarget page Bit 11 = tp-avail Bit 10 = s_avail Bit 9 = cp-avail Bit 8 = dm_avail Bit 7 = advdot Bits 5-0 = [tp,scp3,cp2,cp1,cpO] (i.e. 6 bit input to dot reorg units) WO 2005/120835 PCT/AU2004/000706 863 OxD8 HcuDitherDebu 17 N/A Bit 17 = advdot g1 Bit 16 = dm avail Bit 15-8 = cpldither val Bits 7-0 = cpOjditherval OxDC HcuDitherDebu 17 N/A Bit 17 = advdot g2 Bit 16 = dm avail Bit 15-8 = cp3ditherval Bits 7-0 = cpZdither vall 30.4.3 Control unit The control unit is responsible for controlling the overall flow of the HCU. It is responsible for determining whether or not a dot will be generated in a given cycle, and what dot will actually be generated - including 5 whether or not the dot is in a margin area, and what dither cell values should be used at the specific dot location. A block diagram of the control unit is shown in Figure 239. The inputs to the control unit are a number of avail flags specifying whether or not a given dotgen unit is capable of supplying 'real' data in this cycle. The term 'real' refers to data generated from external sources, such as contone line buffers, bi-level line buffers, and tag plane buffers. Each dotgen unit informs the control 10 unit whether or not a dot can be generated this cycle from real data. It must also check that the DNC is ready to receive data. The contone/spot margin unit is responsible for determining whether the current dot coordinate is within the target contone/spot margins, and the tag margin unit is responsible for determining whether the current dot coordinate is within the target tag margins. 15 The dither matrix table interface provides the interface to DRAM for the generation of dither cell values that are used in the halftoning process in the contone dotgen unit. 30.4.3.1 Determine advdot The HCU does not always require contone planes, bi-level or tag planes in order to produce a page. For example, a given page may not have a bi-level layer, or a tag layer. In addition, the contone and bi-level parts 20 of a page are only required within the contone and bi-level page margins, and the tag part of a page is only required within the tag page margins. Thus output dots can be generated without contone, bi-level or tag data before the respective top margins of a page has been reached, and Os are generated for all color planes after the end of the page has been reached (to allow later stages of the printing pipeline to flush). Consequently the HCU has an AvailMask register that determines which of the various input avail flags 25 should be taken notice of during the production of a page from the first line of the target page, and a TMMask register that has the same behaviour, but is used in the lines before the target page has been reached (i.e. inside the target top margin area). The dither matrix mask bit TMask[O] is the exception, it applies to all margins areas, not just the top margin. Each bit in the AvailMask refers to a particular avail bit: if the bit in the AvailMask register is set, then the corresponding avail bit must be 1 for the HCU to advance a dot. The bit to 30 avail correspondence is shown in Table 192. Care should be taken with TMMask - if the particular data is not WO 2005/120835 PCT/AU2004/000706 864 available after the top margin has been reached, then the HCU will stall, potentially causing a print buffer underrun if the printhead has already commenced printing and the HCU stalls for long enough. Note that the avail bits for contone and spot colors are ANDed with in target_page after the target page area has been reached to allow dot production in the contone/spot margin areas without needing any data in the CFU and 5 SFU. The avail bit for tag color is ANDed with in_tagtarget page after the target tag page area has been reached to allow dot production in the tag margin areas without needing any data in the TFU. Table 192. Correspondence between bit in AvailMask and avail flag bi #i AvaiiMask avi lgdecito 0 dm-avail dither matrix data available 1 cp avail contone pixels available 2 savail spot color available 3 tp-avail tag plane available Each of the input avail bits is processed with its appropriate mask bit and the aftertopmargin flag (note the dither matrix is the exception, as it is processed with intarget_page). The output bits are ANDed together 10 along with Go and output bufffull (which specifies whether the output buffer is ready to receive a dot in this cycle) to form the output bit advdot. We also generate wradvdot. In this way, if the output buffer is full or any of the specified avail flags is clear, the HCU stalls. When the end of the page is reached, inpage is deasserted and the HCU continues to produce 0 for all dots as long as the DNC requests data. A block diagram of the determine advdot unit is shown in Figure 240. 15 The advance dot block also determines if the current page needs a dither matrix. It indicates this to the dither matrix table interface block via the dmreadenable signal. If no dither is required in the margins or in the target page then dmreadenable is 0 and no dither is read in for this page. 30.4.3.2 Position unit The position unit is responsible for outputting the position of the current dot (curr pos, currline) and 20 whether or not this dot is the last dot of a line (advline). Both currpos and currline are set to 0 at reset or when Go transitions from 0 to 1. The position unit relies on the advdot input signal to advance through the dots on a page. Whenever an advdot pulse is received, curr_pos gets incremented. If currpos equals maxdot then an advline pulse is generated as this is the last dot in a line, curr line gets incremented, and the curr_pos is reset to 0 to start counting the dots for the next line. 25 The position unit also generates a filtered version of advline called dmadvline to indicate to the dither matrix pointers to increment to the next line. The dmadvline is only incremented when dither is required for that line. if ((aftertop_margin AND avail-mask[O]) OR tm-mask[0}) then WO 2005/120835 PCT/AU2004/000706 865 dmadvline = advline else dm advline = 0 30.4.3.3 Margin unit 5 The responsibility of the margin unit is to determine whether the specific dot coordinate is within the page at all, within the target page or in a margin area (see Figure 241). This unit is instantiated for both the contone/spot margin unit and the tag margin unit. The margin unit takes the current dot and line position, and returns three flags. * the first, inpage, is 1 if the current dot is within the page, and 0 if it is outside the page. 10 0 the second flag, intarget_page, is 1 if the dot coordinate is within the target page area of the page, and 0 if it is within the target top/left/bottom/right margins. * the third flag, aftertopmargin, is 1 if the current dot is below the target top margin, and 0 if it is within the target top margin. A block diagram of the margin unit is shown in Figure 242. 15 30.4.3.4 Dither matrix table interface The dither matrix table interface provides the interface to DRAM for the generation of dither cell values that are used in the halftoning process in the contone dotgen unit. The control flag dm readenable enables the reading of the dither matrix table line structure from DRAM. If dmreadenable is 0, the dither matrix is not specified in DRAM and no DRAM accesses are attempted. The dither matrix table interface has an output flag 20 dmavail which specifies if the current line of the specified matrix is available. The HCU can be directed to stall when dm_avail is 0 by setting the appropriate bit in the HCU's AvailMask or TMMask registers. When dmavail is 0 the value in the DitherConstant register is used as the dither cell values that are output to the contone dotgen unit. The dither matrix table interface consists of a state machine that interfaces to the DRAM interface, a dither 25 matrix buffer that provides dither matrix values, and a unit to generate the addresses for reading the buffer. Figure 243 shows a block diagram of the dither matrix table interface. 30.4.3.5 Dither data structure in DRAM The dither matrix is stored in DRAM in 256-bit words, transferred to the HCU in 64-bit words and consumed by the HCU in bytes. Table 193 shows the 64-bit words mapping to 256-bit word addresses, and Table 194 30 shows the 8-bit dither value mapping in the 64-bit word.
WO 2005/120835 PCT/AU2004/000706 866 Table 193. Dither Data stored in DRAM 00000 D3 D2 D1 D [255:192] [191:128] [127:64] 00001 D7 D6 D5 D4 [255:192] [191:128] [127:64] [63:0] 00010 Di D10 D9 D8 [255:192] [191:128] [127:64] [63:0] 00011 D15 D14 D13 D12 [255:192] [191:128] [127:64] [63:0] 00100 D19 D18 D17 D16 [255:192] [191:128] [127:64] [63:0] etc When the HCU first requests data from DRAM, the 64-bit word transfer order is DO,D1,D2,D3. On the second request the transfer order is D4,D5,D6,D7 and so on for other requests. Table 194. Dither data stored in HCUs line buffer 00 DO[7:0] 10 D2[7:0] 20 D4[7:0] 01 DO[1 5:8] 11 D2[15:8] 21 D4[15:8] 02 DO[23:16] 12 D2[23:16] 22 D4[23:16] 03 DO[31:24] 13 D2[32:24] 23 D4[31:24] 04 DO[39:32] 14 D2[39:32] 24 D4[39:32] 05 DO[47:40] 15 D2[47:40] 25 D4[47:40] 06 DO[55:48] 16 D2[55:48] 26 D4[55:48] 07 DO[63:56] 17 D2[63:56] 27 D4[63:56] 08 D1[7:0] 18 D3[7:0] 28 D5[7:0] 09 D1[15:8] 19 D3[15:8] 29 D5[15:8] OA D1[23:16] 1A D3[23:16] 2A D5[23:16] OB D1[31:24] 1B D3[31:24] 2B D5[31:24] OC D1 [39:32] 1C D3[39:32] 2C D5[39:32] OD D1 [47:40] 11D D3[47:40] 2D D5[47:40] OE D1[55:48] 1E D3[55:48] 2E D5[55:48] OF D1 [63:56] 1F D3[63:56] 2F D5[63:56] etc. etc.
WO 2005/120835 PCT/AU2004/000706 867 30.4.3.5.1 Dither matrix buffer The state machine loads dither matrix table data a line at a time from DRAM and stores it in a buffer. A single line of the dither matrix is either 256 or 128 8-bit entries, depending on the programmable bit DoubleLineBuf. If this bit is enabled, a double-buffer mechanism is employed such that while one buffer is read from for the 5 current line's dither matrix data (8 bits representing a single dither matrix entry), the other buffer is being written to with the next line's dither matrix data (64-bits at a time). Alternatively, the single buffer scheme can be used, where the data must be loaded at the end of the line, thus incurring a delay. The single/double buffer is implemented using a 256 byte 3-port register array, two reads, one write port, with the reads clocked at double the system clock rate (320MHz) allowing 4 reads per clock cycle. 10 The dither matrix buffer unit also provides the mechanism for keeping track of the current read and write buffers, and providing the mechanism such that a buffer cannot be read from until it has been written to. In this case, each buffer is a line of the dither matrix, i.e. 256 or 128 bytes. The dither matrix buffer maintains a read and write pointer for the dither matrix. The output value dm avail is derived by comparing the read and write pointers to determine when the dither matrix is not empty. The write 15 pointer wradr is incremented each time a 64-bit word is written to the dither matrix buffer and the read pointer rdptr is incremented each time dmadvline is received. If double line buf is 0 the rd_ptr will increment by 2, otherwise it will increment by 1. If the dither matrix buffer is full then no further writes will be allowed (bufffull =1), or if the buffer is empty no further buffer reads are allowed (buff emp= 1). The read addresses are byte aligned and are generated by the read address generator. A single dither matrix 20 entry is represented by 8 bits and an entry is read for each of the four contone planes in parallel. If double buffer is used (doublelinebuf=1) the read address is derived from 7-bit address from the read address generator and 1-bit from the read pointer. If double_line buf=0 then the read address is the full 8-bits from the read address generator. if (double-line-buf == 1 )then 25 read_port(7:0] = {rd_ptr[0],rd_adr[6:0}) // concatenation else readport[7:0] = rdadr(7:0] 30.4.3.5.2 Read address generator For each contone plane there is a initial, lower and upper index to be used when reading dither cell values 30 from the dither matrix double buffer. The read address for each plane is used to select a byte from the current 256-byte read buffer. When Go gets set (0 to 1 transition), or at the end of a line, the read addresses are set to their corresponding initial index. Otherwise, the read address generator relies on advdot to advance the addresses within the inclusive range specified the lower and upper indices, represented by the following pseudocode: 35 if (advdot == 1) then if (advline == 1) then rdadr = dminitindex elsif (rd-adr == dmnkuprindex) then WO 2005/120835 PCT/AU2004/000706 868 rd_adr = dm-(_lwrindex else rd adr ++ else 5 rdadr = rd-adr 30.4.3.5.3 State machine The dither matrix is read from DRAM in single 256-bit accesses, receiving the data from the DIU over 4 clock cycles (64-bits per cycle).The protocol and timing for read accesses to DRAM is described in section 22.9.1 on page 337. Read accesses to DRAM are implemented by means of the state machine described in 10 Figure 245. All counters and flags are cleared after reset or when Go transitions from 0 to 1. While the Go bit is 1, the state machine relies on the dmreadenable bit to tell it whether to attempt to read dither matrix data from DRAM. When dmreadenable is clear, the state machine does nothing and remains in the idle state. When dm read enable is set, the state machine continues to load dither matrix data, 256-bits at a time (received 15 over 4 clock cycles, 64 bits per cycle), while there is space available in the dither matrix buffer, (bufffull != ). The read address and linestart adr are initially set to start_dm_adr. The read address gets incremented after each read access. It takes 4 or 8 read accesses to load a line of dither matrix into the dither matrix buffer, depending on whether single or double buffering is being used. A count is kept of the accesses to DRAM. 20 When a read access completes and access count equals 3 or 7, a line of dither matrix has just been loaded from and the read address is updated to linestartadr plus line-increment so it points to the start of the next line of dither matrix. (linestart adr is also updated to this value). If the read address equals enddmadr then the next read address will be start_dm_adr, thus the read address wraps to point to the start of the area in DRAM where the dither matrix is stored. 25 The write address for the dither matrix buffer is implemented by means of a modulo-32 counter that -is initially set to 0 and incremented when diuhcurvalid is asserted. Figure 244 shows an example of setting start dm_adr and enddmadr values in relation to the line increment and double line buffer settings. The calculation of enddm adr is // end_dn_adr calculation 30 dmheight = Dither matrix height in lines if (double_linebuf == 1) // end_dmadr[21:5] = start_dmadr(21:5] + (((dnheight - 1)*line_inc) + 3) << 5) else 35 end_dim_adr(21:5] = start_diadr[21:5] + (((dmheight - 1)*line-inc) + 7) << 5) 30.4.4 Contone dotgen unit The contone dotgen unit is responsible for producing a dot in up to 4 color planes per cycle. The contone dotgen unit also produces a cpavail flag which specifies whether or not contone pixels are currently WO 2005/120835 PCT/AU2004/000706 869 available, and the output hcu cfuadvdot to request the CFU to provide the next contone pixel in up to 4 color planes. The block diagram for the contone dotgen unit is shown in Figure 246. A dither unit provides the functionality for dithering a single contone plane. The contone image is only 5 defined within the contone/spot margin area. As a result, if the input flag intargetpage is 0, then a constant contone pixel value is used for the pixel instead of the contone plane. The resultant contone pixel is then halftoned. The dither value to be used in the halftoning process is provided by the control data unit. The halftoning process involves a comparison between a pixel value and its corresponding dither value. If the 8-bit contone value is greater than or equal to the 8-bit dither matrix value 10 a 1 is output. If not, then a 0 is output. This means each entry in the dither matrix is in the range 1-255 (0 is not used). Note that constant use is dependant on the intarget_page signal only. If intarget_page is 1 then the cfuhcu_c*_data passes through, regardless of the stalling behaviour or the avail_mask[1] setting. This allows a constant value to be setup on the CFU output data, and the use of different constants while inside and 15 outside the target page. The hcu cfuadvdot will always be zero if the availmask[I] is zero. 30.4.5 Spot dotgen unit The spot dotgen unit is responsible for producing a dot of bi-level data per cycle. It deals with bi-level data (and therefore does not need to halftone) that comes from the LBD via the SFU. Like the contone layer, the bi-level spot layer is only defined within the contone/spot margin area. As a result, if input flag 20 in_targetpage is 0, then a constant dot value (typically this would be 0) is used for the output dot. The spot dotgen unit also produces a savail flag which specifies whether or not spot dots are currently available for this spot plane, and the output hcu sf u_advdot to request the SFU to provide the next bi-level data value. The spot dotgen unit can be represented by the following pseudocode: s_avail = sfuhcuavail 25 if (intargetpage == 1 AND availmask[2] == 0 )OR (in_.targetpage == 0) then hcusfu-advdot = 0 else 30 hcusfuadvdot = advdot if (intargetpage == 1) then sp = sfu-hcu-sdata else 35 sp = sp-constant Note that constant use is dependant on the intarget_page signal only. If intarget_page is 1 then the sfuhcu data passes through, regardless of the stalling behaviour or the availmask setting. This allows a WO 2005/120835 PCT/AU2004/000706 870 constant value to be setup on the SFU output data, and the use of different constants while inside and outside the target page. The hcu sfuadvdot will always be zero if the avail mask[2] is zero. 30.4.6 Tag dotgen unit This unit is very similar to the spot dotgen unit (see Section 30.4.5) in that it deals with bi-level data, in this 5 case from the TE via the TFU. The tag layer is only defined within the tag margin area. As a result, if input flag intagtarget jage is 0, then a constant dot value, tp_constant (typically this would be 0), is used for the output dot. The tagplane dotgen unit also produces a tpavail flag which specifies whether or not tag dots are currently available for the tagplane, and the output hcu _tfuadvdot to request the TFU to provide the next bi level data value. 10 The hcutfuadvdot generation is similar to the SFU and CFU, except it depends only on injtargetpage and advdot. It does not take availmask into account when inside the target page. 30.4.7 Dot reorg unit The dot reorg unit provides a means of mapping the bi-level dithered data, the spotO color, and the tag data to output inks in the actual printhead. Each dot reorg unit takes a set of 6 1-bit inputs and produces a single bit 15 output that represents the output dot for that color plane. The output bit is a logical combination of any or all of the input bits. This allows the spot color to be placed in any output color plane (including infrared for testing purposes), black to be replaced by cyan, magenta and yellow (in the case of no black ink in the Memjet printhead), and tag dot data to be placed in a visible plane. An output for fixative can readily be generated by simply combining desired input bits. 20 The dot reorg unit contains a 64-bit lookup to allow complete freedom with regards to mapping. Since all possible combinations of input bits are accounted for in the 64 bit lookup, a given dot reorg unit can take the mapping of other reorg units into account. For example, a black plane reorg unit may produce a 1 only if the contone plane 3 or spot color inputs are set (this effectively composites black bi-level over the contone). A fixative reorg unit may generate a 1 if any 2 of the output color planes is set (taking into account the mappings 25 produced by the other reorg units). If dead nozzle replacement is to be used (see section 31.4.2 on page 631), the dot reorg can be programmed to direct the dots of the specified color into the main plane, and 0 into the other. If a nozzle is then marked as dead in the DNC, swapping the bits between the planes will result in 0 in the dead nozzle, and the required data in the other plane. 30 If dead nozzle replacement is to be used, and there are no tags, the TE can be programmed with the position of dead nozzles and the resultant pattern used to direct dots into the specified nozzle row. If only fixed background TFS is to be used, a limited number of nozzles can be replaced. If variable tag data is to be used to specify dead nozzles, then large numbers of dead nozzles can be readily compensated for. The dot reorg unit can be used to average out the nozzle usage when two rows of nozzles share the same ink 35 and tag encoding is not being used. The TE can be programmed to produce a regular pattern (e.g. 0101 on one WO 2005/120835 PCT/AU2004/000706 871 line, and 1010 on the next) and this pattern can be used as a directive as to direct dots into the specified nozzle row. Each reorg unit contains a 64-bit IOMapping value programmable as two 32-bit HCU registers, and a set of selection logic based on the 6-bit dot input (26 = 64 bits), as shown in Figure 247. 5 The mapping of input bits to each of the 6 selection bits is as defined in Table 195. Table 195. Mapping of input bits to 6 selection bits ,address bit teto,.likely 0 bi-level dot from contone layer 0 cyan 1 bi-level dot from contone layer 1 magenta 2 bi-level dot from contone layer 2 yellow 3 bi-level dot from contone layer 3 black 4 bi-level spotO dot black 5 bi-level tag dot infra-red 30.4.8 Output buffer The output buffer de-couples the stalling behaviour of the feeder units from the stalling behaviour of the DNC. The larger the buffer the greater de-coupling. Currently the output buffer size is 2. 10 If the Go bit is set to 0 no read or write of the output buffer is permitted. On a 0 to 1 transition of the Go bit the contents of the output buffer are cleared. The output buffer also implements the interface logic to the DNC. If there is data in the output buffer the hcudnc avail signal is 1, otherwise is 0. If both hcudncavail and dnchcu ready are 1 then data is read from the output buffer. 15 On the write side if there is space available in the output buffer the logic indicates to the control unit via the output-bufffull signal. The control unit will then allow writes to the output buffer via the wradvdot signal. If the writes to the output buffer are after the end of a page (indicated by in_page equal to 0) then all dots written into the output buffer are set to zero. 30.4.8.1 HCU to DNC Interface 20 Figure 248 shows the timing diagram and representative logic of the HCU to DNC interface. The hcudnc avail signal indicate to the DNC that the HCU has data available. The dnc hcu ready signal indicates to the HCU that the DNC is ready to accept data. When both signals are high data is transferred from the HCU to the DNC. Once the HCU indicates it has data available (setting the hcudncavail signal high) it can only set the hcudncavail low again after a dot is accepted by the DNC.
WO 2005/120835 PCT/AU2004/000706 872 30.4.9 Feeder to HCU interfaces Figure 249 shows the feeder unit to HCU interface timing diagram, and Figure 250 shows representative logic of the interface with the register positions. sfu_hcudata and sfu_hcu_avail are always registered while the sfuhcuadvdot is not. The hcu _sfuavail signal indicates to the HCU that the feeder unit has data available, 5 and sfu_hcuadvdot indicates to the feeder unit that the HCU has captured the last dot. The HCU can never produce an advance dot pulse while the avail is low. The diagrams show the example of the SFU to HCU interface, but the same interface is used for the other feeder units TFU and CFU. 31 DEAD NOZZLE COMPENSATOR (DNC) 10 31.1 OVERVIEW The Dead Nozzle Compensator (DNC) is responsible for adjusting Memjet dot data to take account of non functioning nozzles in the Memjet printhead. Input dot data is supplied from the HCU, and the corrected dot data is passed out to the DWU. The high level data path is shown by the block diagram in Figure 251. The DNC compensates for a dead nozzles by performing the following operations: 15 - Dead nozzle removal, i.e. turn the nozzle off Ink replacement by direct substitution e.g. K -> Kee * Ink replacement by indirect substitution e.g. K -> CMY * Error diffusion to adjacent nozzles * Fixative corrections 20 The DNC is required to efficiently support up to 5% dead nozzles, under the expected DRAM bandwidth allocation, with no restriction on where dead nozzles are located and handle any fixative correction due to nozzle compensations. Performance must degrade gracefully after 5% dead nozzles. 31.2 DEAD NOZZLE IDENTIFICATION Dead nozzles are identified by means of a position value and a mask value. Position information is 25 represented by a 10-bit delta encoded format, where the 10-bit value defines the number of dots between dead nozzle columns. The delta information is stored with an associated 6-bit dead nozzle mask (dnmask) for the defined dead nozzle position. Each bit in the dnmask corresponds to an ink plane. A set bit indicates that the nozzle for the corresponding ink plane is dead. The dead nozzle table format is shown in Figure 252. The DNC reads dead nozzle information from DRAM in single 256-bit accesses. A 10-bit delta encoding scheme 30 is chosen so that each table entry is 16 bits wide, and 16 entries fit exactly in each 256-bit read. Using 10-bit delta encoding means that the maximum distance between dead nozzle columns is 1023 dots. It is possible that dead nozzles may be spaced further than 1023 dots from each other, so a null dead nozzle identifier is required. A null dead nozzle identifier is defined as a 6-bit dnmask of all zeros. These null dead nozzle identifiers should also be used so that: WO 2005/120835 PCT/AU2004/000706 873 - the dead nozzle table is a multiple of 16 entries (so that it is aligned to the 256-bit DRAM locations) " the dead nozzle table spans the complete length of the line, i.e. the first entry dead nozzle table should have a delta from the first nozzle column in a line and the last entry in the dead nozzle table 5 should correspond to the last nozzle column in a line. Note that the DNC deals with the width of a page. This may or may not be the same as the width of the printhead (printhead ICs may overlap due to misalignment during assembly, and additionally, the LLU may introduce margining to the page). Care must be taken when programming the dead nozzle table so that dead nozzle positions are correctly specified with respect to the page and printhead. 10 31.3 DRAM STORAGE AND BANDWIDTH REQUIREMENT The memory required is largely a factor of the number of dead nozzles present in the printhead (which in turn is a factor of the printhead size). The DNC reads a 16-bit entry from the dead nozzle table for every dead nozzle. Table 196 shows the DRAM storage and average bandwidth requirements for the DNC for different percentages of dead nozzles and different page sizes. Table 196. Dead Nozzle storage and average bandwidth requirements Memory Bandwidth (KBytes) (bits/cycle) A4' 5% 1.44 0.8d 10% 2.7 1.6 15% 4.1 2.4 A3 5% 1.9 0.8 10% 3.8 1.6 15% 5.7 2.4 15 a. Linking printhead has 13824 nozzles per color providing full bleed printing for A4/Letter b. Linking printhead has 19488 nozzles per color providing full bleed printing for A3 c. 16 bits x 13824 nozzles x 0.05 dead d. (16 bits read / 20 cycles) = 0.8 bits/cycle 20 31.4 NOZZLE COMPENSATION The DNC receives 6 bits of dot information every cycle from the HCU, 1 bit per color plane. When the dot position corresponds to a dead nozzle column, the associated 6-bit dn mask indicates which ink plane(s) contains a dead nozzle(s). The DNC first deletes dots destined for the dead nozzle. It then replaces those dead dots, either by placing the data destined for the dead nozzle into an adjacent ink plane (direct substitution) or WO 2005/120835 PCT/AU2004/000706 874 into a number of ink planes (indirect substitution). After ink replacement, if a dead nozzle is made active again then the DNC performs error diffusion. Finally, following the dead nozzle compensation mechanisms the fixative, if present, may need to be adjusted due to new nozzles being activated, or dead nozzles being removed. 5 31.4.1 Dead nozzle removal If a nozzle is defined as dead, then the first action for the DNC is to turn off (zeroing) the dot data destined for that nozzle. This is done by a bit-wise ANDing of the inverse of the dnmask with the dot value. 31.4.2 Ink replacement Ink replacement is a mechanism where data destined for the dead nozzle is placed into an adjacent ink plane 10 of the same color (direct substitution, e.g. K -> Kaitemaive), or placed into a number of ink planes, the combination of which produces the desired color (indirect substitution, e.g. K -> CMY). Ink replacement is performed by filtering out ink belonging to nozzles that are dead and then adding back in an appropriately calculated-pattern. This two step process allows the optional re-inclusion of the ink data into the original dead nozzle position to be subsequently error diffused. In the general case, fixative data destined for a dead nozzle 15 should not be left active intending it to be later diffused. The ink replacement mechanism has 6 ink replacement patterns, one per ink plane, programmable by the CPU. The dead nozzle mask is ANDed with the dot data to see if there are any planes where the dot is active but the corresponding nozzle is dead. The resultant value forms an enable, on a per ink basis, for the ink replacement process. If replacement is enabled for a particular ink, the values from the corresponding 20 replacement pattern register are ORed into the dot data. The output of the ink replacement process is then filtered so that error diffusion is only allowed for the planes in which error diffusion is enabled. The output of the ink replacement logic is ORed with the resultant dot after dead nozzle removal. See Figure 257 on page 642 for implementation details. For example if we consider the printhead color configuration C,M,Y,K 1
,K
2 ,IR and the input dot data from the 25 HCU is b101100. Assuming that the K, ink plane and IR ink plane for this position are dead so the dead nozzle mask is bOO0101. The DNC first removes the dead nozzle by zeroing the Ki plane to produce b101000. Then the dead nozzle mask is ANDed with the dot data to give b000100 which selects the ink replacement pattern for K, (in this case the ink replacement pattern for K, is configured as bOO0010, i.e. ink replacement into the K 2 plane). Providing error diffusion for K 2 is enabled, the output from the ink replacement process is 30 bOOO 10. This is ORed with the output of dead nozzle removal to produce the resultant dot b 101010. As can be seen the dot data in the defective K, nozzle was removed and replaced by a dot in the adjacent K 2 nozzle in the same dot position, i.e. direct substitution. In the example above the K, ink plane could be compensated for by indirect substitution, in which case ink replacement pattern for K, would be configured as bl 11000 (substitution into the CMY color planes), and this 35 is ORed with the output of dead nozzle removal to produce the resultant dot bl 11000. Here the dot data in the defective K ink plane was removed and placed into the CMY ink planes.
WO 2005/120835 PCT/AU2004/000706 875 31.4.3 Error diffusion Based on the programming of the lookup table the dead nozzle may be left active after ink replacement. In such cases the DNC can compensate using error diffusion. Error diffusion is a mechanism where dead nozzle dot data is diffused to adjacent dots. 5 When a dot is active and its destined nozzle is dead, the DNC will attempt to place the data into an adjacent dot position, if one is inactive. If both dots are inactive then the choice is arbitrary, and is determined by a pseudo random bit generator. If both neighbor dots are already active then the bit cannot be compensated by diffusion. Since the DNC needs to look at neighboring dots to determine where to place the new bit (if required), the 10 DNC works on a set of 3 dots at a time. For any given set of 3 dots, the first dot received from the HCU is referred to as dot A, and the second as dot B, and the third as dot C. The relationship is shown in Figure 253. For any given set of dots ABC, only B can be compensated for by error diffusion if B is defined as dead. A 1 in dot B will be diffused into either dot A or dot C if possible. If there is already a 1 in dot A or dot C then a 1 15 in dot B cannot be diffused into that dot. The DNC must support adjacent dead nozzles. Thus if dot A is defined as dead and has previously been compensated for by error diffusion, then the dot data from dot B should not be diffused into dot A. Similarly, if dot C is defined as dead, then dot data from dot B should not be diffused into dot C. Error diffusion should not cross line boundaries. If dot B contains a dead nozzle and is the first dot in a line 20 then dot A represents the last dot from the previous line. In this case an active bit on a dead nozzle of dot B should not be diffused into dot A. Similarly, if dot B contains a dead nozzle and is the last dot in a line then dot C represents the first dot of the next line. In this case an active bit on a dead nozzle of dot B should not be diffused into dot C. Thus, as a rule, a 1 in dot B cannot be diffused into dot A if 25 0 a 1 is already present in dot A, e dot A is defined as dead, * or dot A is the last dot in a line. Similarly, a 1 in dot B cannot be diffused into dot C if * a 1 is already present in dot C, 30 0 dot C is defined as dead, * or dot C is the first dot in a line. If B is defined to be dead and the dot value for B is 0, then no compensation needs to be done and dots A and C do not need to be changed. If B is defined to be dead and the dot value for B is 1, then B is changed to 0 and the DNC attempts to place 35 the I from B into either A or C: WO 2005/120835 PCT/AU2004/000706 876 * If the dot can be placed into both A and C, then the DNC must choose between them. The preference is given by the current output from the random bit generator, 0 for "prefer left" (dot A) or 1 for "prefer right" (dot C). " If dot can be placed into only one of A and C, then the 1 from B is placed into that position. 5 * If dot cannot be placed into either one of A or C, then the DNC cannot place the dot in either position. Table 197. Error Diffusion Truth Table when dot B is dead A 0 1r nu nu A 1ea 0 0 1ed Rn ' A O Cu 0 1 0 1 A input 0 1 0 1 1 X 1 0 C input 1 0 0 X A input 0 C input 1 0 1 X A input 0 C input 1 1 0 X A input 0 1 1 1 1 X A input 0 C input Table 197 shows the truth table for DNC error diffusion operation when dot B is defined as dead. a. Output from random bit generator. Determines direction of error diffusion (0 = left, 1 = right) b. Bold emphasis is used to show the DNC inserted a 1 10 The random bit value used to arbitrarily select the direction of diffusion is generated by a 32-bit maximum length random bit generator. The generator generates a new bit for each dot in a line regardless of whether the dot is dead or not. The random bit generator is initialized with a 32-bit programmable seed value. 31.4.4 Fixative correction After the dead nozzle compensation methods have been applied to the dot data, the fixative, if present, may 15 need to be adjusted due to new nozzles being activated, or dead nozzles being removed. For each output dot the DNC determines if fixative is required (using the FixativeRequiredMask register) for the new compensated dot data word and whether fixative is activated already for that dot. For the DNC to do so it needs to know the color plane that has fixative, this is specified by the FixativeMaski configuration register. Table 198 indicates the actions to take based on these calculations.
WO 2005/120835 PCT/AU2004/000706 877 Table 198. Truth table for fixative correction SPresn eqie 1 1 Output dot as is. 1 0 Clear fixative plane. 0 1 Attempt to add fixative. 0 0 Output dot as is. The DNC also allows the specification of another fixative plane, specified by the FixativeMask2 configuration register, with FixativeMask1 having the higher priority over FixativeMask2. When attempting to add fixative the DNC first tries to add it into the planes defined by FixativeMask1. However, if any of these planes is dead 5 then it tries to add fixative by placing it into the planes defined by FixativeMask2. Note that the fixative defined by FixativeMaski and FixativeMask2 could possibly be multi-part fixative, i.e. 2 bits could be set in FixativeMaski with the fixative being a combination of both inks. 31.5 NOZZLE ACTIVATE LOGIC Ink becomes more viscous in a nozzle the longer it remains uncapped but inactive. This leads to the 10 possibility of the nozzles becoming blocked with ink if they are not fired within a particular time period (ink chemistry dependent). If the time period is longer than the time taken to print a page, then all printhead nozzles can be fired between pages. However, if the time period is shorter than the time taken to print a page, then it is necessary to fire all the nozzles during the printing of the page such that all of the nozzles have been fired at least once during the time period. 15 The DNC implements a simple system to activate a configured mask of nozzles DncKeepWetMaskO after DncKeepWetCntO number of dots and then DncKeepWetMask1 after DncKeepWetCnt1 number of dots. The sequence is repeated for all dot in a page. The DncKeep WetMask is applied ANDed with the DNMask so as to prevent the nozzle activate logic from incorrectly activating a dead nozzle. The nozzle activate logic is applied within the ink replacement unit but before the ink replacement logic. 20 It is probably desirable to have all six nozzles print to the same dot, (a b 111111 dot), but this might be two much ink to put in one place. Thus dot masks are supported, allowing us to spread the load a little (e.g. bOO01 11, b1 11000). If this isn't necessary, then just program DncKeepWetCntO = DncKeepWetCnt1 and DncKeep WetMaskO = DncKeepWetMaskl. The DncKeepWetCntO, DncKeepWetCntl counters need to be programmed correctly in relation to the page 25 width and length, to ensure that all nozzles in a line are fired with sufficient frequency to prevent nozzle blocking, and to ensure that nozzles don't get fired in such a sequence to introduce noticeable on page artifacts.
WO 2005/120835 PCT/AU2004/000706 878 31.6 IMPLEMENTATION A block diagram of the DNC is shown in Figure 254. 31.6.1Definitions of I/O Table 199. DNC port list and description Clocks and Resets pclk 1 In System Clock. prstn 1 In System reset, synchronous active low. PCU interface pcudncsel 1 In Block select from the PCU. When pcu_dnc selis high both pcuadr and pcu dataout are valid. pcurwn 1 In Common read/not-write signal from the PCU. pcu-adr[6:2] 5 In PCU address bus. Only 5 bits are required to decode the address space for this block. pcu-dataout[31:0] 32 In Shared write data bus from the PCU. dnc-pcu-rdy 1 Out Ready signal to the PCU. When dncjpcurdy is high it indicates the last cycle of the access. For a write cycle this means pcudataout has been registered by the block and for a read cycle this means the data on dnc-pcu datain is valid. dnc-pcu-datain[31:0] 32 Out Read data bus to the PCU. DIU interface dnc-diu-rreq 1 Out DNC unit requests DRAM read. A read request must be accompanied by a valid read address. dnc-diu-radr[21:5] 17 Out Read address to DIU, 256-bit word aligned. diudncrack 1 In Acknowledge from DIU that read request has been accepted and new read address can be placed on dnc_diu_radr diudncrvalid 1 In Read data valid, active high. Indicates that valid read data is now on the read data bus, diu_data. diu-data[63:0] 64 In Read data from DIU. HCU interface dnc-hcu-ready 1 Out Indicates that DNC is ready to accept data from the HCU. hcudncavail 1 In Indicates valid data present on hcu_dnc_data. hcu-dnc-data[5:0] 6 In Output bi-level dot data in 6 ink planes. DWU interface dwu.dnc-ready 1 In Indicates that DWU is ready to accept data from the
DNC.
WO 2005/120835 PCT/AU2004/000706 879 dnc_dwuavail 1 Out Indicates valid data present on dnc dwudata. dncdwudata[5:0] 6 Out Output bi-level dot data in 6 ink planes. 31.6.1 31.6.2 Configuration registers The configuration registers in the DNC are programmed via the PCU interface. Refer to section 23.8.2 on page 439 for the description of the protocol and timing diagrams for reading and writing registers in the DNC. 5 Note that since addresses in SoPEC are byte aligned and the PCU only supports 32-bit register reads and writes, the lower 2 bits of the PCU address bus are not required to decode the address space for the DNC. When reading a register that is less than 32 bits wide zeros are returned on the upper unused bit(s) of dncficudatain. Table 200 lists the configuration registers in the DNC. Table 200. DNC configuration registers NC bae+ Reise n tecito Control registers Ox00 Reset 1 Ox1 A write to this register causes a reset of the DNC. Ox04 Go 1 Ox0 Writing 1 to this register starts the DNC. Writing 0 to this register halts the DNC. When Go is asserted all counters, flags etc. are cleared or given their initial value, but configuration registers keep their values. When Go is reasserted the state machines go to their idle states but all counters and configuration registers keep their values. This register can be read to determine if the DNC is running (1 = running, 0 = stopped). Setup registers (constant during processing) Ox10 MaxDot 16 Ox0000 This is the maximum dot number - 1 present across a page. For example if a page contains 13824 dots, then MaxDot will be 13823. Note that this number may or may not be the same as the number of dots across the printhead as some margining may be introduced in the PHI.
WO 2005/120835 PCT/AU2004/000706 880 0x14 LSFR 32 Ox0000 The current value of the LFSR register 0000 used as the 32-bit maximum length random bit generator. Users can write to this register to program a seed value for the 32-bit maximum length random bit generator. Must not be all 1s, as the LFSR taps are applied via XNOR. (It is expected that writing a seed value will not occur during the operation of the LFSR). A read will return the current LSFR value. This LSFR value could also have a possible use as a random source in program code. (Working Register) 0x20 FixativeMask1 6 Ox00 Defines the higher priority fixative plane(s). Bit 0 represents the settings for plane 0, bit 1 for plane 1 etc. For each bit: 1 = the ink plane contains fixative. 0 = the ink plane does not contain fixative. Ox24 FixativeMask2 6 Ox00 Defines the lower priority fixative plane(s). Bit 0 represents the settings for plane 0, bit 1 for plane 1 etc. Used only when FixativeMask1 planes are dead. For each bit: 1 = the ink plane contains fixative. 0 = the ink plane does not contain fixative. Ox28 FixativeRequiredMa 6 0x00 Identifies the ink planes that require sk fixative. Bit 0 represents the settings for plane 0, bit 1 for plane 1 etc. For each bit: 1 = the ink plane requires fixative. 0 = the ink plane does not require fixative (e.g. ink is self-fixing) 0x30 DnTableStartAdr[21: 17 OxO_000 Start address of Dead Nozzle Table in 5] 0 DRAM, specified in 256-bit words. Ox34 DnTableEndAdr[21: 17 OxO_000 End address of Dead Nozzle Table in 5] 0 DRAM, specified in 256-bit words, i.e. the location containing the last entry in the Dead Nozzle Table. The Dead Nozzle Table should be aligned to a 256-bit boundary, if necessary it can be padded with null entries. Ox40 - Ox54 PlaneReplacePatter 6x6 Ox00 Defines the ink replacement pattern for n[5:0] each of the 6 ink planes. PlaneReplacePattern[O] is the ink replacement pattern for plane 0, PlaneReplacePattern[l] is the ink replacement pattern for plane 1, etc. For each 6-bit replacement pattern for a plane, a 1 in any bit positions indicates the alternative ink planes to be used for this plane. Ox58 DiffuseEnable 6 Ox3F Defines whether, after ink replacement, error diffusion is allowed to be performed on each plane. Bit 0 represents the settings for plane 0, bit 1 for plane 1 etc. For each bit: 1 = error diffusion is enabled 0 = error diffusion is disabled WO 2005/120835 PCT/AU2004/000706 881 0x60 DncKeepWetCntO 16 Ox0000 Specifies the number of dots -1 between mask insertion points where the DncKeepWetMaskO is inserted into the dot stream. For example if 0 the mask will be inserted every dot, if 1 it's inserted every second dot. 0x64 DncKeepWetCntl 16 Ox0000 Specifies the number of dots -1 between mask insertion points where the DncKeepWetMaskl is inserted into the dot stream. 0x68 DncKeepWetMask0 6 Ox00 Specifies which nozzles need to be fired after the DncKeepWetCntO number of dots have been transmitted Ox6C DncKeepWetMask1 6 Ox00 Specifies which nozzles need to be fired after the DncKeepWetCntl number of dots have been transmitted Debug registers (read only) 0x70 DncOutputDebug 8 N/A Bit 7 = dwudnc_ready Bit 6 = dnc_dwu avail Bits 5-0 = dncdwudata 0x74 DncReplaceDebug 14 N/A Bit 13 = edu ready Bit 12 = iruavail Bits 11-6 = irudnmask Bits 5-0 = iru data 0x78 DncDiffuseDebug 14 N/A Bit 13 = dwudnc.ready Bit 12 = dncdwu_avail Bits 11-6 = edu_dn_mask Bits 5-0 = edudata 31.6.3 Ink replacement unit Figure 255 shows a sub-block diagram for the ink replacement unit. 31.6.3.1 Control unit 5 The control unit is responsible for reading the dead nozzle table from DRAM and making it available to the DNC via the dead nozzle FIFO. The dead nozzle table is read from DRAM in single 256-bit accesses, receiving the data from the DIU over 4 clock cycles (64-bits per cycle). The protocol and timing for read accesses to DRAM is described in section 22.9.1 on page 337. Reading from DRAM is implemented by means of the state machine shown in Figure 256. 10 All counters and flags should be cleared after reset. When Go transitions from 0 to 1 all counters and flags should take their initial value. While the Go bit is 1, the state machine requests a read access from the dead nozzle table in DRAM provided there is enough space in its FIFO. A modulo-4 counter, rdcount, is used to count each of the 64-bits received in a 256-bit read access. It is incremented whenever diu dnc valid is asserted. When Go is 1, dn table radr is set to dn table start adr. 15 As each 64-bit value is returned, indicated by diu dncrvalid being asserted, dntableradr is compared to dn table end adr: WO 2005/120835 PCT/AU2004/000706 882 e If rd_count equals 3 and dntable radr equals dntableendadr, then dntable radr is updated to dn table start adr. * If rd_count equals 3 and dntableradr does not equal dntable_end_adr, then dntableradr is incremented by 1. 5 A count is kept of the number of 64-bit values in the FIFO. When diudncrvalid is 1 data is written to the FIFO by asserting wren, andfifocontents andfifowradr are both incremented. When fifocontents[3:0] is greater than 0 and eduready is 1, dnchcuready is asserted to indicate that the DNC is ready to accept dots from the HCU. If hcudncavail is also 1 then a dotadv pulse is sent to the GenMask unit, indicating the DNC has accepted a dot from the HCU, and iru avail is also asserted. After Go 10 is set, a single preload pulse is sent to the GenMask unit once the FIFO contains data. When a rd adv pulse is received from the GenMask unit, fifo_rd adr[4:0j is then incremented to select the next 16-bit value. If fiford~adr[1 :0] = 11 then the next 64-bit value is read from the FIFO by asserting rd_en, andfifocontents[3:0] is decremented. 31.6.3.2 Dead nozzle FIFO 15 The dead nozzle FIFO conceptually is a 64-bit input, and 16-bit output FIFO to account for the 64-bit data transfers from the DIU, and the individual 16-bit entries in the dead nozzle table that are used in the GenMask unit. In reality, the FIFO is actually 8 entries deep and 64-bits wide (to accommodate two 256-bit accesses). On the DRAM side of the FIFO the write address is 64-bit aligned while on the GenMask side the read address is 16-bit aligned, i.e. the upper 3 bits are input as the read address for the FIFO and the lower 2 bits 20 are used to select 16 bits from the 64 bits (1st 16 bits read corresponds to bits 15-0, second 16 bits to bits 31 16 etc.). 31.6.3.3 Nozzle activate unit The nozzle activate unit is responsible for activating nozzles periodically to prevent nozzle blocking. It inserts a nozzle activate mask dnckeepwetmask every dnc keep wetcnt number of active dots. The logic 25 alternates between 2 configurable count and mask values, and repeats until Go is deasserted. The logic is implemented with a single counter which is loaded with dnc_.keep wetcntO when the preload signal from the control unit is received. The counter decrements each time an active dot is produced as indicated by the dotadv signal. When the counter is 0, the dnckeepwet maskO is inserted in the dot stream, and the counter is loaded with the dnc__keepwetcntl. The counter is again decremented with each dotadv 30 and when 0 the dnckeepwetmask1 is inserted in the dot stream. The counter is loaded dnckeep__wet_cntO value and the process is repeated. When a dnc keep_wetmask value is inserted in the dot stream the nozzle activate unit checks the dnmask value to prevent a dead nozzle getting activated by the inserted dot. The pseudocode is: 35 if (preload == 1) then WO 2005/120835 PCT/AU2004/000706 883 cnt-sel = 0 dot_cnt = dnc_keepwetcnt[cntsel] elsif ( dotadv == 1 ) then if ( dot-cnt == 0) then 5 // insert nozzle mask dot-insert = (dnckeepwetmask[cntsel] AND NOT(dn_mask)) naudata = hcudncdata OR dot-insert cntsel = NOT(cnt-sel) dot_cnt = dnckeepwetcnt[cntsell 10 else dotcnt - 31.6.3.4 GenMask unit The GenMask unit generates the 6-bit dnmask that is sent to the replace unit. It consists of a 10-bit delta 15 counter and a mask register. After Go is set, the GenMask unit will receive a preload pulse from the control unit indicating the first dead nozzle table entry is available at the output of the dead nozzle FIFO and should be loaded into the delta counter and mask register. A rd adv pulse is generated so that the next dead nozzle table entry is presented at the output of the dead nozzle FIFO. The delta counter is decremented every time a dotadv pulse is received. 20 When the delta counter reaches 0, it gets loaded with the current delta value output from the dead nozzle FIFO, i.e. bits 15-6, and the mask register gets loaded with mask output from the dead nozzle FIFO, i.e. bits 5-0. A rd-adv pulse is then generated so that the next dead nozzle table entry is presented at the output of the dead nozzle FIFO. When the delta counter is 0 the value in the mask register is output as the dnmask, otherwise the dn mask is 25 all Os. The GenMask unit has no knowledge of the number of dots in a line; it simply loads a counter to count the delta from one dead nozzle column to the next. Thus as described in section 31.2 on page 629 the dead nozzle table should include null identifiers if necessary so that the dead nozzle table covers the first and last nozzle column in a line. 30 31.6.3.5 Replace unit Dead nozzle removal and ink replacement are implemented by the combinatorial logic shown in Figure 257. Dead nozzle removal is performed by bit-wise ANDing of the inverse of the dnmask with the dot value. The ink replacement mechanism has 6 ink replacement patterns, one per ink plane, programmable by the CPU. The dead nozzle mask is ANDed with the dot data to see if there are any planes where the dot is active '35 but the corresponding nozzle is dead. The resultant value forms an enable, on a per ink basis, for the ink replacement process. If replacement is enabled for a particular ink, the values from the corresponding replacement pattern register are ORed into the dot data. The output of the ink replacement process is then filtered so that error diffusion is only allowed for the planes in which error diffusion is enabled.
WO 2005/120835 PCT/AU2004/000706 884 The output of the ink replacement process is ORed with the resultant dot after dead nozzle removal. If the dot position does not contain a dead nozzle then the dnmask will be all Os and the dot, hcudncdata, will be passed through unchanged. 31.6.4 Error Diffusion Unit 5 Figure 258 shows a sub-block diagram for the error diffusion unit. 31.6.4.1 Random Bit Generator The random bit value used to arbitrarily select the direction of diffusion is generated by a maximum length 32-bit LFSR. The tap points and feedback generation are shown in Figure 259. The LFSR generates a new bit for each dot in a line regardless of whether the dot is dead or not, i.e shifting of the LFSR is enabled when 10 advdot equals 1. The LFSR can be initialised with a 32-bit programmable seed value, randomseed. This seed value is loaded into the LFSR whenever a write occurs to the RandomSeed register. Note that the seed value must not be all Is as this causes the LFSR to lock-up.\ 31.6.4.2 Advance Dot Unit The advance dot unit is responsible for determining in a given cycle whether or not the error diffuse unit will 15 accept a dot from the ink replacement unit or make a dot available to the fixative correct unit and on to the DWU. It therefore receives the dwu_dncready control signal from the DWU the iru_avail flag from the ink replacement unit, and generates dncdwuavail and edu ready control flags. Only the dwudnc ready signal needs to be checked to see if a dot can be accepted and asserts eduready to indicate this. If the error diffuse unit is ready to accept a dot and the ink replacement unit has a dot available, 20 then a advdot pulse is given to shift the dot into the pipeline in the diffuse unit. Note that since the error diffusion operates on 3 dots, the advance dot unit ignores dwudncready initially until 3 dots have been accepted by the diffuse unit. Similarly dncdwuavail is not asserted until the diffuse unit contains 3 dots and the ink replacement unit has a dot available. 31.6.4.3 Diffuse Unit 25 The diffuse unit contains the combinatorial logic to implement the truth table from Table 197. The diffuse unit receives a dot consisting of 6 color planes (1 bit per plane) as well as an associated 6-bit dead nozzle mask value. Error diffusion is applied to all 6 planes of the dot in parallel. Since error diffusion operates on 3 dots, the diffuse unit has a pipeline of 3 dots and their corresponding dead nozzle mask values. The first dot received is 30 referred to as dot A, and the second as dot B, and the third as dot C. Dots are shifted along the pipeline . whenever advdot is 1. A count is also kept of the number of dots received. It is incremented whenever advdot is 1, and wraps to 0 when it reaches maxdot. When the dot count is 0 dot C corresponds to the first dot in a line. When the dot count is 1 dot A corresponds to the last dot in a line.
WO 2005/120835 PCT/AU2004/000706 885 In any given set of 3 dots, the diffuse unit only compensates for dead nozzles from the point of view of dot B (the processing of data due to the deadness of dot A and/or dot C is undertaken when the data is at dot B i.e. one dot-time earlier for data now in dot A, or one dot-time later for data now in dot C). Dead nozzles are identified by bits set in irudnmask. If dot B contains a dead nozzle(s), the corresponding bit(s) in dot A, dot 5 C, the dead nozzle mask value for A, the dead nozzle mask value for C, the dot count, as well as the random bit value are input to the truth table logic and the dots A, B and C assigned accordingly. If dot B does not contain a dead nozzle then the dots are shifted along the pipeline unchanged. 31.6.5 Fixative Correction Unit The fixative correction unit consists of combinatorial logic to implement fixative correction as defined in 10 Table 201. For each output dot the DNC determines if fixative is required for the new compensated dot data word and whether fixative is activated already for that dot. FixativePresent = ((FixativeMask1 I FixativeMask2) & edudata)!= 0 FixativeRequired = (FixativeRequiredMask & edu_data) != 0 15 It then looks up the truth table to see what action, if any, needs to be taken. Table 201. Truth table for fixative correction 1 1 Output dot as is. dncdwudata = edudata 1 0 Clear fixative dnc.dwu..data = (edu.data) & -(FixativeMaskl I plane. FixativeMask2) 0 1 Attempt to add if (FixativeMask1 & DnMask) != 0 fixative. dncdwudata = (edu-data) I (FixativeMask2 & -DnMask) else dncdwudata = (edu-data) I (FixativeMask1) 0 0 Output dot as is. dnc dwu data = edu data When attempting to add fixative the DNC first tries to add it into the plane defined by FixativeMaskl. However, if this plane is dead then it tries to add fixative by placing it into the plane defined by FixativeMask2. Note that if both FixativeMask1 and FixativeMask2 are both all Os then the dot data will not 20 be changed. 32 DOTLINE WRITER UNIT (DWU) 32.1 OVERVIEW The Dotline Writer Unit (DWU) receives 1 dot (6 bits) of color information per cycle from the DNC. Dot data 25 received is bundled into 256-bit words and transferred to the DRAM. The DWU (in conjunction with the WO 2005/120835 PCT/AU2004/000706 886 LLU) implements a dot line FIFO mechanism to compensate for the physical placement of nozzles in a printhead, and provides data rate smoothing to allow for local complexities in the dot data generate pipeline. 32.2 PHYSICAL REQUIREMENT IMPOSED BY THE PRINTHEAD The physical placement of nozzles in the printhead means that in one firing sequence of all nozzles, dots will 5 be produced over several print lines. The printhead consists of up to 12 rows of nozzles, one for each color of odd and even dots. Nozzles rows of the same color are separated by Di print lines and nozzle rows of different adjacent colors are separated by D 2 print lines. See Figure 261 for reference. The first color to be printed is the first row of nozzles encountered by the incoming paper. In the example this is color 0 odd, although is dependent on the printhead type. Paper passes under printhead moving upwards. 10 Due to the construction limitations the printhead can have nozzles mildly sloping over several lines, or a vertical alignment discontinuity at potentially different horizontal positions per row (D 3 ). The DWU doesn't need any knowledge of the discontinuities only that it stores sufficient lines in the dot store to allow the LLU to compensate. Figure 261 shows a possible vertical misalignment of rows within a printhead segment. There- will also be 15 possible vertical and horizontal misalignment of rows between adjacent printhead segments. The DWU compensates for horizontal misalignment of nozzle rows within printhead segments, and writes data out to half line buffers so that the LLU is able to compensate for vertical misalignments between and within printhead segments. The LLU also compensates for the horizontal misalignment between a printhead segment. 20 For example if the physical separation of each half row is 80gm equating to DI=D 2 =5 print lines at 1600dpi. This means that in one firing sequence, color 0 odd nozzles 1-17 will fire on dotline L, color 0 even nozzles 0 16 will fire on dotline L-DI, color 1 odd nozzles 1-17 will fire on dotline L-DI-D 2 and so on over 6 color planes odd and even nozzles. The total number of physical lines printed onto over a single line time is given as (0+5+5.....+5)+ 1= 1 lx5 + 1 =56. See Figure 262 for example diagram. 25 It is expected that the physical spacing of the printhead nozzles will be 80gm (or 5 dot lines), although there is no dependency on nozzle spacing. The DWU is configurable to allow other line nozzle spacings. Table 202. Relationship between Nozzle color/sense and line firing Ca,-.* . o.-~n edfis d line encountered i Sense line sense line Color 0 Even L even L-5 Odd L-5 odd L Color 1 Even L-10 even L-15 Odd L-15 odd L-10 Color 2 Even L-20 even L-25 WO 2005/120835 PCT/AU2004/000706 887 Odd L-25 odd L-20 Color 3 Even L-30 even L-35 Odd L-35 odd L-30 Color 4 Even L-40 even L-45 Odd L-45 odd L-40 Color 5 Even L-50 even L-55 Odd L-55 odd L-50 32.3 LINE RATE DE-COUPLING The DWU block is required to compensate for the physical spacing between lines of nozzles. It does this by storing dot lines in a FIFO (in DRAM) until such time as they are required by the LLU for dot data transfer to 5 the printhead interface. Colors are stored separately because they are needed at different times by the LLU. The dot line store must store enough lines to compensate for the physical line separation of the printhead but can optionally store more lines to allow system level data rate variation between the read (printhead feed) and write sides (dot data generation pipeline) of the FIFOs. A logical representation of the FIFOs is shown in Figure 263, where N is defined as the optional number of 10 extra half lines in the dot line store for data rate de-coupling. If the printhead contains nozzles sloping over X lines or a vertical misalignment of Y lines then the DWU must store N > X and N > Y lines in the dotstore to allow the LLU to compensate for the nozzle slope and any misalignment. It is also possible that the effects of a slope, and a vertical misalignment are accumulative, in such cases N > (X+Y). 15 32.3.1 Line Length relationship The DNC and the DWU concept of line lengths can be different. The DNC can be programmed to produce less dots than the DWU expects per line, or can be programmed to produce an odd number of dots (the DWU always expect an even number of dots per line). The DWU produces NozzleSkewPadding more dots than it excepts from the DNC per line. If the DNC is required to produce an odd number of dots, the 20 NozzleSkewPadding value can be adjusted to ensure the output from the DWU is still even. The relationship of line lengths between DWU and DNC must always satisfy: (LineSize + 1) * 2 - NozzleSkewPadding == DncLineLength 32.4 DOT LINE STORE STORAGE REQUIREMENTS For an arbitrary page width of d dots (where d is even), the number of dots per half line is d/2. 25 For interline spacing of D 2 and inter-color spacing of DI, with C colors of odd and even half lines, the number of half line storage is (C - 1) (D 2 +Dl) + D 1
.
WO 2005/120835 PCT/AU2004/000706 888 For N extra half line stores for each color odd and even, the storage is given by (N * C * 2). The total storage requirement is ((C - 1) (D 2
+D
1 ) + Di + (N * C * 2)) * d/2 in bits. Note that when determining the storage requirements for the dot line store, the number of dots per line is the page width and not necessarily the printhead width. The page width is often the dot margin number of dots 5 less than the printhead width. They can be the same size for full bleed printing. For example in an A4 page a line consists of 13824 dots at 1600 dpi, or 6912 dots per half dot line. To store just enough dot lines to account for an inter-line nozzle spacing of 5 dot lines it would take 55 half dot lines for color 5 odd, 50 dot lines for color 5 even and so on, giving 55+50+45... 10+5+0= 330 half dot lines in total. If it is assumed that N=4 then the storage required to store 4 extra half lines per color is 4 x 12=48, in 10 total giving 330+48=378 half dot lines. Each half dot line is 6912 dots, at 1 bit per dot give a total storage requirement of 6912 dots x 378 half dot lines / 8 bits = Approx 319 Kbytes. Similarly for an A3 size page with 19488 dots per line, 9744 dots per half line x 378 half dot lines / 8 = Approx 450 Kbytes. Table 203. Storage requirement for dot line store ......gU toag Eyt, sStrg Pageze Saig rqf NO bts required (=)Kye A4 4 264 223 312 263 5 330 278 378 319 A3 4 264 314 312 371 5 330 392 378 450 The potential size of the dot line store makes it unfeasible to be implemented in on-chip SRAM, requiring the 15 dot line store to be implemented in embedded DRAM. This allows a configurable dotline store where unused storage can be redistributed for use by other parts of the system. 32.5 NOZZLE ROW SKEW Due to construction limitations of the printhead it is possible that nozzle rows within a printhead segment may be misaligned relative to each other by up to 5 dots per half line, which means 56 dot positions over 12 half 20 lines (i.e. 28 dot pairs). Vertical misalignment can also occur but is compensated for in the LLU and not considered here. The DWU is required to compensate for the horizontal misalignment. Dot data from the HCU (through the DNC) produces a dot of 6 colors all destined for the same physical location on paper. If the nozzle rows in the within a printhead segment are aligned as shown in Figure 261 then no adjustment of the dot data is needed. 25 A conceptual misaligned printhead is shown in Figure 264. The exact shape of the row alignment is arbitrary, although is most likely to be sloping (if sloping, it could be sloping in either direction).
WO 2005/120835 PCT/AU2004/000706 889 The DWU is required to adjust the shape of the dot streams to take into account the relative horizontal displacement of nozzles rows between 2 adjacent printhead segments. The LLU compensates for the vertical skew between printhead segments, and the vertical and horizontal skew within printhead segments. The nozzle row skew function aligns rows to compensate for the seam between printhead segments (as shown in 5 Figure 264) and not for the seam within a printhead (as shown in Figure 261). The DWU nozzle row function results in aligned rows as shown in the example in Figure 265. To insert the shape of the skew into the dot stream, for each line we must first insert the dots for non-printable area 1, then the printable area data (from the DNC), and then finally the dots for non-printable area 2. This can also be considered as: first produce the dots for non-printable area 1 for line n, and then a repetition of: 10 e produce the dots for the printable area for line n (from the DNC) produce the dots for the non-printable area 2 (for line n) followed by the dots of non-printable area 1 (for line n+1) The reason for considering the problem this way is that regardless of the shape of the skew, the shape of non printable area 2 merged with the shape of non-printable area I will always be a rectangle since the widths of 15 non-printable areas 1 and 2 are identical and the lengths of each row are identical. Hence step 2 can be accomplished by simply inserting a constant number (NozzleSkewPadding) of 0 dots into the stream. For example, if the color n even row non-printable area 1 is of length X, then the length of color n even row non-printable area 2 will be of length NozzleSkewPadding - X. The split between non-printable areas 1 and 2 is defined by the NozzleSkew registers. 20 Data from the DNC is destined for the printable area only, the DWU must generate the data destined for the non-printable areas, and insert DNC dot data correctly into the dot data stream before writing dot data to the fifos. The DWU inserts the shape of the misalignment into the dot stream by delaying dot data destined to different nozzle rows by the relative misalignment skew amount. 32.6 LoCAL BUFFERING 25 An embedded DRAM is expected to be of the order of 256 bits wide, which results in 27 words per half line of an A4 page, and 39 words per half line of A3. This requires 27 words x 12 half colors (6 colors odd and even) = 324 x 256-bit DRAM accesses over a dotline print time, equating to 6 bits per cycle (equal to DNC generate rate of 6 bits per cycle). Each half color is required to be double buffered, while filling one buffer the other buffer is being written to DRAM. This results in 256 bits x 2 buffers x 12 half colors i.e. 6144 bits in 30 total. With 2x buffering the average and peak DRAM bandwidth requirement is the same and is 6 bits per cycle. Should the DWU fail to get the required DRAM access within the specified time, the DWU will stall the DNC data generation. The DWU will issue the stall in sufficient time for the DNC to respond and still not cause a FIFO overrun. Should the stall persist for a sufficiently long time, the PHI will be starved of data and be 35 unable to deliver data to the printhead in time. The sizing of the dotline store FIFO and internal FIFOs should be chosen so as to prevent such a stall happening.
WO 2005/120835 PCT/AU2004/000706 890 32.7 DOTLINE DATA IN MEMORY The dot data shift register order in the printhead is shown in Figure 261 (the transmit order is the opposite of the shift register order). In the example shown dot 1, dot 3, dot 5,...,dot 33, dot 35 would be transmitted to the printhead in that order. As data is always transmitted to the printhead in increasing order it is beneficial to 5 store the dot lines in increasing order to facilitate easy reading and transfer of data by the LLU and PHI. For each line in the dot store the order is the same (although for odd lines the numbering will be different the order will remain the same). Dot data from the DNC is always received in increasing dot number order. The dot data is bundled into 256-bit words and written in increasing order in DRAM, word 0 first, then word 1, and so on to word N, where N is the number of words in a line. The starting point for the first dot in a DRAM 10 word is configured by the AlignmentOffset register. The dot order in DRAM is shown in Figure 266. The start address for each half color N is specified by the ColorBaseAdr[NJ registers and the end address (actually the end address plus 1) is specified by the ColorBaseAdr[N+1]. Note there are 12 colors in total, 0 to 11, the ColorBaseAdr[12] register specifies the end of the color 11 dot FIFO and not the start of a new dot 15 FIFO. As a result the dot FIFOs must be specified contiguously and increasing in DRAM. As each line is written to the FIFO, the DWU increments the FifoFillLevel register, and as the LLU reads a line from the FIFO the FifoFillLevel register is decremented. The LLU indicates that it has completed reading a line by a high pulse on the lludwu_linerd line. When the number of lines stored in the FIFO is equal to the MaxWriteA head value the DWU will indicate to 20 the DNC that it is no longer able to receive data (i.e. a stall) by deasserting the dwu_dnc_ready signal. The ColorEnable register determines which color planes should be processed, if a plane is turned off, data is ignored for that plane and no DRAM accesses for that plane are generated. 32.8 IMPLEMENTATION 32.8.1Definitions of 1/0 Table 204. DWU VO Definition Clocks and Resets pclk 1 In System Clock prstn 1 In System reset, synchronous active low DNC Interface dwudncready 1 Out Indicates that DWU is ready to accept data from the
DNC.
WO 2005/120835 PCT/AU2004/000706 891 dnc-dwu-avail 1 In Indicates valid data present on dnc._dwLdata. dncdwudata[5:0] 6 In Input bi-level dot data in 6 ink planes. LLU Interface dwu_Ilulinewr 1 Out DWU line write. Indicates that the DWU has completed a full line write. Active high llu_dwulinerd 1 In LLU line read. Indicates that the LLU has completed a line read. Active high. PCU Interface pcudwusel 1 In Block select from the PCU. When pcudwu_sel is high both pcu.adr and pcu dataout are valid. pcurwn 1 In Common read/not-write signal from the PCU. pcu.adr[7:2] 6 In PCU address bus. Only 6 bits are required to decode the address space for this block. pcu.dataout[31:0] 32 In Shared write data bus from the PCU. dwu-pcu-rdy 1 Out Ready signal to the PCU. When dwu.pcu.rdy is high it indicates the last cycle of the access. For a write cycle this means pcu_dataout has been registered by the block and for a read cycle this means the data on dwu-pcu datain is valid. dwu-pcu-datain[31:0] 32 Out Read data bus to the PCU. DIU Interface dwu-diu.wreq 1 Out DWU requests DRAM write. A write request must be accompanied by a valid write address together with valid write data and a write valid. dwudiuwadr[21:5] 17 Out Write address to DIU 17 bits wide (256-bit aligned word) diu dwu wack 1 In Acknowledge from DIU that write request has been accepted and new write address can be placed on dwu diu wadr dwudiu.data[63:0] 64 Out Data from DWU to DIU. 256-bit word transfer over 4 cycles First 64-bits is bits 63:0 of 256 bit word Second 64-bits is bits 127:64 of 256 bit word Third 64-bits is bits 191:128 of 256 bit word Fourth 64-bits is bits 255:192 of 256 bit word dwu_diu_wvalid 1 Out Signal from DWU indicating that data on dwudiudata is valid. 32.8.3 Configuration registers The configuration registers in the DWU are programmed via the PCU interface. Refer to section 23.8.2 on page 439 for a description of the protocol and timing diagrams for reading and writing registers in the DWU. 5 Note that since addresses in SoPEC are byte aligned and the PCU only supports 32-bit register reads and writes, the lower 2 bits of the PCU address bus are not required to decode the address space for the DWU.
WO 2005/120835 PCT/AU2004/000706 892 When reading a register that is less than 32 bits wide zeros are returned on the upper unused bit(s) of dwupcu_data. Table 205 lists the configuration registers in the DWU. Table 205. DWU registers description Control Registers 0x00 Reset 1 Ox1 Active low synchronous reset, self de activating. A write to this register will cause a DWU block reset. Ox04 Go 1 Ox0 Active high bit indicating the DWU is programmed and ready to use. A low to high transition will cause DWU block internal states to reset (configuration registers are not reset). Dot Line Store Configuration Ox08 - Ox38 ColorBaseAdr[12:0][2 13x1 Ox0000 Specifies the base address (in words) 1:5] 7 0 in memory where data from a particular half color (N) will be placed. Also specifies the end address + 1 (256-bit words) in memory where fifo data for a particular half color ends. For color N the start address is ColorBaseAdr[N] and the end address +1 is ColorBaseAdr[N+1] 0x40 ColorEnable 6 Ox3F Indicates whether a particular color is active or not. When inactive no data is written to DRAM for that color. 0 - Color off 1 - Color on One bit per color, bit 0 is Color 0 and so on. Ox44 MaxWriteAhead 8 0x00 Specifies the maximum number of lines that the DWU can be ahead of the LLU Ox48 LineSize 15 Ox0000 Indicates the number of dot-pairs -1 per line produced by the DWU. For example a value of 99 implies a line size of 200 dots ((99+1) * 2). Ox4C NozzleSkewPadding 6 Ox00 Specifies the number of dots the DWU needs to generate to flush the data skew buffers. Corresponds to the non printable area of the printhead plus some padding if required. Must be programmed to greater than or equal to the maximum value in the NozzleSkew registers.
WO 2005/120835 PCT/AU2004/000706 893 0x50 - Ox7C NozzleSkew 12x5 0x00 Specifies the relative skew of dot data nozzle rows in the printhead. Valid range is 0 (no skew) through to 31. Units represent dot-pairs, a skew of 1 for a row represents two dots on the page. Bus 0,1 - Even, Odd line color 0 Bus 2,3 - Even, Odd line color 1 Bus 4,5 - Even, Odd line color 2 Bus 6,7 - Even, Odd line color 3 Bus 8,9 - Even, Odd line color 4 Bus 10,11 - Even, Odd line color 5 0x80 AlignmentOffset 8 Ox00 Specifies the starting bit position in a 256 bit DRAM word for the first dot from even and odd data of all colors Working Registers 0x90 LineDotCnt 16 Ox0000 Indicates the number of remaining dots in the current line. (Read Only) 0x94 FifoFillLevel 8 Ox00 Number of lines in the FIFO, written to but not read. (Read Only) A low to high transition of the Go register causes the internal states of the DWU to be reset. All configuration registers will remain the same. The block indicates the transition to other blocks via the dwugopulse signal. 32.8.4 Data skew 5 The data skew block inserts the shape of the printhead skew into the dot data stream by delaying dot data by the relative nozzle skew amount (given by nozzle_skew). It generates zero fill data introduced into the dot data stream to achieve the relative skew (and also to flush dot data from the delay registers). The data skew block consists of 12 31-bit shift registers, one per color odd and even. The shift registers are in groups of 6, one group for even colors, and one for odd colors. Each time a valid data word is received from 10 the DNC the dot data is shifted into either the odd or even group of shift registers. The oddeven_sel register determines which group of shift registers are valid for that cycle and alternates for each new valid data word. When a valid word is received for a group of shift registers, the shift register is shifted by one location with the new data word shifted into the registers (the top word in the register will be discarded). When the dot counter determines that the data skew block should zero fill (zero fill), the data skew block will 15 shift zero dot data into the shift registers until the line has completed. During this time the DNC will be stalled by the de-assertion of the dwudncready signal. The data skew block selects dot data from the shift registers and passes it to the buffer address generator block. The data bits selected are determined by the configured index values in the NozzleSkew registers. // determine when data is valid 20 data-valid = (((dnc-dwu-avail == 1)OR(zero-fill == 1)) AND (dwu-ready ==l)) // implement the zero fill mux if (zero-fill == 1) then dot-data-in = 0 else 25 dot_data_in = dnc-dwudata WO 2005/120835 PCT/AU2004/000706 894 // the data delay buffers if (dwu-go-pulse ==l) then data-delay[1:0][30:0][5:0] = 0 // reset all delay buffer odd=l, even=0 5 odd even_sel = 0 elsif (data-valid == 1) then { odd-even-sel = -odd even-sel // update the odd/even buffers, with shift data-delay[odd even-sell [30:1] [5:01= data-delay[odd-even sell (29:0) [5:0] 10 // shift data data-delay~oddevensel] [0] [5:0] = dot data in[5:0] IIshift in new data // select the correct output data for (i0O;i<6; i++) 15 // skew selector skew = nozzle-skew[ (i,odd-even_sell I //temporary variable // data select array, include data delay and input dot data data select[31:0] = datadelayodd evenesel[30:0], dot datahin} 20 // mux output the data word to next block (33 to 1 mux) dotdatai) = dataselect(skew(i] 25 32.8.5 Fifo fill level The DWU keeps a running total of the number of lines in the dot store FIFO. Each time the DU writes a line to DRAMv (determined by the DIU interface subblock and signalled via line _wr) it increments the fifilevel and signals the line increment to the LLU (pulse on dwululinewr). Conversely if it receives an active flu -dwu -line -rd pulse from the LLU, the flhlevel is decremented. If the filevel increases to the programmed 30 max level (max/write/ahead) then the DIU interface is stalled and further writes to DRAM are prevented. If the DIU buffers subsequently fill the DWvU will stall the DNC by de-asserting the dwu_dnc ready signal. diudinterfaceostall = (filllevel == max_writeahead) If one or more of the DU buffers fill, the DU interface signals the fill level logic via the bufull signal 35 which in turn causes the DWU to de-assert the dwudnc steady signal to stall the DNC. The bufWull signals will remain active until the DIU services a pending request from the full buffer, reducing the buffer level. When the dot counter block detects that it needs to insert zero fill dots (zero fll equals 1) the DU will stall the DNC while the zero dots are being generated (by de-asserting dw dnc ready, but will allow the data skew block to generate zero fill data (the dwud ready signal). 40 dwu-dnc-ready = ( NOT(buf-full==l OR zero-fill==l) AND dwu-go==l) dwu_ready = NOT(buffull==l) The DWU does not increment the fill level until a complete line of dot data is in DRAM not just a complete line received from the DNC. This ensures that the LLU cannot start reading a partial line from DRAM before the DWU has finished writing the line. 45 The fill level is reset to zero each time a new page is started, on receiving a pulse via the dwugoulse signal.
WO 2005/120835 PCT/AU2004/000706 895 The line fifo fill level can be read by the CPU via the PCU at any time by accessing the FifoFillLevel register. 32.8.6 Buffer address generator 32.8.6.1 Buffer address generator description The buffer address generator subblock is responsible for accepting data from the data skew block and writing 5 it to the DIU buffers in the correct order. The buffer address and active bit-write for a particular dot data write is calculated by the buffer address generator based on the dot count of the current line, programmed sense of the color and the line size. All configuration registers should be programmed while the Go-bit is set to zero, once complete the block can be enabled by setting the Go bit to one. The transition from zero to one will cause the internal states to reset. 10 For the first dot in a half color, the bit 0 of the wr bit bus will be active (in buffer word 0), for the second dot bit 1 is active and so on to the 255t dot where bit 63 is active (in buffer word 3). This is repeated for all 256 bit words until the final word where only a partial number of bits are written before the word is transferred to DRAM. The first dot of line does not have to align to a DRAM word. The alignmentoffset register configures the 15 offset amount of the first dot from the 256-bit DRAM word boundary. 32.8.6.2 Bit-write decode The buffer address generator contains 2 instances of the bit-write decode, one configured for odd dot data the other for even. Each block determines if it is active on this cycle by comparing its configured type with the current dot count address and the dataactive signal. 20 The wr bit bus is a direct decoding of the lower 6 count bits (upcnt[6:J]), and the DIU buffer address is the remaining higher bits of the counter (upcnt[1O: 7]). The signal generation is given as follows: // determine if active, based on instance type wr-en = data active & (up.cnt[0] ^ odd-even-type) // odd =1, even =0 25 // determine the bit write value wr_bit[63:0] = decode(up-cnt[6:1]) // determine the buffer 64-bit address wr_adr[3:0] = up-cnt[10:7) 32.8.6.3 Up counter generator 30 The up counter increments for each new dot and is used to determine the write position of the dot in the DIU buffers for odd and even data. At the end of each line of dot data (as indicated by line_fin), the counter is rounded up to the nearest 256-bit word boundary, and the upcnt[8:I] bits are initialized to the alignment offset (note bit 0 is cleared). This causes the DIU buffers to be flushed to DRAM including any partially filled 256-bit words. The counter is reset to alignment offset if the dwugo_pulse is one. 35 WO 2005/120835 PCT/AU2004/000706 896 // Up-Counter Logic if (dwu-gopulse == 1) then upcnt[10:0] = ("00",alignment-offset[7:0],"O"} // zero filled concatenation 5 elsif (line-fin == 1 ) then // round up (line-fin must be coincident with datavalid) up_cnt[10:9]++ // bit-selector upcnt[8:1]= alignmentoffset[7:0] 10 upcnt[O] = 0 elsif (data-valid == 1) then upcnt[10:0]++ 32.8.6.4 Dot counter 15 The dot counter simply counts each active dot received from the data skew block. It sets the counter to linesize * 2 and decrements each time a valid dot is received. When the count equals zero the line-fin signal is pulsed and the counter is reset to linesize * 2. When the count is less than the nozzle_skew_padding value the dot counter indicates to the data skew block to zero fill the remainder of the line (via the zero fill signal). Note that the nozzleskew_padding units are dots 20 as opposed to dot-pairs as used by the linesize, hence the by 2 multiplication for loading of the dot counter. The counter is reset to linesize * 2 when dwu_go_pulse is 1. 32.8.7 DIU buffer The DIU buffer is a 64 bit x 8 word dual port register array with bit write capability. The buffer could be implemented with flip-flops should it prove more efficient. 25 32.8.8 DIU interface 32.8.8.1 DIU interface general description The DIU interface determines when a buffer needs a data word to be transferred to DRAM. It generates the DRAM address based on the dot line position, the color base address and the other programmed parameters. A write request is made to DRAM and when acknowledged a 256-bit data word is transferred. The interface 30 determines if further words need to be transferred and repeats the transfer process. If the FIFO in DRAM has reached its maximum level, or one of the buffers has temporarily filled, the DWU will stall data generation from the DNC. A similar process is repeated for each line until the end of page is reached. At the end of a page the CPU is required to reset the internal state of the block before the next page can be printed. A low to high transition of 35 the Go register will cause the internal block reset, which causes all registers in the block to reset with the exception of the configuration registers. The transition is indicated to subblocks by a pulse on dwugo_pulse signal.
WO 2005/120835 PCT/AU2004/000706 897 32.8.8.2 Interface controller The interface controller state machine waits in Idle state until an active request is indicated by the read pointer (via the reqactive signal) and the DIU access is not stalled by the fifo fill level block (via the diuinterface stall signal). When an active request is received the machine proceeds to the ColorSelect state 5 to determine which buffers need a data transfer. In the ColorSelect state it cycles through each color and determines if the color is enabled (and consequently the buffer needs servicing), if enabled it jumps to the Request state, otherwise the colorcnt is incremented and the next color is checked. In the Request state the machine issues a write request to the DIU and waits in the Request state until the write request is acknowledged by the DIU (diudwu_wack). Once an acknowledge is received the state machine 10 clocks through 4 cycles transferring 64-bit data words each cycle and incrementing the corresponding buffer read address. After transferring the data to the DIU the machine returns to the ColorSelect state to determine if further buffers need servicing. On the transition the controller indicates to the address generator (adrupdate) to update the address for that selected color. If all colors are transferred (color cnt equal to 6) the state machine returns to Idle, updating the last word 15 flags (groupfin) and request logic (requpdate). The dwu_diu_wvalid signal is a delayed version of the buf rden signal to allow for pipeline delays between data leaving the buffer and being clocked through to the DIU block. The state machine will return from any state to Idle if the reset or the dwugo_pulse is 1. 32.8.8.3 Address generator 20 The address generator block maintains 12 pointers (coloradr[11:0]) to DRAM corresponding to current write address in the dot line store for each half color. When a DRAM transfer occurs the address pointer is used first and then updated for the next transfer for that color. The pointer used is selected by the reqsel bus, and the pointer update is initiated by the adr update signal from the interface controller. For all colors the colorbase_adr specifies the address of the first word of first line of the fifo. 25 For each half colors, the initialization value (i.e. when dwugo_pulse is 1) is the colorbaseadr. For each word that is written to DRAM the pointer compared with the base address for the next color. If they are equal then the pointer set to the base address (colorbaseadr), otherwise it is incremented The address is calculated as follows: 30 if (dwu-go-pulse == 1) then color_adr[11:0] = color baseadr[11:0][21:5] elsif (adr-update == 1) then { // determine the color color = reqsel(3:O} 35 // temp variable tmp-adr = coloradr[color] + 1 if (tmp-adr == color_base_adr[color+1]{21:5]) then // wrap around condition WO 2005/120835 PCT/AU2004/000706 898 coloradr[color] = color-base-adrcolor](21:5] else coloradr[color) = tmpadr } 5 // select the correct address, for this transfer dwudiuwadr = coloradr(reqsel] 32.8.8.4 Read Pointer The read pointer logic maintains the buffer read address pointers. The read pointer is used to determine which 64-bit words to read from the buffer for transfer to DRAM. 10 The read pointer logic compares the read and write pointers of each DIU buffer to determine which buffers require data to be transferred to DRAM, and which buffers are full (the buffull signal). Buffers are grouped into odd and even buffers groups. If an odd buffer requires DRAM access the oddpend signals will be active, if an even buffer requires DRAM access the even-Pend signals will be active. If a group of odd buffers are being serviced and an even buffer becomes pending, the odd group of buffers will be 15 completed before the starting the even group, and vice versa. If both odd and even buffers require DRAM access at exactly the same time, the logic selects the alternative group of buffers to the last serviced group. Between each allocation of DRAM resources to a group of buffers the logic stores the last serviced group in the lastserviced register. If any buffer requires a DRAM transfer, the logic will indicate to the interface controller via the reqactive 20 signal, with the oddevensel signal determining which group of buffers get serviced. The interface controller will check the colorenable signal and issue DRAM transfers for all enabled colors in a group. When the transfers are complete it tells the read pointer logic to update the requests pending via req update signal. The reqsel[3:0] signal tells the address generator which buffer is being serviced, it is constructed from the oddeven sel signal and the color cnt[2:0] bus from the interface controller. When data is being transferred 25 to DRAM the word pointer and read pointer for the corresponding buffer are updated. The reqsel determines which pointer should be incremented. // determine if request is active even if ( wr-adr[0][3:2] != rd-adr[0][3:2] even-pend = 1 30 else even-pend = 0 // determine if request is active odd if ( wr-adr[l][3:2] != rdadr[l](3:2] odd-pend = 1 35 else odd_pend = 0 // determine if any buffer is full if ((wr-adr(0][2:0] == rdadr[O][2:0]) AND (wr adr[l][3] != rdadr(l][3])) then buf-full = 1 40 // fixed servicing order, only update when controller dictates so if (req-update == 1) then { // determine which group to service (based on last serviced) sel = (even-pend, odd-pend, last-serviced) case sel WO 2005/120835 PCT/AU2004/000706 899 000 odd_even_sel=0; req_active=0; lastserviced=0; 001 : odd-evensel=0; reqaactive=0; last-serviced=l; 010 : odd evensel=1; req_active=l; last-serviced=l; 011 odd_evensel=l; reqactive=l; lastserviced=l; 5 100 odd-even-sel=0; reqactive=l; last_serviced=0; 101 odd_evensel=0; reqactive=l; last_serviced=0; 110 odd-even-sel=l; req_active=l; last-serviced=l; 111 : oddevensel=0; req_active=l; last-serviced=0; endcase 10 // selected requestor reqsel(3:0] = {colorcnt[2:0] , oddevensell // concatentation The read address pointer logic consists of 2 2-bit counters and a word select pointer. The pointers are reset when dwugo_pulse is one. The word pointer (word_ptr) is common to all buffers and is used to read out the 15 64-bit words from the DIU buffer. It is incremented when buf rd_en is active. When a group of buffers are updated the state machine increments the read pointer (rd_ptr[oddevensel) via the group fin signal. A concatenation of the read pointer and the word pointer are use to construct the buffer read address. The read pointers are not reset at the end of each line. // determine which pointer to update 20 if (dwu-go-pulse == 1) then rdptr[1:0] = 0 word_ptr = 0 elsif (buf_rden == 1) then word-ptr++ // word pointer update 25 elsif (group-fin == 1) then rd-ptr[oddeven_sel]++ // update the read pointer // create the address from the pointer, and word reader rdadr[odd~evensel] = {rdptr[odd evensell,wordptr) // concatenation The read pointer block determines if the word being read from the DIU buffers is the last word of a line. The 30 buffer address generator indicate the last dot is being written into the buffers via the line_fin signal. When received the logic marks the 256-bit word in the buffers as the last word. When the last word is read from the DIU buffer and transferred to DRAM, the flag for that word is reflected to the address generator. // line end set the flags if (dwu-go-pulse == 1) then 35 lastflag[1:0][1:0] = 0 elsif (line-fin == 1 ) then // determines the current 256-bit word even been written to lastflag[0](wradr[0][2]] = 1 // even group flag // determines the current 256-bit word odd been written to 40 last_flagtl](wr-adr[l][2]] = 1 // odd group flag // last word reflection to address generator lastwd = last_flag[odd evensel ][rdptr[reqgsel] [01] // clear the flag if (group_fin == 1 ) then 45 last_flag(odd-evensel][rd_ptr[re._sel](0]] = 0 When a complete line has been written into the DIU buffers (but has not yet been transferred to DRAM), the buffer address generator block will pulse the linefin signal. The DWU must wait until all enabled buffers are transferred to DRAM before signaling the LLU that a complete line is available in the dot line store 50 (dwu-lluline_wr signal). When the line_fin is received all buffers will require transfer to DRAM. Due to the WO 2005/120835 PCT/AU2004/000706 900 arbitration, the even group will get serviced first then the odd. As a result the line finish pulse to the LLU is generated from the last_flag of the odd group. // must be odd,odd group transfer complete and the last word dwu-llu-line-wr = odd_even-sel AND group_fin AND lastwd 5 33 LINE LOADER UNIT (LLU) 33.1 OVERVIEW The Line Loader Unit (LLU) reads dot data from the line buffers in DRAM and structures the data into even and odd dot channels destined for the same print time. The blocks of dot data are transferred to the PHI and 10 then to the printhead. Figure 273 shows a high level data flow diagram of the LLU in context. 33.2 PHYSICAL REQUIREMENT IMPOSED BY THE PRINTHEAD The DWU re-orders dot data into 12 separate dot data line FIFOs in the DRAM. Each FIFO corresponds to 6 colors of odd and even data. The LLU reads the dot data line FIFOs and sends the data to the printhead interface. The LLU decides when data should be read from the dot data line FIFOs to correspond with the 15 time that the particular nozzle on the printhead is passing the current line. The interaction of the DWU and LLU with the dot line FIFOs compensates for the physical spread of nozzles firing over several lines at once. For further explanation see Section 32 Dotline Writer Unit (DWU) and Section 34 PrintHead Interface (PHI). Figure 274 shows the physical relationship between nozzle rows and the line time the LLU starts reading from the dot line store. 20 A printhead is constructed from printhead segments. One A4 printhead can be constructed from up to 11 printhead segments. A single LLU needs to be capable of driving up to 11 printhead segments, although it may be required to drive less. The LLU will read this data out of FIFOs written by the DWU, one FIFO per half-color. The PHI needs to send data out over 6 data lines, each data line may be connected to up to two segments. 25 When printing A4 portrait, there will be 11 segments. This means five of the data lines will have two segments connected and one will have a single segment connected (any printhead channel could have a single segment connected). In a dual SoPEC system, one of the SoPECs will be connected to 5 segments, while the other is connected to 6 segments. Focusing for a moment on the single SoPEC case, SoPEC maintains a data generation rate of 6 bits per cycle 30 throughout the data calculation path. If all 6 data lines broadcast for the entire duration of a line, then each would need to sustain 1 bit per cycle to match SoPECs internal processing rate. However, since there are 11 segments and 6 data lines, one of the lines has only a single segment attached. This data line receives only half as much data during each print line as the other data lines. So if the broadcast rate on a line is 1 bit per cycle, then we can only output at a sustained rate of 5.5 bits per cycle, thus not matching the internal 35 generation rate. These lines therefore need an output rate of at least 6/5.5 bits per cycle. Due to clock generation limitations in SoPEC the PHI datalines can transport data at 6/5 bits per cycle, slightly faster than required.
WO 2005/120835 PCT/AU2004/000706 901 While the data line bandwidth is slightly more than is needed, the bandwidth needed is still slightly over 1 bit per cycle, and the LLU data generators that prepare data for them must produce data at over 1 bit per cycle. To this end the LLU will target generating data at 2 bits per cycle for each data line. The LLU will have 6 data generators. Each data generator will produce the data for either a single segment, or 5 for 2 segments. In cases where a generator is servicing multiple segments the data for one entire segment is generated first before the next segments data is generated. Each data generator will have a basic data production rate of 2 bits per cycle, as discussed above. The data generators need to cater to variable segment width. The data generators will also need to cater for the full range of printhead designs currently considered plausible. Dot data is generated and sent in increasing order. 10 33.3 PRINTHEAD FLEXIBILITY What has to be dealt with in the LLU is summarized here. The generators need to be able to cope with segments being vertically offset. This could be due to poor placement and assembly techniques, or due to each printhead segment being placed slightly above or below the previous printhead segment. 15 They need to be able to cope with the segments being placed at mild slopes. The slopes being discussed and planned for are of the order of 5-10 lines across the width of the printhead (termed Sloped Step). It is necessary to cope with printhead segments that have a single internal step of 3-10 lines thus avoiding the need for continuous slope. Note the term step is used to denote when the LLU changes the dot line it is reading from in the dot line store. To solve this we will reuse the mild sloping facility, but allow the distance 20 stepped back to be arbitrary, thus it would be several steps of one line in most mild sloping arrangements and one step of several lines in a single step printhead. SoPEC should cope with a broad range of printhead sizes. It is likely that the printheads used will be 1280 dots across. Note this is 640 dots/nozzles per half color. It is also necessary that the LLU be able to cope with a single internal step, where the step position varies per nozzle row within a segment rather than per segment (termed Single Step). 25 The LLU can compensate for either a Sloped Step or Single Step, and must compensate all segments in the printhead with the same manner. 33.3.1 Between segments vertical row skew Due to construction limitations of the linking printhead it is possible that nozzle rows may be misaligned relative to each other. Odd and even rows, and adjacent color rows may be horizontally misaligned by up to 5 30 dot positions relative to each other. Vertical misalignment can also occur between printhead segments used to construct the printhead. The DWU compensates for some horizontal misalignment issues (see Section 32.5), and the LLU compensates for the vertical misalignments and some horizontal misalignment.
WO 2005/120835 PCT/AU2004/000706 902 The vertical skew between printhead segments can be different between any 2 segments. For example the vertical difference between segment A and segment B (Vertical skew AB) and between segment B and segment C (Vertical skew BC) can be different. The LLU compensates for this by maintaining a different set of address pointers for each segment. The 5 segment offset register (SegDRAMOffset) specifies the number of DRAM words offset from the base address for a segment. It specifies the number of DRAM words to be added to the color base address for each segment, and is the same for all odd colors and even colors within that segment. The SegDotOffset specifies the bit position within that DRAM word to start processing dots, there is one register for all even colors and one for all odd colors within that segment. The segment offset is programmed to account for a number of dot 10 lines, and compensates for the printhead segment mis-alignment. For example in the diagram above the segment offset for printhead segment B is Seg Width + (LineLength * 3) in DRAM words. 33.3.2 Vertical skew within a segment Vertical skew within a segment can take the form of either a single step of 3-10 lines, or a mild slope of 5-10 lines across the length of the printhead segment. Both types of vertical skew are compensated for by the LLU 15 using the same mechanism, but with different programming. Within a segment there may be a mild slope that the LLU must compensate for by reading dot data from different parts of the dot store as it produces data for a segment. Every SegSpan number of dot pairs the LLU dot generator must adjust the address pointer by StepOffset. The StepOffset is added to the address pointer but a negative offset can be achieved by setting StepOffset sufficiently large enough to wrap around the dot line 20 store. When a dot generator reaches the end of a segment span and jumps to the new DRAM word specified by the offset, the dot pointer (pointing to the dot within a DRAM word) continues on from the same position it finished. It is possible (and likely) that the span step will not align with a segment edge. The span counter must start at a configured value (ColorSpanStart) to compensate for the mis-alignment of the span step and the segment edge. 25 The programming of the ColorSpanStart, StepOffset and SegSpan can be easily reprogrammed to account for the single step case. All segments in a printhead are compensated using the same ColorSpanStart, StepOffset and SegSpan settings, no parameter can be adjusted on a per segment basis. With each step jump not aligned to a 256-bit word boundary, data within a DRAM word will be discarded. 30 This means that the LLU must have increased DRAM bandwidth to compensate for the bandwidth lost due to data getting discarded. 33.3.3 Color dependent vertical skew within a segment The LLU is also required to compensate for color row dependant vertical step offset. The position of the step offset is different for each color row and but the amount of the offset is the same per color row. Color 35 dependent vertical skew will be the same for all segments in the printhead.
WO 2005/120835 PCT/AU2004/000706 903 The color dependant step compensation mechanism is a variation of the sloped and single step mechanisms described earlier. The step offset position within a printhead segment varies per color row. The step offset position is adjusted by setting the span counter to different start values depending on the color row being processed. The step offset is defined as SegSpan - ColorSpanStart[N where N specifies the color row to 5 process. In the skewed edge sloped step case it is likely the mechansim will be used to compensate for effects of the shape of the edge of the printhead segment. In the skewed edge single step case it is likely the mechansim will be used to compensate for the shape of the edge of the printhead segment and to account for the shape of the internal edge within a segment. 10 33.4 HORIZONTAL MISALIGNMENT BETWEEN ADJACENT SEGMENTS The LLU is required to compensate for horizontal misalignments between printhead segments. Figure 278 shows possible misalignment cases. In order for the LLU to compensate for horizontal misalignment it must deal with 3 main issues - Swap odd/even dots to even/odd nozzle rows (case 2 and 4) 15 e Remove duplicated dots (case 2 and 4) e Read dots on a dot boundary rather than a dot pair In case 2 the second printhead segment is misaligned by one dot. To compensate for the misalignment the LLU must send odd nozzle data to the even nozzle row, and even nozzle data to the odd nozzle row in printhead segment 2. The OddAligned register configures if a printhead segment should have odd/even data 20 swapped, when set the LLU reads even dot data and transmits it to the odd nozzle row (and visa versa). When data is swapped, nozzles in segment 2 will overlap with nozzles in segment 1 (indicated in Figure 278), potentially causing the same dot data to be fired twice to the same position on the paper. To prevent this the LLU provides a mechanism whereby the first dots in a nozzle row in a segment are zeroed or prevented from firing. The SegStartDotRemove register configures the number of starting dots (up to a maximum of 3 dots) in 25 a row that should be removed or zeroed out on a per segment basis. For each segment there are 2 registers one for even nozzle rows and one for odd nozzle rows. Another consequence of nozzle row swapping, is that nozzle row data destined for printhead segment 2 is no longer aligned. Recall that the DWU compensates for a fixed horizontal skew that has no knowledge of odd/even nozzle data swapping. Notice that in Case 2b in Figure 278 that odd dot data destined for the even 30 nozzle row of printhead segment 2 must account for the 3 missing dots between the printhead segments, whereas even dot data destined for the odd nozzle row of printhead segment 2 must account for the 2 duplicate dots at the start of the nozzle row. The LLU allows for this by providing different starting offsets for odd and even nozzles rows and a per segment basis. The SegDRAMOffset and SegDotOffset registers have 12 sets of 2 registers, one set per segment, and within a set one register per odd/even nozzle row. The 35 SegDotOffset register allows specification of dot offsets on a dot boundary.
WO 2005/120835 PCT/AU2004/000706 904 33.5 SUB LINE VERTICAL SKEW COMPENSATION BETWEEN ADJACENT SEGMENTS The LLU (in conjunction with sub-line compensation in printhead segments) is required to compensate for sub-line vertical skew between printhead segments. Figure 279 shows conceptual example cases to illustrate the sub-line compensation problem. 5 Consider a printhead segment with 10 rows each spaced exactly 5 lines apart. The printhead segment takes 100us to fire a complete line, lOus per row. The paper is moving continuously while the segment is firing, so row 0 will fire on line A, row 1 will 1Ous later on Line A + 0.1 of a line, and so on until to row 9 which is fire 90us later on line A + 0.9 of a line (note this assumes the 5 line row spacing is already compensated for). The resultant dot spacing is shown in case IA in Figure 279. 10 If the printhead segment is constructed with a row spacing of 4.9 lines and the LLU compensates for a row spacing of 5 lines, case 1B will result with all nozzle rows firing exactly on top of each other. Row 0 will fire on line A, row 1 will fire 1Ous later and the paper will have moved 0.1 line, but the row separation is 4.9 lines resulting in row 1 firing on line A exactly, (line A + 4.9 lines physical row spacing - 5 lines due to LLU row spacing compensation + 0.1 lines due to 1Ous firing delay = line A). 15 Consider segment 2 that is skewed relative to segment 1 by 0.3 of a line. A normal printhead segment without sub-line adjustment would print similar to case 2A. A printhead segment with sub-line compensation would print similar to case 2B, with dots from all nozzle rows landing on Line A + segment skew (in this case 0.3 of a line). If the firing order of rows is adjusted, so instead of firing rows 0,1,2 ... 9, the order is 3,4,5..8,9,0,1,2, and a 20 printhead with no sub-line compensation is used a pattern similar to case 2C will result. A dot from nozzle row 3 will fire at line A + segment skew, row 4 at line A + segment skew + 0.1 of a line etc. (note that the dots are now almost aligned with segment 1). If a printhead with sub-line compensation is used, a dot from nozzle row 3 will fire on line A, row 4 will fire on line A and so on to row 9, but rows 0,1,2 will fire on line B (as shown in case 2D). 25 The LLU is required to compensate for normal row spacing (in this case spacing of 5 lines), it needs to also compensate on a per row basis for a further line due to sub-line compensation adjustments in the printhead. In case 2D, the firing pattern and resulting dot locations for rows 0,1,2 means that these rows would need to be loaded with data from the following line of a page in order to be printing the correct dot data to the correct position. When the LLU adjustments are applied and a sub-line compensating printhead segment is used a dot 30 pattern as shown in case 2E will result, compensating for the sub-line skew between segment 1 and 2. The LLU is configured to adjust the line spacing on a per row per segment basis by programming the SegColorRowInc registers, one register per segment, and one bit per row. The specific sub-line placement of each row, and subsequent standard firing order is dependant on the design of the printhead in question. However, for any such firing order, a different ordering can be constructed, like 35 in the above sample, that results in sub-line correction. And while in the example above it is the first three rows which required adjustment it might equally be the last three or even three non-contiguous rows that WO 2005/120835 PCT/AU2004/000706 905 require different data than normal when this facility is engaged. To support this flexibly the LLU needs to be able to specify for each segment a set of rows for which the data is loaded from one line further into the page than the default programming for that half-color. 33.6 DOT MARGIN 5 The LLU provides a mechanism for generating left and right margin dot data, for transmission to the printhead. In the margin areas the LLU will generate zero data and will not read data from DRAM for margin dots, saving some DRAM bandwidth. The left margin is specified by the LeftMarginEnd and LeftMarginSegment registers. The LeftMarginEnd specifies the dot position that the left margin ends, and the LefiMarginSegment register specifies which 10 segment the margin ends in. The LeftMarginEnd allows a value up the segment size, but larger margins can be specified by selecting further in segments in the printhead, and disabling interim segments. The right margin is specified by the RightMarginStart and RightMarginSegment registers. The RightMarginStart specifies the dot position that the right margin starts, and the RightMarginSegment register specifies which segment the margin start in. 15 33.7 DOT GENERATE AND TRANSMIT ORDER The LLU contains 6 dot generators, each of which generate data in a fixed but configurable order for easy transmission to the printhead. Each dot generator can produce data for 0,1 or 2 printhead segments, and is required to produce dots at a rate of 2 dots per cycle. The number of printhead segments is configured by the SegConfig register. The SegConfig register is a map of active segments. The dot generators will produce zero 20 data for inactive segments and dot data for active segments. Register 0, bits 5:0 of SegConfig specifies group 0 active segments, and register 1 bits 5:0 specify group 1 active segments (in each case one bit per generator). The number of groups of segments is configured by the MaxSegment register. Group 0 segments are defined as the group of segments that are supplied with data first from each generator (segments 0,2,4,6,8,10), and group 1 segments are supplied with data second from each generator (segments 25 1,3,5,7,9,11). The 6 dot generators transfer data to the PHI together, therefore they must generate the same volume of data regardless of the number of segments each is driving. If a dot generator is configured to drive 1 segment then it must generate zero data for the remaining printhead segment. If MaxSegment is set to 0 then all generators will generate data for one segment only, if it's set to 1 then all 30 generators will produce data for 2 segments. The SegConfig register controls if the data produced is dot data or zero data. For each segment that a generator is configured for, it will produce up to N half colors of data configured by the MaxColor register. The MaxColor register should be set to values less than 12 when GenerateOrder is set to 0 and less then 6 when GenerateOrder is 1.
WO 2005/120835 PCT/AU2004/000706 906 For each color enabled the dot generators will transmit one half color of dot data (possibly even data) first in increasing order, and then one half color of dot data in increasing order (possibly odd data). The number of dots produced for each half color (i.e. an odd or even color) is configured by the Seg Width register. The half color generation order is configured by the OddAligned and GenerateOrder registers. The 5 GenerateOrder register effects all generators together, whereas the OddAligned register configures the generation order on a per segment basis. Table 206 shows the half color generation order and how it's effected by the configuration registers. Table 206. Generator data order OdcdAlignd GneratetaOrder l b r L JL 0 0 0,1,2,3,4,5,6,7,8,9,10,1 1 0 1 0,2,4,6,8,10 1 0 1,0,3,2,5,4,7,6,9,8,11,1 0 1 1 1,3,5,7,9,11 An example transmit order is shown in Figure 281. 10 33.8 LLU START-UP At the start of a page the LLU must wait for the dot line store in DRAM to fill to a configured level (given by FifoReadThreshold) before starting to read dot data. Once the LLU starts processing dot data for a page it must continue until the end of a page, the DWU (and other PEP blocks in the pipeline) must ensure there is always data in the dot line store for the LLU to read, otherwise the LLU will stall, causing the PHI to stall and 15 potentially generate a print error. The FifoReadThreshold should be chosen to allow for data rate mismatches between the DWU write side and the LLU read side of the dot line FIFO. The LLU will not generate any dot data until the FifoReadThreshold level in the dot line FIFO is reached. Once the FifoReadThreshold is reached the LLU begins page processing, the FifoReadThreshold is ignored from then on. 20 33.8.1 Dot line FIFO initialization For each dot line FIFO there are conceptually 12 pointers (one per segment) reading from it, each skewed by a number of dot lines in relation to the other (the skew amount could be positive or negative). Determining the exact number of valid lines in the dot line store is complicated by having several pointers reading from different positions in the FIFO. It is convenient to remove the problem by pre-zeroing the dot line FIFOs 25 effectively removing the need to determine exact data validity. The dot FIFOs can be initialized in a number of ways, including WO 2005/120835 PCT/AU2004/000706 907 * the CPU writing Os, * the LBD/SFU writing a set of 0 lines (16 bits per cycle), e the HCU/DNC/DWU being programmed to produce 0 data 33.9 LLU BANDWIDTH REQUIREMENTS 5 The LLU is required to generate data for feeding to the printhead interface, the rate required is dependent on the printhead construction and on the line rate configured. Each dot generator in the LLU can generate dots at a rate of 2 bits per cycle, this gives a maximum of 12 bits per cycle (for 6 dot generators). The SoPEC data generation pipeline (including the DWU) maintains a data rate of 6 bits per cycle. The PHI can transfer data to each printhead segment at maximum raw rate of 288Mb/s, but allowing for line 10 sync and control word overhead of -2%, and 8b 1 Ob encoding, the effective bandwidth is 225 Mb/s or 1.17 bits per pclk cycle per generator. So a 2 dots per cycle generation rate easily meets the LLU to PHI bandwidth requirements. To keep the PHI fully supplied with data the LLU would need to produce 1.17 x 6 = 7.02 bits per cycle. This assumes that there are 12 segments connected to the PHI. The maximum number of segments the PHI will 15 have connected is 11, so the LLU needs to produce data at the rate of 11/12 of 7.02 or approx 6.43 bits per cycle. This is slightly greater than the front end pipeline rate of 6 bits per cycle. The printhead construction can introduce a gentle slope (or line discontinuities) that is not perfectly 256 bit aligned (the size of a DRAM word), this can cause the LLU to retrieve 256 bits of data from DRAM but only use a small amount of it, the remainder resulting in wasted DRAM bandwidth. The DIU bandwidth allocation 20 to the LLU will need to be increased to compensate for this wasted bandwidth. For example if the LLU only uses on average 128 bits out of every 256 bits retrieved from the DRAM, the LLU bandwidth allocation in the DIU will need to be increased to 2 x 6.43 = 12.86 bits per cycle. It is possible in certain localized cases the LLU will use only I bit out of some DRAM words, but this would be local peak, rather than an average. As a result the LLU has quad buffers to average out local peak 25 bandwidth requirements. Note that while the LLU and PHI could produce data at greater than 6 bits per cycle rate, the DWU can only produce data at 6 bits per cycle rate, therefore a single SoPEC will only be able to sustain an average of 6 bits per cycle over the page print duration (unless there are significant margins for the page). If there are significant margins the LLU can operate at a higher rate than the DWU on average, as the margin data is 30 generated by the LLU and not written by the DWU. 33.10 SPECIFYING DOT FIFOs The start address for each half color N is specified by the ColorBaseAdr[N] registers and the end address (actually the end address plus 1) is specified by the ColorBaseAdr[N+1]. Note there are 12 colors in total, 0 WO 2005/120835 PCT/AU2004/000706 908 to 11, the ColorBaseAdr[12] register specifies the end of the color 11 dot FIFO and not the start of a new dot FIFO. As a result the dot FIFOs must be specified contiguously and increasing in DRAM. 33.11 DOT COUNTER The LLU keeps a dot usage count for each of the color planes (called AccumDotCount). If a dot is used in a 5 particular color plane the corresponding counter is incremented. Each counter is 32 bits wide and saturates if not reset. A write to the InkDotCountSnap register causes the AccumDotCount[N] values to be transferred to the InkDotCount[N registers (where N is 5 to 0, one per color). The AccumDotCount registers are cleared on value transfer. The InkDotCount[N registers can be written to or read from by the CPU at any time. On reset the counters 10 are reset to zero. The dot counter only counts dots that are passed from the LLU through the PHI to the printhead. Any dots generated by direct CPU control of the PHI pins will not be counted. 33.12 IMPLEMENTATION 33.12.2 Definitions of 1/O Table 207. LLU I/O definition Pr name.." Pin 10escritio Clocks and Resets pclk 1 In System clock. prst_n 1 In System reset, synchronous active low. PHI Interface llu-phi-data[5:0][1:0] 6x2 Out Dot Data from LLU to the PHI, each 2-bit data stream is output to its corresponding printhead connection. Data is active when Ilu phi avail is 1. phiIlu-ready 1 In Indicates that PHI is ready to accept data from the LLU. llu_phi-avail 1 Out Indicates valid data present on all //uphi data buses. DIU Interface llu_diu-rreq 1 Out LLU requests DRAM read. A read request must be accompanied by a valid read address. Ilu_diu-radr[21:5] 17 Out Read address to DIU 17 bits wide (256-bit aligned word). diullu_rack 1 In Acknowledge from DIU that read request has been accepted and new read address can be placed on ilu_diu_radr.
WO 2005/120835 PCT/AU2004/000706 909 diu-data[63:0] 64 In Data from DIU to LLU. Each access is 256-bits received over 4 clock cycles First 64-bits is bits 63:0 of 256 bit word Second 64-bits is bits 127:64 of 256 bit word Third 64-bits is bits 191:128 of 256 bit word Fourth 64-bits is bits 255:192 of 256 bit word diullu_rvalid 1 In Signal from DIU telling LLU that valid read data is on the diu data bus. DWU Interface dwu-llu-line-wr 1 In DWU line write. Indicates that the DWU has completed a full line write. Active high. Ilu_dwulinerd 1 Out LLU line read. Indicates that the LLU has completed a line read. Active high. PCU Interface pcullusel 1 In Block select from the PCU. When pcu_lulsel is high both pcuadr and pcu_.dataout are valid. pcurwn 1 In Common read/not-write signal from the PCU. pcu-adr[9:2] 8 In PCU address bus. Only 8 bits are required to decode the address space for this block. pcudataout[31:0] 32 In Shared write data bus from the PCU. Ilu-pcu.rdy 1 Out Ready signal to the PCU. When //u_pcu_rdy is high it indicates the last cycle of the access. For a write cycle this means pcu_dataout has been registered by the block and for a read cycle this means the data on //u_pcu_datain is valid. Ilu-pcu-datain[31:0] 32 Out Read data bus to the PCU. 33.12.3 Configuration registers The configuration registers in the LLU are programmed via the PCU interface. Refer to section 23.8.2 on page 439 for a description of the protocol and timing diagrams for reading and writing registers in the LLU. Note 5 that since addresses in SoPEC are byte aligned and the PCU only supports 32-bit register reads and writes, the lower 2 bits of the PCU address bus are not required to decode the address space for the LLU. When reading a register that is less than 32 bits wide zeros are returned on the upper unused bit(s) of llupcu_datain. Table 208 lists the configuration registers in the LLU. Table 208. LLU registers description Control Registers 0x000 Reset 1 Ox1 Active low synchronous reset, self de activating. A write to this register will cause a LLU block reset.
WO 2005/120835 PCT/AU2004/000706 910 0x004 Go 1 Ox0 Active high bit indicating the LLU is programmed and ready to use. A low to high transition will cause LLU block internal states to reset. Configuration Ox010 - ColorBaseAdr[1 2:0][21: 13x1 xO0 Specifies the base address (in words) in 0x040 5] 7 00 memory where data from a particular half color (N) will be placed. Also specifies the end address + 1 (256 bit words) in memory where FIFO data for a particular half color ends. For color N the start address is ColorBaseAdr[N] and the end address +1 is ColorBaseAdr[N+1] 0x044 MaxColor 4 OxB Indicates the number of half colors+1 per segment to produce data for, must be less than 12. e.g. for printheads with 10 half colors set to 9. Ox048 MaxSegment 1 Ox0 Indicates the number of segment groups that the LLU is required to generate data for. 0 - Generate data for 1 group of segments 1 - Generate data for 2 groups of segments Ox050- SegConfig[1:0] 2x6 Ox00 Specifies the active segments for each 0x054 generator. One register per segment group, one bit per segment. 0 - Segment inactive, generate null data 1 - Segment active, generate data Register 0 indicates the first group of segments transmitted from each generator (group 0), register 1 indicates the second group of segments transmitted from each generator (group 1). Ox058 GenerateOrder 1 Ox0 Specifies the data order that all generators should produce. 0 - Alternating odd/even data 1 - Odd or even data only 0x060- ColorSpanStart[1 1:0] 12x1 xOO Specifies the slope counter start value. OxO8C 3 One register per color, must be programmed to less than SegSpan. Ox090 StepOffset 17 Ox000 StepOffset: Specifies the number of DRAM words to jump when a step offset occurs. Ox094 SegSpan 13 xO0 Specifies the number of half color dots to traverse before adjusting a particular DRAM address pointer by StepOffset. OxOAO- SegColorRowlnc[1 1:0] 12x1 xO0 Specifies if the starting DRAM address of Ox0CC 2 a nozzle row in a segment should be adjusted by adding LineOffset[0]. One register per segment, and one bit per color nozzle row. 0 - DRAM address is not adjusted 1 - DRAM address is adjusted by adding LineOffset[0] WO 2005/120835 PCT/AU2004/000706 911 Ox100- SegDRAMOffset[1 1:0][ 12x2 Ox00 Specifies the number of DRAM words Ox1 5c 1:0] x12 that a segment is offset from the dot line start DRAM word. 12 groups of registers, one group per segment. Each group contains 2 registers, register 0 for even nozzle rows, register 1 for odd nozzle rows. 0x160- SegDotOffset[ 1:0][1:0 12x2 OxOO Specifies the start dot index within the Ox1 Bc ] x8 first DRAM word of a color per segment. 12 groups of registers, one group per segment. Each group contains 2 registers, register 0 for even nozzle rows, register 1 for odd nozzle rows. Ox200- SegStartDotRemove[1 12x2 OxO Specifies the number of dots to remove at 0x25C 1:0][1:0] x2 the start of a segment row. 12 groups of registers, one group per segment. Each group contains 2 registers, register 0 for even nozzle rows, register 1 for odd nozzle rows. Ox260 OddAligned 12 OxOO Specifies if the printhead segment is aligned correctly. One bit per segment. 0 - Odd dot data into odd nozzle rows 1 - Odd dot data into even nozzle rows Note the generate order is affected by the odd alignment. Bits 5:0 control group 0 segments, bits 11:6 control group 1 segments. Ox264 LeftMarginEnd 14 Ox0 Specifies the left margin end dot position. Ox268 LeftMarginSegment 4 Ox0 Left margin segment. Specifies the printhead segment the left margin ends in. Ox26C RightMarginStart 14 Ox0 Specifies the right margin start dot position. Ox270 RightMarginSegment 4 Ox0 Right margin segment. Specifies the printhead segment the right margin starts in. Ox274 SegWidth[1 2:3] 10 OxOO Specifies the number of half color dots per printhead segment (must be set to a multiple of 8). Ox280- CurrColorAdr[ 1:0][21: 12x1 OxOO Current working address associated with Ox2DC 5] 7 00 each color. (Working Register) Ox2EO LineOffset[2:0] 3x1 7 Ox000 Specifies the address offset for the 00 ColorBaseAdr per line. The RedundancyEnable specifies which registers are used per color. Specified in DRAM words. Reg 0 - Used when color redundancy is disabled Reg1,2 - Used when color redundancy is enabled 0x2E4 RedundancyEnable 6 OxOO Redundancy enable. One bit per color. When 0 LineOffset[] is used to determine the next line address. When 1 LineOffset[1:0] are used to determine the next alternating line address. For example LineOffset[0] is used of even linae and4 I inafnffcatIil i icar for n^rlr WO 2005/120835 PCT/AU2004/000706 912 lines. Ox300- InkDotCount[5:0] 6x32 Ox000 Indicates the number of Dots used for a 0x314 0_000 particular color, where N specifies a color 0 from 0 to 5. Value valid after a write access to InkDotCountSnap 0x320 InkDotCountSnap 1 Ox0 Write access causes the AccumDotCount values to be transferred to the InkDotCount registers. The AccumDotCount are reset afterwards. (Reads as zero) 0x324 FifoReadThreshold 8 Ox00 Specifies the number of lines that should be in the FIFO before the LLU starts reading. Debug Registers 0x328 FifoFillLevel 8 0x00 Number of lines in the dot line FIFO, lines written in but not read out. (Read Only) 0x340- AccumDotCount[5:0] 6x32 0x000 Current running count of ink dots used. Ox354 00000 One register per color. (Read Only) A low to high transition of the Go register causes the internal states of the LLU to be reset. All configuration registers will remain the same. The block indicates the transition to other blocks via the llu go_pulse signal. 33.12.4 Common counter 5 The dot generation logic consists of 2 parts, a common counter block and 6 individual dot generators. The dot generators read data for the same color and same segment from each buffer together, and determine when to supply a dot collectively. This logic is implemented in the common counters area. The common counter block maintains a color count (color cnt) and a segment group count (segcnt) that are used by each of the dot generators to determine the data generation order. Each dot generator operates 10 independently when producing data for a particular color nozzle row. When a dot generator has completed a color nozzle row it signals to the common block the row is complete (colorjfin) and waits for the common block to determine that all dot generators have completed a color row. Once all are complete the common block updates the color and segment counters and signals to the dot generator to start the next row (next-color). This is repeated until data for all color rows and segments have been generated. 15 The common counter block passes the segment count (segcnt) to each dot generator to allow the dot generator to calculate which segment number they are processing data for. It also determines when the line is complete (line fin) and signals to the FIFO fill level block to increment the line level (which in turn is used to signal the DWU that a complete line was read from the DIU buffers). The generateorder value is also used within the dot generators to determine the data generation order. 20 WO 2005/120835 PCT/AU2004/000706 913 // general decode // trigger the next color when all.are finished nextcolor = (color-fin[5:0] == Ox3F) seg-fin = nextcolor AND (colorcnt == maxcolor) 5 line-fin = seg-fin AND (segcnt == maxsegment) // advance all the counters for each new 2 dots if (llugo-pulse == 1) then colorcnt = 0 10 seg-cnt = 0 elsif (line-fin == 1) then color-cnt = 0 seg-cnt = 0 elsif (seg-fin == 1) then 15 colorcnt = 0 seg-cnt ++ elsif (nextcolor == 1) then color_cnt = colorcnt + 1 20 The common counter block also passes the color count value to the Dot Counter block to allow the dot counter to correctly count active dots for each color plane. 33.12.5 Dot generator In the LLU there are 6 instances of the dot generator, each independently reading data from the DIU buffer for transfer out on a single data channel in the PHI. The dot generator determines the dot generation order, a dots 25 position in a line and in left and right margins. The dot generator determines when data can be read from a DIU buffer and written to the output buffer for sending to the PHI. It waits for the llu en from the fifo fill level block, for data in the DIU buffers (buf emp) and that the output buffer is not full data (ffo_full) before enabling a dot producing cycle (dot-active). The dot generator normally produces 2 dots per cycle, but under certain conditions only one dot may be produced 30 in a cycle. The output buffer smooths the irregular dot production rates between dot generators. Each dot generator maintains a dot count (dot cnt), a slope counter (slopecnt), an index (dot-index) and a read pointer (readadr). The dot count is used to determine when a color nozzle row is complete and for comparison with the left and right margin configuration values to evaluate when a dot is in the margin area and should be zeroed out. 35 The dot index points to the current data bit within the current DIU buffer word (as selected by read pointer). It is used to determine when the read pointer should be incremented. The dot index is initialized to a segdot.offset register value at the start of each new nozzle row. The value used is dependant on the oddness of the nozzle row and the segment the dot generator is producing data for. The dot index is updated as each dot is produced, and is used to index into each 64-bit DIU buffer word to select data to write to the output 40 buffer. When the index count is Ox3F, the counter wraps to 0 and causes a read pointer increment. The read pointer indicates the DIU buffer word to read. The read pointer is normally incremented on an even dot boundary. If a condition happens to cause a read pointer increment on an odd dot boundary then the dot generator must write only one dot to the output buffer and wait until the next clock cycle to read the next dot WO 2005/120835 PCT/AU2004/000706 914 from the new DIU buffer word (a stall condition). When this condition happens the dot generator only produces one dot per cycle (for the current and next cycle) as opposed to the normal 2 dots per cycle. The slope counter tracks the position of nozzle row discontinuities and determines when the dot generator should increment the DIU buffer read pointer to read the next 256 bit word from the buffer. The slope counter 5 is initialized to a colorspan start[N] register value at the start of each new nozzle row N. The value chosen is dependant on the current color row that data is being generated for. The slope counter is incremented as each dot is processed, and when equal to the segspan the read pointer is incremented and the slope counter is reset to 0. The dot generator compares the dot count with the configured left and right margin values and calculates 10 when a generator is processing data for a segment within the margin areas. When in the margin areas it clears the dot data before writing to the output buffer. A similar mechanism is used to remove segment starting dots. // segment number, derived from segment count seg-sel = DOT_GENERATOR_INDEX + (seg-cnt * 2) // segment number 15 right-margin-en = (seg-sel == right-margin-segment) I/ select margin segment leftmargin-en = (seg-sel == left_marginsegment) dot-active = llu-en AND NOT(fifo-full) AND NOT(buf-emp) // dot generator advance color-fin = (dot-cnt == seg-width) // color is finished // advance all the counters each cycle 20 if (llu-go-pulse == 1) then slopecnt = colorspanstart[colorsel] dot-index = segdot_offset[segsel] [oddsel] read_adr = 0 stall = 0 25 elsif (dot-active == 1) then // pointer updates if (nextcolor == 1) then slope-cnt = colorspanstart[colorsel] readadr ++ 30 dotindex = segdotoffset(seg-sel] (oddsel] dot-cnt = 0 stall = 0 else for (n=stall; n<2; n ++) { // loop per dot 35 stall = 0 /clear the stall flag if (color-fin == 0) then // regular dot increase) if ((slope_cnt == segspan) then slope-cnt = 0 if (dot_index == Oxff AND read adr[1:0] = 11) then 40 read_adr = read_adr + 1 // 64bit word inc(also new 256bit word) stall = NOT(n) // only stall if processing dot 0 elsif(dotindex == Oxff) then 45 readadr = reaaadr + 5 // 256bit word and 64bit word increment stall = NOT(n) // only stall if processing dot 0 else 50 read_adr = read_adr + 4 // 256bit word increment WO 2005/120835 PCT/AU2004/000706 915 stall = NOT(n) // only stall if processing dot 0 dotindex ++ else 5 slope-cnt++ // check the index if (dot-index == Oxff) then // wrap around condition read adr ++ stall = NOT(n) // only stall if processing 10 dot 0 dotindex ++ // always increment the dot count dot cnt ++ gen-wr_en[n] = 1 // write enable 15 // determine the data bit(s) to write to the output buffer if ((dotcnt <= seg-start-dot-remove(segsel] [odd-sel}) OR (right-margin-en == 1 AND dot-cnt > rightmarginstart) OR (left-margin en == 1 AND dot-cnt < left marginend)) then gen_wr-data[n} = 0 20 else genwr data[n] = rd_data[dotindex] The dot generator also determines the data generation order based on the OddAligned and GenerateOrder 25 configuration registers. When the generateorder bit is 0, each dot generator produces MaxColor nozzle rows of data (value must be less than 12). The dot generator can produce either odd followed by even data or vice versa. The odd_aligned bit for the current segment configures the order. When the generateorder bit is 1, each dot generator produces MaxColor (value must be less than 6) nozzle 30 rows of data (value must be less than 6), either odd or even rows are produced as configured by the oddaligned bit for the current segment the dot generator is producing data for. // derive the color_sel from the color counter select ordersel = {generate-order,odd-aligned[segsel]} 35 case ordersel 00: color sel = color-cnt(3:0] 01: color-sel = color cnt[3:1] ,NOT(color-cnt(0]) 10: colorsel = color cnt[2:0},0 11: color_sel = colorcnt[2:0],1 40 endcase // select between odd/even control odd~sel = colorsel[0] 33.12.6 Output buffer 45 The output buffer accepts data (either 1 or 2 bits per clock cycle) from each of the dot generators and aligns the data into 12-bit data words for transfer to the PHI. The dot generators don't produce dots at a constant rate, frequently the dot generator will produce only 1 dot per cycle depending on the offset values for the WO 2005/120835 PCT/AU2004/000706 916 printhead segment it's driving. The output buffer smooths the different generation rates of the dot generators, to allow an almost constant transfer rate to the PHI. The output buffer consists of 6 FIFOs each with 8 bits storage. There are 6 independent write pointers (wr_ptr) and one read pointer (rd_ptr). The read and write pointers are compared to determine if data is 5 available for the transfer (fifo empty) to the PHI and if there is room left in the FIFOs (fifofull). The write pointer is incremented every time a dot is written to the output buffer. // update the write pointers and data for(i=0; i<6; i++) { // loop per generators 10 for(n=0; n<2; n++){ // loop per write bit if (gen-wr-en(i][n] == 1) then fifo-data[i] [wradr[i]] = genwr-data[n] wradr[i) ++ } 15 // calculate the fifo full/empty flags for(i=0; i<6; i++) { // loop per generators // fifo full (needs to allow for 2 dots each cycle) if (wradr[i][2:0] == rdadr[2:0]) AND (wr adr[i][3] != rdadr[3]) then 20 fifofull[i] = 1 else fifofull[i] = 0 // fifo empty if (wradr[i][3:0] == rd-adr[3:0])then 25 fifo_empty[i] = I else fifo_empty[i] = 0 } // implement the read side logic 30 if (lluen == 1 AND fifoempty[5:0] == 0x00 AND phi-llu-rdy == 1) then lluphi-avail = 1 lluphidata[5:0] [1:0] = fifodata[5:0] [rdadr+l:rd_adr] rdadr = rdadr + 2 33.12.7 Fifo fill level 35 The LLU keeps a running total of the number of lines in the dot line store FIFO. Every time the DWU signals a line end (dwu-llu_line wr active pulse) it increments the fillevel. Conversely if the LLU detects a line end linenn pulse) the flllevel is decremented and the line read is signalled to the DWU via the llu dwu line rd signal. The LLU fill level block is used to determine when the dot line has enough data stored before the LLU should 40 begin to start reading. The LLU at page start is disabled. It waits for the DWU to write lines to the dot line FIFO, and for the fill level to increase. The LLU remains disabled until the fill level has reached the programmed threshold (fiforead thres). When the threshold is reached it signals the LLU to start processing the page by setting lluen high. Once the LLU has started processing dot data for a page it will not stop if the fillevel falls below the threshold, but will stall iffilievel falls to zero.
WO 2005/120835 PCT/AU2004/000706 917 The line FIFO fill level can be read by the CPU via the PCU at any time by accessing the FifoFillLevel register. The CPU must toggle the Go register in the LLU for the block to be correctly initialized at page start and the FIFO level reset to zero. 5 if (llu-go-pulse == 1) then filllevel = 0 elsif ((line-fin == 1) AND (dwu-lluline-wr == 1)) then // do nothing elsif (line-fin == 1) then 10 fillievel elsif (dwu-llu-line_wr == 1) then filllevel ++ // determine the threshold, and set the LLU going if (llu-go-pulse == 1) 15 llu_enff = 0 elsif (filllevel == fifo-read_threshold) then lluen_ff = 1 // filter the enable base do the fill level llu_en = llu-en_ff AND NOT (filllevel == 0) 20 33.12.8 DIU interface The DIU interface block is responsible for determining when dot data needs to be read from DRAM. It keeps the dot generators supplied with data and calculates the DRAM read address based on configured parameters, FIFO fill levels and position in a line. The fill level block enables DIU requests by activating the llu en signal. The DIU interface controller then 25 issues requests to the DIU for the LLU buffers to be filled with dot line data (or fill the LLU buffers with null data without requesting DRAM access, if required). The DIU interface determines which buffers should be filled with null data and which should request DRAM access. New requests are issued until the dot line is completely read from DRAM, at this point it re-initializes the address pointers and counters, and starts processing the next line. The DIU interface once enabled always 30 tries to keep the DIU buffers full. For each request to the DRAM the address generator calculates where in the DRAM the dot data should be read from. The MaxColor register determines how many half colors are enabled, and the SegConfig register indicates if a segment is enabled, the interface never issues DRAM requests for disabled colors or segments. 33.12.8.1 Interface controller 35 The interface controller co-ordinates and issues requests for data transfers, either from DRAM or null data transfers. It maintains 2 counters, the color count (color cnt) to keep track of the current half color being operated on and the segment pass count (segcnt), to indicate if each generator is transmitting to the first or second group of segments connected to that generator. The state machine operates on a per line basis and once enabled it transfers data for MaxColor number of half colors, and MaxSegment number of segments. If a 40 generator is configured for less than MaxSegment number of segments then null data is generated to fill the WO 2005/120835 PCT/AU2004/000706 918 buffer. Note that when null data is generated the address pointers are updated the same, even though data isn't being read from DRAM. The state machine waits in the Idle state until it is enabled by the LLU controller (llu en). On transition to the GenSelect state it clears all counters and initializes the pointers in the address generator via the init_ptr signal. 5 In the GenState it tests if a buffer is full and if data is required for each generator. It selects the generator to service and then decides if a null or real data transfer is required (based on the SegConfig setting or if the segment is in the left or right margin area). If the request is null it transitions to the NullRequest state pulsing the null update signal indicating to the pointer logic to generate a null data transfer. It waits in the NuliRequest state for the write pointer block to complete the writing of null data into the buffer and once 10 complete it pulses the nullcomplete signal indicating the transfer is complete and the interface controller can continue. If the request is a real data transfer, it transitions to the Request state, issues a request to the DIU and waits for an acknowledge back from the DIU. 15 GENSELECT: for(i=O; i< 6; i++) // determine the next generator to get data for index = (lastwin + i) mod 6 // check the buffer, its configuration, and if it's the last word 20 if (buf-full[index] == 0 AND last_word[index] == 0) gensel = index lastwin = index } // picked the generator winner, determine if null transfer needed 25 if(segconfigtsegcnt](gensel]==O OR in-rightmargin==1 OR in-left_margin==l) then NULLREQUEST // issue a null request else REQUEST // do a regular request 30 When an acknowledge (or null complete) is received the state machine goes to the CntUpdate state to update the internal counters and signal to the address generator to update its address pointers. The CntUpdate state checks the last-word signals from the address generator to determine if all words for all enabled generators have been read from DRAM, and if so it re-initializes the pointers in the address generator to the start of the 35 next color. If all generators are on their last word and the color cnt is equal to max-color, and segment counter is at the maximum the state machine jumps to the Idle state triggering the line update to the current color pointers in the address generator (via the line_fin signal). CNT_UPDATE: 40 // compare all active generators, all colors complete if (last_word == Ox3F) then colorfin= 1 init-ptr = 1 // re -initialize the pointers next_state = GEN_SELECT 45 if (colorcnt == max_color) then color_cnt = 0 if (segcnt == maxsegment) then // line is finished WO 2005/120835 PCT/AU2004/000706 919 seg-cnt = 0 line-fin = 1 nextstate = IDLE else 5 seg-cnt ++ else // increment the color count colorcnt = colorcnt + 1 } 10 else colorfin= 0 In addition to the basic state machine functionality the interface controller also contains logic to select the correct segment and color configuration registers. 15 // segment select, derived from generator select if (segcnt == 0) then segsel = gensel * 2 else 20 seg-sel = (gen-sel * 2) + I // derive the colorsel from the color counter select, and generate order ordersel = {generateorder,oddaligned[segsel]} case ordersel 00: color-sel = color-cnt[3:0] 25 01: colorsel = colorcnt[3:1],NOT(colorcnt[0]) 10: color_sel = color-cnt(2:0],0 11: colorsel = colorcnt(2:01,1 endcase 33.12.8.2 Address generator 30 The address generator logic determines the correct read address to read data from DRAM for the LLU. The address generator takes into account the segment size, segment slope and segment offset to determine the correct stream of DRAM words to be written into the buffers to allow the dot generators to create the correct dot stream to the PHI. Address update logic 35 When a complete line of data has been read from DRAM and placed into the buffers the interface controller will signal to the address generator (via the line fin signal) to update the CurrColorAdr pointers. The CurrColorAdr pointers indicate the start address of each half color in the dot store. The CurrColorAdr pointers can be written to by the CPU, and are programmed with the relative line offsets (converted into DRAM addresses) of each half color at startup. 40 When a line is completed the LLU address pointers are updated by an offset amount. The offset amount depends on the LineOffset[2:0 registers and the RedundancyEnable register. The LLU checks the RedundancyEnable for each color, and then selects the LineOffset value. If redundancy is not enabled the offset for that color will be LineOffset[O]. If redundancy is enabled then the offset will be either LineOffset[2] WO 2005/120835 PCT/AU2004/000706 920 (even lines) or LineOffset[1] (odd lines) depending on the state of the line_ptr. The lineptr selects between alternating offsets for redundancy enabled colors. For each new line, the address generator updates the odd/even line offset select (line_ptr) and then updates the CurrColorAdr pointers, one per clock cycle. Each time it updates a pointer it checks the defined FIFO 5 boundaries for that half color (ColorBaseAdr) and performs wrapping if needed. if (linefin == 1) then // toggle the line offset select line-ptr = NOT(lineptr) // start address update process (12 cycles) 10 for (i=O;i<12;i++) { // select what to update with if (redundancyenable[i/2] == 1) then if (line-ptr == 1) then offset = lineoffset[2] // even lines 15 else offset = line-offset[l] // odd lines else offset = line-offset[0] // assign temporary variables 20 nextadr = currcolor_adr~i] + offset start-adr = colorbaseadr[i] endadr = colorbaseadr[i+l] // check the wrapping if (next-adr > start-adr) then // wrap case 25 curr_color_adr[i] = nextadr - start_adr else currcoloradr(i] = nextadr 30 Segment pointer logic In order to determine the correct address to read from DRAM the address generator maintains a segment span counter, a segment address and a word counter for each dot generator. The word counter (word cnt) counts the number of DRAM words received per half color, and is an indication of the dot position rounded to the nearest DRAM word boundary. It is compared with SegWidth, RightMarginStart and LeftMarginEnd to 35 determine the last word of a color, the right margin and the left margin boundaries respectively. The span counter determines when the read address needs to be adjusted by the StepOffset to compensate for the segment slope. The segment address pointer maintains the current address in DRAM that the next access for that generator will read from. The pointers are initialized before a group of DRAM words for one color is read from DRAM. The interface 40 controller signals the initialization before any DRAM access, setting init_ptr signal high. The word count (word cnt) for generator gensel is set to 0, the span counter (span cnt) for generator gen sel is set to ColorSpanStart selected by the color select (color sel). The address pointer (segadr) for generator segsel is initialized to the color base address pointer for color sel plus the segment offset address SegDRAMOffset selected by the current segment being processed (segsel) plus LineOffset[O] if configured by the WO 2005/120835 PCT/AU2004/000706 921 SegColorRowInc registers. The segment select (segsel), generator select (gensel) and color select (color set) have direct mapping to each other and are determined by the interface controller. Each time the interface controller needs to read data from DRAM it uses the address first and then updates the pointer. It signals the pointer update by setting adrupdate high and indicates the pointer to update with the 5 gensel signal. Every time the interface controller signals an address update the word counter is incremented, and the span counter is updated and compared to determine if the address pointer needs to 'jump by the address offset amount. There are 2 possible span offset cases. If the span counter is greater than or equal to the segment span (SegSpan) and not aligned on 256 bit boundary then the address pointer is incremented by the offset 10 (StepOffset). If it is aligned and is equal to SegSpan then address pointer is incremented by the offset + 1. The span counter is updated to the current value - SegSpan. In all cases when the address pointers are being updated the new value is compared with the FIFO boundaries, and wraps to take the FIFO boundaries into account. The pseudocode is as follows: 15 // calculate the span counter, determine what to do with adr pointer span_tmp = spancnt + 256 color-step-tmp = colorstep[colorsel] oddsel = color-sel(0] // indicates if we're calculating for an odd or even row 20 if (init-ptr == 1) // start condition for spancnt[gen-sel] = colorspanstart(colorsel] // per color per segment adjust if (seg-colorrowinc[segsel](colorsell == 1) then next-adr = coloradr[colorsel] + 25 seg-dram-offset[seg-sel][odd-sel] + line_offset[O] else nextadr = coloradr[colorsel] + seg_dram_offset[segsel][odd-sel] word~cnt[gensel] = 0 30 elsif (adr-update == 1) then wordcnt(gen-sel} = wordcnt[gensel] + 1 if (span-tmp == seqaspan) AND (span_tmp(7:0] == 0)then // span offset jump + inc reqd spancnt[gensel] = 0 35 next-adr = segadr[gensel] + step-offset + 1 elsif (span-tmp > seqspan)then // span offset jump required spancnt[gensel] = spantmp - seqspan next-adr = segadr[gen-sel) + step-offset 40 else spancnt[gensel] = spantmp nextadr = seg-adr[gen-sel} + 1 // perform FIFO boundary wrapping 45 start-adr = colorbaseadr[colorsel] end_adr = color_base_adr[color-sel + 1] // check the wrapping if (next_adr > startadr) then // wrap case seg-adr[segsel] = nextadr - start_adr WO 2005/120835 PCT/AU2004/000706 922 else seg-adr[segsel] = next-adr Output decode logic The output decode logic indicates to the interface controller when a generator is creating dot data within the 5 margin areas for a segment and that dot data for that nozzle row has completed. oddsel = color-sel[0] // indicates if we're calculating for an odd or even row if (adrupdate == 1) then // detect last word to tell state machine (depends on generator selected) 10 dot_cat = {(word-cnt[gen-sell + 1), (256 seg-dot-offset(seg-sel][oddsel][7:0])} if (dotcnt > segwidth) then lastword = 1 else 15 last-word = 0 // calculate the margin info (right) if (seg-sel == right marginsegment) AND (dot-cnt > right margin-start) then inright-margin = 1 20 else inright margin = 0 // calculate the margin info (left) if (segsel == leftmarginsegment) AND (dotcnt < left_margin-end) then inleftmargin = 1 25 else in-left_margin = 0 33.12.8.3 Write pointer The write pointer logic maintains the buffer write address pointers, determines when the DIU buffers need a data transfer and signals when the DIU buffers are empty. The write pointers determine the address in the 30 DIU buffers that the data should be transferred to. The write pointer logic compares the read and write pointers of each DIU buffer to determine which buffers require data to be transferred from DRAM, which buffers are empty (the buf emp signal) and which buffer are full (bufjfull signals). The write pointer logic performs 2 types of write, either a real data write or a null write. A null write fills the 35 buffer with zero data and does not involve a DRAM access. The interface controller indicates a real write with the adrupdate signal and a null write with the null update signal. In the case of a real write, the adrupdate signal is pulsed and the state machine transitions from Idle to Wait state storing the gensel in gen selff This allows the interface controller to begin requesting data for the next dot generator buffer before data for the current buffer has been received. When data arrives the state machine 40 transitions through DataO, Datal, Data2 and to Data3 each time writing a 64-bit word into the buffer selected by genselff WO 2005/120835 PCT/AU2004/000706 923 It is possible (although unlikely) that back to back data transfers could be received from DRAM. If the state machine detects new data access as it is finishing the previous access it updates the gen selff register, transitions back to the DataO state and continues as normal. If the state machine receives a nullupdate signal from the interface controller it stores the selected generator 5 as before and automatically writes 4 zero data words to the selected buffer. The write address pointer logic consists of 6 3-bit counters and a data valid state machine. The counters are reset when llugojulse is one. The write pointers also calculate the buffer full and empty signals. The read and write pointers for each buffer are compared to determine the fill levels. The buffer empty is ORed together before passing to the dot 10 generators. // generate the read buffer full/empty logic for (i=O i< 6; i+=){ // buffer empty if (read-adr[i] == wradr[i]) then 15 bufempfi] = 1; else bufemp[i] = 0; // buffer full if (readadr[i][4] wradr[i][2]) AND 20 readadr[i][3:2] == wr-adr[i][1:0]) buf_full(i] = 1 else buffull[i] = 1 } 25 The write address for each buffer is derived from the pointer for the buffer (wradr[gensel_ffl) and the adrsel signal decoded from the state machine. 33.12.9 Dot counter The dot counter keeps a running count of the number of dots fired for each color plane. The counters are 32 bits wide and saturate. When the CPU wants to read the dot count for a particular color plane it must write to 30 the InkDotCountSnap register. This causes all 6 running counter values to be transferred to the InkDotCount registers in the configuration registers block. The running counter values are then reset. // reset if being snapped if (ink-dotcount_snap == 1) then{ ink dotcount(5:0] = accumdotcount[5:0] 35 accumdotcount[5:0] = 0 // update the counts if (llu-en == 1) then color = colorsel / 2 // half color to normal color 40 for (x=0; x<6; x++) { for (y=0; y<l; y++) { // saturate the counter if (accum-dot.count[color] != Oxfff fffff) AND (llu-phi-data[x] [y] == 1) then 45 accumdot-count [color] ++
}
WO 2005/120835 PCT/AU2004/000706 924 34 PRINTHEAD INTERFACE (PHI) 34.1 OVERVIEW 5 The Printhead interface (PHI) accepts dot data from the LLU and transmits the dot data to the printhead, using the printhead interface mechanism. The PHI generates the control and timing signals necessary to load and drive the printhead. A printhead is constructed from a number of printhead segments. The PHI has 6 transmission lines (printhead channel), each line is capable of driving up to 2 printhead segments, allowing a single PHI to drive up to 12 printhead segments. The PHI is capable of driving any combination of 0,1 or 2 10 segments on any printhead channel. The PHI generates control information for transmission to each printhead segment. The control information can be generated automatically by the PHI based on configured values, or can be constructed by the the CPU for the PHI to insert into the data stream. 34.2 PHYSICAL LAYER 15 The PHI transmits data to printhead segments at a rate of 288Mhz, over 6 LVDS data lines synchronous to 2 clocks. Both clocks are in phase with each other. In order to assist sampling of data in the printhead segments, each data line is encoded with 8b Ob encoding, to minimize the maximum number of bits without a transition. Each data line requires a continuous stream of symbols, if a data line has no data to send it must insert IDLE symbols to enable the receiving printhead to remain synchronized. The data is also scrambled to reduce EMI 20 effects due to long sequences of identical data sent to the printhead segment (i.e. IDLE symbols between lines). The descrambler also has the added benefit in the receiver of increasing the chance single bit errors will be seen multiple times. The 28-bit scrambler is self-synchronizing with a feedback polynomial of 1 + X" + x2 34.3 CONTROL COMMANDS 25 The PHI needs to send control commands to each printhead segment as part of the normal line and page download to each printhead segment. The control commands indicate line position, color row information, fire period, line sync pulses etc. to the printhead segments. A control command consists of one control symbol, followed by 0 or more data or control symbols. A data or control symbol is defined as a 9-bit unencoded word. A data symbol has bit 8 set to 0, the remaining 8 bits 30 represent the data character. A control symbol has bit 8 set to 1, with the 8 remaining bits set to a limited set of other values to complete the 8b10b code set (see Table 213 for control character definitions). Table 209 lists the configurable control commands that are generated internally by the PHI for data transfer to the printhead.
WO 2005/120835 PCT/AU2004/000706 925 Table 209. Command configuration definition Cfg RC* Comand Desc**rition ...... .. ' I .z L. ldleCmdCfg IDLE IDLE Idle symbols are ignored by the printhead segments. Note /dleCmdCfg configures the Idle symbol value directly. CmdCfg[O] RESA RESUMEA Resume line data transfer, printhead segment group A (segments 0,2,4,6,8,10) CmdCfg[1] RESB RESUMEB Resume line data transfer, printhead segment group B (segments 1,3,5,7,9,11) CmdCfg[2] NCA NEXTCOLORA Increment the nozzle row for the last active printhead segments CmdCfg[3] NCB NEXTCOLORB Increment the nozzle row for the last active printhead segments CmdCfg[4] FIRE FIRE Line Sync and FIRE command to all printhead segments Each command is defined by CmdCfg[CMD NAME] register. The command configuration register configures 2 pointers into a symbol array (currently the symbol array is 32 words, but could be extended). Bits 4:0 of the command configuration register indicate the start symbol, and bits 9:5 indicate the end symbol. Bit 5 10 is the empty string bit and is used to indicate that the command is empty, when set the command is ignored and no symbols are sent. When a command is transmitted to a printhead segment, the symbol pointed to by the start pointer is send first, then the start pointer + 1 etc. and all symbols to the end symbol pointer. If the end symbol pointer is less than the start symbol pointer the PHI will send all symbols from start to stop wrapping at 32. 10 The IDLE command is configured differently to the others. It is always only one symbol in length and cannot be configured to be empty. The IDLE symbol value is defined by the IdleCmdCfg register. The symbol array can be programmed by accessing the SymbolTable registers. Note that the symbol table can be written to at any time, but can only be read when Go is set to 0. 34.4 CPU ACCESS 15 The PHI provides a mechanism for the CPU to send data and control words to any individual segment or to broadcast to all segments simultaneously. The CPU writes commands to the command FIFO, and the PHI accepts data from the command FIFO, and transmits the symbols to the addressed printhead segment, or broadcasts the symbols to all printhead segments. The CPU command is of the form: 20 The 9-bit symbol can be a control or data word, the segment address indicates which segment the command should be sent to. Valid segment addresses are 0-11 and the broadcast address is 15. There is a direct mapping of segment addresses to printhead data lines, segment addresses 0 and 1 are sent out printhead channel 0, WO 2005/120835 PCT/AU2004/000706 926 addresses 2 and 3 are sent out printhead channel 1, and so on to addresses 10 and 11 which are send out printhead channel 5. The end of command (EOC) flag indicates that the word is the last word of a command. In multi-word commands the segment address for the first word determines which printhead channel the command gets sent to, the segment address field in subsequent words is ignored. 5 The PHI operates in 2 modes, CPU command mode and data mode. A CPU command always has higher priority than the data stream (or a stream of idles) for transmission to the printhead. When there is data in the command FIFO, the PHI will change to CPU command mode as soon as possible and start transmitting the command word. If the PHI detects data in the command FIFO, and the PHI is in the process of transmitting a control word the PHI waits for the control word to complete and then switches to CPU command mode. Note 10 that idles are not considered control words. The PHI will remain in CPU command mode until it encounters a command word with the EOC flag set and no other data in the command FIFO. The PHI must accept data for all printhead channels from the LLU together, and transmit all data to all printhead segments together. If the CPU command FIFO wants to send data to a particular printhead segment, the PHI must stall all data channels from the LLU, and send IDLE symbols to all other print channels not 15 addressed by the CPU command word. If the PHI enters CPU command mode and begins to transmit command words, and the command FIFO becomes empty but the PHI has not encountered an EOC flag then the PHI will continue to stall the LLU and insert IDLE symbols into the print streams. The PHI remains in CPU command mode until an EOC flag is encountered. To prevent such stalling the command FIFO has an enable bit CmdFIFOEnable which enables the PHI 20 reading the command FIFO. It allows the CPU to write several words to the command FIFO without the PHI beginning to read the FIFO. If the CPU disables the FIFO (setting CmdFIFOEnable to 0) and the PHI is currently in CPU command mode, the PHI will continue transmitting the CPU command until it encounters an EOC flag and will then disable the FIFO. When the PHI is switching from CPU command mode to data transfer mode, it sends a RESUME command 25 to the printhead channel group data transfer that was interrupted. This enables each printhead to easily differentiate between control and data streams. For example if the PHI is transmitting data to printhead group B and is interrupted to transmit a CPU command, then upon return to data mode the PHI must send a RESUMEB control command. If the PHI was between pages (when Go = 0) transmitting IDLE commands and was interrupted by a CPU command, it doesn't need to send any resume command before returning to 30 transmit IDLE. The command FIFO can be written to at any time by the CPU by writing to the CmdFifo register. The CmdFiFO register allows FIFO style access to the command FIFO. Writing to the CmdFIFO register will write data to the command FIFO address pointed to by the write pointer and will increment the write pointer. The CmdFIFO register can be read at any time but will always return the command FIFO value pointed to by 35 the internal read pointer. The current fill level of the CPU command FIFO can be read by accessing the CmdFIFOLevel register. The command FIFO is 32 words x l4bits.
WO 2005/120835 PCT/AU2004/000706 927 34.5 LINE SYNC The PHI synchronizes line data transmission with sync pulses generated by the GPIO block (which in turn could be synchronized to the GPIO block in another SoPEC). The PHI waits for a line sync pulse and then transmits line data and the FIRE command to all printhead segments. 5 It is possible that when a line sync pulse arrives at the PHI that not all the data has finished being sent to the printheads. If the PHI were to forward this signal on then it would result in an incorrect print of that line, which is an error condition. This would indicate a buffer underflow in PEC 1. However, in SoPEC the printhead segments can only receive line sync signals from the SoPEC providing them data. Thus it is possible that the PHI could delay in sending the line sync pulse until it had finished 10 providing data to the printhead. The effect of this would be a line that is printed slightly after where it should be printed. In a single SoPEC system this effect would probably not be noticeable, since all printhead segments would have undergone the same delay. In a multi-SoPEC system delays would cause a difference in the location of the lines, if the delay was great this may be noticeable. If a line sync is early the PHI records it as a pending line sync and will send the corresponding next line and 15 FIRE command at the next available time (i.e. when the current line of data is finished transferring to the printhead). It is possible that there may be multiple pending line syncs, whether or not this is an error condition is printer specific. The PHI records all pending line syncs (LineSyncPend register), and if the level of pending lines syncs rises over a configured level (LineSyncMaxPend register) the PHI will set the MaxSyncPend bit in the PhiStatus register which if enabled can cause an interrupt. The CPU interrupt service 20 routine can then evaluate the appropriate response, which could involve halting the PHI. The PHI also has 2 print speed limitation mechanisms. The LineTimeMin register specifies the minimum line time period in pclk cycles and the DynLineTimeMin register which also specifies the minimum line time period in pclk cycles but is updated dynamically after each FIRE command is transmitted. The PHI calculates DynLineTimeCalcMin value based on the last line sync period adjusted by a scale factor specified by the 25 DynLineTimeMinScaleNum register. When a FIRE command is transmitted to the printhead the PHI moves the DynLineTimeCalcMin to the DynLineTimeMin register to limit the next line time. The DynLineTimeCalcMin value is updated for each new line sync (same as the FirePeriodCalc) whereas the DynLineTimeMin register is updated when a FIRE command is transmitted to the printhead (same as the FirePeriod register). The dynamic minimum line time is intended to ensure the previous calculated fire period 30 will have sufficient time to fire a complete line before the PHI begins sending the next line of data. The scale factor is defined as the ratio of the DynLineTimeMinScaleNum numerator value to a fixed denominator value of Ox 10000, allowing a maximum scale factor of 1. The PHI also provides a mechanism where it can generate an interrupt to the ICU (phi _icu lineirq) after a fixed number of line syncs are received or a fixed number of FIRE commands are sent to the printhead. The 35 LineInterrupt register specifies the number of line syncs (or FIRE commands) to count before the interrupt is generated and the LineInterruptSrc register selects if the count should be line syncs or FIRE commands.
WO 2005/120835 PCT/AU2004/000706 928 34.6 LINE DATA ORDER The PHI sends data to each printhead segment in a fixed order inserting the appropriate control command sequences into the data stream at the correct time. The PHI receives a fixed data stream from the LLU, it is the responsibility of the PHI to determine which data is destined for which line, color nozzle row and 5 printhead segment, and to insert the correct command sequences. The SegWidth register specifies the number of dot pairs per half color nozzle row. To avoid padding to the nearest 8 bits (data symbol input amount) the Seg Width must be programmed to a multiple of 8. The MaxColor register specifies the number of half nozzle rows per printhead segment. The MaxSegment specifies the maximum number segments per printhead channel. If MaxSegment is set to 0 10 then all enabled channels will generate a data stream for one segment only. If MaxSegment is set to 1 then all enabled channels will generate data for 2 segments. The LLU will generate null data for any missing printhead segments. The PageLenLine register specifies the number of lines of data to accept from the LLU and transfer to the printhead before setting the page finished flag (PhiPageFinish) in the PhiStatus register. 15 Printhead segments are divided into 2 groups, group A segments are 0,2,4,6,8,10 and group B segments are 1,3,5,7,9,11. For any printhead channel, group A segment data is transmitted first then group B. Each time a line sync is received from the GPIO, the PHI sends a line of data and a fire (FIRE) command to all printhead segments. The PHI first sends a next color command (NCA) for the first half color nozzle row followed by nozzle data 20 for the first half color dots. The number of dots transmitted (and accepted from the LLU) is configured by SegWidth register. The PHI then sends a next color command indicating to the printhead to reconfigure to accept the next color nozzle data. The PHI then sends the next half color dots. The process is repeated for MaxColor number of half nozzle rows. After all dots for a particular segment are transmitted, the PHI sends a next color B (NCB) command to indicate to the group B printheads to prepare to accept nozzle row data. The 25 command and data sequence is repeated as before. The line transmission to the printhead is completed with the transmission of a FIRE command. The PHI can optionally insert a number of IDLE symbols before each next color command. The number of IDLE symbols inserted is configured by the IdleInsert register. If it's set to zero no symbols will be inserted. When a line is complete, the PHI decrements the PageLenLine counter, and waits for the next line sync pulse 30 from the GPIO before beginning the next line of data. The PHI continues sending line data until the PageLenLine counter is 0 indicating the last line. When the last line is transmitted to the printhead segments, the PHI sets a page finished flag (PhiPageFinish) in the PhiStatus register. The PHI will then wait until the Go bit is toggled before sending the next page to the printhead.
WO 2005/120835 PCT/AU2004/000706 929 34.7 MISCELLANEOUS PRINTHEAD CONTROL Before starting printing SoPEC must configure the printhead segments. If there is more than one printhead segment on a printline, the printhead segments must be assigned a unique ID per print line. The IDs are assigned by holding one group of segments in reset while the other group is programmed by a CPU command 5 stream issued through the PHI. The PHI does not directly control the printhead reset lines. They are connected to CPR block output pins and are controlled by the CPU through the CPR. The printhead also provides a mechanism for reading data back from each individual printhead segment. All printhead segments use a common data back channel, so only one printhead segment can send data at a time. SoPEC issues a CPU command stream directed at a particular printhead segment, which causes the segment 10 to return data on the back channel. The back channel is connected to a GPIO input, and is sampled by the CPU through the GPIO. If SoPEC is being used in a multi-SoPEC printing system, it is possible that not all print channels, or clock outputs are being used. Any unused data outputs can be disabled by programming the PhiDataEnable register, or unused clock outputs disabled by programming the PhiClkEnable. 15 The CPU when enabling or disabling the clock or data outputs must ensure that the printhead segments they are connected to are held in a benign state while toggling the enable status of the output pins. 34.8 FIRE PERIOD The PHI calculates the fire period needed in the printhead segments based on the last line sync period, adjusted by a fractional amount. The fractional factor is dependant on the way the columns in the printhead 20 are grouped, the particular clock used within the printhead to count this period and the proportion of a line time over which the nozzles for that line must be fired. For example, one current plan has fire groups consisting of 32 nozzle columns which are physically located in a way that require them to be fired over a period of around 96% of the line time. A count is needed to indicate a period of (linetime/32)*96% for a 144MHz clock. 25 The fractional amount the fire period is adjusted by is configured by the FireScaleNum register. The scale factor is the ratio of the configurable FireScaleNum numerator register and a fixed denominator of Ox10000. Note that the fire period is calculated in the pclk domain, but is used in the phiclk domain. The fractional registers will need to be programmed to take account of the ratio of the pclk and phiclk frequencies. A new fire period is calculated with every new line sync pulse from the GPIO, regardless of whether the line 30 sync pulse results in a new line of data being send to the printhead segments, or the line sync pending level. The latest calculated fire period by can read by accessing the FirePeriodCalc register. The PHI transfers the last calculated fire period value (FirePeriodCalc) to the FirePeriod register immediately before the FIRE command is sent to the printhead. This prevents the FirePeriod value getting updated during the transfer of a FIRE command to the printhead, possibly sending an incorrect fire period 35 value to the printhead.
WO 2005/120835 PCT/AU2004/000706 930 The PHI can optionally send the calculated fire period by placing META character symbols in a command stream (either a CPU command, or a command configured in the command table). The META symbols are detected by the PHI and replaced with the calculated fire period. Currently 2 META characters are defined. Table 210. META character definition Nam Sybol Replaced by META1 KO.6 FirePeriod[7:0] META2 KO.7 FirePeriod[15:8] 5 The last calculated fire period can be accessed by reading the FirePeriod register. 34.9 PRINT SEQUENCE Immediately after the PHI leaves its reset it will start sending IDLE commands to all printhead data channels. The PHI will not accept any data from the LLU until the Go bit is set. Note the command table can be programmed at any time but cannot be used by the internal PHY when Go is 0. 10 When Go is set to 1 the PHI will accept data from the LLU. When data actually arrives in the data buffer the PHI will set the PhiDataReady bit in the PhiStatus register. The PHI will not start sending data to the printhead until it receives 2 line syncs from the GPIO (gpiophi line sync). The PHI needs to wait for 2 line syncs to allow it to calculate the fire period value. The first line sync will not become pending, and will not result in a corresponding FIRE command. Note that the PHI does not need to wait for data from the LLU 15 before it can calculate the fire period. If the PHI is waiting for data from the LLU any line syncs it receives from the GPIO (except the first one) will become pending. Once data is available and the fire period is calculated the PHI will start producing print streams. For each line transmitted the PHI will wait for a line sync pulse (or the minimum line time if a line sync is pending) before sending the next line of data to the printheads. The PHI continues until a full page of data has been 20 transmitted to the printhead (as specified by the PageLenLine register). When the page is complete the PHI will automatically clear the Go bit and will set the PhiPageFinish flag in the PhiStatus register. Any bit in the PhiStatus register can be used to generate an interrupt to the ICU. 34.10 IMPLEMENTATION 34.10.1 Definitions of 1/0 Table 211. Printhead interface I/O definition Cocks and Resets %. FC'..' ., ___ WO 2005/120835 PCT/AU2004/000706 931 pclk 1 In System Clock. phiclk 1 In PHI data transfer clock. prst-n 1 In System reset, synchronous active low. Synchronous to pck. phirst-n 1 In System reset, synchronous active low. Synchronous to phic/k. General phi-icu-general-irq 1 Out PHI to ICU general interrupt. Active high. phi-icu-line-irq 1 Out Indicates the PHI has detected LineInterrupt number of line syncs or FIRE commands. Active high pulse. gpio-phi-line-sync 1 In GPIO to PHI line sync pulse to synchronise the dot generation output in the printhead with the motor controllers and paper sensors. LLU Interface llu-phi-data[5:0][1:0] 6x2 In Dot Data from LLU to the PHI, 6 data streams, 2bits each. Data is active when llu.phiavail is 1. phillu-ready 1 Out Indicates that PHI is ready to accept data from the LLU. Ilu-phi-avail 1 In Indicates valid data present on corresponding Iluphi data. Printhead Interface phi-data[5:0] 6 Out Dot data output to printhead segments. 1 bit to 1 or 2 printhead segments. phi-datajs n[5:0] 6 Out Dot data tri-state control output. When 0 the corresponding phLdata pins are disabled. phi-clk[1:0] 2 Out Dot data source clocks. phi-clkjtsn[5:0] 2 Out PHI dot data source clocks tri-state enable. When set to 0 the corresponding phi clk output pins are disabled. PCU Interface pcu-phi sel 1 In Block select from the PCU. When pcuphi sel is high both pcu.adr and pcu dataout are valid. pcu-rwn 1 In Common read/not-write signal from the PCU. pcu-adr[8:2] 7 In PCU address bus. Only 7 bits are required to decode the address space for this block. pcu-dataout[31:0] 32 In Shared write data bus from the PCU. phi-pcu-rdy 1 Out Ready signal to the PCU. When phi pcurdy is high it indicates the last cycle of the access. For a write cycle this means pcu_dataout has been registered by the block and for a read cycle this means the data on phi pcudatain is valid. phi-pcu-datain[31:0] 32 Out Read data bus to the PCU.
WO 2005/120835 PCT/AU2004/000706 932 34.10.3 Configuration registers The configuration registers in the PHI are programmed via the PCU interface. Refer to section 23.8.2 on page 439 for a description of the protocol and timing diagrams for reading and writing registers in the PHI. Note 5 that since addresses in SoPEC are byte aligned and the PCU only supports 32-bit register reads and writes, the lower 2 bits of the PCU address bus are not required to decode the address space for the PHI. When reading a register that is less than 32 bits wide zeros are returned on the upper unused bit(s) of phi_pcudatain. Table 212 lists the configuration registers in the PHI Table 212. PHI registers description activating. A write to this register will cause a PHI block reset. Ox004 Go 1 Ox0 Active high bit indicating the PHI is programmed and ready to use. A low to high transition will cause the PHI to reset the Line Sync, Fire Period, data state machine, LLU interface and input buffer. No other sections of the PHI will be affected. General Control Ox010 PageLenLine 32 Ox000 Specifies the number of dot lines in a page. o_000 Indicates the number of lines left to process in O this page while the PHI is running. Note should only be programmed when Go is 0. (Working register) 0x014 MaxColor 4 OxB Indicates the number of half colors+1 per segment to produce data for, must be less than 12. e.g. for printheads with10 half colors set to 9. Ox018 SegWidth[12:3] 10 OxOO Specifies the number of half color dots per printhead segment (must be set to a multiple of 8). OxO1C MaxSegment 1 Ox1 Specifies the maximum number of segments per print channel 0 - 1 segment per print channel 1 - 2 segments per print channel 0x020 Idleinsert 5 Ox00 Specifies the number oDLE symbols to insert before each next color symbol when generating line data. If set to 0 no symbols are inserted.
WO 2005/120835 PCT/AU2004/000706 933 0x024 PhiCIkEnable 2 Ox0 PHI clock enable. One bit per clock output, when 1 enables the output clock, otherwise the output clock is switched off. Bit 0 - Enables phi c/k[0] Bit 1 - Enables phi c/k[1] Also controls the tri-state enable of the phi_c/k outputs. Ox028 PhiDataEnable 6 Ox00 PHI data channel enable. One bit per output print channel. When 1 the output data line is enabled. Bit 0 - Enables phi data[01 Bit 1 - Enables phi data[1] Bit 2 - Enables phi data[2] Bit 3 - Enables phi data[3] Bit 4 - Enables phi data[4] Bit 5 - Enables phi data[5] Also controls the tri-state enable of the phi data outputs. Command Configuration Ox080- CmdTable[31:0] 32x9 Ox00 Command Configuration lookup table. OxOFC 0xI 00- CmdCfg[4:0] 5x1 1 OxOO Command pointer configuration for each 0x120 command. See Table 209 for command definition. One register per command. Bits 4:0 - Start Symbol pointer into CmdTable Bits 9:5 - End Symbol pointer into CmdTable Bit 10 - Command empty 0x124 IdleCmdCfg 9 0x100 Idle Command Symbol value (Defaults to KO.0) CPU Command FIFO 0x130 CmdFIFO 14 OxOO CPU command FIFO access. Each time the 0 register is written to, the buffer write pointer is incremented. A read of this register will return the command FIFO data word pointed to by the read pointer. 0x134 CmdFIFOLevel 6 Ox00 CPU Command FIFO level. Indicates the current CPU command FIFO fill level in words. (Read only Register) 0x138 CmdFIFOEnable 1 OxO CPU Command FIFO enable. When 1 allows the command FIFO to be read by the PHI. Line Sync Control 0x1 40 LineTimeMin 24 OxOO_ Specifies the minimum number of pc/k cycles 0000 between adjacent FIRE commands send to the printhead. Line sync pulses of a shorter period will not translate into a FIRE command immediately and will remain pending until the specified number of pc/k cycles has elapsed. Ox1 44 DynLineTimeMinS 16 OxOO Numerator of dynamic line sync scale factor, caleNum 1 denominator is fixed at Ox1 0000. Must be non zero. Used to calculate the current minimum line time period based on the last line sync.
WO 2005/120835 PCT/AU2004/000706 934 0x148 DynLineTimeMin 24 Ox00_- Specifies the minimum number of pc/k cycles 0000 between adjacent FIRE commands send to the printhead, but is updated dynamically from the DynLineTimeCalcMin register when a FIRE command is transmitted. Line sync pulses of a shorter period will not translate into a FIRE command immediately and will remain pending until the specified number of pck cycles has elapsed. (Read Only Register) 0x14C DynLineTimeCalc 24 0x00 Dynamically calculated minimum line time in Min 0000 pck cycles, updated after each new line sync pulse. (Read Only Register) 0x150 LineInterrupt 16 OxOO Number of line syncs (or F/RE commands) to 0 occur before generating a phi icujlinejirq interrupt. When set to 0 interrupt is disabled. 0x154 LinelnterruptSrc 1 Ox0 Selects the line interrupt source for input into the Line/nterrupt counter 0 - Select raw line input from the GPIO 1 - Select F/RE commands as send out in the print stream 0x1 58 LineSyncMaxPend 10 OxOO Specifies the maximum value for the LineSyncPend register before setting the MaxSyncPend bit in the PhiStatus register. When set to 0, MaxSyncPend bit is disabled and is never set. Ox1 5C FireScaleNum 16 OxOO Numerator of Fire Period scale factor; 1 denominator is fixed at Ox1 0000. Must be non zero. Used to determine the fire period based on the last line sync period 0x160 FirePeriod 16 OxOO Last transmitted fire period value. Updated 0 from the FirePeriodCalc when (a cycle before) a FIRE command is transmitted. (Read Only Register) 0x1 64 FirePeriodCalc 16 Ox000 Last Calculated fire period value. 0 (Read Only Register) 0x170 PhiStatus 4 Ox0 Indicates the status and source of the PHI general interrupt 0 - MaxSyncPend, Max line sync pending interrupt 1 - Invalid 8b10b control command 2 - PhiDataReady, PHI data ready 3 - PhiPageFinish PHI page finish flag All bits are sticky, and can be cleared by writing al to the corresponding bit in PhiStatusClear register. (Read Only Register) 0x174 PhiStatusClear 4 Ox0 PHI status clear register. If written with a 1 it clears corresponding PhiStatus sticky bit. 0 - MaxSyncPend, Max line sync pending interrupt 1 - Invalid 8blOb control command 2 - PhiDataReady, PHI data ready 3 - PhiPageFinish PHI page finish flag For example a write of OxC will clear the PhiDataReady, and PhiPageFinish sticky bit in the PhiStatus register.
WO 2005/120835 PCT/AU2004/000706 935 (Reads as zero) 0x1 78 PhiStatusMask 4 Ox0 Enables the PhiStatus bits as sources to generate a phiicu.generaLirq interrupt. When high the interrupt source bit is masked. Working Registers 0x1 AO OutBufLevel 2 Ox0 Output buffer fill level in words. (Read Only register) 0x1 A4 DataBufferLevel 4 Ox0 Data buffer fill level in words. (Read Only register) 0x1 A8 LineSyncPend 10 xOO Indicates the number of outstanding line syncs (and lines of data) yet to be sent to the printhead. (Read Only register) A low to high transition of the Go register causes the LLU interface and data buffer, Line sync, Fire Period and data state machine to be reset. All other logic and configuration registers in the PHI will remain the same. The block indicates the transition to other blocks via the phi_go_pulse signal. 5 When changing the configuration values PhiDataEnable and PhiClkEnable the phiclk clock must be enabled for the changes to take effect. 34.10.4 Line sync The line sync block implements the line sync pending logic, and determines when an interrupt should be generated and sent to the ICU. It also includes logic to prevent line times of less than the configured minimum 10 size, or the calculated minimum size. The line sync block receives a line sync pulse from the GPIO (via the gpiophi linesync signal), if there is no line data currently being sent (line-complete = 1) and the minimum period time has elapsed (both static and dynamic) then it will generate a line-start pulse to the print stream controller to begin transmitting the next line of data to the printhead segments. 15 If a line sync pulse arrives while there is a line still being transmitted the line sync becomes pending, and the pending counter is incremented. When the current line being transmitted is complete the logic will generate a new line-start pulse and decrement the pending counter. The pending counter can be read by the CPU at any time by reading the LineSyncPend register. The LineTimeMin register specifies the minimum time between successive linestart pulses to the print 20 stream controller. If a line has completed and there are several line syncs pending the next line will not begin WO 2005/120835 PCT/AU2004/000706 936 until the LineTimeMin counter has expired. Once the counter has expired the logic will issue a new linestart pulse and decrement the LineSyncPend counter. Similar logic exists for the DynLineTimeMin value. // all gpio pulses result in a pending except the first one 5 if (gpio-phi-line-sync-first == 1) then line-syncpend_inc = gpio-phi-line-sync elsif (gpio-phi-line-sync == 1) then gpio-phi-line-sync_first = 1 10 // implement the line start control (filtered later by line count) if((minperiod-cnt > linetimemin) AND (min-period-cnt > dyn-line_time_min) AND (line-sync-pend != 0) AND (page-lenline != 0) AND 15 (line-complete == 1) AND (phigo == 1) then linestart = 1 else line-start = 0 // implement the line sync pending count 20 case (linesync-pendinc,line-start) 00: line-sync-pend = line_syncpend 01: line-sync-pend = linesync-pend - 1 10: linesyncpend = line-sync-pend + 1 11: line-syncpend = linesync-pend 25 endcase // implement the min period counter if (linestart == 1) then min-period-cnt = 0 30 elsif (min-periodcnt != OxFFFFFF) then // allow to saturate, no wrap min-period_cnt ++ If the LineSyncPend register exceeds the LineSyncMaxPend configured level the line sync block will set the MaxSyncPend bit in the PhiStatus register. The bit is sticky and can be optionally used to generate an 35 interrupt to the CPU. // max pending interrupt if (phi-go-pulse == 1) then max-pend-int = 0 elsif (line-syncpend > line-syncmaxpend) then 40 maxpendint = 1 The line sync block also generates a line sync interrupt (phiiculineirq) every LineInterrupt number of line syncs received from the GPIO (or FIRE commands sent out in the print stream). The LineInterruptSrc register selects the line sync source. This interrupt can be disabled by programming the LineInterrupt register to 0. 45 // select the line sync source if (line_interruptsrc ==l) then line-sync = line_start else line-sync = gpiophilinesync 50 // the internal line sync count interrupt if (phi_gopulse ==l) then linecount = 0 elsif ( line-sync == 1 AND line-count == 0) then WO 2005/120835 PCT/AU2004/000706 937 linecount = line-interrupt elsif ((line-sync == 1) AND (linecount != 0)) then line-count - // determine when to pulse the interrupt 5 if (lineinterrupt == 0 ) then // interrupt disabled phi_iculine-irq = 0; elsif (linesync == 1 AND linecount == 1) then phi-icu_line-irq = 1 The line sync block also keeps track of the number of lines generated by the PHI. The PageLenLine registers 10 is a working register, and must be programmed to the number of lines per page before the Go bit is set to 1 to enable the PHI. After a line is transmitted by the PHI the PageLenLine register will be decremented. When the counter decrements to 0, the line sync block will set the PhiPageFinish bit in the PhiStatus register. This sticky can be used to optionally trigger an interrupt to the CPU. No further line-start pulses will be created while the PageLenLine is 0. 15 // implement the page line count if (pagelenwren == 1) then page-lenline = cpuwrdata // cpu write access 20 elsif (line-sync-pend-dec == 1 AND page-lenline 0) then // else working mode page-lenline else // hold page-lenline = page-len-line // generate the page finish 25 page-finish-int = (pagelen_line == 0) AND (linecomplete == 1) 34.10.5 Fire period The fire period calculator measures the line sync period and scales the period to produce the fire period and dynamic line time minimum value. The fire period can optionally be sent to the printhead by inserting META 30 characters in the definition of commands. The META characters are defined in Table 210. The scale factor for the FirePeriod is defined by the FireScaleNum (with a denominator of Ox10000), and the scale factor for the DynLineTimeCalcMin value is defined by the DynLineTimeMinScaleNum (with a denominator value of Ox10000). 35 if (phi-go-pulse == 1) then fire-period-calc = 0 curr_fireperiod = 0 fireaccum = 0 elsif (gpiophilinesync == 1) then 40 fireperiod_calc = curr-fire-period curr-fire-period = 0 else fire-var(16:0] = fireaccum[15:0] + fire_scale_num[15:0] // update the counter on each wrap 45 if (firevar[16] == 1) then // detect an overflow curr_fireperiod ++ // update the accum fireaccum(15:0] = fire-var[15:0] WO 2005/120835 PCT/AU2004/000706 938 Similar logic is used to calculate to the DynLineTimeMin value. When the print stream controller transitions to the FIRE command state it issues afirestart pulse to indicate to the line sync block to capture the calculated minimum line time and fire period. // update the dynamic value when a FIRE is sent 5 if (firestart == 1) then dyn-line-time-min = dyn-line-time-calc_min fire-period = fireperiodcalc 34.10.6 LLU interface 10 The LLU interface accepts data from the LLU in 6x2 data bit form and constructs 48-bit data words over 4 cycles and writes them into the Data buffer. The LLU interface accepts data from the LLU as long as the data buffer is not full and the Go bit is set. The LLU interface also calculates the buffer empty signal to indicate to the print stream controller when the data buffer has data available. // philluready generation 15 phijllu-ready = phigo AND NOT( dbbuf_full) // a valid dot data word is wordvalid = phi_llu-ready AND lluphiavail // generate the address and de-serializer pointers if (phigopulse == 1) then 20 wradr = 0 elsif (word-valid == 1) then wr-adr ++ // write address is allowed to wrap naturally // generate the bit mask from the read address 25 dbwren = wordvalid dbwradr = wr_adr[5:2] case wradr[1:0] 00 : db_wrmask[47:0] = 0x0303_0303_0303 01: db-wr-mask[47:0] = OxOCOC_OCOC_OCOC 30 10: db-wr-mask[47:0] = 0x3030_3030_3030 11: dbwr-mask[47:0] = OxCOCOCOCO_COCO endcase // generate the buffer empty/full signals dbbuf_emp = (rdadr[4:0] == wr_adr[6:2]) 35 // buffer full level if ((rd-adr[4] != wradr[6]) AND (rdadr{4:0] == wr_adr[5:2]) then db_buf_full = 1 else db_buf_full = 0 40 The db buf emp bit is used in the configuration registers to generate the PhiDataReady status bit in the PhiStatus register. After reset the PhiDataReady bit is set to zero. When the data buffer becomes non-empty for the first time the PhiDataReady bit will get set to one. For the LLU interface timing diagram see Figure 248 on page 627.
WO 2005/120835 PCT/AU2004/000706 939 34.10.7 Command table The command table logic contains programmed values for the control symbol lookup table. The print stream controller reads locations in the command table to determine the values of symbols used to construct control commands. The lookup pointers per command are configured by the CmdCfg registers. 5 The CPU programs the command table by writing to the CmdTable registers. The CPU can write to the command table at any time. But to ensure correct operation of the PHI the CPU should only change the command table when the Go bit is 0. The command table logic is implemented using a register array (to save logic area). The register array has one read and one write port. The write port is dedicated to the CPU, but the read port needs to be shared between 10 CPU read access and PHI internal read access. To simplify arbitration on the read port, the Go bit is used to switch between CPU access (Go = 0) and PHI internal access (Go = 1). 34.10.8 Command FIFO The command FIFO provides a mechanism for the CPU to send control or data commands to printhead segments. The CPU writes a sequence of command words to the FIFO (by writing to the CmdFIFO registers) 15 to make a command. Each command word contains 9 symbol bits, 4 segment address bits and an end of command (EOC) bit (as defined in Figure 290). A command consists of one or more command words terminated with the EOC bit set in the last word. Each write access to any CmdFIFO register location causes the write pointer to get incremented. The CmdFIFOEnable bit controls if data in the FIFO is to be presented to the PHI for transmission to the printhead segments. If CmdFIFOEnable is 0 the cmdemp signal is forced 20 high indicating to the print stream controller that the CmdFIFO is empty. If CmdFIFOEnable is 1 then any data in the CmdFIFO will be available for transfer. The CmdFIFOEnable bit is intended to allow the CPU to write a complete command (which could be a number of command words) to the FIFO before the print stream controller begins reading data from the command FIFO. If the print stream controller has started transmitting a command from the command FIFO, and the command 25 FIFO becomes empty then the controller will wait until a terminating command word is sent (i.e. EOC flag set to zero) before reverting back to transmitting regular data. While it is waiting for an EOC flag it will insert IDLE symbols into the print stream. The FIFO reports the fill level of the command FIFO via the CmdFifoLevel register. The command FIFO is implemented using a register array (to save logic area). 30 // implement the write pointers if (cf-wr-en == 1) then // active CPU write wradr ++ // generate the buffer empty signals 35 cmdemp = (wr-adr == cmdrdadr ) OR (cf-fifo-enable == 0) // determine FIFO fill level cf_fifo-level = (wradr - cmd_rd_adr) // connect the read rdadr = cmd_rdadr WO 2005/120835 PCT/AU2004/000706 940 34.10.9 Print stream generator The print stream generator consists of 2 controller state machines and some logic to maintain the output buffer. The PHI mode controller arbitrates and controls access to the output buffer. It arbitrates between CPU 5 sourced commands or data streams, and data controller sourced commands or data streams. The data controller state machine accepts nozzle data from the data buffer (or indirectly from the LLU). It generates and wraps the nozzle data with the appropriate command symbols to produce the print stream. 34.10.9.1 Data controller The data controller state machine accepts nozzle data from the LLU (via the data buffer) and wraps the raw 10 nozzle data with control commands to correctly indicate to each printhead segment the correct destination of the nozzle row data. The state machine creates the command and data sequence as shown in Figure 291. The data controller state machine resets to the Wait state. While in the Wait state it inserts Idle commands into the print stream. It remains in the Wait state until it receives a start line pulse from the line sync block (via the linestart signal). When true the state machine begins generating the control and data streams for transmission 15 to the printhead segments. The state machine transitions to the IdleInsert state, and produces idleinsert number of Idle symbols. If idle-insert is 0 the state is bypassed. All transitions to IdleInsert cause the idlecnt counter to reset. When complete the state machine transitions to NCCmd state. On transition into a command state (NCCmd) the command table read address (dcrdadr) is loaded with 20 configured start pointer for that command CmdCfg[NC][STPTR]. The command could be NCA or NC_B depending on the value of the segment counter (segcnt). While in the command state the dcrdadr address is incremented each time a symbol word is written into the output buffer. If the output buffer becomes full the pointer will remain at the current value. While in the NCCmd state the state machine indicates to the symbol mux to select symbols from the command table (ct rd data). The state machine determines the command has 25 completed by comparing the dcrdadr with the configured end pointer for that command CfgCmd[NC][ENDPTR]. If the CfgCmd[NC][EMP] empty bit is set the NCCmd state is bypassed. When the command transfer is complete the state machine transitions to the NozzleData state to transfer data from the data buffer to the output buffer and eventually to the printhead. All transitions to the NozzleData state cause the word counter to reset (word-cnt). While in the NozzleData state the wordcnt counter is 30 incremented each time a data word is transferred from the data buffer to the output buffer. The state machine remains in this state until all data words for one nozzle row of a half color are transmitted. It determines the end of a nozzle row by comparing the word count with configured segment width (SegWidth). The SegWidth register is specified as the number of dot pairs per nozzle row, and a data word is equivalent to 8 dot-pairs. In order to compare like units, the comparison uses the SegWidth[13:3] bits as the bottom bits are redundant 35 (hence the requirement that Seg Width must be programmed to a multiple of 8). While in the NozzleData state the db rddata is switched through the symbol mux to the output buffer (ob-wr-data).
WO 2005/120835 PCT/AU2004/000706 941 When the NozzleData state has detected that the nozzle data transfer has completed, the state machine tests the color counter. If the counter is less than the configured MaxColor it will return to the IdleInsert state and increment the color counter. The loop is repeated until all colors have been transmitted to the printhead. When the color count is equal to MaxColor the state machine determines if it needs to send data for the next 5 printhead segment group by comparing the segment count (segcnt) to the configured number of segments (MaxSegment). If they are equal the state machine transitions to the Fire state. If not the state machine increments the seg_cnt, transitions to the IdleInsert state and begins generating the command and data stream for the next group of segments as before. When the state machine transitions to the Fire state the command table read address is set to 10 CfgCmd[FIRE][STPTR, and the fire-start signal is pulse. The firestart pulse indicates to the line sync block to update the fire period and dynamic line time minimum value. While in the Fire state the command table address is incremented, and the symbol mux is set to select symbols from the command table (ct rd data), and is output to all print channels. The state machine remains in the Fire state until the dcrdadr is equal the configured fire command end pointer CmdCfg[FIRE][ENDPTR]. When true the state 15 machine transitions back to the Wait state to wait for the next line start pulse. If the CmdCfg[FIRE][EMP] bit is set the Fire state is bypassed and the state machine transitions from the NozzleData state directly to the Wait state. At any time when the state machine is generating commands or data symbols, the output buffer could become full. If this happens the state machine will halt and wait for space to become available before starting again. 20 If the state machine is in the NozzleData state and the input data buffer becomes empty, the state machine will signal to the symbol mux to generate idle symbols until the data buffer has data available again. When the data controller state machine is in the process of sending control commands to the print channels, it needs to disable the PHI mode state machine from switching in CPU control words. It disables the PHI mode machine by setting the mode_chgok signal to 0. When the machine is in a nozzle data transfer state or Wait 25 state the modechg_ok is set to 1 enabling the mode change state machine. 34.10.9.2 PHI mode controller The PHI mode controller determines the symbol source for the output print stream, arbitrates between CPU command mode (CPU sourced stream) and data mode (data controller sourced stream), and handles the switching between both modes. 30 The state machine resets to the DataMode state. It allows the data controller state machine control of the symbol mux (symsel=dc-sel) and command table (ct-rdadr=dc_rd_adr). The state machine will remain in the DataMode, until it detects that there is data available in the CPU command FIFO (cmd emp = 0). If the data controller state machine is not in the middle of sending a control command (as indicated by the modechgok signal) then it will then transition to the CmdMode state. 35 When in the CmdMode state the state machine routes symbols from the command FIFO to the print channels as defined by the address in the command FIFO. The state machine will remain in the CmdMode until the WO 2005/120835 PCT/AU2004/000706 942 command FIFO is empty and the end of command (EOC) flag is detected in the last control word from the command FIFO. If the command FIFO becomes empty while in the CmdMode state, but the command is not terminated with the EOC flag the state machine transitions to the IdleGen state and fills the print streams with IDLE symbols. 5 It remains in the IdleGen state until more data is available in the command FIFO. When the state machine detects that it needs to return to DataMode it must send a RESUME command to all previously active printhead segments to allow the printhead segments to easily distinguish between command and nozzle data. If there are 2 segments configured per print channel (phi-mode ==1) then the state machine will send a RESUMEA command if the segment group interrupted was group A (indicated by the segcnt) or 10 a RESUMEB command if the segment group interrupted was group B. The RESUME commands are sent and generated the same way as the NC (New Color) commands for the data controller. If the state machine detects the empty flag for the RESUMEA or RESUMEB commands is set it will bypass the ResumeA/B generation states and transition directly from CmdMode to DataMode. When the RESUME commands are transmitted the state machine returns to the DataMode state and re 15 enables the data controller. If the transmission of CPU commands did not interrupt any data transfer to the printheads then the state machine can transition directly from CmdMode to DataMode without considering the RESUME states. The state machine determines if it has been printing by the status of the Go bit. 34.10.9.3 Symbol mux 20 The symbol mux selects the input symbols and constructs the outgoing data word to the output buffer based on control signals from the mode and data controllers. The input source symbols can come from the the CPU command FIFO, the Data buffer, the Command Table, or from the state machines directly. The symbol mux monitors the all outgoing symbols for special meta characters (see Table 210 for definition). If encountered the symbol mux inserts the last calculated FirePeriod values instead of the meta characters. 25 // implement the mux case (sym-sel) IDLE: for (i=0;i<6;i++){ 30 ob-wr-data(i] (8:0] = idle_cmd_cfg CMD: for (i=0;i<6;i++)( ob-wr-data[i][8:0] = ct-rd-data[8:01 35 1 DATA: ob_wr-data[0][8:0] = (0,db_rd-data[7:01) obwr-data[l][8:0] = (0,db.rd-data[15:8]) ob_wr-data[2][8:0] = (0,dbrd-data[23:16]) 40 obwr-data[3](8:0] = (0,db_rd_data[31:24]) obwrdata[4][8:0] = (0,db_rd_data[39:32) ob_wr-data[5](8:0] = (0,db_rd_data[47:40]) WO 2005/120835 PCT/AU2004/000706 943 CPU_CMD: if (cmd_rddata[ADR] == BROADCAST) then for (i=0;i<6;i++)( ob-wr-data[i](8:0] = cmd_rddata[8:0] 5 } elsif (cmdrddata[ADR] < 12) // valid segment address // prefill with idles for (i=0;i<6;i++)( ob-wr-data[i} [8:0] = idle-cmd-cfg(8:0] 10 // determine the correct printline index = (cmd-rd-data{ADR] >> 1 ) // divide by 2 ob-wrdata[index] = cmd_rddata[8:0] else // invalid segment address (all 15 idles) for (i=0;i<6;i++)( ob_wr_data(i] (8:0] = idlecmd_cfg8:0] endcase 20 // test for META Characters for (i=0;i<6;i++){ if (ob-wr-data[i] == METAl) then ob-wr-data[i] = (0,fire-period[7:0]) elsif (ob-wr-data[i] == META2) then 25 obwr-datati] = (0,fire-period[15:8]) } 34.10.9.4 Output buffer logic The output buffer is 2 word by 54 bits wide and is primarily used separate the pclk and phiclk clock domains. The print stream generator maintains a read and write pointer to the output buffer. Each time generator logic 30 produces an output data word (either control or data) the word is written to the output buffer and write pointer is incremented. Each time the encoder logic reads a word from the output buffer it sends a rd_ptrinclong pulse (of 2 phiclk duration) to the print stream generator. The pulse is resynced to the pclk domain by a synchronizer and is positive edge detected. When an edge is detected the read pointer in the to the output buffer is incremented. The read and writer pointers are compared to determine when there is space available 35 in the output buffer and to allow the print stream controller to continue. 34.10.10 Encoder The encoder block consists of a 8bOb encoder, a serializer and a 28-bit scrambler for each print channel. All print channels operate together, so common control logic can be shared between each of the channels. The encoder block will begin generating data as soon as the reset is released. The timing of the reset to the 40 encoder will always ensure that the output buffer feeder logic can put at least 1 word of data into the buffer before the encoder block can read it. After that it is the responsibility of the feeder blocks to ensure that the output buffer always has data in it for the encoder to read. All logic in the encoder block clocks on the phiclk. All configuration registers in the PHI are clocked on pclk. Any change in the configuration of PhiDataEnable and PhiCkEnable will be resynchronized to phiclk before WO 2005/120835 PCT/AU2004/000706 944 being applied in the phiclk domain. To ensure that the PHI data clock pins are correctly tri-stated, the phiclk domain must be active when programming the PhiDataEnable and PhiCkEnable configuration registers. 34.10.10.1 Serializer The serializer circuit accepts a l0bit encoded word from the 8blOb encoder and produces a serial scrambled 5 data stream. The serializer consists of a read address pointer used to select a word from the output buffer and a serial counter used to select one of the 10 output bits from the 8b10b encoder for input into the scrambler. Each time a new bit is output the serial counter is incremented, when it reaches 9 it is reset to 0 and the read pointer is incremented, reading a new value from the output buffer. Once enabled the serializer continues reading the output buffer and producing data. It never checks the output buffer for buffer empty signals. It is 10 the responsibility of the output buffer feeding units to ensure that it always has data available. Note that if the raw data feed to the PHI gets stalled the print stream controller will insert IDLE commands to keep the output buffer full. Every time the encoder block updates the output buffer read pointer it needs to inform the print stream controller that the word is free. It sends a 2 cycle long pulse (rd_ptrinclong) to the print stream controller to 15 indicate that a word was read. The pulse needs to be 2 cycles long to always ensure that it will be detected in the slower pclk domain. If the ratio of the phiclk to pclk is changed to be greater than 1.5 then the pulse will need to be further lengthened. Note that the output of the serializer is LSB transmitted first, e.g. enc dat[O] first, encdati]....., enc-dat[8] and enc-dat[9]. 20 34.10.10.2 Scrambler The scrambler is 28-bit register with the feedback generator of G(x) = 1 + x'S + x 28 . For each active clock cycle the scrambler is updated and a new data bit is generated. 34.10.10.3 8b10b Encoding The data out of each printhead channel is encoded using 8b10b encoding. The encoding prevents long streams 25 of 0 or is and helps the printhead to find and retain lock. The encoder takes 8 data bits and a control bit as input and generates a 10 bit encoded output. The output pattern generated is 6/4, 5/5 or 4/6 ratio of ones to zeros, all other patterns are invalid. This ensures that the maximum consecutive run of ones or zeros in a serial stream is limited to 5. The nomenclature used is Zxx.y where Z is either D for data characters or K for control characters, xx is the 30 decimal value of the input bits 4:0, and Y the decimal representation of input bits 7:5. Each output symbol has a positive, neutral or negative disparity associated with it. Positive disparity symbols have more ones than zeros, negative disparity have more zeros than ones and neutral symbols have equal numbers of ones and zeros. All 256 data characters map to either 1 or 2 symbols. Of the data characters that map to only one symbol, the disparity of that symbol is neutral. Any data character that maps into a positive disparity symbol 35 also maps into negative disparity symbols. Some characters map into 2 different neutral disparity symbols.
WO 2005/120835 PCT/AU2004/000706 945 The encoder maintains a running disparity for each print channel. The disparity bit is used to select between encoded symbols where 2 exist, and follows the following rules: e Neutral disparity symbols leave the disparity bit unchanged. e If running disparity bit is negative, choose a symbol with positive disparity, if it exists and change 5 disparity bit to positive. * If running disparity bit is positive, choose a symbol with negative disparity, if it exists and change disparity bit to negative. e Running disparity bit starts negative after reset. In addition to normal data encoding several control characters are defined. Table 213 shows the possible legal 10 control characters and their encoded outputs. Any attempts to encode other control characters will result in an encode error causing the 8b10b error_flag to get set in the PhiStatus register. Table 213. 8b10b control characters input M utput [9:] Notesa M ~ K0.0 1 000 00000 1111_000000 0000_111111 flip Idle Character K1.0 100000001 1110_000011 0001_111100 same Write Character The data character encoder is split into a 5b/6b encoder and a 3b/4b encoder. The 5b/6b encoder encodes input bits 4:0 to produce output bits 5:0 and a running disparity. The 3b/4b encoder encodes input bits 7:5 to 15 produce output bits 9:6 and an output running disparity. The running disparity of the 5b/6b encoder is used as the disparity input to the 3b/4b encoder. Table 214 and Table 215 indicate the codes used for data characters. Table 214. 5b/6b data character encoding Cod iut:0 Outpu-tD{5:0] DO 00000 000110 111001 flip D1 00001 010001 101110 flip D2 00010 010010 101101 flip D3 00011 100011 same D4 00100 010100 101011 flip D5 00101 100101 same D6 00110 100110 same D7 00111 111000 000111 same D8 01000 011000 100111 flip WO 2005/120835 PCT/AU2004/000706 946 D9 01001 101001 same D10 01010 101010 same D11 01011 001011 same D12 01100 101100 same D13 01101 001101 same D14 01110 001110 same D15 01111 000101 111010 flip D16 10000 001001 110110 flip D17 10001 110001 same D18 10010 110010 same D19 10011 010011 same D20 10100 110100 same D21 10101 010101 same D22 10110 010110 same D23 10111 101000 010111 flip D24 11000 001100 110011 flip D25 11001 011001 same D26 11010 011010 same D27 11011 100100 011011 flip D28 11100 011100 same D29 11101 100010 011101 flip D30 11110 100001 011110 flip D31 11111 001010 110101 flip Table 215. 3b/4b data character code Dx.0 000 0010 1101 flip Dx.1 001 1001 same Dx.2 010 1010 same Dx.3 011 1100 0011 same Dx.4 100 0100 1011 flip Dx.5 101 0101 same Dx.6 110 0110 same Dx.7 111 1000 0111 flip WO 2005/120835 PCT/AU2004/000706 947 1.5 PAGE SIZES Table 216. A4 and US Letter page sizes Millimetres Inchles Width Length Width Lengh A4 210.0 297.0 8.26 11.69 US Letter 215.9 279.4 8.5 11 BI-LITHIC 5 This section describes the bi-lithic printhead (as distinct from the linking printhead) from the point of view of printing 30ppm from a SoPEC ASIC, as well as architectures that solve the 60ppm printing requirement using the bi-lithic printhead model. 2. 30PPM 10 To print at 30 ppm, the printheads must print a single page within 2 seconds. This would include the time taken to print the page itself plus any inter-page gap (so that the 30 ppm target could be met). The required printing rate assumes an inter-sheet spacing of 4 cm. A baseline SoPEC system connecting to two printhead segments is shown in Figure 297. The two segments (A and B) combine to form a printhead of typical width 13,824 nozzles per color. 15 We assume decoupling of data generation, transmission to the printhead, and firing. 2.1 GENERATING THE DOT DATA A single SoPEC produces the data for both printheads for the entire page. Therefore it has the entire line time in which to generate the dot data. 2.1.1 Letter pages 20 A Letter page is 11 inches high. Assuming 1600 dpi and a 4cm inter-page gap, there are 20,120 lines. This is a line rate of 10.06KHz (a line time of 99.4us). The printhead is 14,080 dots wide. To calculate these dots within the line time, SoPEC requires a 140.8MHz dot generation rate. Since SoPEC is run at 160MHz and generates 1 dot per cycle, it is able to meet the Letter page requirement and cope with a small amount of stalling during the dot generation process.
WO 2005/120835 PCT/AU2004/000706 948 2.1.2 A4 pages An A4 page is 297mm high. Assuming 62.5 dots/mm and a 4cm inter-page gap, there are 21,063 lines. This is a line rate of 10.54KHz (a line time of 9 4 .8us). The printhead is 14,080 dots wide. To calculate these dots within the line time, SoPEC requires a 148.5MHz 5 dot generation rate. Since SoPEC is run at 160MHz and generates 1 dot per cycle, it is able to meet the A4 page requirement and cope with minimal stalling. 2.2 TRANSMITTING THE DOT DATA TO THE PRINTHEAD Assuming an n-color printhead, SoPEC must transmit 14,080 dots x n-bits within the line time. i.e. n x the 10 data generation rate = n-bits x 14,080 dots x 10.54KHz. Thus a 6-color printhead requires 874.2Mb/sec. The transmission time is further constrained by the fact that no data must be transmitted to the printhead segments during a window around the linesync pulse. Assuming a 1% overhead for linesync overhead (being very conservative), the required transmission bandwidth for 6 colors is 883Mb/sec. However, the data is transferred to both segments simultaneously. This means the longest time to transfer data 15 for a line is determined by the time to transfer print data to the longest print segment. There are 9744 nozzles per color across a type7 printhead. We therefore must be capable of transmitting 6-bits x 9744 dots at the line rate i.e. 6-bits x 9744 x 10.54KHz = 616.2Mb/sec. Again, assuming a 1% overhead for linesync overhead, the required transmission bandwidth to each printhead is 622.4Mb/sec. The connections from SoPEC to each segment consist of 2 x 1-bit data lines that operate at 320MHz each. 20 This gives a total of 640 Mb/sec. Therefore the dot data can be transmitted at the appropriate rate to the printhead to meet the 30ppm requirement. 2.3 HARDWARE SPECIFICATION 25 2.3.1 Dot Generation Hardware SoPEC has a dot generation pipeline that generates 1 x 6-color dot per cycle. The LBD and TE are imported blocks from PEC1, with only marginal changes, and these are therefore capable of nominally generating 2 dots per cycle. However the rest of the pipeline is only capable of generating 1 dot per cycle. 30 2.3.2 Dot Transmission Hardware SoPEC is capable of transmitting data to 2 printheads simultaneously. Connections are 2 data plus 1 clock, each sent as an LVDS 2-wire pair. Each LVDS wire-pair is run at 320MHz.
WO 2005/120835 PCT/AU2004/000706 949 SoPEC is in a 100-pin QFP, with 12 of those wires dedicated to the transmission of print data (6 wires per printhead segment). Additional wires connect SoPEC to the printhead, but they are not considered for the purpose of this discussion. 2.3.3 Within the printhead 5 The dot data is accepted by the printhead at 2-bits per cycle at 320MHz. 6 bits are available after 3 cycles at 320MHz, and these 6-bits are then clocked into the shift registers within the printhead at a rate of 106 MHz. Thus the data movement within the printhead shift registers is able to keep up with the rate at which data arrives in the printhead. 10 3. 60PPM This chapter describes the issues introduced by printing at 60ppm, with the cases of 4, 5, and 6 colors in the printhead. The arrangement is shown in Figure 298. 3.1 DATA GENERATION 15 A 60ppm printer is 1 page per second.i.e e A4 = 21,063 lines. This is a line rate of 21.06KHz (a line time of 47.4us) " Letter = 20,120 lines. This is a line rate of 20.12KHz (a line time of 49.7us) If each SoPEC is responsible for generating the data for its specific printhead, then the worst case for dot generation is the largest printhead. The dot generation rate for the 3 printhead configurations is shown in 20 Table 218. Table 218 Dot generation rate required # dots in largest printhead 6912 8328 9744 segment Required dot generation rate 145.6MH 175.4MH 205.2MH z z z Since the preferred embodiment of SoPEC is run at 160MHz, it is only able to meet the dot requirement rate for the 5:5 printhead, and not the 6:4 or 7:3 printheads. 3.2 TRANSMITTING THE DOT DATA TO THE PRINTHEAD 25 Each SoPEC must transmit a printhead's worth of bits per color to the printhead per line. The transmission time is further constrained by the fact that no data must be transmitted to the printhead segments during a WO 2005/120835 PCT/AU2004/000706 950 window around the linesync pulse. Assuming that the line sync overhead is constant regardless of print speed, then a 1% overhead at 30ppm translates into a 2% overhead at 60ppm. The required transmission bandwidths are therefore as described in Table 219. Table 219 Transmission bandwidth required # dots in largest printhead 6912 8328 9744 segment Transmission rate per color plane 145.6 175.4 205.2 Mb/sec Mb/sec Mb/sec With linesync overhead of 2% 148.5 179 Mb/sec 209.3 Mb/sec Mb/sec Transmission rate for 4 colors 594 Mb/sec 716 837 Mb/sec Mb/sec Transmission rate for 5 colors 743 895 1047 Mb/sec Mb/sec Mb/sec Transmission rate for 6 colors 891 1074 1256 Mb/sec Mb/sec Mb/sec 5 Since we have 2 lines to the printhead operating at 320 MHz each, the total bandwidth available is 640 Mb/sec. The existing connection to the printhead will only deliver data to a 4-color 5:5 arrangement printhead fast enough for 60ppm. The connection speed in the preferred embodiment is not fast enough to support any other printhead or color configuration. 3.3 WITHIN THE PRINTHEAD 10 The dot data is currently accepted by the printhead at 2-bits per cycle at 320MHz. Although the connection rate is only fast enough for 4 color 5:5 printing (see Section 3.2), the data must still be moved around in the shift registers once received. The 5:5 printer 4-color dot data is accepted by the printhead at 2-bits per cycle at 320MHz. 4 bits are available after 2 cycles at 320MHz, and these 4-bits would then need to be clocked into the shift registers within the 15 printhead at a rate of 160 MHz. Since the 6:4 and 7:3 printhead configuration schemes require additional bandwidth etc., the printhead needs some change to support these additional forms of 60ppm printing. 4 EXAMPLES OF 60PPM ARCHITECTURES 20 Given the problems described in Section 3, the following issues have been addressed for 60ppm printing based on the earlier SoPEC architecture: e rate of data generation WO 2005/120835 PCT/AU2004/000706 951 * transmission to the printhead * shift register setup within the printhead. Assuming the current bi-lithic printhead, there are 3 basic classes of solutions to allow 60ppm: a. Each SoPEC generates dot data and transmits that data to a single printhead connection, as shown in 5 Figure 299. b. One SoPEC generates data and transmits to the smaller printhead, but both SoPECs generate and transmit directly to the larger printhead, as shown in Figure 300. c. Same as (b) except that SoPEC A only transmits to printhead B via SoPEC B (i.e. instead of directly), as shown in Figure 301 10 4.1 CLAss A: EACH SoPEC WRITES TO A PRINTHEAD This solution class is where each SoPEC generates dot data and transmits that data to a single printhead connection, as shown in Figure 299. The existing SoPEC architecture is targeted at this class of solution. Two methods of implementing a 60ppm solution of this class are examined in the following sections. 4.1.1 Basic Speed Improvement 15 To achieve 60ppm using the same basic architecture as currently implemented, the following needs to occur: * Increase effective dot generation rate to 206 MHz (see Table 2) " Increase bandwidth to printhead to 1256 Mb/sec (see Table 3) * Increase bandwidth of printhead shift registers to match transmission bandwidth It should be noted that even when all these speed improvements are implemented, one SoPEC will still be 20 producing 40% more dots than it would be under a 5:5 scheme. i.e. this class of solution is not load balanced. 4.1.2 Connect printheads together to appear logically as a 5:5 In this scenario, each SoPEC generates data as if for a 5:5 printhead, and the printhead, even though it is physically a 5:5, 6:4 or 7:3 printhead, maintains a logical appearance of a 5:5 printhead. There are a number of means of accomplishing this logical appearance, but they all rely on the two printheads 25 being connected in some way, as shown in Figure 300. In this embodiment, the dot generation rate no longer needs to be addressed as only the 5:5 dot generation rate is required, and the current speed of 160MHz is sufficient. 4.2 CLASS B: Two SoPECS WRITE DIRECTLY TO A SINGLE PRINTHEAD This solution class is where one SoPEC generates data and transmits to the smaller printhead, but both 30 SoPECs generate and transmit directly to the larger printhead, as shown in Figure 301. i.e. SoPEC A transmits WO 2005/120835 PCT/AU2004/000706 952 to printheads A and B, while SoPEC B transmits only to printhead B. The intention is to allow each SoPEC to generate the dot data for a type 5 printhead, and thereby to balance the dot generation load. Since the connections between SoPEC and printhead are point-to-point, it requires a doubling of printhead connections on the larger printhead (one connection set goes to SoPEC A and the other goes to SoPEC B). 5 The two methods of implementing a 60ppm solution of this class depend on the internals of the printhead, and are examined in the following sections. 4.2.1 Serial Load This is the scenario when the two connections on the printhead are connected to the same shift register. Thus 10 the shift register can be driven by either SoPEC, as shown in Figure 302. The 2 SoPECs take turns (under synchronisation) in transmitting on their individual lines as follows: e SoPEC B transmits even (or odd) data for 5 segments e SoPEC A transmits data for 5-printhead A segments even and odd e SoPEC B transmits the odd (or even) data for 5 segments. 15 Meanwhile SoPEC A is transmitting the data for printhead A, which will be length 3, 4, or 5. Note that SoPEC A is transmitting as if to a printhead combination of N:5-N, which means that the dot generation pathway (other than synchronization) is already as defined. Although the dot generation problem is resolved by this scenario (each SoPEC generates data for half the page width and therefore it is load balanced), the transmission speed for each connection must be sufficient to 20 deliver to a type7 printhead i.e. 1256 Mb/sec (see Table 3). In addition, the bandwidth of the printhead shift registers must be altered to match the transmission bandwidth. 4.2.2 Parallel Load This is the scenario when the two connections on the printhead are connected to different shift registers, as 25 shown in Figure 303. Thus the two SoPECs can write to the printhead in parallel. Note that SoPEC A is transmitting as if to a printhead combination of N:5-N, which means that the dot generation pathway is already as defined. The dot generation problem is resolved by this scenario since each SoPEC generates data for half the page width and therefore it is load balanced. 30 Since the connections operate in parallel, the transmission speed required is that required to address 5:5 printing, i.e. 891 Mb/sec. In addition, the bandwidth of the printhead shift registers must be altered to match the transmission bandwidth. 4.3 CLASS C: Two SoPECs WRITE TO A SINGLE PRINTHEAD, ONE INDIRECTLY 35 This solution class is the same as that described in Section 4.2 except that SoPEC A only transmits to printhead B via SoPEC B (i.e. instead of directly), as shown in Figure 304 i.e. SoPEC A transmits directly to printhead A and indirectly to printhead B via SoPEC B, while SoPEC B transmits only to printhead B.
WO 2005/120835 PCT/AU2004/000706 953 This class of architecture has the attraction that a printhead is driven by a single SoPEC, which minimizes the number of pins on a printhead. However it requires receiver connections on SoPEC B. It becomes particularly practical (costwise) if those receivers are currently unused (i.e. they would have been used for transmitting to the second printhead in a single SoPEC system). Of course this assumes that the pins are not being used to 5 achieve the higher bandwidth. Since there is only a single connection on the printhead, the serial load scenario as described in Section 4.2.1 would be the mechanism for transfer of data, with the only difference that the connections to the printhead are via SoPEC B. Although the dot generation problem is resolved by this scenario (each SoPEC generates data for half the 10 page width and therefore it is load balanced), the transmission speed for each connection must be sufficient to deliver to a type7 printhead i.e. 1256 Mb/sec. In addition, the bandwidth of the printhead shift registers must be altered to match the transmission bandwidth. If SoPEC B provides at least a line buffer for the data received from SoPEC A, then the transmission between SoPEC A and printhead A is decoupled, and although the bandwidth from SoPEC B to printhead B must be 15 1256 Mb/sec, the bandwidth between the two SoPECs can be lower i.e. enough to transmit 2 segments worth of data (359 Mb/sec). 4.4 ADDITIONAL COMMENTS ON ARCHITECTURES A, B, AND C Architecture A has the problem that no matter what the increase in speed, the solution is not load balanced, leaving architecture B or C the more preferred solution where load-balancing between SoPEC chips is 20 desirable or necessary. The main advantage of an architecture A style solution is that it reduces the number of connections on the printhead. All architectures require the increase in bandwidth to the printhead, and a change to the internal shift register structure of the printhead. 25 4.5 OTHER ARCHITECTURES Other architectures can be used where different printhead modules are used. For example, in one embodiment, the dot data is provided from a single printed controller (SoPEC) via multiple serial links to a printhead. Preferably, the links in this embodiment each carry dot data for more than one channel (color, etc) of the printhead. For example, one link can carry CMY dot data from the printer controller and the other 30 channel can carry K, IR and fixative channels.
WO 2005/120835 PCT/AU2004/000706 954 5. METHODS OF SOLUTION 5.1 INCREASING DOT GENERATION RATE 5.1.1 Clock speed increase 5 The clock frequency of SoPEC could be increased from 160MHz, e.g. to 176 or 192 MHz. 192 MHz is convenient because it allows the simple generation of a 48MHz clock as required for the USB cores. Under architecture A, a 176 MHz clock speed would be sufficient to generate dot data for 5:5 and 6:4 printheads (see Table 2), but would not be sufficient to generate data for a 7:3 printhead. With architectures B and C, any clock speed increase can be applied to increasing the inter-page gap, or the 10 ability to cope with local stalling. The cost of increasing the dot generation speed is: * a slight increase in area within SoPEC * an increase in time to achieve timing closure in SoPEC * the possibility of the JPEG core being reduced to half speed if it can't be run at the target 15 frequency (current speed rating on CUl I is 185 MHz) * the possibility of the LEON core being reduced in speed if it can't be run at the target frequency e an increase in power consumption thereby requiring a different (more expensive) package. All of these factors are exacerbated by the proportion of speed increase. A 10% speed increase is within the 20 JPEG core tolerance. 5.1.2 Load sharing Since a single SoPEC is incapable of generating the data required for a type6 or type 7 printhead, yet is capable of generating the data for a type printhead, it is possible to share the generation load by having each SoPEC generate the data for half the total printhead width. 25 Architectures B and C are specifically designed to load share dot generation. The problem introduced by load sharing is that the data from both SoPEC A and SoPEC B must be transmitted to the larger printhead. See Section 4 for more details.
WO 2005/120835 PCT/AU2004/000706 955 5.2 INCREASING TRANSMISSION BANDWIDTH 5.2.1 Bandwidth increase with no change in connections for SoPEC At present there are 2 sets of connections from SoPEC to the printheads. Each set consists of 2 data plus a clock, running at twice the nominal SoPEC clock frequency i.e. 160MHz gives 320 Mb/sec per channel. 5 If one of the clocks can be re-used as a data connection, it is possible to have up to 5 channels going to the printhead, as shown in Table 220. Table 220 Increasing # of Channels 160 MHz 320 640 960 Mb/sec 1280 1600 Mb/sec Mb/sec Mb/sec Mb/sec 176 MHz 352 704 1056 1408 1760 Mb/sec Mb/sec Mb/sec Mb/sec Mb/sec 192 MHz 384 768 1152 1536 1920 Mb/sec Mb/sec Mb/sec Mb/sec Mb/sec For all clock speeds of SoPEC from 160MHz to 192 MHz: * Architecture A requires 4 channels on SoPEC and 4 on the printhead 10 - Architecture B serial requires 4 channels on SoPEC and 8 on the printhead * Architecture B parallel requires 3 channels on SoPEC and 6 on the printhead. * Architecture C requires 8 channels. Since SoPEC only has 5, this scenario would only be possible by allocating more pins to transmission. 5.2.2 Bandwidth increase with clock forwarding scheme 15 Assuming we keep our clock forwarding scheme, our 1/0 could run at 450 MHz, with resultant bandwidths as shown in Table 221. Table 221. Increasing # of Channels at 450 MHz 450 MHz 450 900 1350 1800 2250 Mb/sec Mb/sec Mb/sec Mb/sec Mb/sec The following would then be true: e Architecture A requires 3 channels on SoPEC and 3 on the printhead 20 e Architecture B serial requires 3 channels on SoPEC, and 6 on the printhead WO 2005/120835 PCT/AU2004/000706 956 " Architecture B parallel requires 2 channels on SoPEC, and 4 on the printhead. * Architecture C requires 6 channels and 6 on the printhead. Since SoPEC only has 5 (4 + reuse of clock as data), this scenario would only be possible by allocating more pins to transmission. 5 5.2.3 Bandwidth increase with encoded clock scheme Assuming our own flavour of SerDes, 600 Mb/sec might be possible. To accomplish 600 Mb/sec, SerDes would be required on the printhead (extra PLL plus approx 1mm 2 of logic). The fastest possible SerDes on 0.35micron CMOS is in the order of 0.75Gbit/sec, which gives an 10 effective data rate per channel of 600 Mb/sec. The resultant bandwidths as shown in Table 222. Table 222. Increasing # of Channels at 600 MHz 600 MHz 600 1200 1800 2400 3200 Mb/sec Mb/sec Mb/sec Mb/sec Mb/sec The following would then be true: * Architecture A requires 2 channels and 2 on the printhead 15 * Architecture B serial could possibly get away with 2 channels on SoPEC (1200 vs 1256), and 4 on the printhead * Architecture B parallel requires 2 channels on SoPEC, and 4 on the printhead. * Architecture C requires 4 channels and 4 on the printhead. Going faster with SerDes with IBM-specific macros does not give any benefits because: 20 e the printhead is limited due to 0.35 micron process * there is a significant cost for the SerDes core plus a royalty per chip * it would require a change of package to flip-chip style, more than doubling the cost of SoPEC e there are physical constraints on the connection between SoPEC and the printhead cartridge, 25 esp in the 3R printer application.
WO 2005/120835 PCT/AU2004/000706 957 5.3 BANDWIDTH WITHIN THE PRINTHEAD 5.3.1 Shift registers that shift in I direction Instead of having the odd and even nozzles connected by a single shift register, as is currently done and 5 shown in Figure 305, it is possible to place the even and odd nozzles on separate shift registers, as shown in Figure 306. By having the odd and even nozzles on different shift registers, the 6-bits of data is still received at the high rate (e.g. 320 MHz), but the shift register rate is halved, since each shift register is written to half as frequently. Thus it is possible to collect 12 bits (an odd and even dot), then shift them into the 12 shift 10 registers (6 even, 6 odd) at 80 MHz (or whatever appropriate). The effect is that data for even and odd dots has the same sense (i.e. always increasing or decreasing depending on the orientation of the printhead to the paper movement). However for the two printhead segments (and therefore the 2 SoPECs), the sense would be opposite (i.e. the data is always shifting towards the join point at the centre of the printhead). 15 As long as each SoPEC is responsible for writing to a single printhead segment (in a 5:5 printer this will be the case), then no change is required to SoPEC's DWU or PHI given the shift register arrangement in Figure 306. The LLU needs to change to allow reading of odd and even data in an interleaved fashion (in the preferred form, all evens are read before all odds or vice versa). Additionally, the LLU would need to be changed be to permit the data rate required for data transmission. 20 However testing the integrity of the shift registers is of concern since there is no path back. 5.3.1.1 Interwoven shift registers Instead of having odd and even dots on separate shift registers (as described in Section 5.3.1), it is possible to interweave the shift registers to keep the same sense of data transmission (e.g. from within the LLU), but keep the CMOS testing and lower speed shift-registers. Thus it is possible to collect 12 bits (representing two dots), 25 then shift them into the 12 shift registers at 80 MHz (or as appropriate). The arrangement is shown Figure 307. The interweaving requires more wiring that the solution described in Section 5.3.1, however it has the following advantages: * The DWU is unchanged. 30 0 The LLU stays the same in so far as the even dots are generated first, then the odd dots (or vice versa). The LLU still needs the bandwidth change for transmission. " A shift register test path is enabled.
WO 2005/120835 PCT/AU2004/000706 958 * The relative dot generation and bandwidth required is lower for A4 printing due to only half of the off-page dots needing to be sent. 5.4 60PPM BI-LITHIC SUMMARY 60ppm printing using bi-lithic printheads is risky due to increased CPU requirements, increased numbers of 5 pins, and the high data rates at which the transmission occurs. It also relies on stitching working correctly on the printheads to allow the creation of long printheads over several reticles. Therefore an alternative to 60ppm printing via bi-lithic printheads should be found. LINKING PRINTHEADS 10 6. BASIC CONCEPTS The basic idea of the linking printhead is that we create a printhead from tiles each of which can be fully formed within the reticle. The printheads are linked together as shown in Figure 308 to form the page-width printhead. For example, an A4/Letter page is assembled from 11 tiles. 15 The printhead is assembled by linking or butting up tiles next to each other. The physical process used for linking means that wide-format printheads are not readily fabricated (unlike the 21mm tile). However printers up to around A3 portrait width (12 inches) are expected to be possible. The nozzles within a single segment are grouped physically to reduce ink supply complexity and wiring complexity. They are also grouped logically to minimize power consumption and to enable a variety of 20 printing speeds, thereby allowing speed/power consumption trade-offs to be made in different product configurations. Each printhead segment contains a constant number of nozzles per color (currently 1280), divided into half (640) even dots and half (640) odd dots. If all of the nozzles for a single color were fired at simultaneously, the even and odd dots would be printed on different dot-rows of the page such that the spatial difference 25 between any even/odd dot-pair is an exact number of dot lines. In addition, the distance between a dot from one color and the corresponding dot from the next color is also an exact number of dot lines. The exact distance between even and odd nozzle rows, and between colors will vary between embodiments, so it is preferred that these relationships be programmable with respect to SoPEC. 6.1 DATA INTERFACE 30 Each printhead segment has minimum signal pins to reduce cost. Table 223 Signal Pins
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WO 2005/120835 PCT/AU2004/000706 959 Clk Input 2 x LDVS Clock to sample Data, and for internal 288 Receiver processing. MHz s with no terminatio n Data Input 2 x LDVS Data is a 8b:1 Ob encoded data stream. 288 Receiver This stream contains add data and MHz s with no command to the print head. terminatio n RstL Input 1 x 3.3V Active low reset. Puts all control DC CMOS registers into a known test, and Input disables printing. Do Output 1 x 3.3 Do is a general purpose output, usually 28.8 CMOS used to read register values back from MHz Tristate the print head. Default state is tristate. Output 6.1.1 Building a 30ppm printer with SoPEC When 11 segments are joined together to create a 30ppm printhead, a single SoPEC will connect to them as shown in Figure 309 below. 5 Notice that each phDataOutn lvds pair goes to two adjacent printhead segments, and that each phClkn signal goes to 5 or 6 printhead segments. EachphRstn signal goes to alternate printhead segments. 6.1.2 Assigning ids to the printheads for further communication SoPEC drives phRstO and phRstl to put all the segments into reset. SoPEC then lets phRst1 come out of reset, which means that all the segment 1, 3, 5, 7, and 9 are now alive 10 and are capable of receiving commands. SoPEC can then communicate with segment 1 by sending commands down phDataOutO, and program the segment 1 to be id 1. It can communicate with segment 3 by sending commands down phDataOutl, and program segment 3 to be id 1. This process is repeated until all segments 1, 3, 5, 7, and 9 are assigned ids of 1. The id only needs to be unique per segment addressed by a given phDataOutn line. 15 SoPEC can then let phRstO come out of reset, which means that segments 0, 2, 4, 6, 8, and 10 are all alive and are capable of receiving commands. The default id after reset is 0, so now each of the segments is capable of receiving commands along the same pDataOutn line. 6.1.3 Sending commands to the printhead 20 SoPEC needs to be able to send commands to individual printheads, and it does so by writing to particular registers at particular addresses.
WO 2005/120835 PCT/AU2004/000706 960 The exact relationship between id and register address etc. is yet to be determined, but at the very least it will involve the CPU being capable of telling the PHI to send a command byte sequence down a particular phDataOutn line. One possibility is that one register contains the id (possibly 2 bits of id). Further, a command may consist of: 5 - register write e register address * data A 10-bit wide fifo can be used for commands in the PHI. 6.1.4 Building a 60ppm printer with 2 SoPECs 10 When 11 segments are joined together to create a 60ppm printhead, the 2 SoPECs will connect to them as shown in Figure 310 below. In the 60ppm case only phClkO and phRstO are used (phClk1 and phRstl are not required). However note that lineSync is required instead. It is possible therefore to reuse phRstl as a lineSync signal for multi-SoPEC synchronisation. It is not possible to reuse the pins from phClkl as they are lvds. It should be possible to 15 disable the lvds pads of phClkl on both SoPECs and phDataOut5 on SoPEC B and therefore save a small amount of power. 6.2 SEGMENT OPTIONS This section details various classes of printhead that can be used. With the exception of the PEC1 style slope printhead, SoPEC is designed to be capable of working with each of these printhead types at full 60ppm 20 printing speed. 6.2.1 A-chip / A-chip This printhead style consists of identical printhead tiles (type A) assembled in such a way that rows of nozzles between 2 adjacent chips have no vertical misalignment. 25 The most ideal format for this kind of printhead from a data delivery point of view is a rectangular join between two adjacent printheads, as shown in Figure 311. However due to the requirement for dots to be overlapping, a rectangular join results in a it results in a vertical stripe of white down the join section since no nozzle can be in this join region. A white stripe is not acceptable, and therefore this join type is not acceptable. 30 Figure 312 shows a sloping join similar to that described for the bi-lithic printhead chip, and Figure 313 is a zoom in of a single color component, illustrating the way in which there is no visible join from a printing point of view (i.e. the problem seen in Figure 311 has been solved).
WO 2005/120835 PCT/AU2004/000706 961 6.2.2 A-chip / A-chip growing offset The A-chip / A-chip setup described in Section 6.2.1 requires perfect vertical alignment. Due to a variety of factors (including ink sealing) it may not be possible to have perfect vertical alignment. To create more space between the nozzles, A-chips can be joined with a growing vertical offset, as shown in Figure 314. 5 The growing offset comes from the vertical offset between two adjacent tiles. This offset increases with each join. For example, if the offset were 7 lines per join, then an 11 segment printhead would have a total of 10 joins, and 70 lines. To supply print data to the printhead for a growing offset arrangement, the print data for the relevant lines must be present. A simplistic solution of simply holding the entire line of data for each additional line 10 required leads to increased line store requirements. For example, an 11 segment x 1280-dot printhead requires an additional 11 x 1280-dots x 6-colors per line i.e. 10.3125Kbytes per line. 70 lines requires 722Kbytes of additional storage. Considering SoPEC contains only 2.5MB total storage, an additional 722Kbytes just for the offset component is not desirable. Smarter solutions require storage of smaller parts of the line, but the net effect is the same: increased storage requirements to cope with the growing vertical offset. 15 6.2.3 A-chip / A-chip aligned nozzles, sloped chip placement The problem of a growing offset described in Section 6.2.2 is that a number of additional lines of storage need to be kept, and this number increases proportional to the number of joins i.e. the longer the printhead the more lines of storage are required. However, we can place each chip on a mild slope to achieve a a constant number of printlines regardless of 20 the number of joins. The arrangement is similar to that used in PEC 1, where the printheads are sloping. The difference here is that each printhead is only mildly sloping, for example so that the total number of lines gained over the length of the printhead is 7. The next printhead can then be placed offset from the first, but this offset would be from the same base. i.e. a printhead line of nozzles starts addressing line n, but moves to different lines such that by the end of the line of nozzles, the dots are 7 dotlines distant from the startline. This 25 means that the 7-line offset required by a growing-offset printhead can be accommodated. The arrangement is shown in Figure 315. If the offset were 7 rows, then a total of 72.2 KBytes are required to hold the extra rows, which is a considerable saving over the 722 Kbytes required by the solution in Section 6.2.2. Note also, that in this example, the printhead segments are vertically aligned (as in PECI). It may be that the 30 slope can only be a particular amount, and that growing offset compensates for additional differences - i.e. the segments could in theory be misaligned vertically. In general SoPEC must be able to cope with vertically misaligned printhead segments as defined in Section 6.2.2. The question then arises as to how much slope must be compensated for at 60ppm speed. Basically - as much as can comfortably handled without too much logic. However, amounts like 1 in 256 (i.e. 1 in 128 with 35 respect to a half color), or 1 in 128 (i.e. 1 in 64 with respect to a half color) must be possible. Greater slopes WO 2005/120835 PCT/AU2004/000706 962 and weirder slopes (e.g. 1 in 129 with respect to a half color) must be possible, but with a sacrifice of speed i.e. SoPEC must be capable even if it is a slower print. Note also that the nozzles are aligned, but the chip is placed sloped. This means that when horizontal lines are attempted to be printed and if all nozzles were fired at once, the effect would be lots of sloped lines. However, 5 if the nozzles are fired in the correct order relative to the paper movement, the result is a straight line for n dots, then another straight line for n dots 1 line up. 6.2.3.1 PEC1 style slope This is the physical arrangement used by printhead segments addressed by PEC1. Note that SoPEC is not 10 expected to work at 60ppm speed with printheads connected in this way. However it is expected to work and is shown here for completeness, and if tests should prove that there is no working alternative to the 2 1mm tile, then SoPEC will require significant reworking to accommodate this arrangement at 60ppm. In this scheme, the segments are joined together by being placed on an angle such that the segments fit under each other, as shown in Figure 316. The exact angle will depend on the width of the Memjet segment and the 15 amount of overlap desired, but the vertical height is expected to be in the order of Imm, which equates to 64 dot lines at 1600 dpi. Figure 317 shows more detail of a single segment in a multi-segment configuration, considering only a single row of nozzles for a single color plane. Each of the segments can be considered to produce dots for multiple sets of lines. The leftmost d nozzles (d depends on the angle that the segment is placed at) produce dots for 20 line n, the next d nozzles produce dots for line n-1, and so on. 6.2.4 A-chip / A-chip with inter-line slope compensation This is effectively the same as described in Section 6.2.3 except that the nozzles are physically arranged inside the printhead to compensate for the nozzle firing order given the desire to spread the power across the printhead. This means that one nozzle and its neighbor can be vertically separated on the printhead by 1 25 printline. i.e. the nozzles don't line up across the printhead. This means a jagged effect on printed "horizontal lines" is avoided, while achieving the goal of averaging the power. The arrangement of printheads is the same as that shown in Figure 315. However the actual nozzles are slightly differently arranged, as illustrated via magnification in Figure 318. 6.2.5 A-chip / B-chip 30 Another possibility is to have two kinds of printing chips: an A-type and a B-type. The two types of chips have different shapes, but can be joined together to form long printheads. A parallelogram is formed when the A-type and B-type are joined. The two types are joined together as shown in Figure 319.
WO 2005/120835 PCT/AU2004/000706 963 Note that this is not a growing offset. The segments of a multiple-segment printhead have alternating fixed vertical offset from a common point, as shown in Figure 320. If the vertical offset from a type-A to a type-B printhead were n lines, the entire printhead regardless of length would have a total of n lines additionally required in the line store. This is certainly a better proposition than a 5 growing offset). However there are many issues associated with an A-chip / B-chip printhead. Firstly, there are two different chips i.e. an A-chip, and a B-chip. This means 2 masks, 2 developments, verification, and different handling, sources etc. It also means that the shape of the joins are different for each printhead segment, and this can also imply different numbers of nozzles in each printhead. Generally this is not a good option. 10 6.2.6 A-B chip with SoPEC compensation The general linking concept illustrated in the A-chip / B-chip of Section 6.2.5 can be incorporated into a single printhead chip that contains the A-B join within the single chip type. This kind of joining mechanism is referred to as the A-B chip since it is a single chip with A and B characteristics. The two types are joined together as shown in Figure 321. 15 This has the advantage of the single chip for manipulation purposes. Note that as with the A-chip / B-chip of Section 6.2.5, SoPEC must compensate for the vertical misalignment within the printhead. The amount of misalignment is the amount of additional line storage required. Note that this kind of printhead can effectively be considered similar to the mildly sloping printhead described in Section 6.2.3 except that the step at the discontinuity is likely to be many lines vertically (on the order of 7 20 or so) rather than the 1 line that a gentle slope would generate. 6.2.7 A-B chip with printhead compensation This kind of printhead is where we push the A-B chip discontinuity as far along the printhead segment as possible - right to the edge. This maximises the A part of the chip, and minimizes the B part of the chip. If the 25 B part is small enough, then the compensation for vertical misalignment can be incorporated on the printhead, and therefore the printhead appears to SoPEC as if it was a single typeA chip. This only makes sense if the B part is minimized since printhead real-estate is more expensive at 0.35 microns rather than on SoPEC at 0.18 microns. The arrangement is shown in Figure 322. 30 Note that since the compensation is accomplished on the printhead, the direction of paper movement is fixed with respect to the printhead. This is because the printhead is keeping a history of the data to apply at a later time and is only required to keep the small amount of data from the B part of the printhead rather than the A part.
WO 2005/120835 PCT/AU2004/000706 964 6.2.8 Various combinations of the above Within reason, some of the various linking methods can be combined. For example, we may have a mild slope of 5 over the printhead, plus an on-chip compensation for a further 2 lines for a total of 7 lines between type A chips. The mild slope of 5 allows for a 1 in 128 per half color (a reasonable bandwidth increase), and the 5 remaining 2 lines are compensated for in the printheads so do not impact bandwidth at all. However we can assume that some combinations make less sense. For example, we do not expect to see an A B chip with a mild slope. We are currently aiming for the arrangement shown in Section 6.2.7. However if this proves difficult we will aim for a combination of Section 6.2.7 and Section 6.2.3. 10 6.2.9 Redundancy SoPEC also caters for printheads and printhead modules that have redundant nozzle rows. The idea is that for one print line, we fire from nozzles in row x, in the next print line we fire from the nozzles in row y, and the next print line we fire from row x again etc. Thus, if there are any defective nozzles in a given row, the visual effect is halved since we only print every second line from that row of nozzles. This kind of redundancy 15 requires SoPEC to generate data for different physical lines instead of consecutive lines, and also requires additional dot line storage to cater for the redundant rows of nozzles. Redundancy can be present on a per-color basis. For example, K may have redundant nozzles, but C, M, and Y have no redundancy. In the preferred form, we are concerned with redundant row pairs, i.e. rows 0+1 always print odd and even 20 dots of the same colour, so redundancy would require say rows 0+1 to alternate with rows 2+3. To enable alternating between two redundant rows (for example), two additional registers REDUNDANTROWS_0[7:0] and REDUNDANTROWS_1[7:0] are provided at addresses 8 and 9. These are protected registers, defaulting to xO. Each register contains the following fields: Bits [2:0] - RowPairA (000 means rows 0+1, 001 means rows 2+3 etc) 25 Bits [5:3] - RowPairB (000 means rows 0+1, 001 means rows 2+3 etc) Bit [6] - toggleAB (0 means loadA/fireB, 1 means loadB/fireA) Bit [7] - valid (0 means ignore the register). The toggle bit changes state on every FIRE command; SoPEC needs to clear this bit at the start of a page. 30 The operation for redundant row printing would use similar mechanism to those used when printing less than 5 colours: - with toggleAB = 0, the RowPairA rows would be loaded in the DATANEXT sequence, but the RowPairB rows would be skipped. The TDC FIFO would insert dummy data for the RowPairB rows. The RowPairA rows would not be fired, while the RowPairB rows would be fired.
WO 2005/120835 PCT/AU2004/000706 965 - with toggleAB = 1, the RowPairB rows would be loaded in the DATANEXT sequence, but the RowPairA rows would be skipped. The TDC FIFO would insert dummy data for the RowPairA rows. The RowPairB rows would not be fired, while the RowPairA rows would be fired. In other embodiments, one or more redundant rows can also be used to implement per-nozzle replacement in 5 the case of one or more dead nozzles. In this case, the nozzles in the redundant row only pirnt dots for positions where a nozzle in the main row is defective. This may mean that only a relatively small numbers of nozzles in the redundant row ever print, but this setup has the advantage that two failed printhead modules (ie, printhead modules with one or more defective nozzles) can be used, perhaps mounted alongside each other on the one printhead, to provide gap-free printing. Of course, if this is to work correctly, it is important to select 10 printhead modules that have different defective nozzles, so that the operative nozzles in each printhead module can compensate for the dead nozzle or nozzles in the other. Whilst probably of questionable commercial usefullness, it is also possible to have more than one additional row for redundancy per color. It is also possible that only some rows have redundant equivalents. For example, black might have a redundant row due to its high visibility on white paper, whereas yellow might be 15 a less likely candidate since a defective yellow nozzle is much less likely to produce a visually objectionable result. 7. DWU To accomplish the various printhead requirements described in Section 6, the DWU specification must be 20 updated. This document assumes version 3.3 of the SoPEC spec as a starting reference. The changes to the DWU are minor and basically result in a simplification of the unit. 7.1 NOZZLE SKEW The preferred data skew block copes with a maximum skew of 24 dots by the use of 12 12-bit shift registers 25 (one shift register per half-color). This can be improved where desired; to cope with a 64 dot skew (i.e. 12 32-bit shift registers), for example. 7.2 AsCENDING ONLY The DWU currently has an ability to write data in an increasing sense (ascending addresses) or in a decreasing 30 sense (descending addresses). So for example, registers such as ColorLineSense specify direction for a particular half-color. The DWU now only needs to deal with increasing sense only. 8. LLU 35 To accomplish the various printhead requirements described in Section 6, the LLU specification must be updated. This document assumes version 3.3 of the SoPEC spec as a starting reference.
WO 2005/120835 PCT/AU2004/000706 966 The LLU needs to provide data for up to eleven printhead segments. It will read this data out of fifos written by the DWU, one fifo per half-color. The PHI needs to send data out over 6 data lines, where each data line may be connected to up to two segments. When printing A4 portrait, there will be 11 segments. This means five of the datalines will have 5 two segments connected and one will have a single segment connected. (I say 'one' and not 'the last', since the singly used line may go to either end, or indeed into the middle of the page.) In a dual SoPEC system, one of the SoPECs will be connected to 5 segments, while the other is connected to 6 segments. Focusing for a moment on the single SoPEC case. Sopec maintains a data generation rate of 6 bpc throughout the data calculation path. If all six data lines broadcast for the entire duration of a line, then each would need 10 to sustain 1 bpc to match SoPEC's internal processing rate. However, since there are eleven segments and six data lines, one of the lines has only a single segment attached. This dataline receives only half as much data during each print line as the other datalines. So if the broadcast rate on a line is 1 bpc, then we can only output at a sustained rate of 5.5 bpc, thus not matching the internal generation rate. These lines therefore need an output rate of at least 6/5.5 bpc. However, from an earlier version of the plan for the PHI and printheads the 15 dataline is set to transport data at 6/5 bpc, which is also a convenient clock to generate and thus has been retained. So, the datalines carry over one bit per cycle each. While their bandwidth is slightly more than is needed, the bandwidth needed is still slightly over 1 bpc, and whatever prepares the data for them must produce the data at over 1 bpc. To this end the LLU will target generating data at 2 bpc for each data line. 20 The LLU will have six data generators. Each data generator will produce the data from either a single segment, or two segments. In those cases where a generator is servicing multiple segments the data for one entire segment is generated before the next segment is generated. Each data generator will have a basic data production rate of 2 bpc, as discussed above. The data generators need to cater to variable segment width. The data generators will also need to cater for the full range of printhead designs currently considered plausible. 25 Dot data is generated and sent in increasing order. 8.1 PRINTHEAD FLEXIBILITY ISSUES The full range of printheads is discussed in Section 6. What has to be dealt with will be summarised here. The generators need to be able to cope with segments being vertically offset relative to each other. This could 30 be due to poor placement and assembly techniques, or due to each printhead being placed slightly above or below the previous printhead. They need to be able to cope with the segments being placed at mild slopes. The slopes being discussed and thus planned for are on the order of 5-10 lines across the width of the printhead. It is necessary to cope with printhead that have a single internal step of 3-10 lines thus avoiding the need for 35 continuous slope. To solve this we will reuse the mild sloping facility, but allow the distance stepped back to WO 2005/120835 PCT/AU2004/000706 967 be arbitrary, thus it would be several steps of one line in most mild sloping arrangements and one step of several lines in a single step printhead. SoPEC should cope with a broad range of printhead sizes. It is likely that the printheads used will be 1280 dots across. Note this is 640 dots/nozzles per half color. 5 8.2 COMMENTS WITH RESPECT TO THE CURRENT SPEC * If the printheads attempt to read from data that the DWU has not written (such as negative line addresses) this data will be pre-zeroed by some means prior to the print. o The basic diagram of the block can be altered. For example, instead of Odd/Even generators, there can be just six generators, where each generator processes all colours for the segments under its control. 10 * Registers list and descriptions have changed to support different LLU design. The new registers are discussed below. 8.3 NEW DESIGN 8.3.1 Dot generator A dot generator will process zero or one or two segments, based on a two bit configuration. When processing 15 a segment it will process the twelve half colors in order, color zero even first, then color zero odd, then color 1 even, etc. The LLU will know how long a segments is, and we will assume all segments are the same length. .To process a color of a segment the generator will need to load the correct word from dram. Each color will have a current base address, which is a pointer into the dot fifo for that color. Each segment has an address offset, which is added to the base address for the current color to find the first word of that colour. For each 20 generator we maintain a current address value, which is operated on to determine the location future reads occur from for that segment. Each segment also has a start bit index associated with it that tells it where in the first word it should start reading data from. A dot generator will hold a current 256 bit word it is operating on. It maintains a current index into that word. This bit index is maintained for the duration of one color (for one segment), it is incremented whenever data is 25 produced and reset to the segment specified value when a new color is started. 2 bits of data are produced for the PHI each cycle (subject to being ready and handshaking with the PHI). From the start of the segment each generator maintains a count, which counts the number of bits produced from the current line. The counter is loaded from a start-count value (from a table indexed by the half-color being processed) that is usually set to 0, but in the case of the A-B printhead, may be set to some other non 30 zero value. The LLU has a slope span value, which indicates how many dots may be produced before a change of line needs to occur. When this many dots have been produced by a dot generator, it will load a new data word and load 0 into the slope counter. The new word may be found by adding a dram address offset value held by the LLU. This value indicates the relative location of the new word; the same value serves for all segment and all colours. When the new word is loaded, the process continues from the current bit index, if WO 2005/120835 PCT/AU2004/000706 968 bits 62 and 63 had just been read from the old word (prior to slope induced change) then bits 64 and 65 would be used from the newly loaded word. When the current index reaches the end of the 256 bits current data word, a new word also needs to be loaded. The address for this value can be found by adding one to the current address. 5 It is possible that the slope counter and the bit index counter will force a read at the same time. In this case the address may be found by adding the slope read offset and one to the current address. Observe that if a single handshaking is use between the dot generators and the PHI then the slope counter as used above is identical between all 6 generators, i.e. it will hold the same counts and indicate loads at the same times. So a single slope counter can be used. However the read index differs for each generator (since 10 there is a segment configured start value. This means that when a generator encounters a 256-bit boundary in the data will also vary from generator to generator. 8.3.2 Line handling After all of the generators have calculated data for all of their segments the LLU should advance a line. This 15 involves signalling the consumption to the DWU, and incrementing all the base address pointers for each color. This increment will generally be done by adding an address offset the size of a line of data. However, to support a possible redundancy model for the printheads, we may need to get alternate lines from different offsets in the fifo. That is, we may print alternate lines on the page from different sets of nozzles in the print head. This is presented as only a single line of nozzles to the PHI and LLU, but the offset of that line with 20 respect to the leading edge of the printhead changes for alternating line. To support this incrementing the LLU stores two address offsets. These offsets are applied on alternate lines. In the normal case both these offsets will simply be programmed to the same value, which will equate to the line size. The fill level remains as currently described in 31.7.5. The LLU allows the current base addresses for each color to be writeable by the CPU. These registers will 25 then be set to point to appropriate locations with respect to the starting location used by the DWU, and the design of the printhead in question. 8.3.3 Configuration Each data generator needs 30 e A 2 bit description indicating how many segments it is dealing with. * Each segment (allowing for 12) requires: * A bit index (2 bit aligned) * A dram address offset. (indicates the relative location of the first address to be loaded to the current base address for that color WO 2005/120835 PCT/AU2004/000706 969 Each page/printhead configuration requires: " segment width (from the perspective of half colors so eg 640, not 1280) * slope span (dots counted before stepping) e start count [x12] (loaded into the slope counter at the start of the segment), typically 0 5 e slope step dram offset (distance to new word when a slope step occurs) e current color base address [x12] (writeable work registers) " line dram offset [x2] (address offset for current color base address for each alternating line) The following current registers remain: e Reset 10 0 Go e FifoReadThreshold, * FillLevel (work reg) Note each generator is specifically associated with two entries in the segment description tables. (So generator 0->0&1, 1->2&3, etc.) 15 The 2 bits indicating how many segments can be a counter, or just a mask. The latter may contribute to load balancing in some cases. 8.3.4 State Data generation involves 20 e a current nozzle count * a current slope count * a current data word. 0 a current index. * a current segment (of the two to choose from) 25 e future data words, pre-loaded by some means. 8.3.5 Address calculation and DIU issues. Firstly a word on bandwidth. The old LLU needed to load the full line of data once, so it needed to process at the same basic rate as the rest of SoPEC, that is 6 bpc. The new LLU loads data based on individual colors for 30 individual segments. A segment probably has 640 nozzles in it. At 256 bits per read, this is typically three reads. However obviously not all of what is read is used. At best we use all of two 256-bit reads, and 128 bits WO 2005/120835 PCT/AU2004/000706 970 of a third read. This results in a 6/5 wastage. So instead of 6bpc will would need to average 7.2 bpc over the line. If implemented, mild sloping would make this worse. 8.3.6 Address calculation 5 Dram reads are not instantaneous. As a result, the next word to be used by a generators should attempt to be loaded in advance, How do we do this? Consider a state the generator may be in. Say it has the address of the last word we loaded. It has the current index, into that word, as well as the current count versus the segment width and the current count used to handle sloping. By inspecting these variables we can readily determine if the next word to be read for a line 10 we are generating will be read because the slope count was reached or a 256-bit boundary was reached by the index, or both, or because the end of the segment was reached. Since we can make that determination, it is simple to calculate now the next word needed, instead of waiting until it is actually needed. Note with the possibility that the end of the segment will be reached before, or at, either slope or 256-bit effect, in which case the next read in based on the next color (or the next segment). 15 If that were all we did, it would facilitate double buffering, because whenever we loaded 256 bit data value into the generator we can deduce from the state at that time the next location to read from and start loading it. Given the potentially high bandwidth requirements for this block it is likely that a significant over-allocation of DIU slots would be needed to ensure timely delivery. This can be avoided by using more buffering as is done for the CFU. 20 On this topic, if the number of slots allocated is sufficiently high, it may be required that the LLU be able to access every second slot in a particular programming of the DIU. For this to occur, it needs to be able to lodge its next request before it has completed processing the prior request. i.e. after the ack it must be able to request instead of waiting for all the valids like the rest of the PEP units do. Consider having done the advance load as described above. Since we know why we did the load, it is a simple 25 matter to calculate the new index and slope count and dot count (vs printhead width) that would coincide with it being used. If we calculate these now and store them separately to the ones being used directly by the data generator, then we can use them to calculate the next word again. And continue doing this until we ran out of buffer allocation, at which point we could hold these values until the buffer was free. Thus if a certain size buffer were allocated to each data generator, it would be possible for it to fill it up with 30 advance reads, and maintain it in that state if enough bandwidth was allocated. One point not yet considered is the end-of-line. When the lookahead state says we have finished a color we can move to the next, and when it says we have finished the first of two segments, we can move to the next. But when we finished reading the last data of our last segment (whether two or one) we need to wait for the line based values to update before we can continue reading. This could be done after the last read, or before 35 the first read which ever is easier to recognize. So, when the read ahead for a generator realises it needs to WO 2005/120835 PCT/AU2004/000706 971 start a new line, it should set a bit. When all the non-idle generators have reached this start then the line advance actions take place. These include updating the color base address pointers, and pulsing the DWU. The above implies a fifo for each generator, of (3-4)x256 bits, and this may be a reasonable solution. It may in fact be smaller to have the advance data read into a common storage area, such as 1x6x256 bit for the 5 generators, and 12x256 bit for the storage area for example. 9. PHI 9.1 OVERVIEW The PHI has six input data lines and it needs to have a local buffer for this data. The data arrives at 2 bits per 10 cycle, needs to be stored in multiples of 8 bits for exporting, and will need to buffer at least a few of these bytes to assist the LLU, by making its continuous supply constraints much weaker. 9.2 OVERVIEW The PHI accepts data from the LLU, and transmits the data to the printheads. Each printhead is constructed 15 from a number of printhead segments. There are six transmission lines, each of which can be connected to two printhead segments, so up to 12 segments may be addressed. However, for A4 printing, only 11 segments are needed, so in a single SOPEC system, 11 segments will be connected. In a dual SOPEC system, each SOPEC will normally be connect to 5 or 6 segments. However, the PHI should cater for any arrangement of segments off its data lines. 20 Each data line performs 8b10b encoding. When transmitting data, this converts 8 bits of data to a 10 bit symbol for transmission. The encoding also support a number of Control characters, so the symbol to be sent is specified by a control bit and 8 data bits. When processing dot data, the control bit can be inferred to be zero. However, when sending command strings or passing on CPU instructions or writes to the printhead, the PHI will need to be given 9 bit values, allowing it to determine what to do with them. 25 The PHI accepts six 2-bit data lines from the LLU. These data lines can all run off the same enable and if so the PHI will only need to produce a single ready signal (or which fine grained protocol is selected). The PHI collects the 2-bit values from each line, and compiles them into 8-bit values for each line. These 8 bit values are store in a short fifo, and eventually fed to the encoder for transmission to printheads. There is a fixed mapping between the input lines and the output lines. The line are label 0 to 5 and they address segments 0 to 30 11. (0->[0,1] and 1->[2,3]). The connection requirements of the printheads are as follows. Each printhead has 1 LVDS clk input, 1 LVDS data input, 1 RstL input and one Data out line. The data out lines will combined to a single input back into the SOPEC (probably via the GPIO). The RstL needs to be driven by the board, so the printhead reset on power up, but should also be drivable by SOPEC (thus supporting differentiation for the printheads, this would also 35 be handled by GPIOs, and may require 2 of them.
WO 2005/120835 PCT/AU2004/000706 972 The data is transmitted to each printhead segment in a specified order. If more than one segment is connected to a given data line, then the entire data for one segment will be transmitted, then the data for the other segment. For a particular segment, a line consists of a series of nozzle rows. These consist of a control sequence to start 5 each color, followed by the data for that row of nozzles. This will typically be 80 bytes. The PHI is not told by the LLU when a row has ended, or when a line has ended, it maintains a count of the data from the LLU and compares it to a length register. If the LLU does not send used colors, the PHI also needs to know which colors aren't used, so it can respond appropriately. To avoid padding issues the LLU will always be programmed to provide a segment width that is a multiple of 8 bits. After sending all of the lines, the PHI will 10 wait for a line sync pulse (from the GPIO) and, when it arrives, send a line sync to all of the printheads. Line syncs handling has changed from PEC1 and will be described further below. It is possible that in addition to this the PHI may be required to tell the printhead the line sync period, to assist it in firing nozzles at the correct rate. To write to a particular printhead the PHI needs to write the message over the correct line, and address it to 15 the correct target segment on that line. Each line only supports two segments. They can be addressed separately or a broadcast address can be used to address them both. The line sync and if needed the period reporting portion of each line can be broadcast to every printhead, so broadcast address on every active line. The nozzle data portion needs to be line specific. Apart from these line related messages, SOPEC also needs to send other commands to the printheads. These 20 will be register read and write commands. The PHI needs to send these to specific segments or broadcast them, selected on a case by case basis. This is done by providing a data path from the CPU to the printheads via the PHI. The PHI holds a command stream the CPU has written, and sends these out over the data lines. These commands are inserted into the nozzle data streams being produced by the PHI, or into the gap between line syncs and the first nozzle line start. Each command terminates with a resume nozzle data instruction. 25 CPU instructions are inserted into the dot data stream to the printhead. Sometimes these instructions will be for particular printheads, and thus go out over single data line. If the LLU has a single handshaking line then the benefit of stalling only on will be limited to the depth of the fifo of data coming from the LLU. However there if a number of short commands are sent to different printheads they could effectively mask each other by taking turns to load the fifo corresponding to that segment. In some cases, the benefit in time may not warrant 30 the additional complexity, since with single handshaking and good cross segment synchronisation, all the fifo logic can be simplified and such register writes are unlikely to be numerous. If there is multiple handshaking with the LLU, then stalling a single line while the CPU borrows it is simple and a good idea. 9.3 TRANSPORT LAYER 35 The data is sent via LVDS lines to the printhead. The data is 8blOb encoded to include lots of edges, to assist in sampling the data at the correct point. The line requires continuous supply of symbols, so when not sending data the PHI must send Idle commands. Additionally the line is scrambled using a self-synchronising WO 2005/120835 PCT/AU2004/000706 973 scrambler. This is to reduce emissions when broadcast long sequences of identical data, as would be the case when idling between lines. See printhead doc for more info. 9.4 CPU SECTION 5 9.5 LINE SYNC SECTION It is possible that when a line sync pulse arrives at the PHI that not all the data has finished being sent to the printheads. If the PHI were to forward this signal on then it would result in an incorrect print of that line, which is an error condition. This would indicate a buffer underflow in PEC1. However, in SoPEC the printhead can only receive line sync signals from the SOPEC providing them data. Thus it is possible that the 10 PHI could delay in sending the line sync pulse until it had finished providing data to the printheads. The effect of this would be a line that is printed very slightly after where it should be printed. In a single SOPEC system the this effect would probably not be noticeable, since all printhead would have undergone the same delay. In a multi-SoPEC system delays would cause a difference in the location of the lines, if the delay was great this may be noticeable. So, rather than entering an error state when a line sync arrive prior to sending the line, we 15 will simply record its arrival and send it as soon as possible. If a single line sync is early (with respect to data processing completing) than it will be sent out with a delay, however it is likely the next line sync will arrive early as well. If the reason for this is mechanical, such as the paper is moving too fast, then it is conceivable that a line sync may arrive at a point in which a line sync is currently pending, so we would have. two pending. Whether or not this is an error condition may be printer specific, so rather than forcing it to be an error 20 condition, the PHI will allow a substantial number of pending line syncs. To assist in making sure no error condition has arrived in a specific system, the PHI will be configured to raise an interrupt when the number pending exceeds a programmed value. The PHI continues as normal, handling the pending line sync as before, it is up to the CPU to deal with the possibility this is an error case. This means a system may be programmed to notice a single line sync that is only a few cycles early, or to remain unaware of being several lines behind 25 where it is supposed to be. The register counting the number of pending line syncs should be 10+ bits and should saturate if incremented past that. Given that line syncs aren't necessarily performing any synchronisation it may be preferrable to rename them, perhaps line fire. As in PEC 1 there is a need to set a limiting speed. This could be done at the generation point, but since motor control may be a share responsibility with the OEM, it is safer to place a limiting factor in the PHI. 30 Consequently the PHI will have a register which is the minimum time allowed between it sending line syncs. If this time has not expire when a line sync would have otherwise been sent, then the line remains pending, as above, until the minimum period has passed. 9.6 CONFIG. PHI NEEDS 35 A Segment width in nozzles.
WO 2005/120835 PCT/AU2004/000706 974 Optionally a six bit mask of active lines. Segment IPresent bit: describes if data should be generated for segments 0 & 1, or just segment 0 of each line. A "colors present" count. Optionally a 12 bit mask showing the presence of each segment. 5 Command array, containing symbols for printhead instructions the PHI needs to know. Can be 10 x 9-bit. Command sequences The printhead will support a small range of activities. Most likely these include register reads and writes and line fire actions. The encoding scheme being used between the PHI and the printhead sends 10 bits symbols, 10 which decode to either 8 bit data values or to a small number of non-data symbols. The symbols can be used to form command sequences. For example, a 16-bit register write might take the form of <WRITE SYMBOL><data regaddr> <data valuel><data value2>. More generally, a command sequence will be considered to be a string of symbols and data of fixed length, which starts with a non-data symbol and which has a known effect on the printhead. This definition covers write, reads, line syncs, idle indicators, etc. 15 Unfortunately there are a lot of symbols and data to be sent in a typical page. There is a trade-off that can be made between the lengths of command sequences and their resistance to isolated bit errors. Clearly, resisting isolated bit errors in the communications link is a good thing, but reducing overhead sent with each line is also a good thing. Since noise data for this line is difficult to guess in advance, and the tolerance for print 20 failure may vary from system to system, as will the tolerance for communication overhead, the PHI will try to approach it requirements in a very general way. Rather than defining at this point the specific content and structure of the command sequences the printhead will accept, instead we will define the general nature, and the specific purpose of each command that the PHI 25 needs to know about. General Line Processing The PHI has a bit mask of active segments. It processes the data for the line in two halves: the even segments and then the odd segments. If none of the bits are set for a particular half, then it is skipped. 30 Processing of segment data involves collecting data from the LLU, collating it, and passing through the encoder, wrapped in appropriate command sequences. If the PHI was required to transmit register addresses of each nozzle line, prior to sending the data, then it would need either storage for twenty four command strings (one for each nozzle row on each segment for a wire), or it would need to be able to calculate the string to send, which would require setting that protocol exactly. Instead, printheads will accept a "start of WO 2005/120835 PCT/AU2004/000706 975 next nozzle data" command sequence, which instruct the printhead that the following bytes are data for the next nozzle row. This command sequence needs to be printhead specific, so only one of the two printheads on any particular line will start listen for nozzle data. Thus to send a line's worth of data to a particular segment one needs to, for each color in the printhead, send a StartNextNozzleRow string followed by SegmentWidth 5 bytes of data. When sending nozzle data, if the supply of data fails, the IDLE command sequence should be inserted. If necessary this can be inserted many times. After sending all of the data to one segment, data is then sent to the other segment. After all the nozzle data is sent to both printhead the PHI should issue IDLE command sequences until it receives a line sync pulse. At this point it should send the LineSync command sequence and start the next line. 10 The PHI has six data out lines. Each of these needs a fifo. To avoid having six separate fifo management circuits, the PHI will process the data for each line in synch with the other lines. To allow this the same number of symbols must be placed into each fifo at a time. For the nozzle data this is managed by having the PHI unaware of which segments actually exist, it only needs to know if any have two segments. If any have two segments, then it produces two segments worth of data onto every active line. If adding command data 15 from the CPU to a specific fifo then we insert Idle command sequences into each of the other fifos so that an equal number of byte have been sent. It is likely that the IDLE command sequence will be a single symbol, if it isn't then this would require that all CPU command sequences were a multiple of the length of the IDLE sequence. This guarantee has been given by the printhead designers. 20 9.7 LINE SYNC PERIODS The PHI may need to tell the printheads how long the line syncs are. It is possible that the printheads will determine this for themselves, this would involve counting the time since the last lsync. This would make it difficult to get the first line correct on a page and require that the first line be all zeroes, or otherwise tolerant of being only partially fired. 25 Other options include: PHI calculated and transmits a period with each line sync. the PCU calculates a period and writes it to the printheads occasionally. the line fire command includes a line sync period (again written by the CPU or perhaps calculated by the PHI. 30 FREQUENCY MODIFIER ALGORITHM STUDY I INTRODUCTION The frequency modifier is required to alter the pulse rate from an optical encoder used to monitor the printer speed. The output rate will then be used to trigger the printing of a new line. Due to mechanical jitter, input 35 pulses will not be evenly spaced. High frequency jitter should be filtered out by the modifier leaving it to track the remaining jitter.
WO 2005/120835 PCT/AU2004/000706 976 A secondary requirement is to provide an output which is proportional to frequency that can be used by the motor control loop. Key specification * Input frequency range 500Hz to 10kHz 5 e Frequency multiplication factor 1-6 * FM output jitter <0.2% e Lock within 20 input cycles e Long term (1 page) output frequency accuracy typ. ±0.01% ±0.1% max. * Filter dependant characteristics 10 - Cut off frequency F, programmable 0.01-1 x input frequency - Settling time <=(1/F,) - Output frequency overshoot <5% Several possible solutions were considered. Firstly, a PLL was studied but the characteristics were found to vary significantly over the 10:1 input frequency range making it unsuitable. Secondly, a scheme which 15 avoided calculating frequency (an unpleasant l/X calculation) was modelled which involved filtering in the period domain. The 1/X non-linearity gave rise to an asymetric transient response which would be different depending on the sense of a frequency step which was considered to be undesirable. The scheme described here requires a calculation of K/X thus providing and output proportional to frequency and good transient behaviour. 20 2 IMPLEMENTATION System clock cycles are counted over the period between input pulses resulting in count P. The calculation K/P, where K is a constant, results in an output proportional to instantaneous frequency. This is low pass filtered to attenuate input jitter and then multiplied by M, the output frequency multiplier (which may also be 25 achieved by changing the filter gain). The resulting signal controls the frequency of the NCO which may be divided by the output divider in order to reduce the size of the NCO accumulator. The system clock Fy, is expected to be 192MHz. 2.1 AccURACY The accuracy requirements for each block impact on the hardware gate count or CPU cycle count so should be 30 minimised/optimised to achieve the target output frequency accuracy.
WO 2005/120835 PCT/AU2004/000706 977 2.1.1 Period measurement and NCO The period measurement accuracy will be lowest for the highest frequency, currently 10kHz. The period count will then be 192MHz/lOkHz = 19200 resulting in an accuracy of 0.0052% The long term output frequency accuracy will only be limited by the precision of the calculations following 5 the period measurement (and the measurement itself). The NCO can only produce jitter free output frequencies which are an integer division of FYy Fractional frequencies are derived by alternating between adjacent integer divisions. The worst case accuracy is for the highest output frequency which will be 6 x 10kHz = 60kHz resulting in an accuracy of 0.0313%. Assuming frequency errors only due to the period measurement and NCO, F,,, F FoWtL = ssFouIH F / ceil floor MX ceil -F-] Mxfloor Y)] 10 ' F) 1 1 Fi These equations are plotted below for F.y = 192MHz and M = 6. The division K/P requires a sufficiently large K to preserve the accuracy of P but the least accurate result is obtained for the most accurate (largest) value of P. For K = 2^32, and P=384000, the error will be about 15 0.0089% which is greater than the 0.0052% maximum error for P. However, since the overall accuracy required is 0.5%, K can be reduced. Kbitmin = ceil Iog2( sYs x For Fi 1 m. = 500Hz, tol = 0.5%, Kbimin = 27 bits (or 26 bits if rounding can be applied) assuming no other significant sources of error. Reducing K will reduce the computational effort for K/P and the result can be 20 represented by 13 bits. Accounting for K and rounding, FouL= F,,,/(ceil(K/(M xfloor(0.5 + K/(ceil(F,,,/F,)))))) FoutH -Fy/(foor(K(M xfloor(0.5 + K/(floor(F,,,/F;,)))))) This is plotted below for F.y = 192MHz and M = 6. 25 A further bit could be saved by relaxing the specification to 0.56%. The NCO accumulator can be reduced by increasing its speed and dividing down after; the maximum allowable frequency being Fy/2. Also, the simplest NCO counts modulo 2^N as does the divider. The maximum output frequency required after division is 60kHz.
WO 2005/120835 PCT/AU2004/000706 978 Division of Fsys/2 for 60kHz is 1600 so choose 1024 requiring 10 bits (D) in the divider. The NCO would then run at 1024 x 60kHz = 61.44MHz. The width of the NCO is then K-D = 27 -10 = 17 bits. The accuracy of both the period measurement and NCO are better than required with F.y. = 192MHz. The limiting factor is the output jitter specification of <0.2% (taken to mean peak). Reducing F.y. by 4 to 48MHz 5 will result in worst case output jitter of ±0.146%. K can also be reduced by 2 bits so that the low and high frequency accuracy are the same as shown in Figure 326. 2.1.2 Filter The accuracy of the filter required will depend on the actual filter coefficients used and the Q's of the filter poles (distance from the unit circle on the Z-plane). Low Q poles are usd to meet the overshoot requirement of 10 <5% and so internal signal swings and coefficient accuracy are moderate. Since there is no requirement for linear phase, it is be assumed that IIR filters can be used as these usually require less computation than an equivalent FIR filter. These can then be built from general purpose biquad sections; a second order section may be sufficent and can provide 2 poles (complex conjugate pair) and 2 H(z) = bO+b1z +b2z~ zeroes with the transfer function :- I + aIz- + a2z 15 (Note that the use of a's and b's in numerator and denominator varies in the literature) The direct form II of this filter is popular since a common shift register is used for both numerator and denominator calculation. The overall filter gain can be scaled by multiplying the b coefficients by a constant; in this case M. The internal gain at points A and B needs to be checked to ensure there is sufficient overhead in the word 20 lengths used. An example is shown for a 2nd order Butterworth filter with F, = 0.125 with al=0.941753, a2= 0.332960, bO=0.097802, bl=0.195603, b2=0.097802. The recursive part of the filter needs to be handled correctly; the two adders to the left shown with bars (Figure 327) need to saturate to prevent overflow (and underflow). The result needs to be truncated and rounded so as to limit the precision in the recursive loop. 25 If a full scale input were applied to this filter, at least an additional 2 bits is needed internally to avoid overflow. Alternatively, the input level can be reduced with loss of precision. The filter internal gain is inversely proportional to the normalised cut off frequency so the lowest cut off required will determine the number of internal bits and coefficient wordlength. A Butterworth filter with a normalised cut-off frequency of 0.01, intended to represent the likely lower limit, 30 has been simulated. This requires 20 bits of internal precision, 16 bit coefficients and an allowance of 9 bits for internal gain. H(0) = bO+bl +b2 The dc gain of the filter is 1 - a1 - a2 (accounting for the sign of a's) WO 2005/120835 PCT/AU2004/000706 979 For the filter to be stable, the gain around the recursive part must be less than 1 so that (al+a2) < 1. Table 224 Butterworth filter coefficients Cut-off a1 A2 bO b1 b2 Lim- ->-2 ->-1 ->1 ->2 ->1 >0.5 0.2 0.368189 - 0.206863 2*bO bO 0.195640 0.1 1.142078 - 0.067581 2*bO bO 0.412403 0.05 1.752252 - 0.006869 2*bO bO 0.779727 0.01 1.911091 - 0.000947 2*bO bO 0.914879 0.005 1.955525 - 0.000242 2*bO bO 0.956493 Lim->0 ->2 ->-1 ->0 ->0 ->0 The lower the cut-off frequency, the higher the internal gain due to the demominator. For low cut-off frequencies, the largest signal occurs after multiplication by al. The largest number that has to be 5 accomodated is then al/(1-al-a2). If a cut-off frequency of 0.005 were to be used (with a full scale input representing an encoder frequency of 20kHz), then the maximum internal level is 2020 x the input level requiring 11 extra bits. The limit cases above also hold true for elliptic and Chebyshev type I filters (and probably other common filter types under extreme conditions). 10 The most important factor in determining the filter accuracy is how its gain changes as a function of input level; fixed gain errors can be trimmed elsewhere or the coefficients adjusted for less quantisation error (with some small error in cut-off frequency). The input level is swept from 1 (full scale) to 0.01 for an input word length of 19 bits showing a gain error of < 0.01%. For each setting of input level, a step response simulation was performed allowing the output to 15 settle before measuring the level. 2.1.3 Printed accuracy An A4 page is 30cm long and at 1600dpi, will require 18.9K lines full bleed. An ideal target of 0.01% cumulative error (scaling error in M) over the page has been set although 0.1% should be acceptable. Error in the accuracy of the NCO does not accumulate over time; in fact the mean value will become more accurate 20 when averaged over a longer period. The period measurement is also expected to become more accurate when averaged over time. Cumulative error will result in gain errors due to the calculation of K/P and the accuracy WO 2005/120835 PCT/AU2004/000706 980 of the filter coefficients. Also, M needs to be quantised far more accurately than fractional increments of 0.1 given in the first version of the specification (which would result in an error of 10% worst case). A clock frequency of 192MHz will therefore be used and K increased to 32 bits. With an input frequency of 10KHz and M =1.9, the short term accuracy will be 0.015%. The filter dc gain should be accurate to within 5 0.005dB. 3 MATLAB MODEL The frequency modifier has been modelled in Matlab with a typical result shown in Figure 330. This shows the response to an input step frequency from 0.5kHz to 10kHz using a single pole filter with a 10 normalised cut off frequency of 0.25 and Fy = 48MHz. The upper trace shows the instantaneous output frequency and input frequency multiplied by M = 6 for reference. Input and output pulses are plotted in the lower trace. Figure 331 shows the quantisation of output frequency following a ramping input frequency. 3.1 CUMULATIVE ERROR 15 A long (1 page = 1 second) simulation was used to check if there was any systematic error in the period measurement and NCO parts of the algorithm (Figure 333). The encoder frequency of 3.4kHz was generated by an NCO and measured using a system clock of 192MHz. The result is multiplied (mathematically) by 6 to produce Fm and Fu, is the measured output frequency. The histogram shows that both Fm and F 0 ,, are approximated by two discrete frequencies (quantisation due to 20 sampling); note that the spread of F., = 6 x the spread of Fi. Furthermore, the other bins in the histogram are empty The mean of Fm and F,,, are also calculated to determine Fm.r = (F,,t - F )/Fe which is the cumulative frequency error measured over 1 second. The cumulative error with filtering has been simulated with a stepped frequency input. Since the filter 25 response time depends on the encoder frequency, a step down in frequency will take longer to settle than a step up resulting in a mean output frequency error. A single pole filter with a normallised cut-off frequency of 0.01 was used. The mean frequency needs to be measured over an integer number of cycles to ensure no errors due to including part of a cycle. The above shows a step frequency increase by 10% from 20kHz to 22kHz. This resulted in a mean frequency error of 30 0.0675% measured over the last 80% of the simulation. Note that this error does not accumulate. With a frequency step of 1%, the frequency error was found to be 0.000627% indicating the error is proportional to the area under the frequency error curve. 4 HARDWARE SPECIFICATION 35 Assumption - data from the encoder has been deglitched WO 2005/120835 PCT/AU2004/000706 981 4.1 BIT ALLOCATION Table 225 Signals Meaning P Period count K Division constant F Frequency estimate = K/P C Filter coefficient (signed) B Filter states (delay elements) N NCO input (no output divider) Table 226 Bit allocation (dec) 3 3 2 2 7 2 2 2 2 2 2 2 1 1 111 0 9 8765 4 3 2 1 0 9 8 7 6j PIP PIP P P P IP P IP IP P IP IP P P IP P IP K 1K K K K K 1K 1K 1K 1K K KKK K 1K K 1K 1K 1K K K K 1K IK K K K 1K IK K K OFF FFF FFF F F FF F F F FF F F CCCCCCCCCCCCCCCCCCCCC B BBBBB BB B B B B B B B B B B B B B B B B B B B B 0 0 0000 0 0 0 N N NNNNNN N N N N N N N N N N N Coefficients will be in the range -2 < C <+2 with the top MSB being the sign bit. Bits of B to the left of the 5 decimal point are to handle the maximum internal gain of the filter. The encoder frequency input to the frequency modifier may be divided (externally) and the NCO accumulator length programmed allowing optimum use of the available dynamic range of the filter. With K=2^32 - 1, 19 bits will allow the NCO to operate over the range 0 - 23.44kHz. 4.2 ARITHMETIC UNIT 10 A time shared accumulator will be able to perform the division K/P and the filter computations (MAC). For the biquad, 2 state and 5 coefficient registers are required. A temporary storage register will be needed to hold the result of the K/P calculation as input to the biquad and 3 temporary registers for intermediate biquad calculations. Left and right shifting may also be needed to optimise input signal scaling to the biquad. Optionally, some or all the (slow) calculation may be performed in software. Thus, the output of the period 15 measurement counter could be sent to the CPU which will calculate K/P which is needed for motor control.
WO 2005/120835 PCT/AU2004/000706 982 The result is either output to the filter hardware or the filter calculated in software. In both cases, a result needs to be written to a register which can be read by the hardware. Note (Period threshold to add in div2 if > 5kHz) 4.2.1 Division 5 Since both K and A will be positive numbers, division is more straightforward than multiplication. 4.2.2 Multiplication For the biquad, input samples will always be positive and coefficients may be positive or negative. However, internal states may be bipolar. It may be simpler to represent the coefficients in sign magnitude and the data in 2's complement. Coefficients are then placed in the A register and data in the B register. 10 The adder/subtractor must saturate in the event of an overflow/underflow. 4.3 PERIOD COUNTER AND DIVIDE BY 1 OR 2 Count cycles of the system clock. On receiving a rising edge from the encoder (Refedge) transfer the count to a holding register and reset the counter to 1 (not 0). The counter should saturate at periodMax=2^19 -1 and flag an error. If the period is less than periodMin, set the holding register to periodMin and flag an error. 15 The divide by 1 or 2 counter is used to limit the interrupt rate to the CPU. If the input frequency is measured to be >5kHz, the input is divided by 2; the output of the period counter is corrected for this. Note that in all the following pseudocode, execution is sequential and not concurrent. %divide by 1 or 2 20 if div2d>O div2=div2d- 1; else div2=endiv2; end; 25 if Refedge=1 div2d=div2; end; carrydiv2=Refedge&(div2d=0); 30 %Period counter if carrydiv2=0; if carryN= 1; percnt=percnt+1; %Will need saturation end; 35 else if endiv2 I %Correct period for div by 2 WO 2005/120835 PCT/AU2004/000706 983 period=floor(percnt/2); %Is this ok? else period=perent; %Transfer result to reg period end; 5 perent=1; end; if period>periodMax %Saturate period=periodMax; end; 10 if period<=periodMin %Lower limit period=periodMin; end; if period<fivek endiv2=l&CPUfilt; 15 else endiv2=0; end; 4.4 BIQUAD FILTER 20 The filter updates as new input edges arrive. Note that the multiplication factor M will be built into the coefficients bO, bI and b2. if canydiv2== z2=zl; 25 zl=zO; zO=Fest(i)+al *zl+a2*z2; Yo=bO*zO+bl *zl+b2*z2; end; 30 4.5 NCO AND OUTPUT DIVIDER Out is the 2^wordlength of the output divider = 210- 1. The input multiplexer is not coded. %NCO (fowards only) NCO=NCOd+Filtout; 35 if NCO>=K/Out-I NCO=NCO-K/Out; end; %NCO edge detector (forwards only) 40 if NCOd>NCO WO 2005/120835 PCT/AU2004/000706 984 NCOedge=l; else NCOedge=O; end; 5 NCOd=NCO; %Output divider if divoutd>0 divout=divoutd-1; 10 else divout=Out-1; end; if NCOedge== divoutd=divout; 15 end; carryOut=NCOedge&(divoutd=0); 1 RESETS INTRODUCTION 20 The following sections specify the reset requirements for the SoPEC ASIC and SoPEC-based systems. It presents a solution designed to meet all the requirements. REQUIREMENTS 2 RESET REQUIREMENTS 25 2.1 SoPEC DEVICES The requirements for resetting the SoPEC ASIC are as follows: e SoPEC needs to be able to generate its own power-on-reset because it may be the system master, and it is therefore possible, and potentially more cost effective, that no external reset will be supplied. The power-on-reset may happen before the bufrefclk is running. Therefore, this event 30 needs to be asynchronously trapped, and then acted-upon as soon as the clock starts running. * SoPEC also needs to be able to protect itself, and the system, during a brown-out event. To this end, it is required to monitor the unregulated power supply, with the assumption that it will exhibit the brown-out sooner than Vce,. e If a brown-out event occurs, the event must remain active for at least 10Os before SoPEC resets 35 itself (providing 100 s of deglitching on the reset event). Beyon 100ps, if the event remains active, SoPEC will continue to be held in reset, until the 100ps after the event has been cleared. * SoPEC requires a fail-safe mechanism, in case the internal analog reset circuitry is found to be defective. Another pin may be used to allow this circuitry to be bypassed.
WO 2005/120835 PCT/AU2004/000706 985 - SoPEC must provide a means for allowing itself to be reset by an external device. It must provide deglitching of the external reset, similar to that provided for the brown-out detection. 2.2 SoPEC-BASED SYSTEMS The reset requirements for systems containing SoPEC device(s) are as follows: 5 - If no external reset source is supplied, then SoPEC should be able to distribute its own internally generated reset to the rest of the system, and so there is a need for a reset-out pad, which can also support SoPEC resetting the system through software. As well as directly resetting other system devices, this signal can be used to cycle the power on the QA chips, forcing them to reset themselves. 10 - The printhead segments require special consideration for reset purposes. It is preferable to have them remain reset as soon as the system begins powering up and during brown-out. Also, there is a requirement to reset even-numbered printhead segments together, and likewise for the odd numbered ones. So, two separate outputs are required to achieve this. These outputs should also be software controllable so that SoPEC can determine which group of printheads are reset, and when. 15 Figure 342 presents a diagram of the overall solution designed to meet all of the reset requirements. The following sections discuss in more detail, the various components making up the solution. Solutions 20 3 POWER-ON-RESET DETECTION This section presents the requirements and a solution for the internal power-on-reset detection functionality. 3.1 FUNCTIONAL REQUIREMENTS The functionality of the power-on-reset detection circuit can be summarised as follows: * Where the supply voltage is rising, the output of the circuit must transition from 0 to 1 at a voltage 25 threshold where the core standard cell logic is able to record this transition. * While the core voltage remains above the threshold, the output of the detection circuit must remain stable at 1. * If the core voltage drops below the threshold voltage, then the circuit's output must drop back to 0, permitting the device to be reset correctly if the core voltage rises again. 30 The waveforms in Figure 337 show the functionality that is required for the power-on-reset detection circuit within SoPEC.
WO 2005/120835 PCT/AU2004/000706 986 3.2 PROPOSED SOLUTION The existing POR macro from IBM is capable of achieving the power-up part of requirement. However, it must be modified in order for its output to fall back to 0 if the core voltage drops below the threshold. Removing the output stages that "clamp" the POR macro output to Vdd is sufficient for the macro to behave as 5 shown above. Note that this change will also meet a requirement of the brown-out detection circuit. 3.3 SPECIAL CONSIDERATIONS 3.3.1 Glitch protection Because the output of the power-on-reset detection can (and most likely will) be active long before the 10 internal clock of the device is active, the fact that the circuit's output was 0 must be recorded asynchronously. This is achieved by using the POR macro's output to asynchronously clear a flip-flop, as shown in Figure 342. Because there is no guarantee that the clocks are running when the macro indicates that the core voltage has risen, it is not possible to deglitch, by digital means, this circuit's output. This means that glitches on the core voltage will reset the entire device, and anything connected to SoPEC's output reset pins. 15 Therefore, it may be desirable to place this macro in an area of the chip where it will be exposed to less noise, e.g. away from high-speed switching I/Os. 3.3.2 Test pin This circuit requires a dedicated input test pin, to facilitate in-package testing. There is the possibility that this input pin can be driven by an external source, in functional mode. This may 20 provide a means of using a reset from an external source which does not need to be deglitched. 4 BROWN-OUT DETECTION This section presents the requirements and a solution for the internal brown-out detection functionality. 4.1 FUNCTIONAL REQUIREMENTS 25 The functionality of the brown-out detection circuit can be summarised as follows: * The circuit must monitor a divided-down version, V,,, of the unregulated power supply. * If the V,,p input falls below the threshold (the same as that of the POR macro), then the output must drop to 0, and remain at 0 while V,,,p is lower than the threshold. * If Vcomp rises above the threshold, then the output must go to 1 and remain there while Vmp is 30 above the threshold.
WO 2005/120835 PCT/AU2004/000706 987 4.2 PROPOSED SOLUTION It is proposed to use a modified version of the existing IBM POR macro to meet the requirements for brown out detection. If the existing POR macro is modified to allow its output to drop to 0 when the voltage falls below the 5 threshold, then the same modified macro can be used to achieve the behaviour required for the brown-out detection. As shown in Figure 339, the + input of the comparator must be hooked up to the input Vop pad to allow the external unregulated supply to be monitored. The internal voltage divider, that is present on this comparator input, needs to be disconnected. 10 4.3 SPECIAL CONSIDERATIONS 4.3.1 Vcomp input voltages The voltage range on this pin needs to be flexible to suit a number of power-supply configurations. It is intended that the maximum operational voltage on this input will be 3.6V, in accordance with recommendations from discussions with IBM. The brown-out circuit therefore requires 3.6V ESD protection, 15 with a thick oxide comparator differential pair. A standard 3.3V analog input pad should be sufficient for the Veop input. Appendix A contains an analysis of the expected behaviour of the modified macro in brown-out situations, with Vomp derived from different unregulated supply voltages. Note that the maximum voltage that will be applied to this pin will never exceed 3.6V. 20 If brown-out detection is required, then this input will be driven by an external resistive voltage divider, in order to ensure that the voltage on this pin drops below the diode voltage thresold, during a brown-out event. If brown-out detection is not required, then this pin will be tied to 1.5V, thereby causing the output of the brown-out comparator to go to 1. 4.3.2 Test pin 25 This circuit requires a dedicated input test pin, to facilitate in-package testing. 5 BYPASS MODE AND EXTERNAL RESET 5.1 FUNCTIONAL REQUIREMENTS A fail-safe mechanism must be provided to allow the analog reset circuits to be bypassed, and an external 30 source to be used to reset the device.
WO 2005/120835 PCT/AU2004/000706 988 5.2 PROPOSED SOLUTION An input macro-disable pin, with an internal pull-down resistor, will be used to allow the outputs of both analog reset circuits to be disabled. This pin only needs to be hooked up externally if there is a problem with either of the analog reset circuits. 5 A separate input pin, reset n, will be used for the purposes of providing an external reset to SoPEC. Any source that is driving the reset n pin is required to ensure that it activates the reset for long enough for SoPEC's internal PLL is to start running (which can take of the order of l0ms, following power-up), and for the deglitch circuit to then establish that the external reset has been active for at least 100 [0s. It is not proposed to allow just one of the internal reset circuits to be active, but the other bypassed. Instead, 10 where either of these circuits is not functioning appropriately, both will be bypassed, and the provision of power-on-reset and brown-out protection will be carried out by an external source, via the resetn input of SoPEC. Note that the external reset can be used, regardless of whether the internal analog reset circuits are bypassed or not. 15 6 DEGLITCHING This section outlines the requirements for deglitching of the various reset-related signals within SoPEC. 6.1 FUNCTIONAL REQUIREMENTS * As shown in Figure 340, the deglitch circuit must activate the internal reset of SoPEC, resetlnt_n, if the POR macro output goes to 0. It should hold resetlntn active for 10O s, before deactivating it 20 (assuming that the POR output is no longer active). This functionality is simply intended to provide 100s of settling time for the core voltage. * Note that bufrefclk may not be active when the core voltage has risen above the threshold. For this reason, the deglitch circuit must asynchronously capture any transition to 0 that happens on the output of the POR macro, and react appropriately when bufrefclk becomes active. 25 - As shown in Figure 341, the deglitch circuit must provide deglitching of the brown-out detection circuit's output, by checking that it has been at 0 for at least 100ps before activating the internal reset. It should continue to hold resetlntn active for 100ps following a transition to 1 of the brown-out detection output. " The deglitch circuit must also provide deglitching of the external reset, resetn, by checking that it 30 has been held at 0 for at least 100ps before activating the internal reset. It should continue to hold resetlntn active for 100ps following a transition to 1 of resetn.
WO 2005/120835 PCT/AU2004/000706 989 6.2 PROPOSED SOLUTION This section contains sample pseudo code for the state machine used to deglitch the brown-out and external reset signals, and to extend the reset activation time following a power-on-reset. It is envisaged that this counter and state-machine logic, along with any other standard-cell logic required for 5 the entire solution shown in Figure 342, will be contained within SoPEC's CPR module. if (porClrResyncn == 0) # Reset the state machine following power-up state 4- activate_poweronreset count <- 0 resetInt_n 4-- 0 # Using an active low internal reset 10 endif idle resetIntn 4- 1 count <-- 0 15 state <- idle if (porClrResync_n == 0) state <- activate-poweron_reset elsif (extResetResyncn == 0) state <-- falling_extreset 20 elsif (boResyncn == 0) state +- falling_bo endif # Activate the internal reset if (and while) porClrResyncn is 0. 25 # When porClrResync-n goes to 1, hold the reset active for a further 100ps activatepower_on.reset resetIntn <-0# Continue to hold the internal reset active count +- 0 state <- activate-poweron_reset 30 if ( porClrResync-n == 1) # POR has been deasserted if ( count + 100ps) state <-- activate-power_on_reset resetIntn <-0# Continue to hold the internal reset active for 100ps count <-count+1 35 else state <- idle endif endif 40 # If boResyncn goes to 0, deglitch before activating internal reset falling_bo resetInt_n <-- 1 # Hold inactive until the required time has been reached state +- idle if (boResyncn == 0) # While boResync-n remains low, increment count 45 if ( count * 100ps) state <- falling-bo count <-count+1 else state +- activate_bo_reset 50 count <-0 endif endif # Generate the reset due to brown-out internally for at least 100ps 55 activatebo_reset if (boResync n == 0) # If brown-out is still active, hold reset active count <-0 resetInt-n <-0# Continue to hold the internal reset active state +- activate_bo_reset 60 elsif ( count # 100ps) # Hold reset active for 100ps after brown-out clears state +- activatebo_reset WO 2005/120835 PCT/AU2004/000706 990 resetIntn <-O# Hold the internal reset active for 100s count <- count +1 else state <- idle 5 endif # If extResetResyncfn goes to 0, deglitch before activating internal reset falling_ext_reset resetInt-n <-- 1 # Hold inactive until the required time has been reached 10 state <-- idle if (extResetResync-n == 0) # While extResetResync_n remains low, inc. count if ( count # 100ps) state <- fallingextreset 15 count <-count + 1 else state <- activateextreset count <--0 endif 20 endif # Generate the reset due to brown-out internally for at least 100gs activateext.reset if (extResetResyncn == 0) # If ext. reset is still active, hold reset 25 active count <--0 resetIntn <-0# Continue to hold the internal reset active state <-- activate-ext-reset elsif ( count # 100s) # Hold reset active for 100ps after ext reset 30 clears state <-- activate_extreset resetIntn <-0# Hold the internal reset active for 100gs count (--count+ 1 else 35 state <- idle endif 6.3 SPECIAL CONSIDERATIONS 40 6.3.1 DEGLITCH TIME PERIOD There may be a strong argument for making the deglitch time a metal-programmable feature, in case the deglitch time needs to be extended (counter then has to be designed to be large enough to handle the possibility of the time being increased up to say, 100ms). 6.3.2 Test mux 45 A test mux needs to be added to allow the asynchronously resettable register, which captures the fact that the power-on-reset detection circuit's output was 0 before bufrefclk was running, to be fully controllable during test mode. Overall Solution WO 2005/120835 PCT/AU2004/000706 991 7 TOP-LEVEL RESET CIRCUIT 7.1 TOP-LEVEL SCHEMATIC Figure 342 presents the overall solution to the requirements, and shows how the various sub-solutions, outlined in the previous sections, relate to each other. 5 7.2 SIGNAL Table 227:Description of signals presented in Figure 342 Port Name PadDecito Type External Ports VComp Analog Input voltage for brown-out detection comparator. If the voltage on Input this input, which is derived from the unregulated power supply, 3.3V drops below the output of the voltage reference circuit, then the output of the comparator is set low. resetn Input This active-low signal can be used to provide an external reset to 3.3V SoPEC. Schmitt This signal must be activated long enough to ensure that SoPEC's trigger. internal PLL is running (taking of the order of 1 Oms on power-up) so that this signal can be deglitched for 1000s. por_test Input This is a signal for the in-package testing of the IBM POR macro. 1.5V botest Input This is a signal for the in-package testing of the IBM macro, 1.5V modified for brown-out detection. macrodisabl Input This active high signal allows the analog power-on-reset and e 3.3V with brown-out detection circuits to be completely bypassed. pull- If unconnected, it will be pulled down by its pad to ensure that it down remains inactive, allowing the internal analog circuits to reset the device. resetOutn Output This active low output can be used to reset other devices in the 3.3V system. The signal is active when the internal power-on-reset is active (not deglitched), or if the internal SoPEC reset has been activated by a brown-out or external power-on-reset (deglitched), or where the systemResetn register in the CPR block is set to 0 by the CPU. Note that this signal can be used to adjust the V,,Ompthreshold for the brown-out detector, if so desired. phRst0_n Output This active low output can be used to reset the even-numbered 3.3V printhead segments. The signal is active when the internal power on-reset is active (not deglitched), or if the internal SoPEC reset has been activated by a brown-out or external power-on-reset (deglitched), or where the phReset0_n register in the CPR block is set to 0 by the CPU. phRst1_n Output This active low output can be used to reset the odd-numbered 3.3V printhead segments. The signal is active when the internal power on-reset is active (not deglitched), or if the internal SoPEC reset has been activated by a brown-out or external power-on-reset (rinnliteh-rn nr whnrp thp nhRamti n raninqtr in thp- C.PR hinn'k in WO 2005/120835 PCT/AU2004/000706 992 set to 0 by the CPU. Internal Signals Bufrefclk Output from PLL. Operational from 0.9 V upwards. Requires 1Oms wake-up time. brownOut n Asynchronous output from the brown-out detector, ORed with the macro_disable signal. It is active low if V ,has fallen so low that Vcomp (which has been derived by dividing down V,) is below the voltage reference threshold of the macro. BoResync-n Active low, it is brownOut n synchronised to bufrefc/k. extResetRes Active low, it is resetn synchronised to bufrefc/k. ync-n porn Active low power-on-reset signal, output from macro~disable OR gate. porAsyncActi Active low signal derived from por_n. This signal goes low during ve_n power-up, and remains low until resetlntn gets deasserted. It is used to drive SoPEC's output reset signals. PorClrResyn Active low signal derived from por n being active (low). c n Resynchronised to bufrefc/k, this signal indicates that porn has gone to 0, even if bufrefclkwas not running when this occurred. Resetlntn This is the active low internal reset signal for SoPEC. It is a deglitched version of the reset activity. This signal is active immediately following an internal power-on-reset, or if an external reset or brown-out event has been activated for more than 1000s. systemReset This active low signal is the output from the systemReset n register _n in the CPR module. It allows the CPU to reset other devices in the system, by writing 0 to the register. PhReset0_n This active low signal is the output from the phResetCLn register in the CPR module. It allows the CPU to reset the even-numbered printhead segments by writing 0 to the register. PhReset1 n This active low signal is the output from the phResetLn register in the CPR module. It allows the CPU to reset the odd-numbered printhead segments by writing 0 to the register. Appendix A: Brown-out design example The comparison voltage of the brown-out detector is derived from a diode with a temperature sensitivity of 5 2.2mV/*C. The variation in trigger point for the IBM POS is taken from the datasheet and shown in the table 228 below. As shown in Figure 339, there is a potential divider which increases the trigger point voltage of the circuit compared with the actual diode voltage. The divider has a ratio of 15/16 (derived from the detailed IBM supplied schematic). The actual diode voltage used can then be calculated.
WO 2005/120835 PCT/AU2004/000706 993 Table 228 POS temperature sensitivity Trigger Temperat voltage I ure Diode voltage 0.75±5mV 1000C 0.7031 (Vdmin) 0.95±5mV 25*C 0.8906 1.05±5mV -200C 0.9844 (Vdmax) The design range for brown-out detection can then be calculated (the 5mV offset and resistor tolerance will be ignored for now). 5 Case1 Suppose the lower limit for detection is the point at which a linear regulator deriving a 3.3V supply drops out. Then VdetL1 = V&rop + 3.3V, where a typical value for Varop = 0.5V. To guarantee this, the lowest comparison voltage is used. The required resistor division ratio is then DivL = Vamin/VdetL1 then VdetHl = Vdmax/DivL 10 Case 2 Alternatively, let the upper limit for detection VdetH2 = Vpos - Vmarg, where Vmag represents a voltage margin to prevent false triggering of the detector (say 0.5V). The highest comparison voltage then must be used giving a resistor division ratio DivH = Vamax/VdetH2. Then VdetL2 = Vdmin DivH Results for this are shown below. Table 229 Macro behaviour for different supply voltages (V.) V- Case1 Case2 VdelL1 VsiON1 Vee VdetH2 iV Vj - 5 3.8 5.321 3.213 4.5 8 3.8 5.321 5.355 7.5 12 3.8 5.321 8.214 11.5 15 These results show that there is no feasible solution for VpO, = 5V since VdetL2 < VdetL1 and VdetH1 > VdtH2- The minimum value for Vp, meeting both requirements is 5.832V. If the maximum divider current is Iivmax, then the lower resistor RL = VposDiv/Idivax and the upper resistor Ru = Vpos(1-Div)/Iivmax.
WO 2005/120835 PCT/AU2004/000706 994 4 REQUIREMENTS 4.1 FUNCTIONAL REQUIREMENTS 1. Place the PEP Subsystem in sleep mode; 5 - At system reset the PEP Subsystem is initialised and left on. It is the Boot ROM's responsibility to place the PEP Subsystem in sleep mode, thereby saving power until the PEP Subsystem is required. 2. Copy Boot ROM software (itself) into RAM; 0 The Boot ROM is copied to RAM because running from ROM is too slow. 3. Enable watchdog timer to catch unexpected timeouts and errant software; 10 4. Load application software; * Memory must be cleared before loading application software, to clear any information left over from the software previously run. * First attempt to load from an LSS device; then * Attempt to load from the USB device. 15 5. Verify loaded application software has a correct digital signature; * Application software without a correct digital signature is not run. 6. Run loaded and verified application software; 7. The boot time from SoPEC suspend mode must be less than 1 second; * The boot time from applying power is less important than the boot time from suspend, however it 20 should also be in the same order of time. 8. 10 pins should only be initialised as they are required during the boot-strap process. * This enables 10 pins to be used for other purposes, if they are not required for booting in the current hardware configuration. 4.2 NON-FUNCTIONAL REQUIREMENTS 25 1. Object code size must be minimized, and should be less than 64 Kbytes; 2. Software will use an abstraction layer to read and write to all 10 devices; * This will enable 10 devices simulation for host testing. 5 DESIGN 30 Notes: * All multi-byte quantities shown throughout this design are stored in most significant byte first byte order (big-endian) format, to match the architecture of the SoPEC's SPARC CPU. Please beware that all SoPEC blocks other than the SPARC CPU are least significant byte first byte-order (little endian) format.
WO 2005/120835 PCT/AU2004/000706 995 5.1 FIRST STAGE BOOT LOADER The First Stage Boot Loader is a smaller loader that only loads the Second Stage Boot Loader program from ROM into RAM. It does this so the main Boot ROM functionality will run from RAM. Running from RAM is much quicker than running from ROM, as the ROM has a narrower memory bus and is not cached. Running 5 the Boot Loader from RAM will give a much faster boot time. The First Stage Boot Loader loads the Second Stage Boot Loader program into RAM using the format described in Section 5.1.1. Notes: 0 The First Stage Boot Loader software should not require a stack. 10 - Although the First Stage Boot Loader could copy its copy routine from ROM to RAM to reduce boot time slightly, this is not done, and the copy function is run directly from ROM. The calculation below shows the time reduction does not warrant the complexity or ROM code size it adds: - Fetching an opcode from the cache takes 1 cycle 15 - Fetching an opcode from the ROM takes 8 cycles. - The copy loop will be 6 opcodes: - Load double from source - Store double to destination - Increment source 20 - Increment destination - Decrement loop count - Branch - For a 64k image, this will loop 8192 times (it copies 8 bytes at a time). 25 Running from ROM therefore increases the boot time by: 7 x 6 x 8192 = 344064 cycles = 1.8ms 5.1.1 First Stage Image Format The First Stage Boot Loader loads an image with the format described in Figure 343 and Table 230, that is located in ROM, directly beyond the First Stage Boot Loader itself.
WO 2005/120835 PCT/AU2004/000706 996 Table 230 First Stage Image Fields Size bits (bytes) [32-bit Field words] Description Length 32 (4) [1] The Length of the Data field. Note: The unit for this length is to be determined during implementation, from what is most efficient. The unit selected could be 32-bit, 64-bit or 256-bit words. Load 32 (4) [1] The RAM address to start loading the contents of the Data field at. Address Run 32 (4) [1] The address to start execution of the loaded image at. Address Data variable The Second Stage Boot Loader software image to load. Notes: * The size of each field, including variable size fields, must be a multiple of 32-bit words, to maintain a consistent 32-bit word alignment. 5 5.2 SECOND STAGE BOOT LOADER The Second Stage Boot Loader loads Application Software from an SBR4320 Serial Flash, an LSS EEPROM or the USB device interface - from a USB host such as a PC or another SoPEC. The Second Stage Boot Loader first attempts to load Application Software from SBR4320, then from EEPROM, and finally from USB. 10 For Application software to be loaded, validated, and run, it must pass all verification checks. These verification checks are listed in Table 5. The Application Software, whether loaded from SBR4320, EEPROM or a USB host, is contained within the same Second Stage image format. This image format is described in Section 5.2.1. Application Software will only be loaded into RAM between the Minimum Address and Maximum Address 15 inclusive, as define in Table 231. Table 231 RAM Load Address Range Address Value Description Minimum The bottom of SoPEC Application Software can only be loaded on or Address RAM above this address. Maximum The top of SoPEC RAM Application Software can only be loaded on or Address less 128 Kbytes below this address. Notes: * The Second Stage Boot Loader is loaded as high as possible in the SoPEC RAM block.
WO 2005/120835 PCT/AU2004/000706 997 - The stack for the Second Stage Boot Loader is directly below the Second Stage Boot Loader software in RAM and grow down. * The Second Stage Boot Loader stack must not grow down to Maximum Address as defined in Table 2. If it does, this is a programming/software configuration error. The top 128 Kbytes of RAM are 5 reserved for the Second Stage Loader. * The top 128 Kbytes of RAM are available for the Application Software once software loading is complete and the Application Software is running. 5.2.1 Second Stage Image Format The Second Stage image format is described in Figure 344 and Table 232. 10 Table 232 Second Stage Image Fields Size bits (bytes) [32-bit Field words] Description Magic 32 (4) [1] Used to quickly identify this as a SoPEC Second Stage image. This field also identifies the version of the Second Stage image format itself, allowing scope for different formats. The values for this field are random numbers, with no additional meaning implied. The value is: 0x42189FDA LSS Speed 32 (4) [1] Only valid when an image is stored in an LSS device. The value is used to program the SoPEC LssClockHighLowDuration while reading the remainder of this image. The Magic through Header Verify fields are initially read at 100 KHz. This enables the remainder of the image to be read at a different speed. If the value is 0, the speed will remain at 100 KHz. Total Length 32 (4) [1] The total length in 32-bit words of the image following the Header Verify field - Body Verify through Non-verified Software fields inclusive. Header Verify 160 (20) [5] Used to verify the header fields - Magic through Total Length fields. It is a SHA-1 of these fields. This allows the Magic, LSS Speed and Total Length fields to be verified before they are used to load the remainder of the image. Body Verify 2048 (256) Used to verify the verified body fields - Verified Body Length [64] through Verified Software fields inclusive. This field is a 2048-bit RSA encrypted digital signature Verified Body 32 (4) [1] The length in 32-bit words of the verified body fields - Verified Length Body Length through Verified Software fields inclusive. Run Address 32 (4) [1] The address within the Verified Software to run from on completion of software load and verification. This address must always be within one of the Verified Software blocks when located in RAM to enforce the security model. If it is not, the boot ROM will not run this image. Verified variable The software block that is verified and trusted by the boot ROM. Software The SOPEC will only run software that verifies correctly. The Verified Software may be made up of one or more Data Blocks.
WO 2005/120835 PCT/AU2004/000706 998 Non-verified variable The optional software block. This software block is not verified by Software the boot ROM. This software block may be verified by the application software. The Non-verified Software may be made up of one or more Data Blocks. Data Block 32 (4) [1] The RAM addresses in 32-bit words to skip, from the current Skip running RAM load address counter, before starting to load this Data Block. Data Block 32 (4) [1] The length in 32-bit words of the data in this Data Block. The Length running RAM load address counter is incremented by this amount. Data Block variable The data to load for this Data Block. Data Notes: * The size of each field, including variable size fields, must be a multiple of 32-bit words, to maintain a consistent 32-bit word alignment. 5 0 At the start or re-start of the Second Stage load process, the running RAM load address counter is initialised to the Minimum Address of RAM as defined in Table 2. * The Data Block Skip field is not allowed to wrap the running RAM load address counter. If wrapping were not guarded against, a Data Block could be made to overwrite other Data Blocks, allowing the SoPEC security model to be compromised, i.e. Non-verfied Software could be made 10 to overwrite Venfied Software. 5.3 LOGic FLOW The logical flow of the Boot ROM is described in the following sections. 5.3.1 Overall Logic Flow 5.3.2 Initialisation 15 Notes: * Once the Watchdog is started, all software running after this must continue to periodically kick the Watchdog, or the SoPEC will be reset. * Hardware initialisation includes: placing the PEP in sleep mode; and enabling RAM in the DIU. * The First Stage Image is copied into RAM and run from there because it is too slow to run 20 directly from ROM. * The First Stage Image contains the Second Stage Loader software. * The Second Stage Loader software sets up the Watchdog to have a timeout period for its own operation. * The Second Stage Loader software clears the rest of RAM including its own stack space. This is 25 done to avoid the possibility of the new application software discovering protected information from software that was previously run. For example, if the supervisor stack from the previous WO 2005/120835 PCT/AU2004/000706 999 software happens to be in user memory for the new software, the new software could access information that should not be disclosed. e The C++ runtime is initialised last, after RAM is cleared. 5.3.3 Load & Verify Second Stage Image 5 Notes: e The Second Stage Image is first loaded from an LSS device, if available there. e If a Second Stage Image is not found in any LSS device, the Boot ROM waits for a USB host to attach to the SoPEC and send a valid Second Stage Image. 5.3.3.1 Load from LSS 10 Notes: * LSS devices are searched for on 2 buses. The GPIO pins for these 2 LSS buses is yet to be defined. * The same LSS bus is always searched first and the second LSS bus is only accessed if a load image is not found on the first bus. This allows the GPIO pins for the second LSS bus to be used for other purposes, in applications where a second boot-strap LSS bus is not required. 15 0 3 types of LSS devices are searched for: a) SBR4320 vl.0 with address 0101_100; b) SBR4320 Serial Flash with address 1111_010; and c) EEPROM with address 1010_000. * The LSS devices are searched for in the order, a first, then b, then c. The search does not continue 20 after the first valid load image is located. e At the start of an LSS device search, a SBR4320 Serial Flash Activate command addressed to the global id must be issued on an LSS bus. This initialises any SBR4320 Serial Flash devices that are on the bus. * The SBR4320 Serial Flash Activate command also serves as a first pass discovery method for 25 SBR4320 Serial Flash devices, as any of these devices on the bus will acknowledge the Activate command. * As a method to avoid LSS bus errors, all LSS commands are issued, if needed, 3 times before considering a command has timed out or returned invalid data. e The speed an LSS device is read at can be configured in the LSS Speed field as described in Section 30 5.2.1. * If software is found in an LSS device, but the image body verification fails, it is considered a non recoverable failure and the SoPEC will be reset. e The SoPEC LSS interface provides a 20 byte TxRx data buffer. The 20 byte buffer is organised as 5 x 32-bit registers. The SoPEC LSS transmits and receives bytes to and from its 32-bit buffer 35 registers in least significant byte first order (little-endian) format. However, the SoPEC CPU is most significant bytefirst order (big-endian). This means the byte order of the Second Stage Image
Claims (1523)
1. A method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: (a) determining the rotational displacement; 5 (b) determining at least one correction factor that at least partially compensates for the ink dot displacement; and (c) using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. 10 2. A method according to claim 1, wherein step (c) includes altering a timing of a fire signal to at least one of the nozzles on the basis of the correction factor, thereby to effect the at least partial compensation.
3. A method according to claim 1, wherein the nozzles are disposed in a plurality of rows, and step (c) includes reallocating at least one of the ink dots from at least one original print line to at least one alternate print 15 line, thereby to effect the at least partial compensation.
4. A method according to claim 3, wherein step (c) further includes the step of altering a timing of fire signals to at least one of the nozzles on the basis of the correction factor, thereby to effect the at least partial compensation. 20
5. A method according to claim 4, wherein the altered fire signals are supplied to both reallocated ink dots and non-reallocated ink dots.
6. A method according to claim 1, wherein the correction factor is stored in a memory associated with the 25 printhead.
7. A method according to claim 6, wherein the memory is mounted with the printhead, the printhead being mounted on the print engine. 30 8. A method according to claim 1, wherein the rotational displacement is roll.
9. A method according to claim 1, wherein the rotational displacement is yaw,.
10. A method according to claim 1, the printhead module being one of a plurality of printhead modules 35 mounted on a carrier to form a printhead and the error in ink dot placement being an error relative to ink dots output by one or more of the other printhead modules SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1259
11. A method according to claim 1, wherein the printer is a pagewidth printer.
12. A method according to claim 1, wherein the printer is a pagewidth printer. 5 13. - A printer controller programmed and configured to implement the method of claim 1.
14. A method according to claim 1, the method including expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a 10 fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), ... , nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
15. A method according to claim 1, the method including expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel 15 ink in response to a fire signal, the method comprising the steps of: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set 20 have been fired, and then firing the central nozzle.
16. A method according to claim 1, the method including manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least 25 one of the printhead modules is right-handed and at least another is left-handed.
17. A method according to claim 1, the method being performed in conjunction with a printhead module including: at least one row of print nozzles; 30 at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers.
18. A method according to claim 1, the method being performed in a printer comprising: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at 35 least one row of print nozzles for expelling ink; and SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1260 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. 5 19. A method according to claim 1, the method being performed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the 10 second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them.
20. A method according to claim 1, the method being performed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each 15 other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead 20 module.
21. A method according to claim 1, the method being performed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer 25 than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data 30 received from the first printer controller.
22. A method according to claim 1, the method being performed in conjunction with a printer controller for supplying dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational 35 displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1261 determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. 5
23. A method according to claim 1, the method being performed in conjunction with a printer controller for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least 10 some of the nozzles in response to the temperature rising above a first threshold.
24. A method according to claim 1, the method being performed in conjunction with a printer controller for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of 15 the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more 20 control signals that control the order of firing of the nozzles.
25. A method according to claim 1, the method being performed in conjunction with a printer controller for outputting to a printhead module: dot data to be printed with at least two different inks; and 25 control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks.
26. A method according to claim 1, the method being performed in conjunction with a printhead module 30 including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
27. A method according to claim 1, the method being performed in conjunction with a printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print 35 data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1262 a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. 5 28. A method according to claim 1, the method being performed in conjunction with a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 10 29. A method according to claim 1, the method being used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; 15 (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 20
30. A method according to claim 1, the method being used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with 25 the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
31. A method according to claim 1, the method being performed in conjunction with a printer controller for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a 30 similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to 35 the printhead module for printing. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1263
32. A method according to claim 1, the method being performed in conjunction with a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured 5 to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
33. A method according to claim 1, the method being performed in conjunction with a printer controller for 10 receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead, wherein each of the serial outputs is configured to supply dot data for at least two channels of the at least one printhead.
34. A method according to claim 1, the method being performed in conjunction with a printhead module 15 including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 20
35. A method according to claim 1, the method being performed in conjunction with a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, 25 wherein the first number is greater than the second number.
36. A method according to claim 1, the method being performed in conjunction with a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in 30 plan.
37. A method according to claim 1, the method being performed in conjunction with a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in 35 accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1),. nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1264
38. A method according to claim 1, the method being performed in conjunction with a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, 5 until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. 10 39. A method according to claim 1, the method being performed in conjunction with a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. 15 40. A method according to claim 1, the method being performed in conjunction with a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
41. A method according to claim 1, the method being performed in conjunction with a printhead module 20 having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the 25 nozzles of each subsequent row.
42. A method according to claim 1, the method being performed in conjunction with a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended 30 media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. 35 43. A method according to claim 1, the method being performed in conjunction with a printer controller for providing data to a printhead module that includes: at least one row of print nozzles; SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1265 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 5 44. A method according to claim 1, the method being performed in conjunction with a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. 10
45. A method according to claim 1, the method being performed in conjunction with a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second 15 row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
46. A method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire 20 signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle'position 2, nozzle position (n-1), ... , nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
47. A method according to claim 46,wherein the nozzle at each given position within the set is fired 25 simultaneously with the nozzles in the other sets at respective corresponding positions.
48. A method according to claim 46,wherein the printhead module includes a plurality of the rows of nozzles, the method including sequentially repeating the for each of the rows of nozzles. 30 49. A method according to claim 48, wherein the rows are disposed in pairs.
50. A method according to claim 49, wherein the rows in each pair of rows are offset relative to each other.
51. A method according to claim 50, wherein each pair of rows is configured to print the same color ink. 35
52. A method according to claim 51, wherein each pair of rows is connected to a common ink source. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1266
53. A method according to claim 46,wherein the sets of nozzles are adjacent each other.
54. A method according to claim 46,wherein the sets of nozzles are separated by an intermediate nozzle, the intermediate nozzle being fired either prior to the nozzle at position I in each set, or following the nozzle at 5 position n.
55. A method according to claim 46,including the step of providing the fire sequence to the printhead module from a printer controller, the fire signals being based on the fire sequence. 10 56. A method according to claim 55, wherein the fire sequence is loaded into a shift register in the printhead module.
57. A method according to claim 46,the method at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module 15 relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: (a). determining the rotational displacement; (b). determining at least one correction factor that at least partially compensates for the ink dot displacement; and (c). using the correction factor to alter the output of the ink dots to at least partially compensate for the 20 rotational displacement.
58. A method according to claim 46,the method including expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: 25 (a). providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b). providing a fire signal to the next inward pair of nozzles in each set; (c). in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 30
59. A method according to claim 46,the method including manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. 35
60. A method according to claim 46,the method being performed in conjunction with a printhead module including: SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1267 at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 5 61. A method according to claim 46,the method being performed in a printer comprising: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of-the 10 printhead.
62. A method according to claim 46,the method being performed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of ajoin region; 15 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 20 63. A method according to claim 46,the method being performed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot 25 data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module.
64. A method according to claim 46,the method being performed in a printer comprising: 30 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and 35 the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1268
65. A method according to claim 46,the method being performed in conjunction with a printer controller for supplying dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational 5 displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and 10 supply the dot data to the printhead module.
66. A method according to claim 46,the method being performed in conjunction with a printer controller for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature 15 at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold.
67. A method according to claim 46,the method being performed in conjunction with a printer controller for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module 20 having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired 25 before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles.
68. A method according to claim 46,the method being performed in conjunction with a printer controller for outputting to a printhead module: 30 dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 35 69. A method according to claim 46,the method being performed in conjunction with a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1269
70. A method according to claim 46,the method being performed in conjunction with a printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: 5 a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. 10 71. A method according to claim 46,the method being performed in conjunction with a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 15 72. A method according to claim 46,the method being used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: providing a fire signal to nozzles at a first and nth position in each set of nozzles; 20 providing a fire signal to the next inward pair of nozzles in each set; in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 25 73. A method according to claim 46,the method being used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], 30 wherein nozzle positionx is at or adjacent the centre of the set of nozzles.
74. A method according to claim 46,the method being performed in conjunction with a printer controller for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in 35 the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1270 printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing.
75. A method according to claim 46,the method being performed in conjunction with a printer controller for 5 supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position 10 where the faulty nozzle would otherwise have printed it.
76. A method according to claim 46,the method being performed in conjunction with a printer controller for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead, wherein each of the serial outputs is 15 configured to supply dot data for at least two channels of the at least one printhead.
77. A method according to claim 46,the method being performed in conjunction with a printhead module including: at least one row of print nozzles; 20 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
78. A method according to claim 46,the method being performed in conjunction with a printhead capable of 25 printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. 30 79. A method according to claim 46,the method being performed in conjunction with a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 35 80. A method according to claim 46,the method being performed in conjunction with a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1271 accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
81. A method according to claim 46,the method being performed in conjunction with a printhead module 5 including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and 10 in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle.
82. A method according to claim 46,the method being performed in conjunction with a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot 15 data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data.
83. A method according to claim 46,the method being performed in conjunction with a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the 20 displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
84. A method according to claim 46,the method being performed in conjunction with a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being 25 configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. 30 85. A method according to claim 46,the method being performed in conjunction with a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the 35 first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1272
86. A method according to claim 46,the method being performed in conjunction with a printer controller for providing data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift 5 register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
87. A method according to claim 46,the method being performed in conjunction with a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each 10 of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold.
88. A method according to claim 46,the method being performed in conjunction with a printhead module 15 comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 20
89. A method according to claim 46,wherein the printhead module includes a plurality of the rows, the method including firing each nozzle in each row simultaneously with the nozzle or nozzles at the same position in the other rows. 25 90. A method according to claim 46,including a plurality of pairs of the rows, each pair of rows including an odd row and an even row, the odd and even rows in each pair being offset from each other in both x and y directions relative to an intended direction of print media movement relative to the printhead, the method including causing firing of at least a plurality of the odd rows prior to firing any of the even rows, or vice versa. 30 91. A method according to claim 90, wherein all the odd rows are fired before any of the even rows are fired, or vice versa.
92. A method according to claim 90, wherein the odd rows, or the even rows, or both, are fired in a predetermined order. 35
93. A method according to claim 92, wherein the predetermined order is selectable from a plurality of predetermined available orders. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1273
94. A method according to claim 90, wherein the predetermined order is sequential.
95. A method according to claim 94, wherein the predetermined order can commence at any of a plurality of 5 the rows.
96. A method of expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: (a) providing a fire signal to nozzles at a first and nth position in each set of nozzles; 10 (b) providing a fire signal to the next inward pair of nozzles in each set; (c) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 15 97. A method according to claim 96, wherein the printhead module includes a plurality of the rows of nozzles, the method including sequentially repeating steps (a) to (d) for each of the rows of nozzles.
98. A method according to claim 97, wherein the rows are disposed in pairs. 20 99. A method according to claim 98, wherein the rows in each pair of rows are offset relative to each other.
100. A method according to claim 99, wherein each pair of rows is configured to print the same color ink.
101. A method according to claim 100, wherein each pair of rows is connected to a common ink source. 25
102. A method according to claim 96, wherein the sets of nozzles are adjacent each other.
103. A method according to claim 96, wherein the sets of nozzles are separated by an intermediate nozzle, the intermediate nozzle being fired either prior to the nozzle at position 1 in each set, or following the nozzle at 30 position n.
104. A method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: 35 [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1274
105. A method according to claim 104, wherein the nozzle at each given position within the set is fired simultaneously with the nozzles in the other sets at respective corresponding positions.
106. A method according to claim 96, the method at least partially compensating for errors in ink dot 5 placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: (a) determining the rotational displacement; (b) determining at least one correction factor that at least partially compensates for the ink dot displacement; and 10 (c) using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement.
107. A method according to claim 96, the method including expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being 15 configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), ... , nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
108. A method according to claim 96, the method including manufacturing a plurality of printhead modules, at 20 least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed.
109. A method according to claim 96, the method being performed in conjunction with a printhead module 25 including: (a). at least one row of print nozzles; (b). at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 30 110. A method according to claim 96, the method being performed in a printer comprising: (a). a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and (b). at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input 35 of the printhead.
111. A method according to claim 96, the method being performed in a printer comprising: SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1275 (a). a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a joi region; (b). at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead 5 module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them.
112. A method according to claim 96, the method being performed in a printer comprising: (a). a printhead comprising first and second elongate printhead modules, the printhead modules being parallel 10 to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; (b). at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second 15 printhead module.
113. A method according to claim 96, the method being performed in a printer comprising: (a). a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is 20 longer than the second priithead module; (b). at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least 25 some of the dot data received from the first printer controller.
114. A method according to claim 96, the method being performed in conjunction with a printer controller for supplying dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational 30 displacement of the printhead module relative to a carrier, the printer being configured to: (a). access a correction factor associated with the at least one printhead module; (b). determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and 35 (c). supply the dot data to the printhead module. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1276
115. A method according to claim 96, the method being performed in conjunction with a printer controller for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least .5 some of the nozzles in response to the temperature rising above a first threshold.
116. A method according to claim 96, the method being performed in conjunction with a printer controller for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of 10 the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more 15 control signals that control the order of firing of the nozzles.
117. A method according to claim 96, the method being performed in conjunction with a printer controller for outputting to a printhead module: (a). dot data to be printed with at least two different inks; and 20 (b). control data for controlling printing of the dot data; (c). the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 25 118. A method according to claim 96, the method being performed in conjunction with a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
119. A method according to claim 96, the method being performed in conjunction with a printer controller for 30 supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: (a). a first mode, in which the printhead module is configured to receive data for a first number of the channels; and (b). a second mode, in which the printhead module is configured to receive print data for a second number of 35 the channels, wherein the first number is greater than the second number; (c). wherein the printer controller is selectively configurable to supply dot data for the first and second modes. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1277
120. A method according to claim 96, the method being performed in conjunction with a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is 5 determined by its geometric shape in plan.
121. A method according to claim 96, the method being used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to 10 a fire signal, such that: (d) providing a fire signal to nozzles at a first and nth position in each set of nozzles; (e) providing a fire signal to the next inward pair of nozzles in each set; (f) in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (g) in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set 15 have been fired, and then firing the central nozzle.
122. A method according to claim 96, the method being used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in 20 response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: (nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle positionx is at or adjacent the centre of the set of nozzles.
123. A method according to claim 96, the method being performed in conjunction with a printer controller for 25 supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configuiable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are 30 printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing.
124. A method according to claim 96, the method being performed in conjunction with a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of 35 rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, SUBSTITUTE SHEET (RULE 26) ROIAU WO 2005/120835 PCT/AU2004/000706 1278 a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
125. A method according to claim 96, the method being performed in conjunction with a printer controller for 5 receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead, wherein each of the serial outputs is configured to supply dot data for at least two channels of the at least one printhead.
126. A method according to claim 96, the method being performed in conjunction with a printhead module 10 including: (a). at least one row of print nozzles; (b). at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 15
127. A method according to claim 96, the method being performed in conjunction with a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: (a). a first mode, in which the printhead is configured to receive print data for a first number of the channels; and 20 (b). a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number.
128. A method according to claim 96, the method being performed in conjunction with a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the 25 printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan.
129. A method according to claim 96, the method being performed in conjunction with a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being 30 configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-),. nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
130. A method according to claim 96, the method being performed in conjunction with a printhead module 35 including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from SUBSTITUTE SHEET (RULE 26) ROIAU WO 2005/120835 PCT/AU2004/000706 1279 nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: (a). in the event n is an even number, all of the nozzles in each set has been fired; and (b). in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and 5 then to fire the central nozzle.
131. A method according to claim 96, the method being performed in conjunction with a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors 10 and the control data.
132. A method according to claim 96, the method being performed in conjunction with a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 15
133. A method according to claim 96, the method being performed in conjunction with a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence 20 from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row.
134. A method according to claim 96, the method being performed in conjunction with a printhead module 25 comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the.second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair 30 of rows.
135. A method according to claim 96, the method being performed in conjunction with a printer controller for providing data to a printhead module that includes: (a). at least one row of print nozzles; 35 (b). at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1280
136. A method according to claim 96, the method being performed in conjunction with a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the 5 printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold.
137. A method according to claim 96, the method being performed in conjunction with a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the 10 printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 15 138. A method according to claim 96, wherein the printhead module includes a plurality of the rows, the method including firing each nozzle in each row simultaneously with the nozzle or nozzles at the same position in the other rows.
139. A method according to claim 96, wherein the printhead module includes a plurality of the rows, the 20 method including firing each nozzle in each row simultaneously with the nozzle or nozzles at the same position in the other rows.
140. A method according to claim 96, including a plurality of pairs of the rows, each pair of rows including an odd row and an even row, the odd and even rows in each pair being offset from each other in both x and y 25 directions relative to.an intended direction of print media movement relative to the printhead, the method including causing firing of at least a plurality of the odd rows prior to firing any of the even rows, or vice versa.
141. A method according to claim 140, wherein all the odd rows are fired before any of the even rows are fired, or vice versa. 30
142. A method according to claim 140, wherein the odd rows, or the even rows, or both, are fired in a predetermined order.
143. A method according to claim 142, wherein the predetermined order is selectable from a plurality of 35 predetermined available orders.
144. A method according to claim 140, wherein the predetermined order is sequential. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1281
145. A method according to claim 144, wherein the predetermined order can commence at any of a plurality of the rows.
146. A method of manufacturing a plurality of printhead modules, at least some of which are capable of being 5 combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed.
147. A method of manufacturing a plurality of pagewidth printheads, the method comprising the steps of: 10 manufacturing a plurality of printhead modules in accordance with claim 1; and assembling pairs of at least some of the printhead modules to form pagewidth printheads, wherein each of the printhead modules in each pagewidth printhead is shorter than the pagewidth.
148. A method according to claim 147, wherein the printhead modules of at least one of the pagewidth 15 printheads are of relatively different lengths.
149. A method according to claim 147, wherein the printhead modules of at least one of the pagewidth printheads are of the same length. 20 150. A method according to claim 147, wherein the printhead modules of at least one of the pagewidth printheads are of relatively different lengths, and the printhead modules of at least another of the pagewidth printheads are of the same length.
151. A method according to claim 147, wherein at least some of the printhead modules are larger than a reticle 25 step used in laying out those printhead modules.
152. A method according to claim 146, including the step of laying out a plurality of left-handed and right handed printhead modules. 30 153. A method according to claim 152, including the step of laying out a plurality of different lengths of left handed and right-handed printhead modules.
154. A method according to claim 146, the method at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module 35 relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: (a). determining the rotational displacement; SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1282 (b). determining at least one correction factor that at least partially compensates for the ink dot displacement; and (c). using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. 5
155. A method according to claim 146, the method including expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle 10 position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
156. A method according to claim 146, the method including expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: 15 (a). providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b). providing a fire signal to the next inward pair of nozzles in each set; (c). in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 20
157. A method according to claim 146, the method being performed in conjunction with a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, 25 wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers.
158. A method according to claim 146, the method being performed in a printer comprising: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and 30 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead.
159. A method according to claim 146, the method being performed in a printer comprising: 35 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1283 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 5
160. A method according to claim 146, the method being performed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; 10 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. 15 161. A method according to claim 146, the method being performed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot 20 data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller, and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. 25 162. A method according to claim 146, the method being performed in conjunction with a printer controller for supplying dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; 30 determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. 35 163. A method according to claim 146, the method being performed in conjunction with a printer controller for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature SUBSTITUTE SHEET (RULE 26) ROIAU WO 2005/120835 PCT/AU2004/000706 1284 at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold.
164. A method according to claim 146, the method being performed in conjunction with a printer controller 5 for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence 10 in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles.
165. A method according to claim 146, the method being performed in conjunction with a printer controller 15 for outputting to a printhead module: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 20
166. A method according to claim 146, the method being performed in conjunction with a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 25 167. A method according to claim 146, the method being performed in conjunction with a printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the 30 channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes.
168. A method according to claim 146, the method being performed in conjunction with a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a 35 reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1285
169. A method according to claim 146, the method being used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: 5 (a). providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b). providing a fire signal to the next inward pair of nozzles in each set; (c). in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 10
170. A method according to claim 146, the method being used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with 15 the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
171. A method according to claim 146, the method being performed in conjunction with a printer controller for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a 20 similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to 25 the printhead module for printing.
172. A method according to claim 146, the method being performed in conjunction with a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at 30 least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 35 173. A.method according to claim 146, the method being performed in conjunction with a printer controller for receiving first data and manipulating the first data to produce dot data to be printed, the print controller SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1286 including at least two serial outputs for supplying the dot data to at least one printhead, wherein each of the serial outputs is configured to supply dot data for at least two channels of the at least one printhead.
174. A method according to claim 146, the method being performed in conjunction with a printhead module 5 including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 10
175. A method according to claim 146, the method being performed in conjunction with a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, 15 wherein the first number is greater than the second number.
176. A method according to claim 146, the method being performed in conjunction with a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its 20 geometric shape in plan.
177. A method according to claim 146, the method being performed in conjunction with a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in 25 accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1),. nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
178. A method according to claim 146, the method being performed in conjunction with a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles 30 being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire 35 the central nozzle. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1287
179. A method according to claim 146, the method being performed in conjunction with a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. 5
180. A method according to claim 146, the method being performed in conjunction with a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 10 181. A method according to claim 146, the method being performed in conjunction with a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other 15 fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row.
182. A method according to claim 146, the method being performed in conjunction with a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in 20 the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. 25
183. A method according to claim 146, the method being performed in conjunction with a printer controller for providing data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift 30 register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
184. A method according to claim 146, the method being performed in conjunction with a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each 35 of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1288
185. A method according to claim 146, the method being performed in conjunction with a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and 5 being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
186. A printhead module including: 10 at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers.
187. A printhead module according to claim 186, wherein there is a one to one correspondence between the 15 nozzles and elements of the two shift registers.
188. A printhead module according to claim 187, wherein each of the shift registers supplies dot data to about half of the nozzles. 20 189. A printhead module according to claim 186, including at least one pair of rows of the nozzles, the rows in each pair being offset with respect to each other by half the intra-row nozzle spacing.
190. A printhead module according to claim 189, wherein each of the at least two shift registers supplies dot data to at least some of the nozzles in at least one pair of rows. 25
191. A printhead comprising a plurality of printhead modules according to claim 186.
192. A printhead according to claim 191, wherein the printhead is a pagewidth printhead. 30 193. A printhead module according to claim 186, configured to receive dot data to which a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier has been applied, the nozzles being disposed on the printhead module, the method comprising the steps of: (a). determining the rotational displacement; 35 (b). determining at least one correction factor that at least partially compensates for the ink dot displacement; and SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1289 (c). using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement.
194. A printhead module according to claim 186, configured to receive dot data to which a method of 5 expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 10
195. A printhead module according to claim 186, configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: 15 (a). providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b). providing a fire signal to the next inward pair of nozzles in each set; (c). in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 20
196. A printhead module according to claim 186, having been manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is 25 left-handed.
197. A printhead module according to claim 186, including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, 30 wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers.
198. A printhead module according to claim 186, installed in a printer comprising: a printhead comprising at least the first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and 35 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1290
199. A printhead module according to claim 186, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; 5 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 10 200. A printhead module according to claim 186, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot 15 data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module.
201. A printhead module according to claim 186, installed in a printer comprising: 20 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and 25 the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller.
202. A printhead module according to claim 186, in communication with a printer controller for supplying dot 30 data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead 35 modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1291
203. A printhead module according to claim 186, in communication with a printer controller for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or 5 adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold.
204. A printhead module according to claim 186, in communication with a printer controller for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a 10 plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired 15 before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles.
205. A printhead module according to claim 186, in communication with a printer controller for outputting to a printhead module: 20 dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 25 206. A printhead module according to claim 186, including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
207. A printhead module according to claim 186, in communication with a printer controller for supplying 30 print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; 35 wherein the printer controller is selectively configurable to supply dot data for the first and second modes. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1292
208. A printhead module according to claim 186, in communication with a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 5
209. A printhead module according to claim 186, used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: 10 (a). a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b). a fire signal is provided to the next inward pair of nozzles in each set; (c). in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each 15 set have been fired, and then the central nozzle is fired.
210. A printhead module according to claim 186, used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the- printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a 20 fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), ... , nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
211. A printhead module according to claim 186, in communication with a printer controller for supplying dot 25 data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles 30 from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing.
212. A printhead module according to claim 186, in communication with a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the 35 rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1293 corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
213. A printhead module according to claim 186, in communication with a printer controller for receiving first 5 data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead.
214. A printhead module according to claim 186, including: at least one row of print nozzles; 10 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
215. A printhead module according to claim 186 being capable of printing a maximum of n of channels of 15 print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. 20 216. A printhead comprising a plurality of printhead modules according to claim 186, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan.
217. A printhead module according to claim 186, including at least one row that comprises a plurality of sets 25 of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 30 218. A printhead module according to claim 186, including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and 35 in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. SUBSTITUTE SHEET (RULE 26) ROIAU WO 2005/120835 PCT/AU2004/000706 1294
219. A printhead module according to claim 186, for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. 5 220. A printhead module according to claim 186, including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
221. A printhead module according to claim 186, having a plurality of rows of nozzles configured to extend, 10 in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. 15
222. A printhead module according to claim 186, comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output 20 to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows.
223. A printhead module according to claim 186, in communication with a printer controller for providing data to a printhead module that includes: 25 at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 30 224. A printhead module according to claim 186, having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. 35 225. A printhead module according to claim 186, comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1295 row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
226. A printer comprising: 5 a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. 10
227. A printer according to claim 226, including at least one synchronization means between the first and second printer controllers for synchronizing the supply of dot by the printer controllers.
228. A printer according to claim 226, configured such that the first and second printer controllers 15 sequentially provide the dot data to the common input
229. A printer according to claim 226, further including a second printhead module, the printer being configured such that: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. 20
230. A printer according to claim 229, wherein the printhead modules are configured such that no dot data passes between them.
231. A printer according to claim 229, wherein each of the printer controllers is configurable to supply the dot 25 data to printhead modules of a plurality of different lengths.
232. A printer according to claim 226, wherein the printhead is a pagewidth printhead.
233. A print engine comprising: 30 a carrier; a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the 35 printhead. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1296
234. A printer according to claim 233, including at least one synchronization means between the first and second printer controllers for synchronizing the supply of dot by the printer controllers.
235. A printer according to claim 233, configured such that the first and second printer controllers alternately 5 provide the dot data to the common input.
236. A printer according to claim 233, further including a second printhead module, the printer being configured such that: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. 10
237. A printer according to claim 236, wherein the printhead modules are configured such that no dot data passes between them.
238. A printer according to claim 236, wherein each of the printer controllers is configurable to supply the dot 15 data to printhead modules of a plurality of different lengths.
239. A printer according to claim 233, wherein the printhead is a pagewidth printhead.
240. A printer comprising: 20 a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least first and second rows of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to the printhead to supply data for the first and second rows of nozzles, respectively. 25
241. A printer according to claim 240, including at least one synchronization means between the first and second printer controllers for synchronizing the supply of dot by the printer controllers.
242. A printer according to claim 240, wherein the printhead modules are configured such that no dot data 30 passes between them.
243. A printer according to claim 240, wherein the printhead is a pagewidth printhead.
244. A printer according to claim 226, for implementing a method of at least partially compensating for errors 35 in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1297 determining the rotational displacement; determining at least one correction factor that at least partially compensates for the ink dot displacement; and using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. 5
245. A printer according to claim 226 for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, 10 nozzle position (n-1), ... , nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
246. A printer according to claim 226, for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being 15 configured to expel ink in response to a fire signal, the method comprising the steps of: (a). providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b). providing a fire signal to the next inward pair of nozzles in each set; (c). in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set 20 have been fired, and then firing the central nozzle.
247. A printer according to claim 226, manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on 25 a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed.
248. A printer according to claim 226, including a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, 30 wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers.
249. A printer according to claim 226, comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; 35 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1298 second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them.
250. A printer according to claim 226, comprising: 5 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and 10 the second printhead module; and the second printer controller outputs dot data only to the second printhead module.
251. A printer according to claim 226, comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each 15 other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein 20 the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller.
252. A printer according to claim 226, including at least one printhead module, configured for at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due 25 to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and 30 supply the dot data to the printhead module.
253. A printer according to claim 226, including a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer being configured to 35 modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1299
254. A printer according to claim 226, for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles 5 of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. 10 255. A printer according to claim 226, including a printer controller for sending to a printhead: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 15
256. A printer according to claim 226, including a printer controller for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 20 257. A printer according to claim 226, including a printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the 25 channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes.
258. A printer according to claim 226, including a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the 30 modules, the printhead comprising at least two types of the modules, wherein each type is detennined by its geometric shape in plan.
259. A printer according to claim 226, including a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n 35 adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a). a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b). a fire signal is provided to the next inward pair of nozzles in each set; SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1300 (c). in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. 5
260. A printer according to claim 226, including a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, 10 nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
261. A printer according to claim 226, including a printer controller for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some 15 nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for 20 printing.
262. A printer according to claim 226, including a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows 25 configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 30 263. A printer according to claim 226, including a printer controller for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead.
264. A printer according to claim 226, including a printer controller for supplying data to a printhead module 35 including: at least one row of print nozzles; SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1301 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 5 265. A printer according to claim 226, including a printer controller for supplying data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. 10
266. A printer according to claim 226, including a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 15
267. A printer according to claim 226, including a printer controller for supplying data to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1),. 20 nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
268. A printer according to claim 226, including a printer controller for supplying data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from 25 nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. 30
269. A printer according to claim 226, including a printer controller for supplying data to a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. 35 SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1302
270. A printer according to claim 226, including a printer controller for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 5 271. A printer according to claim 226, including a printer controller for supplying data to a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other 10 fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row.
272. A printer according to claim 226, including a printer controller for supplying data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in 15 the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. 20
273. A printer according to claim 226, including a printer controller for providing data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift 25 register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
274. A printer according to claim 226, including a printer controller for supplying data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each 30 of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold.
275. A printer according to claim 226, including a printer controller for supplying data to a printhead module 35 comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1303 row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
276. A printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each 5 other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 10
277. A printer according to claim 276, including at least one synchronization means between the first and second printer controllers for synchronizing the supply of dot by the printer controllers.
278. A printer according to claim 276, wherein each of the printer controllers is configurable to supply the dot 15 data to a printhead module of arbitrary length.
279. A printer according to claim 276, wherein the first and second printhead modules are equal in length.
280. A printer according to claim 276, wherein the first and second printhead modules are unequal in length. 20
281. A printer according to claim 276, wherein the printhead is a pagewidth printhead.
282. A print engine comprising: a carter; 25 a printhead comprising first and second elongate printhead modules, the printhead modules being mounted parallel to each other end to end on the carrier on either side of a join region; at least first and second printer controllers mounted on the carrier and being configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead 30 module, wherein the printhead modules are configured such that no dot data passes between them.
283. A print engine according to claim 282, including at least one synchronization means between the first and second printer controllers for synchronizing the supply of dot by the printer controllers. 35 284. A print engine according to claim 282, wherein each of the printer controllers is configurable to supply the dot data to a printhead module of arbitrary length. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1304
285. A print engine according to claim 282, wherein the first and second printhead modules are equal in length.
286. A print engine according to claim 282, wherein the first and second printhead modules are unequal in 5 length.
287. A print engine according to claim 282, wherein the printhead is a pagewidth printhead.
288. A printer according to claim 276, for implementing a method of at least partially compensating for errors 10 in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: determining the rotational displacement; determining at least one correction factor that at least partially compensates for the ink dot displacement; and 15 using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement.
289. A printer according to claim 276 for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles 20 being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 25 290. A printer according to claim 276, for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: providing a fire signal to nozzles at a first and nth position in each set of nozzles; providing a fire signal to the next inward pair of nozzles in each set; 30 in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle.
291. A printer according to claim 276, manufactured in accordance with a method of manufacturing a 35 plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1305
292. A printer according to claim 276, including a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, 5 wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers.
293. A printer according to claim 276, comprising: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and 10 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead.
294. A printer according to claim 276, comprising: 15 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and 20 the second printhead module; and the second printer controller outputs dot data only to the second printhead module.
295. A printer according to claim 276, comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each 25 other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein 30 the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller.
296. A printer according to claim 276, including at least one printhead module, configured for at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due 35 to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1306 determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. 5
297. A printer according to claim 276, including a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. 10
298. A printer according to claim 276, for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles 15 of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. 20 299. A printer according to claim 276, including a printer controller for sending to a printhead: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 25
300. A printer according to claim 276, including a printer controller for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 30 301. A printer according to claim 276, including a printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the 35 channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1307
302. A printer according to claim 276, including a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 5
303. A printer according to claim 276, including a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a). a fire signal is provided to nozzles at a first and nth position in each set of nozzles; 10 (b). a fire signal is provided to the next inward pair of nozzles in each set; (c). in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. 15
304. A printer according to claim 276, including a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, 20 nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
305. A printer according to claim 276, including a printer controller for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some 25 nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for 30 printing.
306. A printer according to claim 276, including a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows 35 configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1308 in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
307. A printer according to claim 276, including a printer controller for receiving first data and manipulating 5 the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead.
308. A printer according to claim 276, including a printer controller for supplying data to a printhead module including: 10 at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 15 309. A printer according to claim 276, including a printer controller for supplying data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. 20
310. A printer according to claim 276, including a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 25
311. A printer according to claim 276, including a printer controller for supplying data to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1),. 30 nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
312. A printer according to claim 276, including a printer controller for supplying data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from 35 nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1309 in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle.
313. A printer according to claim 276, including a printer controller for supplying data to a printhead module 5 for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data.
314. A printer according to claim 276, including a printer controller for supplying data to a printhead module 10 including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
315. A printer according to claim 276, including a printer controller for supplying data to a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the 15 nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. 20
316. A printer according to claim 276, including a printer controller for supplying data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first 25 and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows.
317. A printer according to claim 276, including a printer controller for providing data to a printhead module 30 that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 35
318. A printer according to claim 276, including a printer controller for supplying data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thennal sensors, each SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1310 of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. 5 319. A printer according to claim 276, including a printer controller for supplying data to a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise 10 have printed it.
320. A printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer 15 than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. 20
321. A printer according to claim 320, wherein the printhead modules are configured such that no dot data passes between them.
322. A printer according to claim 320, including at least one synchronization means between the first and 25 second printer controllers for synchronizing the supply of dot data by the printer controllers.
323. A printer according to claim 320, wherein each of the printer controllers is configurable to supply the dot data to printhead modules of a plurality of different lengths. 30 324. A printer according to claim 320, wherein the printhead is a pagewidth printhead.
325. A print engine comprising: a carrier; a printhead comprising first and second elongate printhead modules, the printhead modules being mounted 35 parallel to each other end to end on the carrier on either side of a join region, wherein the first printhead module is longer than the second printhead module; SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1311 at least first and second printer controllers mounted on the carrier and being configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. 5
326. A print engine according to claim 325, wherein the printhead modules are configured such that no dot data passes between them.
327. A print engine according to claim 326, including at least one synchronization means between the first and 10 second printer controllers for synchronizing the supply of dot by the printer controllers.
328. A print engine according to claim 326, wherein each of the printer controllers is configurable to supply the dot data to printhead modules of a plurality of different lengths. 15 329. A print engine according to claim 326, wherein the printhead is a pagewidth printhead.
330. A printer according to claim 320, for implementing a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method comprising 20 the steps of: determining the rotational displacement; determining at least one correction factor that at least partially compensates for the ink dot displacement; and using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. 25
331. A printer according to claim 320 for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, 30 nozzle position (n-1),..., nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
332. A printer according to claim 320, for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being 35 configured to expel ink in response to a fire signal, the method comprising the steps of: (a). providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b). providing a fire signal to the next inward pair of nozzles in each set; SUBSTITUTE SHEET (RULE 26) ROIAU WO 2005/120835 PCT/AU2004/000706 1312 (c). in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired, and (d). in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 5 333. A printer according to claim 320, manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. 10 334. A printer according to claim 320, including a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 15 335. A printer according to claim 320, comprising: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the 20 printhead.
336. A printer according to claim 320, comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; 25 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 30 337. A printer according to claim 320, comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot 35 data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1313 the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller.
338. - A printer according to claim 320, including at least one printhead module, configured for at least partially 5 compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least 10 partially compensate for the rotational displacement; and supply the dot data to the printhead module.
339. A printer according to claim 320, including a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being 15 configured to respond to a temperature at or adjacent at least one of the nozzles, the printer being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold.
340. A printer according to claim 320, for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, 20 across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer 25 controller is configured to provide one or more control signals that control the order of firing of the nozzles.
341. A printer according to claim 320, including a printer controller for sending to a printhead: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; 30 the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks.
342. A printer according to claim 320, including a printer controller for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the 35 displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1314
343. A printer according to claim 320, including a printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and 5 a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes.
344. A printer according to claim 320, including a printer controller for supplying data to a printhead 10 comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan.
345. A printer according to claim 320, including a printer controller for supplying one or more control signals 15 to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a). a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b). a fire signal is provided to the next inward pair of nozzles in each set; (c). in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; 20 and (d). in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired.
346. A printer according to claim 320, including a printer controller for supplying one or more control signals 25 to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: (nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 30
347. A printer according to claim 320, including a printer controller for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in 35 the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1315 second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing.
348. A printer according to claim 320, including a printer controller for supplying dot data to at least one 5 printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle 10 would otherwise have printed it.
349. A printer according to claim 320, including a printer controller for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. 15
350. A printer according to claim 320, including a printer controller for supplying data to a printhead module including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift 20 register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
351. A printer according to claim 320, including a printer controller for supplying data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: 25 a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number.
352. A printer according to claim 320, including a printer controller for supplying data to a printhead 30 comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan.
353. A printer according to claim 320, including a printer controller for supplying data to a printhead module 35 including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1316 accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1),. nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
354. A printer according to claim 320, including a printer controller for supplying data to a printhead module 5 including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and 10 in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle.
355. A printer according to claim 320, including a printer controller for supplying data to a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the 15 dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data.
356. A printer according to claim 320, including a printer controller for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the 20 displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
357. A printer according to claim 320, including a printer controller for supplying data to a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being 25 configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. 30 358. A printer according to claim 320, including a printer controller for supplying data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the 35 first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1317
359. A printer according to claim 320, including a printer controller for providing data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift 5 register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
360. A printer according to claim 320, including a printer controller for supplying data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each 10 of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold.
361. A printer according to claim 320, including a printer controller for supplying data to a printhead module 15 comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 20
362. A printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer 25 than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot. data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data 30 received from the first printer controller.
363. A printer according to claim 362, wherein the printhead modules are configured such that no dot data passes between them. 35 364. A printer according to claim 362, including at least one synchronization means between the first and second printer controllers for synchronizing the supply of dot data by the printer controllers. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1318
365. A printer according to claim 362, wherein each of the printer controllers is configurable to supply the dot data to printhead modules of a plurality of different lengths.
366. A printer according to claim 362, wherein the printhead is a pagewidth printhead. 5
367. A print engine comprising: a carrier; a printhead comprising first and second elongate printhead modules, the printhead modules being mounted parallel to each other end to end on the carrier on either side of a join region, wherein the first printhead module is 10 longer than the'second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second-printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data 15 received from the first printer controller.
368. A print engine according to claim 367, wherein the printhead modules are configured such that no dot data passes between them. 20 369. A print engine according to claim 368, including at least one synchronization means between the first and second printer controllers for synchronizing the supply of dot by the printer controllers.
370. A print engine according to claim 368, wherein each of the printer controllers is configurable to supply the dot data to printhead modules of a plurality of different lengths. 25
371. A print engine according to claim 368, wherein the printhead is a pagewidth printhead.
372. A printer controller according to claim 362, for implementing a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of 30 a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: determining the rotational displacement; determining at least one correction factor that at least partially compensates for the ink dot displacement; and using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational 35 displacement. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1319
373. A printer controller according to claim 362 for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, 5 nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
374. A printer controller according to claim 362, for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles 10 being configured to expel ink in response to a fire signal, the method comprising the steps of: (a). providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b). providing a fire signal to the next inward pair of nozzles in each set; (c). in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set 15 have been fired, and then firing the central nozzle.
375. A printer controller according to claim 362, manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on 20 a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed.
376. A printer controller according to claim 362, for supplying data to a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, 25 wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers.
377. A printer controller according to claim 362, installed in a printer comprising: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and 30 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead.
378. A printer controller according to claim 362, installed in a printer comprising: 35 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1320 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 5
379. A printer controller according to claim 362, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; 10 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. 15 380. A printer controller according to claim 362, for supplying dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; 20 determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. 25 381. A printer controller according to claim 362, for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. 30
382. A printer controller according to claim 362, for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, 35 the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1321 printer controller is configured to provide one or more control signals that control the order of firing of the nozzles.
383. A printer controller according to claim 362, for outputting to a printhead module: 5 dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 10 384. A printer controller according to claim 362, for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
385. A printer controller according to claim 362, for supplying print data to at least one printhead module 15 capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for-a second number of the channels, wherein the first number is greater than the second number; 20 wherein the printer controller is selectively configurable to supply dot data for the first and second modes.
386. A printer controller according to claim 362, for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 25
387. A printer controller according to claim 362, for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a). a fire signal is provided to nozzles at a first and nth position in each set of nozzles; 30 (b). a fire signal is provided to the next inward pair of nozzles in each set; (c). in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. 35
388. A printer controller according to claim 362, for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1322 nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 5
389. A printer controller according to claim 362, for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second 10 pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing.
390. A printer controller according to claim 362, for supplying dot data to at least one printhead module, the at 15 least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have 20 printed it.
391. A printer controller according to claim 362, for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. 25
392. A printer controller according to claim 362, for supplying data to a printhead module including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at 30 least one of the other groups of the nozzles.
393. A printer controller according to claim 362, for supplying data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and 35 a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1323
394. A printer controller according to claim 362, for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 5 395. A printer controller according to claim 362, for supplying data to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle positionx is at or adjacent the centre of the set of nozzles. 10
396. A printer controller according to claim 362, for supplying data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: 15 in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle.
397. A printer controller according to claim 362, for supplying data to a printhead module for receiving dot 20 data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data.
398. A printer controller according to claim 362, for supplying data to a printhead module including at least 25 one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
399. A printer controller according to claim 362, for supplying data to a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each 30 row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. 35
400. A printer controller according to claim 362, for supplying data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1324 aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. 5
401. A printer controller according to claim 362, for providing data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at 10 least one of the other groups of the nozzles.
402. A printer controller according to claim 362, for supplying data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead 15 module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold.
403. A printer controller according to claim 362, for supplying data to a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead 20 module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 25 404. A printer controller for supplying dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead 30 modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module.
405. A printer controller according to claim 404, wherein the nozzles are disposed in a plurality of rows, and 35 the printer controller is configured to reallocate at least one of the ink dots from at least one original print line to at least one alternate print line, thereby to effect the at least partial compensation. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1325
406. A printer controller according to claim 404, configured to retrieve the correction factor from a memory associated with the printhead.
407. A printer controller according to claim 406, wherein the memory is mounted with the printhead, the 5 printhead being mounted on the print engine.
408. A printer controller according to claim 404, wherein the rotational displacement is roll.
409. A printer controller according to claim 404, wherein the rotational displacement is yaw. 10
410. A printer controller according to claim 404, the printhead module being one of a plurality of printhead modules mounted on a carrier to form a printhead and the error in ink dot placement being an error relative to ink dots output by one or more of the other printhead modules 15 411. A printer controller according to claim 404, wherein the printhead module is part of a printhead comprising a plurality of the modules, the printer controller being configured to determine an order in which at least some of the dot data is supplied to a plurality of the printhead modules, the order being determined at least partly on the basis of one or more of the correction factors, thereby to at least partially compensate for the rotational displacement of the plurality of the printheads. 20
412. A printer controller according to claim 404, wherein the correction factor is at least partially based on a thickness of media being printed on.
413. A printer controller according to claim 412, configured to at least improve first order continuity between 25 ink dots printed by adjacent printhead modules.
414. A print engine including a print controller according to claim 404 and a plurality of the printhead modules that define a printhead, the print engine being configured to compensate for the rotational displacement of at least one of the printhead modules. 30
415. A print engine according to claim 4042, further including a memory for storing the correction factor in a form accessible to the printer controller.
416. A print engine according to claim 4042, configured to alter a timing of fire signals supplied to at least 35 one of the nozzles on the basis of the correction factor, thereby to further effect the at least partial compensation. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1326
417. A print engine according to claim 4044, configured to supply the altered fire signals are to both reallocated ink dots and non-reallocated ink dots.
418. A print engine according to claim 4042, wherein the printhead is a pagewidth printhead. 5
419. A printer including a print controller according to claim 404.
420. A printer according to claim 4045, further including a pagewidth printhead comprising a plurality of the printhead modules. 10
421. A printer controller according to claim 404, for implementing a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: 15 determining the rotational displacement; determining at least one correction factor that at least partially compensates for the ink dot displacement; and using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. 20 422. A printer controller according to claim 404 for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), ... , nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of 25 nozzles.
423. A printer controller according to claim 404, for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: 30 (a). providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b). providing a fire signal to the next inward pair of nozzles in each set; (c). in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 35
424. A printer controller according to claim 404, manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1327 pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed.
425. -A printer controller according to claim 404, for supplying data to a printhead module including: 5 at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers.
426. A printer controller according to claim 404, installed in a printer comprising: 10 a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. 15
427. A printer controller according to claim 404, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot 20 data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them.
428. A printer controller according to claim 404, installed in a printer comprising: 25 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and 30 the second printhead module; and the second printer controller outputs dot data only to the second printhead module.
429. A printer controller according to claim 404, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each 35 other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1328 at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data 5 received from the first printer controller.
430. A printer controller according to claim 404, for supplying dot data to a printhead module having a plurality of nozzles for expelling ink,.the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer 10 controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold.
431. A printer controller according to claim 404, for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to 15 extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the 20 printer controller is configured to provide one or more control signals that control the order of firing of the nozzles.
432. A printer controller according to claim 404, for outputting to a printhead module: dot data to be printed with at least two different inks; and 25 control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks.
433. A printer controller according to claim 404, for supplying data to a printhead module including at least 30 one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
434. A printer controller according to claim 404, for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable 35 into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1329 a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. 5 435. A printer controller according to claim 404, for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan.
436. A printer controller according to claim 404, for supplying one or more control signals to a printhead 10 module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a). a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b). a fire signal is provided to the next inward pair of nozzles in each set; (c). in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; 15 and (d). in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired.
437. A printer controller according to claim 404, printheadsupplying one or more control signals to a 20 printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 25
438. A printer controller according to claim 404, for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second 30 pairs of rows are fired such that some dots output to print media are printed to-by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing.
439. A printer controller according to claim 404, for supplying dot data to at least one printhead module, the at 35 least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1330 module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 5 440. A printer controller according to claim 404, for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead.
441. A printer controller according to claim 404, for supplying data to a printhead module including: 10 at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 15 442. A printer controller according to claim 404, for supplying data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. 20
443. A printer controller according to claim 404, for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 25 444. A printer controller according to claim 404, for supplying data to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), ... , nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 30
445. A printer controller according to claim 404, for supplying data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: 35 in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706
446. A printer controller according to claim 404, for supplying data to a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the 5 control data.
447. A printer controller according to claim 404, for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 10
448. A printer controller according to claim 404, for supplying data to a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is 15 fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row.
449. A printer controller according to claim 404, for supplying data to a printhead module comprising at least 20 first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. 25
450. A printer controller according to claim 404, for providing data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at 30 least one of the other groups of the nozzles.
451. A printer controller according to claim 404, for supplying data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead 35 module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. SUBSTITUTE SHEET (RULE 26) ROIAU WO 2005/120835 PCT/AU2004/000706 1332
452. A printer controller according to claim 404, for supplying data to a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row 5 prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
453. A printer controller for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being 10 configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold.
454. A printer controller according to claim 453, configured to modify the operation of the nozzles at or 15 adjacent the at least one thermal sensor, such that operation of nozzles not at or adjacent the at least one thermal sensor is not modified.
455. A printer controller according to claim 454, wherein each thermal sensor is associated with a predetermined group of the nozzles, the printer controller being configured to modify operation of the nozzles in 20 the predetermined group for which the temperature has risen above the first threshold.
456. A printer controller according to claim 455, wherein each thermal sensor is associated with a single nozzle. 25 457. A printer controller according to claim 456, wherein the modification includes the printer controller preventing operation of the nozzle.
458. A printer controller according to claim 457, wherein the modification includes the printer controller preventing operation of the nozzle for a predetermined period. 30
459. A printer controller according to claim 457, wherein the modification includes the printer controller preventing operation of the nozzle until the temperature drops below a second threshold.
460. A printer controller according to claim 459, wherein the second threshold is lower than the first 35 threshold. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1333
461. A printer controller according to claim 460, wherein the second threshold is the same as the first threshold.
462. *A printer controller according to claim 453, wherein the temperature is not determined explicitly by the 5 at least one thermal sensor or the module.
463. A printer controller according to claim 453, wherein each of the nozzles including a thermal ink ejection mechanism. 10 464. A printer controller according to claim 463, wherein the thermal sensor comprises at least part of one of the thermal inkjet mechanisms.
465. A printer controller according to claim 464, wherein the thermal sensor comprises a heating element. 15 466. A printer controller according to claim 465, wherein the thermal sensor determines the temperature by determining a resistance of the heating element.
467. A printer controller according to claim 453, configured to: receive thermal information from the at least one thermal sensor; 20 determine the modification based on the thermal information; and send control information back to the printhead module, the control information being indicative of the modification to make to the operation of the one or more nozzles.
468. A print engine including a printer controller according to claim 467 and the printhead module, wherein 25 the printhead module further includes a plurality of data latches, the data latches being configured to provide dot data to respective ones of the nozzles, at least some of the data latches being configured to receive thermal signals from respective ones of the thermal sensors during an acquisition period.
469. A print engine according to claim 468, wherein the data latches are configured to form a shift register, 30 the shift register being configured to: shift the print data in during a print load phase; sample the signals from the thermal sensors during a temperature load phase; and shift the thermal signals out to the printer controller during an output phase. 35 470. A print engine according to claim 469, wherein the output phase coincides with a subsequent print load phase. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1334
471. A print engine according to claim 470, further including logic circuitry configured to perform a bitwise operation on: each thermal signal as it is clocked out of the shift register; and each piece of dot data to be clocked into the shift register, such that when a thermal signal is indicative of a thermal problem with a nozzle, the logic circuitry prevents loading of data that would cause firing of that nozzle. 5
472. A print engine according to claim 471, wherein the logic circuitry includes an AND circuit that receives as inputs the dot data and the thermal signal corresponding to the nozzle for which the dot data is intended, an output of the AND circuit being in communication with an input of the shift register. 10 473. A printer controller according to claim 453, wherein each thermal sensor is associated with a pair of the nozzles.
474. A printer controller according to claim 453, for implementing a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational 15 displacement of a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: determining the rotational displacement; determining at least one correction factor that at least partially compensates for the ink dot displacement; and using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational 20 displacement.
475. A printer controller according to claim 453 for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of 25 nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
476. A printer controller according to claim 453, for implementing a method of expelling ink from a 30 printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: (a). providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b). providing a fire signal to the next inward pair of nozzles in each set; (c). in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and 35 (d). in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1335
477. A printer controller according to claim 453, manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is 5 left-handed.
478. A printer controller according to claim 453, for supplying data to a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, 10 wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers.
479. A printer controller according to claim 453, installed in a printer comprising: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and 15 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead.
480. A printer controller according to claim 453, installed in a printer comprising: 20 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are 25 configured such that no dot data passes between them.
481. A printer controller according to claim 453, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer 30 than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. 35
482. A printer controller according to claim 453, installed in a printer comprising: SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1336 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot 5 data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. 10 483. A printer controller according to claim 453, for supplying dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; 15 determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. 20 484. A printer controller according to claim 453, for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously 25 with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. 30 485. A printer controller according to claim 453, for outputting to a printhead module: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 35 SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1337
486. A printer controller according to claim 453, for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 5 487. A printer controller according.to claim 453, for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the 10 channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes.
488. A printer controller according to claim 453, for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead 15 comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan.
489. A printer controller according to claim 453, for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: 20 (a). a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b). a fire signal is provided to the next inward pair of nozzles in each set; (c). in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each 25 set have been fired, and then the central nozzle is fired.
490. A printer controller according to claim 453, for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising 30 providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
491. A printer controller according to claim 453, for supplying dot data to a printhead module comprising at 35 - least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1338 pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing, 5 492. A printer controller according to claim 453, for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints 10 an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
493. A printer controller according to claim 453, for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data 15 to at least one printhead.
494. A printer controller according to claim 453, for supplying data to a printhead module including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift 20 register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
495. A printer controller according to claim 453, for supplying data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: 25 a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number.
496. A printer controller according to claim 453, for supplying data to a printhead comprising a plurality of 30 printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan.
497. A printer controller according to claim 453, for supplying data to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink 35 in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1339
498. A printer controller according to claim 453, for supplying data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and 5 nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. 10 499. A printer controller according to claim 453, for supplying data to a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. 15 500. A printer controller according to claim 453, for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
501. A printer controller according to claim 453, for supplying data to a printhead module having a plurality 20 of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent 25 row.
502. A printer controller according to claim 453, for supplying data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to 30 the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows.
503. A printer controller according to claim 453, for providing data to a printhead module that includes: 35 at least one row of print nozzles; SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1340 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 5 504. A printer controller according to claim 453, for supplying data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. 10
505. A printer controller according to claim 453, for supplying data to a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row 15 prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
506. A printer controller according to claim 472, further including a logic circuit accepting as inputs a masking signal and the thermal signal corresponding to the nozzle for which the dot data is intended, the logic 20 circuit outputting the thermal signal to the input of the AND circuit in reliance on a value of the masking signal.
507. A printer controller according to claim 506, wherein the value of the masking signal enables masking of the thermal signal for at least one nozzle position, including the nozzle for which the current dot data is intended. 25 508. A printer controller according to claim 506, wherein the value of the masking signal enables masking of the thermal signal for a plurality of nozzle positions corresponding to a region of the printhead associated the nozzle for which the current dot data is intended.
509. A printer controller according to claim 506, wherein the value of the masking signal enables masking of 30 the thermal signal for all of the nozzle positions of the printhead.
510. A printer controller for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second 35 fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that SUBSTITUTE SHEET (RULE 26) ROIAU WO 2005/120835 PCT/AU2004/000706 1341 the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles.
511. A printer controller according to claim 510, wherein the one or more control signals include a fire control 5 sequence indicative of a first fire group to be fired.
512. A printer controller according to claim 511, the printhead being configured to shift the fire control sequence through a shift register to cause subsequent firing of the second and any other fire groups, wherein the printer controller is configured to provide the fire control sequence during an initiation phase of the printhead, 10 such that the fire control sequence does not need to be repeatedly provided by the printer controller while printing is taking place.
513. A printer controller according to claim 511, the printhead being configured to shift the fire control sequence through a shift register to cause subsequent firing of the second and any other fire groups, wherein 'the 15 printer controller is configured to provide the fire control sequence periodically during printing.
514. A printer controller according to claim 513, configured to provide the fire control sequence on a per row or per print-line basis. 20 515. A printer controller according to claim 510, configured to provide a fire enable signal in addition to the one or more fire control signals, such that the combination of the fire enable and fire control signals cause selected ones of the nozzles to fire in the predetermined sequence and in accordance with a predetermined timing.
516. A print engine including a printhead and a printer controller, the printhead comprising at least one 25 monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row 30 by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles.
517. A print engine according to claim 516, wherein the one or more control signals include a fire control 35 sequence indicative of a first fire group to be fired. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1342
518. A print engine according to claim 517, the printhead being configured to shift the fire control sequence through a shift register to cause subsequent firing of the second and any other fire groups, wherein the printer controller is configured to provide the fire control sequence during an initiation phase of the printhead, such that the fire control sequence does not need to be repeatedly provided by the printer controller while printing is taking 5 place.
519. A print engine according to claim 517, the printhead being configured to shift the fire control sequence through a shift register to cause subsequent firing of the second and any other fire groups, wherein the printer controller is configured to provide the fire control sequence periodically during printing. 10
520. A print engine according to claim 513, configured to provide the fire control sequence on a per row or per print-line basis.
521. A print engine according to claim 510, configured to provide a fire enable signal in addition to the one or 15 more fire control signals, such that the combination of the fire enable and fire control signals cause selected ones of the nozzles to fire in the predetermined sequence and in accordance with a predetermined timing.
522. A printer controller according to claim 510, for implementing a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of 20 a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: determining the rotational displacement; determining at least one correction factor that at least partially compensates for the ink dot displacement; and using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational 25 displacement.
523. A printer controller according to claim 510 for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of 30 nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
524. A printer controller according to claim 510, for implementing a method of expelling ink from a printhead 35 module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: providing a fire signal to nozzles at a first and nth position in each set of nozzles; SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1343 providing a fire signal to the next inward pair of nozzles in each set; in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 5
525. A printer controller according to claim 510, manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. 10
526. A printer controller according to claim 510, for supplying data to a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 15
527. A printer controller according to claim 510, installed in a printer comprising: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink, and at least first and second printer controllers configured to receive print data and process the print data to output dot 20 data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead.
528. A printer controller according to claim 510, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each 25 other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 30
529. A printer controller according to claim 510, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; 35 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1344 the second printhead module; and the second printer controller outputs dot data only to the second printhead module.
530. A printer controller according to claim 510, installed in a printer comprising: 5 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and 10 the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller.
531. A printer controller according to claim 510, for supplying dot data to at least one printhead module and at 15 least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead 20 modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module.
532. A printer controller according to claim 510, for supplying dot data to a printhead module having a 25 plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. 30 533. A printer controller according to claim 510, for outputting to a printhead module: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some-of the control data and at least some of the dot data for the at least two inks. 35 SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1345
534. A printer controller according to claim 510, for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 5 535. A printer controller according to claim 510, for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the 10 channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes.
536. A printer controller according to claim 510, for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead 15 comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan.
537. A printer controller according to claim 510, for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: 20 (a). a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b). a fire signal is provided to the next inward pair of nozzles in each set;. (c). in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each 25 set have been fired, and then the central nozzle is fired.
538. A printer controller according to claim 510, for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising 30 providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), ... nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
539. A printer controller according to claim 510, for supplying dot data to a printhead module comprising at 35 least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1346 pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. 5 540. A printer controller according to claim 510, for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints 10 an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
541. A printer controller according to claim 510, for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data 15 to at least one printhead.
542. A printer controller according to claim 510, for supplying data to a printhead module including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift 20 register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
543. A printer controller according to claim 510, for supplying data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: 25 a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number.
544. A printer controller according to claim 510, for supplying data to a printhead comprising a plurality of 30 printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan.
545. A printer controller according to claim 510, for supplying data to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink 35 in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1347
546. A printer controller according to claim 510, for supplying data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and 5 nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. 10 547. A printer controller according to claim 510, for supplying data to a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. 15 548. A printer controller according to claim 510, for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
549. A printer controller according to claim 510, for supplying data to a printhead module having a plurality 20 of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent 25 row.
550. A printer controller according to claim 510, for supplying data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to 30 the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows.
551. A printer controller according to claim 510, for providing data to a printhead module that includes: 35 at least one row of print nozzles; SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1348 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 5 552. A printer controller according to claim 510, for supplying data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. 10
553. A printer controller according to claim 510, for supplying data to a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row 15 prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
554. A printer controller according to claim 510, wherein the printhead module includes a plurality of pairs of the rows, each pair of rows including an odd row and an even row, the odd and even rows in each pair being offset 20 from each other in both x and y directions relative to an intended direction of print media movement relative to the printhead, the printer controller being configured to control the at least one printhead module to cause firing of at least a plurality of the odd rows prior to firing any of the even rows, or vice versa.
555. A printer controller according to claim 554, wherein all the odd rows are fired before any of the even 25 rows are fired, or vice versa.
556. A printer controller according to claim 554, configured to control the printhead module such that the odd rows, or the even rows, or both, are fired in a predetermined order. 30 557. A printer controller according to claim 556, configurable such that the predetermined order is selectable from a plurality of predetermined available orders.
558. A printer controller according to claim 554, wherein the predetermined order is sequential. 35 559. A printer controller according to claim 558, configurable such that the predetermined order can commence at any of a plurality of the rows. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1349
560. A printer controller for outputting to a printhead module: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being 5 configured to output at least some of the control data and at least some of the dot data for the at least two inks.
561. A printer controller according to claim 560, wherein the communication output is configured to output the dot data and control data serially. 10 562. A printer controller according to claim 560, further including a plurality of the communication outputs.
563. A printer controller according to claim 561, further including a plurality of the communication outputs.
564. A print engine comprising a print controller according to claim 560 and a plurality of printhead modules, 15 the printhead modules being disposed end to end for printing a width exceeding that of any of the individual printhead modules, the communications input of each of the printhead modules being connected to a common dot data and control data bus, the common dot data and control data bus being in functional communication with the communication output. 20 565. A print engine according to claim 564, wherein each module is configured to respond to dot data and control data on the bus only when it is intended for that module.
566. A printer incorporating a print engine according to claim 564. 25 567. A printer incorporating a print controller according to claim 560.
568. A print engine according to claim 564, wherein the printhead modules together form a pagewidth printhead. 30 569. A printer according to claim 567, further including a pagewidth printhead comprising a plurality of the printhead modules.
570. A printer controller according to claim 560, for implementing a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of 35 a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: determining the rotational displacement; SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1350 determining at least one correction factor that at least partially compensates for the ink dot displacement; and using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. 5 571. A printer controller according to claim 560 for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of 10 nozzles.
572. A printer controller according to claim 560, for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: 15 (a). providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b). providing a fire signal to the next inward pair of nozzles in each set; (c). in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 20
573. A printer controller according to claim 560, manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. 25
574. A printer controller according to claim 560, for supplying data to a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 30
575. A printer controller according to claim 560, installed in a printer comprising: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot 35 data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1351
576. A printer controller according to claim 560, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot 5 data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them.
577. A printer controller according to claim 560, installed in a printer comprising: 10 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and 15 the second printhead module; and the second printer controller outputs dot data only to the second printhead module.
578. A printer controller according to claim 560, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each 20 other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein 25 the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller.
579. A printer controller according to claim 560, for supplying dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the 30 printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being. determined at least partly on the basis of the correction factor, thereby to at least 35 partially compensate for the rotational displacement; and supply the dot data to the printhead module. SUBSTITUTE SHEET (RULE 26) ROIAU WO 2005/120835 PCT/AU2004/000706 1352
580. A printer controller according to claim 560, for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature 5 rising above a first threshold.
581. A printer controller according to claim 560, for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped 10 into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the 15 nozzles.
582. A printer controller according to claim 560, for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 20
583. A printer controller according to claim 560, for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and 25 a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes.
584. A printer controller according to claim 560, for supplying data to a printhead comprising a plurality of 30 printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan.
585. A printer controller according to claim 560, for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, 35 each of the nozzles being configured to expel ink in response to a fire signal, such that: (a). a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b). a fire signal is provided to the next inward pair of nozzles in each set; SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1353 (c). in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. 5
586. A printer controller according to claim 560, for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle 10 position n, nozzle position 2, nozzle position (n-), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
587. A printer controller according to claim 560, for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row 15 being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. 20
588. A printer controller according to claim 560, for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second-rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead 25 module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
589. A printer controller according to claim 560, for receiving first data and manipulating the first data to 30 produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead.
590. A printer controller according to claim 560, for supplying data to a printhead module including: at least one row of print nozzles; 35 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1354
591. A printer controller according to claim 560, for supplying data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and 5 a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number.
592. A printer controller according to claim 560, for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead 10 comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan.
593. A printer controller according to claim 560, for supplying data to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the 15 sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
594. A printer controller according to claim 560, for supplying data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to 20 expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. 25
595. A printer controller according to claim 560, for supplying data to a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. 30
596. A printer controller according to claim 560, for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 35 597. A printer controller according to claim 560, for supplying data to a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1355 fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. 5
598. A printer controller according to claim 560, for supplying data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows 10 are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows.
599.' A printer controller according to claim 560, for providing data to a printhead module that includes: at least one row of print nozzles; 15 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
600. A printer controller according to claim 560, for supplying data to a printhead module having a plurality 20 of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. 25 601. A printer controller according to claim 560, for supplying data to a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise 30 have. printed it.
602. A printer controller for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed, the printer controller being 35 configured to control order and timing of the data supplied to the printhead such that the dropped row is compensated for during printing by the printhead module. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1356
603. A printer controller according to claim 602, wherein the displaced row portion is disposed adjacent one end of the printhead module.
604. A printer controller according to claim 602, wherein the printhead module includes a plurality of the 5 rows, wherein each of at least a plurality of the rows includes one of the displaced row portions.
605. A printer controller according to claim 604, wherein the displaced row portions of at least some of the rows are different in length than the displaced row portions of at least some of the other rows. 10 606. A printer controller according to claim 605, wherein each of the rows has a displaced row portion, and the sizes of the respective displaced row portions increase from row to row in the direction normal to that of the pagewidth to be printed.
607. A printer controller according to claim 602, for supplying supplying the data to a printhead comprising a 15 plurality of the printhead modules.
608. A printer controller according to claim 602 for supplying data to a printhead comprising a plurality of the printhead modules, wherein the displaced row portion of at least one of the printhead modules is disposed adjacent another of the printhead modules. 20
609. A printer controller according to claim 608, wherein the printhead modules are the same shape and configuration as each other, and are arranged end to end across the intended print width.
610. A printer controller according to claim 608,,the printhead being a pagewidth printhead. 25
611. A printer controller according to claim 609, the printhead being a pagewidth printhead.
612. A printer controller according to claim 602, for implementing a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of 30 a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: determining the rotational displacement; determining at least one correction factor that at least partially compensates for the ink dot displacement; and using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational 35 displacement. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1357
613. A printer controller according to claim 602 for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, 5 nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
614. A printer controller according to claim 602, for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles 10 being configured to expel ink in response to a fire signal, the method comprising the steps of: (a). providing a fire signal to nozzles at a firsthand nth position in each set of nozzles; (b). providing a fire signal to the next inward pair of nozzles in each set; (c). in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set 15 have been fired, and then firing the central nozzle.
615. A printer controller according to claim 602, manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on 20 a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed.
616. A printer controller according to claim 602, for supplying data to a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, 25 wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers.
617. A printer controller according to claim 602, installed in a printer comprising: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and 30 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead.
618. A printer controller according to claim 602, installed in a printer comprising: 35 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1358 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 5
619. A printer controller according to claim 602, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; 10 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. 15 620. A printer controller according to claim 602, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot 20 data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller, and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. 25 621. A printer controller according to claim 602, for supplying dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; 30 determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. 35 622. A printer controller according to claim 602, for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1359 controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold.
623. A printer controller according to claim 602, for controlling a printhead comprising at least one 5 monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row 10 by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles.
624. A printer controller according to claim 602, for outputting to a printhead module: 15 dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 20 625. A printer controller according to claim 602, for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the 25 channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes.
626. A printer controller according to claim 602, for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead 30 comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan.
627. A printer controller according to claim 602, for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: 35 (a). a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b). a fire signal is provided to the next inward pair of nozzles in each set; SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1360 (c). in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. 5
628. A printer controller according to claim 602, for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle 10 position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
629. A printer controller according to claim 602, for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row 15 being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. 20
630. A printer controller according to claim 602, for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead 25 module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
631. A printer controller according to claim 602, for receiving first data and manipulating the first data to 30 produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead.
632. A printer controller according to claim 602, for supplying data to a printhead module including: at least one row of print nozzles; 35 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1361
633. A printer controller according to claim 602, for supplying data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and 5 a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number.
634. A printer controller according to claim 602, for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead 10 comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan.
635. A printer controller according to claim 602, for supplying data to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the 15 sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), ... , nozzle position x], wherein nozzle position x is at or adjacent the centre of the, set of nozzles.
636. A printer controller according to claim 602, for supplying data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to 20 expel'the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. 25
637. A printer controller according to claim 602, for supplying data to a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. 30
638. A printer controller according to claim 602, for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 35 639. A printer controller according to claim 602, for supplying data to a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each rmw hpino an-ned into at least first and second fire groups, the printhead module being configured to sequentially SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1362 fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. 5
640. A printer controller according to claim 602, for supplying data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows 10 are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows.
641. A printer controller according to claim 602, for providing data to a printhead module that includes: at least one row of print nozzles; 15 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
642. A printer controller according to claim 602, for supplying data to a printhead module having a plurality 20 of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. 25 643. A printer controller according to claim 602, for supplying data to a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise 30 have printed it.
644. A printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and 35 a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1363
645. A printer controller according to claim 644, wherein the first number is n.
646. . A printer controller according to claim 644, wherein the first number is less than n. 5
647. A printer controller according to claim 644, wherein the printhead module being configurable into at least one other mode, in which the at least one printhead module is configured to receive print data for a third number of print channels other than the first and second numbers, the printer controller being selectively configurable to supply the print data for the third number of print channels. 10
648. A printer controller according to claim 644, wherein n is 4 and the second number is less than 4.
649. A printer controller according to claim 644, wherein n is 5 and the second number is less than 5. 15 650. A printer controller according to claim 644, wherein n is 6 and the second number is less than 6.
651. A printer controller according to claim 650, wherein the second number is 3, 4 or 5.
652. A print engine including the print controller according to claim 644 and the at least one printhead 20 module.
653. A print engine according to claim 652, wherein the mode is selected based on the contents of a memory associated with the at least one printhead module. 25 654. A printhead according to claim 652, wherein the memory is a register.
655. A printhead according to claim 652, wherein the register is on an integrated circuit forming part of the print engine. 30 656. A printer including a printer controller according to claim 644.
657. A printer including a print engine according to claim 652.
658. A printer according to claim 656, including a pagewidth printhead comprising a plurality of the printhead 35 modules of claim 1. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1364
659. A printer controller according to claim 644, for implementing a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: 5 determining the rotational displacement; determining at least one correction factor that at least partially compensates for the ink dot displacement; and using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. 10 660. A printer controller according to claim 644 for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of 15 nozzles.
661. A printer controller according to claim 644, for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: 20 (a). providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b). providing a fire signal to the next inward pair of nozzles in each set; (c). in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 25
662. A printer controller according to claim 644, manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. 30
663. A printer controller according to claim 644, for supplying data to a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 35
664. A printer controller according to claim 644, installed in a printer comprising: SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1365 a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the 5 printhead.
665. A printer controller according to claim 644, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; 10 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 15 666. A printer controller according to claim 644, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot 20 data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module.
667. A printer controller according to claim 644, installed in a printer comprising: 25 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and 30 the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller.
668. A printer controller according to claim 644, for supplying dot data to at least one printhead module and at 35 least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1366 access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and 5 supply the dot data to the printhead module.
669. A printer controller according to claim 644, for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer 10 controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold.
670. A printer controller according to claim 644, for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to 15 extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the 20 printer controller is configured to provide one or more control signals that control the order of firing of the nozzles.
671. A printer controller according to claim 644, for outputting to a printhead module: dot data to be printed with at least two different inks; and 25 control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks.
672. A printer controller according to claim 644, for supplying data to a printhead module including at least 30 one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
673. A printer controller according to claim 644, for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead 35 comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1367
674. A printer controller according to claim 644, for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a). a fire signal is provided to nozzles at a first and nth position in each set of nozzles; 5 (b). a fire signal is provided to the next inward pair of nozzles in each set; (c). in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. 10
675. A printer controller according to claim 644, for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle 15 position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
676. A printer controller according to claim 644, for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row 20 being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. 25
677. A printer controller according to claim 644, for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead 30 module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
678. A printer controller according to claim 644, for receiving first data and manipulating the first data to 35 produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1368
679. A printer controller according to claim 644, for supplying data to a printhead module including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at 5 least one of the other groups of the nozzles.
680. A printer controller according to claim 644, for supplying data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and 10 a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number.
681. A printer controller according to claim 644, for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead 15 comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan.
682. A printer controller according to claim 644, for supplying data to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the 20 sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
683. A printer controller according to claim 644, for supplying data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to 25 expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. 30
684. A printer controller according to claim 644, for supplying data to a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. 35 SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1369
685. A printer controller according to claim 644, for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 5 686. A printer controller according to claim 644, for supplying data to a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the 10 nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row.
687. A printer controller according to claim 644, for supplying data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being 15 aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. 20 688. A printer controller according to claim 644, for providing data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 25
689. A printer controller according to claim 644, for supplying data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first 30 threshold.
690. A printer controller according to claim 644, for supplying data to a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being 35 configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706
691. A printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types 5 of the modules, wherein each type is determined by its geometric shape in plan.
692. A printer controller according to claim 691, wherein the printhead comprises a plurality of at least one of the types of module. 10 693. A printer controller according to claim 692, wherein the printhead comprises a plurality of each of at least two of the types of module.
694. A printer controller according to claim 691, wherein the printhead comprises two types of the module. 15 695. A printer controller according to claim 694, wherein the two types of module alternate across a print width of the printhead.
696. A printer controller according to claim 691, each of the modules including at least one row of print nozzles, wherein each of the at least one row of print nozzles includes at least a portion that extends at an acute 20 angle to an intended relative direction of movement between the printhead and print media.
697. A printer controller according to claim 696, wherein the different types of modules are configured, and arranged relative to each other, such that there is substantially no growth in offset of each of the at least one row of print nozzles in a direction across an intended print width of the printhead. 25
698. A printer controller according to claim 691, wherein each of the printhead modules is a monolithic integrated circuit.
699. A printer controller according to claim 691, each of the modules including at least one row of print 30 nozzles, wherein each of the at least one rows includes at least two sub-rows, each of the sub-rows being parallel to each other and displaced relative to each other -in a direction of intended movement of print media relative to the printhead.
700. A printer controller according to claim 691, wherein at least one row in each of the printhead modules 35 prints an ink corresponding to at least one row on an adjacent printhead module, wherein the corresponding rows of at least two of the different printhead modules are offset from each other in a direction of intended movement of print media relative to the printhead, SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1371
701. A printer controller according to claim 691, the printhead being a pagewidth printhead.
702. A printer controller according to claim 697, the printhead being a pagewidth printhead. 5
703. A printer controller according to claim 702, the printhead being a pagewidth printhead.
704. A printer controller according to claim 691, for implementing a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of 10 a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: determining the rotational displacement; determining at least one correction factor that at least partially compensates for the ink dot displacement; and using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational 15 displacement.
705. A printer controller according to claim 691 for implementing a method of expelling ink from a printhead. module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of 20 nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
706. A printer controller according to claim 691, for implementing a method of expelling ink from a printhead 25 module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: (a). providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b). providing a fire signal to the next inward pair of nozzles in each set; (c). in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and 30 (d). in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle.
707. A printer controller according to claim 691, manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic 35 pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706
708. A printer controller according to claim 691, for supplying data to a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 5
709. A printer controller according to claim 691, installed in a printer comprising: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot 10 data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead.
710. A printer controller according to claim 691, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each 15 other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 20
711. A printer controller according to claim 691, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; 25 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. 30 712. A printer controller according to claim 691, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot 35 data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein SUBSTITUTE SHEET (RULE 26) ROIAU WO 2005/120835 PCT/AU2004/000706 1373 the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller.
713. A printer controller according to claim 691, for supplying dot data to at least one printhead module and at 5 least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead 10 modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module.
714. A printer controller according to claim 691, for supplying dot data to a printhead module having a 15 plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. 20 715. A printer controller according to claim 691, for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously 25 with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. 30 716. A printer controller according to claim 691, for outputting to a printhead module: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 35 SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1374
717. A printer controller according to claim 691, for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 5 718. A printer controller according to claim 691, for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the 10 channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes.
719. A printer controller according to claim 691, for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, 15 each of the nozzles being configured to expel ink in response to a fire signal, such that: (a). a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b). a fire signal is provided to the next inward pair of nozzles in each set; (c). in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and 20 (d). in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired.
720. A printer controller according to claim 691, for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent 25 nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 30 721. A printer controller according to claim 691, for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of 35 rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1375
722. A printer controller according to claim 691, for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead 5 module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in. the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
723. A printer controller according to claim 691, for receiving first data and manipulating the first data to 10 produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead.
724. A printer controller according to claim 691, for supplying data to a printhead module including: at least one row of print nozzles; 15 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
725. A printer controller according to claim 691, for supplying data to a printhead capable of printing a 20 maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. 25 726. A printer controller according to claim 691, for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan.
727. A printer controller according to claim 691, for supplying data to a printhead module including at least 30 one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 35 728. A printer controller according to claim 691, for supplying data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1376 expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire 5 the central nozzle.
729. A printer controller according to claim 691, for supplying data to a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the 10 control data.
730. A printer controller according to claim 691, for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 15
731. A printer controller according to claim 691, for supplying data to a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is 20 fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all. fired before the nozzles of each subsequent row.
732. A printer controller according to claim 691, for supplying data to a printhead module comprising at least 25 first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. 30
733. A printer controller according to claim 691, for providing data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at 35 least one of the other groups of the nozzles. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1377
734. A printer controller according to claim 691, for supplying data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first 5 threshold.
735. A printer controller according to claim 691, for supplying data to a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being 10 configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
736. A printer controller for supplying one or more control signals to a printhead module, the printhead 15 module including at least one row that comprises a plurality of. sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a). a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b). a fire signal is provided to the next inward pair of nozzles in each set; (c). in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; 20 and (d). in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired.
737. A printer controller according to claim 736, wherein the printhead module includes a plurality of the 25 rows of nozzles, the printer controller being configured to control the printhead module such that steps (a) to (d) are repeated for each of the rows of nozzles.
738. A printer controller according to claim 737, wherein the rows are disposed in pairs. 30 739. A printer controller according to claim 738, wherein the rows in each pair of rows are offset relative to each other.
740. A printer controller according to claim 739, wherein each pair of rows is configured to print the same color ink. 35
741. A printer controller according to claim 740, wherein each pair of rows is connected to a common ink source. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1378
742. A printer controller according to claim 736, wherein the sets of nozzles are adjacent each other.
743. A printer controller according to claim 736, wherein the sets of nozzles are separated by an intermediate 5 nozzle, the intermediate nozzle being fired either prior to the nozzle at position 1 in each set, or following the nozzle at position n.
744. A printer controller according to claim 736, wherein the printhead module is one of a plurality of printhead modules that form a pagewidth printhead, the printer controller being configure to supply the control 10 signals to at least a plurality of the printhead modules.
745. A printer controller according to claim 736, for implementing a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method 15 comprising the steps of: determining the rotational displacement; determining at least one correction factor that at least partially compensates for the ink dot displacement; and using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. 20
746. A printer controller according to claim 736 for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, 25 nozzle position (n-1), ... , nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
747. A printer controller according to claim 736, for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles 30 being configured to expel ink in response to a fire signal, the method comprising the steps of: (a). providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b). providing a fire signal to the next inward pair of nozzles in each set; (c). in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set 35 have been fired, and then firing the central nozzle. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1379
748. A printer controller according to claim 736, manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. 5
749. A printer controller according to claim 736, for supplying data to a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 10
750. A printer controller according to claim 736, installed in a printer comprising: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot 15 data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead.
751. A printer controller according to claim 736, installed in a printer comprising: a printhead comprising first and second. elongate printhead modules, the printhead modules being parallel to each 20 other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 25
752. A printer controller according to claim 736, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of ajoin region, wherein the first printhead module is longer than the second printhead module; 30 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. 35 753. A printer controller according to claim 736, installed in a printer comprising: SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1380 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot 5 data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller, and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. 10 754. A printer controller according to claim 736, for supplying dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; 15 determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. 20 755. A printer controller according to claim 736, for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. 25
756. A printer controller according to claim 736, for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, 30 the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. 35
757. A printer controller according to claim 736, for outputting to a printhead module: dot data to be printed with at least two different inks; and SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1381 control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 5 758. A printer controller according to claim 736, for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
759. A printer controller according to claim 736, for supplying print data to at least one printhead module 10 capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; 15 wherein the printer controller is selectively configurable to supply dot data for the first and second modes.
760. A printer controller according to claim 736, for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 20
761. A printer controller according to claim 736, for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle 25 position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
762. A printer controller according to claim 736, for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row 30 being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. 35
763. A printer controller according to claim 736, for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1382 ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have 5 printed it.
764. A printer controller according to claim 736, for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. 10
765. A printer controller according to claim 736, for supplying data to a printhead module including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at 15 least one of the other groups of the nozzles.
766. A printer controller according to claim 736, for supplying data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and 20 a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number.
767. A printer controller according to claim 736, for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead 25 comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan.
768. A printer controller according to claim 736, for supplying data to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the 30 sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
769. A printer controller according to claim 736, for supplying data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to 35 expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1383 in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle.
770. A printer controller according to claim 736, for supplying data to a printhead module for receiving dot 5 data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data.
771. A printer controller according to claim 736, for supplying data to a printhead module including at least 10 one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
772. A printer controller according to claim 736, for supplying data to a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each 15 row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. 20
773. A printer controller according to claim 736, for supplying data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows 25 are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows.
774. A printer controller according to claim 736, for providing data to a printhead module that includes: at least one row of print nozzles; 30 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
775. A printer controller according to claim 736, for supplying data to a printhead module having a plurality 35 of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1384 module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold.
776. A printer controller according to claim 736, for supplying data to a printhead module comprising a 5 plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 10
777. A printer controller according to claim 736, wherein the printhead module includes a plurality of the rows, the printer controller being configured to cause firing of each nozzle in each row simultaneously with the nozzle or nozzles at the same position in the other rows. 15 778. A printer controller according to claim 736, including a plurality of pairs of the rows, each pair of rows including an odd row and an even row, the odd and even rows in each pair being offset from each other in both x and y directions relative to an intended direction of print media movement relative to the printhead, the printer controller being configured to control the at least one printhead module to cause firing of at least a plurality of the odd rows prior to firing any of the even rows, or vice versa. 20
779. A printer controller according to claim 778, wherein all the odd rows are fired before any of the even rows are fired, or vice versa.
780. A printer controller according to claim 778, configured to control the printhead such that the odd rows, or 25 the even rows, or both, are fired in a predetermined order.
781. A printer controller according to claim 780, configurable such that the predetermined order is selectable from a plurality of predetermined available orders. 30 782. A printer controller according to claim 778, wherein the predetermined order is sequential.
783. A printer controller according to claim 782, configurable such that the predetermined order can commence at any of a plurality of the rows. 35 784. A printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1385 nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 5 785. A printer controller according to claim 784, configured to cause the nozzle at each given position within the set to be fired simultaneously with the nozzles in the other sets at respective corresponding positions.
786. A printer controller according to claim 784, wherein the printhead module includes a plurality of the rows of nozzles, the printer controller being configured to control the printhead module such that the steps are 10 repeated for each of the rows of nozzles.
787. A printer controller according to claim 786, wherein the rows are disposed in pairs.
788. A printer controller according to claim 787, wherein the rows in each pair of rows are offset relative to 15 each other.
789. A printer controller according to claim 788, wherein each pair of rows is configured to print the same color ink. 20 790. A printer controller according to claim 789, wherein each pair of rows is connected to a common ink source.
791. A printer controller according to claim 784, wherein the sets of nozzles are adjacent each other. 25 792. A printer controller according to claim 784, wherein the sets of nozzles are separated by an intermediate nozzle, the intermediate nozzle being fired either prior to the nozzle at position 1 in each set, or following the nozzle at position n.
793. A printer controller according to claim 784, wherein the printhead module is one of a plurality of 30 printhead modules that form a pagewidth printhead, the printer controller being configure to supply the control signals to at least a plurality of the printhead modules.
794. A printer controller according to claim 784, for implementing a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of 35 a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: determining the rotational displacement; SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1386 determining at least one correction factor that at least partially compensates for the ink dot displacement; and using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. 5 795. A printer controller according to claim 784 for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle positionx is at or adjacent the centre of the set of 10 nozzles.
796. A printer controller according to claim 784, for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: 15 (a). providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b). providing a fire signal to the next inward pair of nozzles in each set; (c). in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 20
797. A printer controller according to claim 784, manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the'printhead modules is right-handed and at least another is left-handed. 25
798. A printer controller according to claim 784, for supplying data to a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 30
799. A printer controller according to claim 784, installed in a printer comprising: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot 35 data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1387
800. A printer controller according to claim 784, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot 5 data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them.
801. A printer controller according to claim 784, installed in a printer comprising: 10 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and 15 the second printhead module; and the second printer controller outputs dot data only to the second printhead module.
802. A printer controller according to claim 784, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each 20 other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein 25 the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller.
803. A printer controller according to claim 784, for supplying dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the 30 printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least 35 partially compensate for the rotational displacement; and supply the dot data to the printhead module. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1388
804. A printer controller according to claim 784, for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature 5 rising above a first threshold.
805. A printer controller according to claim 784, for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped 10 into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the 15 nozzles.
806. A printer controller according to claim 784, for outputting to a printhead module: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; 20 the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks.
807. A printer controller according to claim 784, for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of 25 the row portion including a component in a direction normal to that of a pagewidth to be printed.
808. A printer controller according to claim 784, for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: 30 a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. 35 809. A printer controller according to claim 784, for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1389
810. A printer controller according to claim 784, for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: 5 (a). a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b). a fire signal is provided to the next inward pair of nozzles in each set; (c). in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each 10 set have been fired, and then the central nozzle is fired.
811. A printer controller according to claim 784, for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first-row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel 15 relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. 20 812. A printer controller according to claim 784, for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints 25 an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
813. A printer controller according to claim 784, for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data 30 to at least one printhead. . 814. A printer controller according to claim 784, for supplying data to a printhead module including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift 35 register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1390
815. A printer controller according to claim 784, for supplying data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, 5 wherein the first number is greater than the second number.
816. A printer controller according to claim 784, for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 10
817. A printer controller according to claim 784, for supplying data to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], 15 wherein nozzle position x is at or adjacent the centre of the set of nozzles.
818. A printer controller according to claim 784, for supplying data to a printhead module including at least one row that'comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and 20 nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. 25 819. A printer controller according to claim 784, for supplying data to a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. 30 820. A printer controller according to claim 784, for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
821. A printer controller according to claim 784, for supplying data to a printhead module having a plurality 35 of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1391 fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. 5 822. A printer controller according to claim 784, for supplying data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least 10 some other dots output to print media are printed to by nozzles from the second pair of rows.
823. A printer controller according to claim 784; for providing data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift 15 register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
824. A printer controller according to claim 784, for supplying data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal 20 sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold.
825. A printer controller according to claim 784, for supplying data to a printhead module comprising a 25 plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 30
826. A printer controller according to claim 784, wherein the printhead module includes a plurality of the rows, the printer controller being configured to cause firing of each nozzle in each row simultaneously with the nozzle or nozzles at the same position in the other rows. 35 827. A printer controller according to claim 784, including a plurality of pairs of the rows, each pair of rows including an odd row and an even row, the odd and even rows in each pair being offset from each other in both x and y directions relative to an intended direction of print media movement relative to the printhead, the printer SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1392 controller being configured to control the at least one printhead module to cause firing of at least a plurality of the odd rows prior to firing any of the even rows, or vice versa.
828. A printer controller according to claim 827 wherein all the odd rows are fired before any of the even 5 rows are fired, or vice versa.
829. A printer controller according to claim 827 configured to control the printhead such that the odd rows, or the even rows, or both, are fired in a predetermined order. . 10 830. A printer controller according to claim 829, configurable such that the predetermined order is selectable from a plurality of predetermined available orders.
831. A printer controller according to claim 827 wherein the predetermined order is sequential. 15 832. A printer controller according to claim 831, configurable such that the predetermined order can' commence at any of a plurality of the rows.
833. A printer controller for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with 20 respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. 25
834. A print engine comprising a printer controller according to claim 833 and the printhead module, wherein the printhead module is controllable such that either of the nozzles in each aligned pair of nozzles in the first and second rows can be selected to output ink for a selected dot to be printed on the print media. 30 835. A print engine according to claim 834, wherein, in the event a nozzle in the first row is faulty, the corresponding nozzle in the second row is selected to output ink for a dot for which the faulty nozzle would otherwise have output ink.
836. A print engine according to claim 834, including a plurality of sets of the first and second rows. 35
837. A print engine according to claim 836, wherein each of the sets of the first and second rows is configured to print in a single color or ink type. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1393
838. A print engine according to claim 837, wherein the first and second rows in at least one of the sets are separated by one or more rows from the other set or sets. 5 839. A print engine according to claim 833, wherein each of the rows includes an odd sub-row and an even sub-row, the odd and even sub-rows being offset with respect to each other in a direction of intended print media travel relative to the printhead.
840. A print engine according to claim 839, wherein the odd and even sub-rows are transversely offset relative 10 to each other.
841. A print engine according to claim 834, configured such that the first and second rows are fired alternately. 15 842. A print engine according to claim 834, comprising a plurality of the printhead modules.
843. A printer including a printer controller according to claim 833.
844. A printer including a print engine according to claim 834. 20
845. A printer controller according to claim 833, for implementing a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: 25 determining the rotational displacement; determining at least one correction factor that at least partially compensates for the ink dot displacement; and using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. 30 846. A printer controller according to claim 833 for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of 35 nozzles. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1394
847. A printer controller according to claim 833, for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: (a). providing a fire signal to nozzles at a first and nth position in each set of nozzles; 5 (b). providing a fire signal to the next inward pair of nozzles in each set; (c). in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 10 848. A printer controller according to claim 833, manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. 15 849. A printer controller according to claim 833, for supplying data to a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 20 850. A printer controller according to claim 833, installed in a printer comprising: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the 25 printhead.
851. A printer controller according to claim 833, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; 30 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 35 852. A printer controller according to claim 833, installed in a printer comprising: SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1395 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot 5 data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module.
853. A printer controller according to claim 833, installed in a printer comprising: 10 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and 15 the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller.
854. A printer controller according to claim 833, for supplying dot data to at least one printhead module and at 20 least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead 25 modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module.
855. A printer controller according to claim 833, for supplying dot data to a printhead module having a 30 plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. 35 856. A printer controller according to claim 833, for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1396 into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the 5 printer controller is configured to provide one or more control signals that control the order of firing of the nozzles.
857. A printer controller according to claim 833, for outputting to a printhead module: dot data to be printed with at least two different inks; and 10 control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks.
858. A printer controller according to claim 833, for supplying data to a printhead module including at least 15 one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
859. A printer controller according to claim 833, for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable 20 into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number, wherein the printer controller is selectively configurable to supply dot data for- the first and second modes. 25
860. A printer controller according to claim 833, for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 30 861. A printer controller according to claim 833, for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: a fire signal is provided to nozzles at a first and nth position in each set of nozzles; a fire signal is provided to the next inward pair of nozzles in each set; 35 in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1397
862. A printer controller according to claim 833, for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising 5 providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
863. A printer controller according to claim 833, for supplying dot data to at least one printhead module, the at 10 least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have 15 printed it.
864. A printer controller according to claim 833, for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. 20
865. A printer controller according to claim 833, for supplying data to a printhead module including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at 25 least one of the other groups of the nozzles.
866. A printer controller according to claim 833, for supplying data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and 30 a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number.
867. A printer controller according to claim 833, for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead 35 comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1398
868. A printer controller according to claim 833, for supplying data to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: (nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], 5 wherein nozzle position x is at or adjacent the centre of the set of nozzles.
869. A printer controller according to claim 833, for supplying data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and 10 nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. 15 870. A printer controller according to claim 833, for supplying data to a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. 20 871. A printer controller according to claim 833, for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
872. A printer controller according to claim 833, for supplying data to a printhead module having a plurality 25 of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent 30 row.
873. A printer controller according to claim 833, for supplying data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to 35 the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1399
874. A printer controller according to claim 833, for providing data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift 5 register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
875. A printer controller according to claim 833, for supplying data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal 10 sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold.
876. A printer controller according to claim 833, for supplying data to a printhead module comprising a 15 plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 20
877. A printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, 25 in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
878. A print engine comprising a printer controller according to claim 877 and the at least one printhead module, wherein each nozzle in the first row is paired with a nozzle in the second row, such that each pair of 30 nozzles is aligned in an intended direction of print media travel relative to the printhead module.
879. A print engine according to claim 878, including a plurality of sets of the first and second rows.
880. A print engine according to claim 879, wherein each of the sets of the first and second rows is configured 35 to print in a single color or ink type. SUBSTITUTE SHEET (RULE 26) ROIAU WO 2005/120835 PCT/AU2004/000706 1400
881. A print engine according to claim 877, wherein each of the rows includes an odd and an even sub-row, the odd and even sub-rows being offset with respect to each other in a direction of print media travel relative to the printhead in use. 5 882. A print engine according to claim 881, wherein the odd and even sub-rows are transversely offset with respect to each other.
883. A printer including at least one printer controller according to claim 877. 10 884. A printer including at least one print engine according to claim 878.
885. A printer controller according to claim 877, for implementing a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method 15 comprising the steps of: determining the rotational displacement; determining at least one correction factor that at least partially compensates for the ink dot displacement; and using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. 20
886. A printer controller according to claim 877 for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, 25 nozzle position (n-1), ... , nozzle position x], wherein nozzle positionx is at or adjacent the centre of the set of nozzles.
887. A printer controller according to claim 877, for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles 30 being configured to expel ink in response to a fire signal, the method comprising the steps of: (a). providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b). providing a fire signal to the next inward pair of nozzles in each set; (c). in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set 35 have been fired, and then firing the central nozzle. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1401
888. . A printer controller according to claim 877, manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. 5
889. A printer controller according to claim 877, for supplying data to a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 10
890. A printer controller according to claim 877, installed in a printer comprising: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot 15 data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead.
891. A printer controller according to claim 877, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each 20 other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 25
892. A printer controller according to claim 877, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; 30 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. 35 893. A printer controller according to claim 877, installed in a printer comprising: SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1402 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot 5 data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller, and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. 10 894. A printer controller according to claim 877, for supplying dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; 15 determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. 20 895. A printer controller according to claim 877, for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. 25
896. A printer controller according to claim 877, for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, 30 the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. 35
897. A printer controller according to claim 877, for outputting to a printhead module: dot data to be printed with at least two different inks; and SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1403 control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 5 898. A printer controller according to claim 877, for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
899. A printer controller according to claim 877, for supplying print data to at least one printhead module 10 capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; 15 wherein the printer controller is selectively configurable to supply dot data for the first and second modes.
900. A printer controller according to claim 877, for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 20
901. A printer controller according to claim 877, for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a). a fire signal is provided to nozzles at a first and nth position in each set of nozzles; 25 (b). a fire signal is provided to the next inward pair of nozzles in each set; (c). in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. 30
902. A printer controller according to claim 877, for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle 35 position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1404
903. A printer controller according to claim 877, for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second 5 pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing.
904. A printer controller according to claim 877, for receiving first data and manipulating the first data to 10 produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead.
905. A printer controller according to claim 877, for supplying data to a printhead module including: at least one row of print nozzles; 15 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
906. A printer controller according to claim 877, for supplying data to a printhead capable of printing a 20 maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data. for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. 25 907. A printer controller according to claim 877, for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan.
908. A printer controller according to claim 877, for supplying data to a printhead module including at least 30 one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 35 909. A printer controller according to claim 877, for supplying data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1405 expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire 5 the central nozzle.
910. A printer controller according to claim 877, for supplying data to a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the 10 control data.
911. A printer controller according to claim 877, for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 15
912. A printer controller according to claim 877, for supplying data to a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is 20 fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row.
913. A printer controller according to claim 877, for supplying data to a printhead module comprising at least 25 first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. 30
914. A printer controller according to claim 877, for providing data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at 35 least one of the other groups of the nozzles. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1406
915. A printer controller according to claim 877, for supplying data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first 5 threshold.
916. A printer controller according to claim 877, for supplying data to a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being 10 configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it
917. A printer controller for receiving first data and manipulating the first data to produce dot data to be 15 printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead, wherein each of the serial outputs is configured to supply dot data for at least two channels of the at least one printhead.
918. A printer controller according to claim 917, wherein the at least two channels include at least two color 20 channels.
919. A printer controller according to claim 917, wherein the at least two channels include at least one fixative channel. 25 920. A printer controller according to claim 917, wherein the at least two channels include at least one infrared ink channel.
921. A printer controller according to claim 917, wherein the first data includes one or more instructions associated with production of the dot data from the first data, the print controller including processing means for 30 producing the dot data from the first data on the basis of the one or more instructions.
922. A printer controller according to claim 917, wherein the printhead is a pagewidth printhead.
923. A printer controller according to claim 917, for implementing a method of at least partially compensating 35 for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1407 determining the rotational displacement; determining at least one correction factor that at least partially compensates for the ink dot displacement; and using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. 5
924. A printer controller according to claim 917 for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, 10 nozzle position (n-1), ... , nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
925. A printer controller according to claim 917, for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles 15 being configured to expel ink in response to a fire signal, the method comprising the steps of: (a). providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b). providing a fire signal to the next inward pair of nozzles in each set; (c). in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and 20(d). in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle.
926. A printer controller according to claim 917, manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic 25 pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed.
927. A printer controller according to claim 917, for supplying data to a printhead module including: at least one row of print nozzles; 30 at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers.
928. A printer controller according to claim 917, installed in a printer comprising: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at 35 least one row of print nozzles for expelling ink, and SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1408 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. 5 929. A printer controller according to claim 917, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the 10 second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them.
930. A printer controller according to claim 917, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each 15 .other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead 20 module.
931. A printer controller according to claim 917, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer 25 than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data 30 received from the first printer controller.
932. A printer controller according to claim 917, for supplying dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer 35 being configured to: access a correction factor associated with the at least one printhead module; SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1409 determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. 5
933. A printer controller according to claim 917, for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature 10 rising above a first threshold.
934. 'A printer controller according to claim 917, for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped 15 into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the 20 nozzles.
935. A printer controller according to claim 917, for outputting to a printhead module: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; 25 the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks.
936. A printer controller according to claim 917, for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of 30 the row portion including a component in a direction normal to that of a pagewidth to be printed.
937. A printer controller according to claim 917, for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: 35 a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1410 wherein the printer controller is selectively configurable to supply dot data for the first and second modes.
938. A printer controller according to claim 917, for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead 5 comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan.
939. A printer controller according to claim 917, for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: 10 (a). a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b). a fire signal is provided to the next inward pair of nozzles in each set; (c). in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each 15 set have been fired, and then the central nozzle is fired.
940. A printer controller according to claim 917, for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising 20 providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
941. A printer controller according to claim 917, for supplying dot data to a printhead module comprising at 25 least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the 30 printer controller being configurable to supply dot data to the printhead module for printing.
942. A printer controller according to claim 917, for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a 35 similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1411 an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
943. A printer controller according to claim 917, for supplying data to a printhead module including: 5 at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 10 944. A printer controller according to claim 917, for supplying data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. 15
945. A printer controller according to claim 917, for supplying data to a printhead comprising a plurality of printhead modules,.the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 20 946. A printer controller according to claim 917, for supplying data to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 25
947. A printer controller according to claim 917, for supplying data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: 30 in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle.
948. A printer controller according to claim 917, for supplying data to a printhead module for receiving dot 35 data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1412
949. A printer controller according to claim 917, for supplying data to a printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 5
950. A printer controller according to claim 917, for supplying data to a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is 10 fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row.
951. A printer controller according to claim 917, for supplying data to a printhead module comprising at least 15 first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. 20
952. A printer controller according to claim 917, for providing data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at 25 least one of the other groups of the nozzles.
953. A printer controller according to claim 917, for supplying data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead 30 module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold.
954. A printer controller according to claim 917, for supplying data to a printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead 35 module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1413 prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
955. A printhead module including: 5 at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 10 956. A printhead module according to claim 955, wherein there is a one to one correspondence between the nozzles and respective elements of the first and second shift registers.
957. A printhead module according to claim 956, wherein each of the shift registers supplies dot data to about half of the nozzles in a row. 15
958. A printhead module according to claim 955, including at least one pair of rows of the nozzles, the rows in each pair being offset in a direction parallel to the rows by half the intra-row nozzle spacing.
959. A printhead module according to claim 959, wherein each of the at least two shift registers supplies dot 20 data to at least some of the nozzles in at least the pair of rows.
960. A printhead module according claim 955, including a plurality of the rows configured to print using at least two ink channels, the nozzles for each of the ink channels being fed the dot data from at least one pair of first and second registers. 25
961. A printhead module according to claim 955, configured to receive dot data to which a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier has been applied, the nozzles being disposed on the printhead module, the method comprising the steps of: 30 determining the rotational displacement; determining at least one correction factor that at least partially compensates for the ink dot displacement; and using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. 35 962. A printhead module according to claim 955, configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1414 response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 5 963. A printhead module according to claim 955, configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: (a). providing a fire signal to nozzles at a first and nth position in each set of nozzles; 10 (b). providing a fire signal to the next inward pair of nozzles in each set; (c). in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 15 964. A printhead module according to claim 955, having been manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. 20
965. A printhead module according to claim 955, including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 25
966. A printhead module according to claim 955, installed in a printer comprising: a printhead comprising at least the first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data arid process the print data to output dot 30 data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead.
967. A printhead module according to claim 955, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each 35 other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1415 second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them.
968. A printhead module according to claim 955, installed in a printer comprising: 5 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and 10 the second printhead module; and the second printer controller outputs dot data only to the second printhead module.
969. A printhead module according to claim 955, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each 15 other and being disposed end to end on either side of ajoin region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein- the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein 20 the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller.
970. A printhead module according to claim 955, in communication with a printer controller for supplying dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least 25 one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least 30 partially compensate for the rotational displacement; and supply the dot data to the printhead module.
971. A printhead module according to claim 955, in communication with a printer controller for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a 35 plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1416
972. A printhead module according to claim 955, in communication with a printer controller for controlling a head comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the 5 nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control 10 signals that control the order of firing of the nozzles.
973. A printhead module according to claim 955, in communication with a printer controller for outputting to a printhead module: dot data to be printed with at least two different inks; and 15 control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks.
974. A printhead module according to claim 955, including at least one row of printhead nozzles, at least one 20 row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
975. A printhead module according to claim 955, in communication with a printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at 25 least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. 30
976. A printhead module according to claim 955, in communication with a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 35
977. A printhead module according to claim 955, used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1417 a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a). a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b). a fire signal is provided to the next inward pair of nozzles in each set; 5 (c). in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. 10 978. A printhead module according to claim 955, used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], 15 wherein nozzle position x is at or adjacent the centre of the set of nozzles.
979. A printhead module according to claim 955, in communication with a printer controller for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row 20 in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. 25
980. A printhead module according to claim 955, in communication with a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the 30 dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
981. A printhead module according to claim 955, in communication with a printer controller for receiving first 35 data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1418
982. A printhead module according to claim 955, including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at 5 least one of the other groups of the nozzles.
983. A printhead module according to claim 955 being capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and 10 a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number.
984. A printhead comprising a plurality of printhead modules according to claim 955, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, 15 wherein each type is determined by its geometric shape in plan.
985. A printhead module according to claim 955, including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position 20 n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
986. A printhead module according to claim 955, including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire 25 signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. 30
987. A printhead module according to claim 955, for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. 35 988. A printhead module according to claim 955, including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1419
989. A printhead module according to claim 955, having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each 5 fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row.
990. A printhead module according to claim 955, comprising at least first and second rows configured to print 10 ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. 15
991. A printhead module according to claim 955, in communication with a printer controller for providing data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift 20 register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
992. A printhead module according to claim 955, having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a 25 temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold.
993. A printhead module according to claim 955, comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows 30 configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
994. A printhead module capable of printing a maximum of n of channels of print data, the printhead module 35 being configurable into: a first mode, in which the printhead module is configured to receive print data for a first number of the channels; and SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1420 a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number.
995. A printhead module according to claim 994, wherein the first number is n. 5
996. A printhead module according to claim 994, wherein the first number is less than n.
997. A printhead module according to claim 994, configurable into at least one other mode, in which the printhead is configured to receive print data for a number of print channels other than the first and second 10 numbers.
998. A printhead module according to claim 994, wherein n is 4 and the second number is less than 4.
999. A printhead module according to claim 994, wherein n is 5 and the second number is less than 5. 15
1000. A printhead module according to claim 994, wherein n is 6 and the second number is less than 6.
1001. A printhead module according to claim 1000, wherein the second number is 3, 4 or 5. 20 1002. A printhead module according to claim 994, wherein the selected mode is selected based on the contents of a memory associated with the printhead. .
1003. A printhead module according to claim 1002, wherein the memory is a register. 25 1004. A printhead module according to claim 1002, wherein the register is on an integrated circuit, and wherein the integrated circuit and the printhead are mounted to a print engine.
1005. A printhead according to claim 994, comprising a plurality of printhead modules. 30 1006. A printhead according to claim 1005, wherein the printhead is a pagewidth printhead.
1007. A printhead module according to claim 994, configured to receive dot data to which a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier has been applied, the nozzles being disposed on 35 the printhead module, the method comprising the steps of: determining the rotational displacement; determining at least one correction factor that at least partially compensates for the ink dot displacement; and SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1421 using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement.
1008. A printhead module according to claim 994, configured to receive dot data to which a method of 5 expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 10
1009. A printhead module according to claim 994, configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: 15 (a). providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b). providing a fire signal to the next inward pair of nozzles in each set; (c). in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 20
1010. A printhead module according to claim 994, having been manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is 25 left-handed.
1011. A printhead module according to claim 994, including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, 30 wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers.
1012. A printhead module according to claim 994, installed in a printer comprising: a printhead comprising at least the first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and 35 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1422
1013. A printhead module according to claim 994, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; 5 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 10 1014. A printhead module according to claim 994, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot 15 data to the printhead, wherein: the first.printer controller outputs dot data to both the first printhead module and. the second printhead module; and the second printer controller outputs dot data only to the second printhead module.
1015. A printhead module according to claim 994, installed in a printer comprising: 20 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and 25 the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller.
1016. A printhead module according to claim 994, in communication with a printer controller for supplying dot 30 data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead 35 modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1423
1017. A printhead module according to claim 994, in communication with a printer controller for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or 5 adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold.
1018. A printhead module according to claim 994, in communication with a printer controller for controlling a head comprising at least one monolithic printhead module, the at least one printhead module having a plurality of 10 rows of nozzles configured to extend, in use, across at least part of a printable.pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the 15 nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles.
1019. A printhead module according to claim 994, in communication with a printer controller for outputting to a printhead module: 20 dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 25 1020. A printhead module according to claim 994, including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
1021. A printhead module according to claim 994, in communication with a printer controller for supplying 30 print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; 35 wherein the printer controller is selectively configurable to supply dot data for the first and second modes. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1424
1022. A printhead module according to claim 994, in communication with a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 5
1023. A printhead module according to claim 994, used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: 10 (a). a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b). a fire signal is provided to the next inward pair of nozzles in each set; (c). in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each 15 set have been fired, and then the central nozzle is fired.
1024. A printhead module according to claim 994, used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a 20 fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
1025. A printhead module according to claim 994, in communication with a printer controller for supplying dot 25 data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles 30 from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing.
1026. A printhead module according to claim 994, in communication with a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the 35 rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1425 corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
1027. A printhead module according to claim 994, in communication with a printer controller for receiving first 5 data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead.
1028. A printhead module according to claim 994, including: at least one row of print nozzles; 10 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
1029. A printhead comprising a plurality of printhead modules according to claim 994, the printhead being 15 wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan.
1030. A printhead module according to claim 994, including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for 20 each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), ... , nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
1031. A printhead module according to claim 994, including at least one row that comprises a plurality of 25 adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired, and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire 30 the central nozzle.
1032. A printhead module according to claim 994, for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. 35 SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1426
1033. A printhead module according to claim 994, including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 5 1034. A printhead module according to claim 994, having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that 10 the nozzles of each row are all fired before the nozzles of each subsequent row.
1035. A printhead module according to claim 994, comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module 15 being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows.
1036. A printhead module according to claim 994, in communication with a printer controller for providing 20 data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 25
1037. A printhead module according to claim 994, having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. 30
1038. A printhead module according to claim 994, comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent 35 a position where the faulty nozzle would otherwise have printed it. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1427
1039. A printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 5 1040. A printhead according to claim 1039, comprising a plurality of at least one of the types of module.
1041. A printhead according to claim 1040, comprising a plurality of each of at least two of the types of module. 10 1042. A printhead according to claim 1039, comprising two types of the module.
1043. A printhead according to claim 1042, wherein the two types of module alternate across a print width of the printhead. 15 1044. A printhead according to claim 1039, each of the modules including at least one row of print nozzles, wherein each of the at least one row of print nozzles includes at least a portion that extends at an acute angle to an intended relative direction of movement between the printhead and print media.
1045. A printhead according to claim 1044, wherein the different types of modules are configured, and 20 arranged relative to each other, such that there is substantially no growth in offset of each of the at least one row of print nozzles in a direction across an intended print width of the printhead.
1046. A printhead according to claim 1039, wherein each of the printhead modules is a monolithic integrated circuit. 25
1047. A printhead according to claim 1039, each of the modules including at least one row of print nozzles, wherein each of the at least one rows includes at least two sub-rows, each of the sub-rows being parallel to each other and displaced relative to each other in a direction of intended movement of print media relative to the printhead. 30
1048. A printhead according to claim 1039, the printhead being a pagewidth printhead.
1049. A printhead according to claim 1045, the printhead being a pagewidth printhead. 35 1050. A printhead according to claim 1049, the printhead being a pagewidth printhead. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1428
1051. A printhead according to claim 1039, configured to receive dot data to which a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier has been applied, the nozzles being disposed on the printhead module, the method comprising the steps of: 5 determining the rotational displacement; determining at least one correction factor that at least partially compensates for the ink dot displacement; and using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement 10 1052. A printhead according to claim 1039, configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], 15 wherein nozzle position x is at or adjacent the centre of the set of nozzles.
1053. A printhead according to claim 1039, configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire 20 signal, the method comprising the steps of: (a). providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b). providing a fire signal to the next inward pair of nozzles in each set; (c). in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set 25 have been fired, and then firing the central nozzle.
1054. A printhead according to claim 1039, having been manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead 30 modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed.
1055. A printhead according to claim 1039, including: at least one row of print nozzles; 35 at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. SUBSTITUTE SHEET (RULE 26) ROIAU WO 2005/120835 PCT/AU2004/000706 1429
1056. A printhead according to claim 1039, installed in a printer comprising: a printhead comprising at least the first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot 5 data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead.
1057. A printhead according to claim 1039, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each 10 other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 15
1058. A printhead according to claim 1039, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; 20 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. 25 1059. A printhead according to claim 1039, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot 30 data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. 35 1060. A printhead according to claim 1039, in communication with a printer controller for supplying dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1430 a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead 5 modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module.
1061. A printhead according to claim 1039, in communication with a printer controller for supplying dot data to 10 a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. 15 1062. A printhead according to claim 1039, in communication with a printer controller for controlling a head comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire 20 group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. 25 1063. A printhead according to claim 1039, in communication with a printer controller for outputting to a printhead module: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being 30 configured to output at least some of the control data and at least some of the dot data for the at least two inks.
1064. A printhead according to claim 1039, including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 35 SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1431
1065. A printhead according to claim 1039, in communication with a printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and 5 a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes.
1066. A printhead according to claim 1039, in communication with a printer controller for supplying data to a 10 printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan.
1067. A printhead according to claim 1039, used in conjunction with a printer controller for supplying one or 15 more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a). a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b). a fire signal is provided to the next inward pair of nozzles in each set; 20 (c). in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. 25 1068. A printhead according to claim 1039, used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], 30 wherein nozzle position x is at or adjacent the centre of the set of nozzles.
1069. A printhead according to claim 1039, in communication with a printer controller for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a 35 direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1432 the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing.
1070. A printhead according to claim 1039, in communication with a printer controller for supplying dot data to 5 at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty 10 nozzle would otherwise have printed it.
1071. A printhead according to claim 1039, in communication with a printer controller for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. 15
1072. A printhead according to claim 1039, including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at 20 least one of the other groups of the nozzles.
1073. A printhead according to claim 1039 being capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and 25 a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number.
1074. A printhead according to claim 1039, including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each 30 set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
1075. A printhead according to claim 1039, including at least one row that comprises a plurality of adjacent 35 sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1433 in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. 5 1076. A printhead according to claim 1039, for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data.
1077. A printhead according to claim 1039, including at least one row of printhead nozzles, at least one row 10 including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
1078. A printhead according to claim 1039, having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second 15 fire groups, the printhead being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. 20 1079. A printhead according to claim 1039, comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are 25 printed to by nozzles from the second pair of rows:
1080. A printhead according to claim 1039, in communication with a printer controller for providing data to a printhead module that includes: at least one row of print nozzles; 30 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
1081. A printhead according to claim 1039, having a plurality of nozzles for expelling ink, the printhead 35 module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1434
1082. A printhead according to claim 1039, comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first 5 row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
1083. A printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a 10 fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), ... , nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
1084. A printhead module according to claim 1083, wherein the nozzle at each given position within the set is 15 fired simultaneously with the nozzles in the other sets at respective corresponding positions.
1085. A printhead module according to claim 1083, wherein the printhead module includes a plurality of the rows of nozzles, the printhead module being configured to fire all the nozzles on each row prior to firing any nozzles from a subsequent row. 20
1086. A printhead module according to claim 1084, wherein the rows are disposed in pairs.
1087. A printhead module according to claim 1085, wherein the rows in each pair of rows are offset relative to each other. 25
1088. A printhead module according to claim 1086, wherein each pair of rows is configured to print the same color ink.
1089. A printhead module according to claim 1087, wherein each pair of rows is connected to a common ink 30 source.
1090. A printhead module according to claim 1083, wherein the sets of nozzles are adjacent each other.
1091. A printhead module according to claim 1083, wherein the sets of nozzles are separated by an 35 intermediate nozzle, the intermediate nozzle being fired either prior to the nozzle at position 1 in each set, or following the nozzle at position n. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1435
1092. A printhead comprising a plurality of printhead modules according to claim 1083.
1093. A printhead according to claim 1092, wherein the printhead is a pagewidth printhead. 5 1094. A printhead module according to claim 1083, configured to receive dot data to which a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier has been applied, the nozzles being disposed on the printhead module, the method comprising the steps of: determining the rotational displacement; 10 determining at least one correction factor that at least partially compensates for the ink dot displacement; and using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement.
1095. A printhead module according to claim 1083, configured to receive dot data to which a method of 15 expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), ... , nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 20
1096. A printhead module according to claim 1083, configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: 25 (a). providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b). providing a fire signal to the next inward pair of nozzles in each set; (c). in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 30
1097. A printhead module according to claim 1083, having been manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is 35 left-handed.
1098. A printhead module according to claim 1083, including: SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1436 at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 5 1099. A printhead module according to claim 1083, installed in a printer comprising: a printhead comprising at least the first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the 10 printhead.
1100. A printhead module according to claim 1083, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; 15 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 20 1101. A printhead module according to claim 1083, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot 25 data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module.
1102. A printhead module according to claim 1083, installed in a printer comprising: 30 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and 35 the second controller, and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1437
1103. A printhead module according to claim 1083, in communication with a printer controller for supplying dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the 5 printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and 10 supply the dot data to the printhead module.
1104. A printhead module according to claim 1083, in communication with a printer controller for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or 15 adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold.
1105. A printhead module according to claim 1083, in communication with a printer controller for controlling a head comprising at least one monolithic printhead module, the at least one printhead module having a plurality of 20 rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the 25 nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles.
1106. A printhead module according to claim 1083, in communication with a printer controller for outputting to a printhead module: 30 dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 35 1107. A printhead module according to claim 1083, including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the.displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1438
1108. A printhead module according to claim 1083, in communication with a printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: 5 a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. 10 1109. A printhead module according to claim 1083, in communication with a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 15 1110. A printhead module according to claim 1083, used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a). a fire signal is provided to nozzles at a first and nth position in each set of nozzles; 20 (b). a fire signal is provided to the next inward pair of nozzles in each set; (c). in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d), in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. 25
1111. A printhead module according to claim 1083, used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the 30 sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
1112. A printhead module according to claim 1083, in communication with a printer controller for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type 35 or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1439 to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. 5 1113. A printhead module according to claim 1083, in communication with a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a 10 corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
1114. A printhead module according to claim 1083, in communication with a printer controller for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least 15 two serial outputs for supplying the dot data to at least one printhead.
1115. A printhead module according to claim 1083, including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift 20 register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
1116. A printhead module according to claim 1083 being capable of printing a maximum of n of channels of print data, the printhead being configurable into: 25 a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number.
1117. A printhead comprising a plurality of printhead modules according to claim 1083, the printhead being 30 wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan.
1118. A printhead module according to claim 1083, including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire 35 signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1440 in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle.
1119. A printhead module according to claim 1083, for receiving dot data to be printed using at least two 5 .different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data.
1120. A printhead module according to claim 1083, including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a 10 direction normal to that of a pagewidth to be printed.
1121. A printhead module according to claim 1083, having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each 15 fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row.
1122. A printhead module according to claim 1083, comprising at least first and second rows configured to 20 print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. 25
1123. A printhead module according to claim 1083, in communication with a printer controller for providing data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift 30 register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
1124. A printhead module according to claim 1083, having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond 35 to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1441
1125. A printhead module according to claim 1083, comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or 5 adjacent a position where the faulty nozzle would otherwise have printed it.
1126. A printhead module according to claim 1083, comprising a plurality of the rows, the printhead module being configured to fire each nozzle in each row simultaneously with the nozzle or nozzles at the same position in the other rows. 10
1127. A printhead module according to claim 1083, including a plurality of pairs of the rows, each pair of rows including an odd row and an even row, the odd and even rows in each pair being offset from each other in both x and y directions relative to an intended direction of print media movement relative to the printhead, the printhead module being configured to cause firing of at least a plurality of the odd rows prior to firing any of the even rows, 15 or vice versa.
1128. A printhead module according to claim 1127, wherein all the odd rows are fired before any of the even rows are fired, or vice versa. 20 1129. A printhead module according to claim 1127, wherein all the odd rows, or the even rows, or both, are fired in a predetermined order.
1130. A printhead module according to claim 1129, configurable such that the predetermined order is selectable from a plurality of predetermined available orders. 25
1131. A printhead module according to claim 1127, wherein the predetermined order is sequential.
1132. A printhead module according to claim 1131, configurable such that the predetermined order can commence at any of a plurality of the rows. 30
1133. A printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: 35 in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1442
1134. A printhead module according to claim 1133, wherein the printhead module includes a plurality of the rows of nozzles, the printhead module being configured to fire all the nozzles on each row prior to firing any nozzles from a subsequent row. 5
1135. A printhead module according to claim 1134, wherein the rows are disposed in pairs.
1136. A printhead module according to claim 1135, wherein the rows in each pair of rows are offset relative to each other. 10
1137. A printhead module according to claim 1136, wherein each pair of rows is configured to print the same color ink.
1138. A printhead module according to claim 1137, wherein each pair of rows is connected to a common ink 15 source.
1139. A printhead module according to claim 1133, wherein the sets of nozzles are adjacent each other.
1140. A printhead module according to claim 1133, wherein the sets of nozzles are separated by an 20 intermediate nozzle, the intermediate nozzle being fired either prior to the nozzle at position 1 in each set, or following the nozzle at position n.
1141. A printhead module according to claim 1133, configured to receive dot data to which a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous 25 rotational displacement of a printhead module relative to a carrier has been applied, the nozzles being disposed on the printhead module, the method comprising the steps of: determining the rotational displacement; determining at least one correction factor that at least partially compensates for the ink dot displacement; and using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational 30 displacement.
1142. A printhead module according to claim 1133, configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in 35 response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle positionx is at or adjacent the centre of the set of nozzles. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1443
1143. A printhead module according to claim 1133, configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to 5 a fire signal, the method comprising the steps of: (a). providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b). providing a fire signal to the next inward pair of nozzles in each set; (c). in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set 10 have been fired, and then firing the central nozzle.
1144. A printhead module according to claim 1133, having been manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead 15 modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed.
1145. A printhead module according to claim 1133, including: at least one row of print nozzles; 20 at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers.
1146. A printhead module according to claim 1133, installed in a printer comprising: a printhead comprising at least the first elongate printhead module, the at least one printhead module including at 25 least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. 30 1147. A printhead module according to claim 1133, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the 35 second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1444
1148. A printhead module according to claim 1133, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; 5 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. 10 1149. A printhead module according to claim 1133, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot 15 data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. 20 1150. A printhead module according to claim 1133, in communication with a printer controller for supplying dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; 25 determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. 30 1151. A printhead module according to claim 1133, in communication with a printer controller for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. 35
1152. A printhead module according to claim 1133, in communication with a printer controller for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1445 plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in 5 the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles.
1153. A printhead module according to claim 1133, in communication with a printer controller for outputting to 10 a printhead module: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 15
1154. A printhead module according to claim 1133, including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 20 1155: A printhead module according to claim 1133, in communication with a printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the 25 channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes.
1156. A printhead module according to claim 1133, in communication with a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used 30 in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan.
1157. A printhead module according to claim 1133, used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises 35 a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a). a fire signal is provided to nozzles at a first and nth position in each set of nozzles; SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1446 (b). a fire signal is provided to the next inward pair of nozzles in each set; (c). in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each 5 set have been fired, and then the central nozzle is fired.
1158. A printhead module according to claim 1133, used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a 10 fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
1159. A printhead module according to claim 1133, in communication with a printer controller for supplying 15 dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by 20 nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing.
1160. A printhead module according to claim 1133, in communication with a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of 25 the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 30
1161. A printhead module according to claim 1133, in communication with a printer controller for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. 35 1162. A printhead module according to claim 1133, including: at least one row of print nozzles; SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1447 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 5 1163. A printhead module according to claim 1133 being capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. 10
1164. A printhead comprising a plurality of printhead modules according to claim 1133, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 15 1165. A printhead module according to claim 1133, including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), ... , nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 20
1166. A printhead module according to claim 1133, for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. 25 1167. A printhead module according to claim 1133, including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
1168. A printhead module according to claim 1133, having a plurality of rows of nozzles configured to extend, 30 in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. 35
1169. A printhead module according to claim 1133, comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 -1448 corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. 5
1170. A printhead module according to claim 1133, in communication with a printer controller for providing data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift 10 register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
1171. A printhead module according to claim 1133, having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond 15 to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold.
1172. A printhead module according to claim 1133, comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second 20 rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
1173. A printhead module according to claim 1133, comprising a plurality of the rows, the printhead module 25 being configured to fire each nozzle in each row simultaneously with the nozzle or nozzles at the same position in the other rows.
1174. A printhead module according to claim 1133, including a plurality of pairs of the rows, each pair of rows including an odd row and an even row, the odd and even rows in each pair being offset from each other in both x 30 and y directions relative to an intended direction of print media movement relative to the printhead, the printhead module being configured to cause firing of at least a plurality of the odd rows prior to firing any of the even rows, or vice versa.
1175. A printhead module according to claim 1174, wherein all the odd rows are fired before any of the even 35 rows are fired, or vice versa. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1449
1176. A printhead module according to claim 1174, wherein all the odd rows, or the even rows, or both, are fired in a predetermined order.
1177. A printhead module according to claim 1176, configurable such that the predetermined order is selectable 5 from a plurality of predetermined available orders.
1178. A printhead module according to claim 1174, wherein the predetermined order is sequential.
1179. A printhead module according to claim 1178, configurable such that the predetermined order can 10 commence at any of a plurality of the rows.
1180. A printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. 15
1181. A printhead module according to claim 1180, wherein the communication input is configured to receive the dot data and control data serially.
1182. A printhead module according to claim 1180, further including a plurality of the communication inputs. 20
1183. A printhead module according to claim 1181, further including a plurality of the communication inputs.
1184. A printhead comprising a plurality of printhead modules according to claim 1180, the printhead modules being disposed end to end for printing a width exceeding that of any of the individual printhead modules, the 25 communications input of each of the printhead modules being connected to a common dot data and control data bus.
1185. A printhead according to claim 1184, wherein each module is configured to respond to dot data and control data on the bus only when it is intended for that module. 30
1186. A printhead module according to claim 1180, configured to receive dot data to which a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier has been applied, the nozzles being disposed on the printhead module, the method comprising the steps of: 35 determining the rotational displacement; determining at least one correction factor that at least partially compensates for the ink dot displacement; and SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1450 using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement.
1187. A printhead module according to claim 1180, configured to receive dot data to which a method of 5 expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1),..., nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 10
1188. A printhead module according to claim 1180, configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: 15 (a). providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b). providing a fire signal to the next inward pair of nozzles in each set; (c). in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 20
1189. A printhead module according to claim 1180, having been manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is 25 left-handed.
1190. A printhead module according to claim 1180, including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, 30 wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers.
1191. A printhead module according to claim 1180, installed in a printer comprising: a printhead comprising at least the first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and 35 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1451
1192. A printhead module according to claim 1180, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; 5 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 10 1193. A printhead module according to claim 1180, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of ajoin region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot 15 data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module.
1194. A printhead module according to claim 1180, installed in a printer comprising: 20 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and 25 the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller.
1195. A printhead module according to claim 1180, in communication with a printer controller for supplying 30 dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead 35 modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement and supply the dot data to the printhead module. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1452
1196. A printhead module according to claim 1180, in communication with a printer controller for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or 5 adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold.
1197. A printhead module according to claim 1180, in communication with a printer controller for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a 10 plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired 15 before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles.
1198. A printhead module according to claim 1180, in communication with a printer controller for outputting to a printhead module: 20 dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 25 1199. A printhead module according to claim 1180, including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
1200. A printhead module according to claim 1180, in communication with a printer controller for supplying 30 print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; 35 wherein the printer controller is selectively configurable to supply dot data for the first and second modes. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1453
1201. A printhead module according to claim 1180, in communication with a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 5
1202. A printhead module according to claim 1180, used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: 10 (a). a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b). a fire signal is provided to the next inward pair of nozzles in each set; (c). in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each 15 set have been fired, and then the central nozzle is fired.
1203. A printhead module according to claim 1180, used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a 20 fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
1204. A printhead module according to claim 1180, in communication with a printer controller for supplying 25 dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by 30 nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing.
1205. .A printhead module according to claim 1180, in communication with a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of 35 the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1454 corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
1206. A printhead module according to claim 1180, in communication with a printer controller for receiving 5 first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead.
1207. A printhead module according to claim 1180, including: at least one row of print nozzles; 10 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
1208. A printhead module according to claim 1180 being capable of printing a maximum of n of channels of 15 print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. 20 1209. A printhead comprising a plurality of printhead modules according to claim 1180, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan.
1210. A printhead module according to claim 1180, including at least one row that comprises a plurality of sets 25 of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 30 1211. A printhead module according to claim 1180, including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next iAward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and 35 in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1455
1212. A printhead module according to claim 1180, including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 5 1213. A printhead module according to claim 1180, having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that 10 the nozzles of each row are all fired before the nozzles of each subsequent row.
1214. A printhead module according to claim 1180, comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the 15 printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows.
1215. A printhead module according to claim 1180, in communication with a printer controller for providing 20 data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 25
1216. A printhead module according to claim 1180, having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. 30
1217. A printhead module according to claim 1180, comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or 35 adjacent a position where the faulty nozzle would otherwise have printed it. SUBSTITUTE SHEET (RULE 26) ROIAU WO 2005/120835 PCT/AU2004/000706 1456
1218. A printhead module including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 5 1219. A printhead module according to claim 1218, wherein the displaced row portion is disposed adjacent one end of the monolithic printhead module.
1220. A printhead module according to claim 1218, including a plurality of the rows, wherein each of at least a plurality of the rows includes one of the displaced row portions. 10
1221. A printhead module according to claim 1220, wherein the displaced row portions of at least some of the rows are different in length than the displaced row portions of at least some of the other rows.
1222. A printhead module according to claim 1221, wherein each of the rows has a displaced row portion, and 15 the sizes of the respective displaced row portions increase from row to row in the direction normal to that of the pagewidth to be printed.
1223. A printhead module according to claim 1222, wherein the dropped rows together comprise a generally trapezoidal shape, in plan. 20
1224. A printhead module according to claim 1222, wherein the dropped rows together comprise a generally triangular shape, in plan.
1225. A printhead comprising a plurality of printhead modules, including at least one of the printhead modules 25 according to claim 1218.
1226. A printhead comprising a plurality of printhead modules, including at least one the printhead modules according to claim 2, wherein the displaced row portion of at least one of the printhead modules is disposed adjacent another of the printhead modules. 30
1227. A printhead according to claim 1226, wherein the printhead modules are the same shape and configuration as each other, and are arranged end to end across the intended print width.
1228. A printhead according to claim 1225, the printhead being a pagewidth printhead. 35
1229. A printhead according to claim 1227, the printhead being a pagewidth printhead. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1457
1230. A printhead module according to claim 1218, configured to receive dot data to which a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier has been applied, the nozzles being disposed on the printhead module, the method comprising the steps of: 5 determining the rotational displacement; determining at least one correction factor that at least partially compensates for the ink dot displacement; and using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. 10 1231. A printhead module according to claim 1218, configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], 15 wherein nozzle positionx is at or adjacent the centre of the set of nozzles.
1232. A printhead module according to claim 1218, configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to 20 a fire signal, the method comprising the steps of: (a). providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b). providing a fire signal to the next inward pair of nozzles in each set; (c). in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set 25 have been fired, and then firing the central nozzle.
1233. A printhead module according to claim 1218, having been manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead 30 modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed.
1234. A printhead module according to claim 1218, including: at least one row of print nozzles; 35 at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 .1458
1235. A printhead module according to claim 1218, installed in a printer comprising: a printhead comprising at least the first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot 5 data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead.
1236. A printhead module according to claim 1218, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each 10 other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 15
1237. A printhead module according to claim 1218, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; 20 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. 25 1238. A printhead module according to claim 1218, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to.receive print data and process the print data to output dot 30 data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. 35 1239. A printhead module according to claim 1218, in communication with a printer controller for supplying dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1459 least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead 5 modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module.
1240. A printhead module according to claim 1218, in communication with a printer controller for supplying 10 dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. 15 1241. A printhead module according to claim 1218, in communication with a printer controller for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the 20 sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. 25 1242. A printhead module according to claim 1218, in communication with a printer controller for outputting to a printhead module: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication outputjbeing 30 configured to output at least some of the control data and at least some of the dot data for the at least two inks.
1243. A printhead module according to claim 1218, including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 35 SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1460
1244. A printhead module according to claim 1218, in communication with a printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and 5 a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes.
1245. A printhead module according to claim 1218, in communication with a printer controller for supplying 10 data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan.
1246. A printhead module according to claim 1218, used in conjunction with a printer controller for supplying 15 one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a). a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b). a fire signal is provided to the next inward pair of nozzles in each set; 20 (c). in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. 25 1247. A printhead module according to claim 1218, used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], 30 wherein nozzle positionx is at or adjacent the centre of the set of nozzles.
1248. A printhead module according to claim 1218, in communication with a printer controller for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second 35 row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1461 nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing.
1249. A printhead module according to claim 1218, in communication with a printer controller for supplying 5 dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position 10 where the faulty nozzle would otherwise have printed it.
1250. A printhead module according to claim 1218, in communication with a printer controller for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. 15
1251. A printhead module according to claim 1218, including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at 20 least one of the other groups of the nozzles.
1252. A printhead module according to claim 1218 being capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and 25 a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number.
1253. A printhead comprising a plurality of printhead modules according to claim 1218, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, 30 wherein each type is determined by its geometric shape in plan.
1254. A printhead module according to claim 1218, including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position 35 n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1462
1255. A printhead module according to claim 1218, including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: 5 in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle.
1256. A printhead module according to claim 1218, for receiving dot data to be printed using at least two 10 different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data.
1257. A printhead module according to claim 1218, having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and 15 second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. 20 1258. A printhead module according to claim 1218, comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots 25 output to print media are printed to by nozzles from the second pair of rows.
1259. A printhead module according to claim 1218, in communication with a printer controller for providing data to a printhead module that includes: at least one row of print nozzles; 30 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
1260. A printhead module according to claim 1218, having a plurality of nozzles for expelling ink, the 35 printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1463
1261. A printhead module according to claim 1218, comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the 5 first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
1262. A printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the 10 printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. 15 1263. A printhead module according to claim 1262 wherein the rows are disposed in pairs extending generally transverse to a direction media is to be moved relative to the printhead.
1264. A printhead module according to claim 1263, wherein the rows in each pair of rows are configured to print the same color ink as each other. 20
1265. A printhead module according to claim 1264, wherein the rows in each pair of rows share an ink supply.
1266. A printhead module according to claim 1262, wherein the rows in each pair of rows are offset with respect to each other. 25
1267. A printhead module according to claim 1262 configured to fire the nozzles such that at least some ink dots from one row land on top of dots previously deposited by one or more of the other rows.
1268. A printhead module according to claim 1262 operable in at least two fire modes, wherein at least some of 30 the at least two fire modes define relatively different numbers of nozzles in each of the fire groups.
1269. A printhead module according to claim 1268, wherein at least some of the at least two fire groups define relatively different fire group sequences. 35 1270. A printhead comprising a plurality of printhead modules according to claim 1262.
1271. A printhead according to claim 1270, wherein the printhead is a pagewidth printhead. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1464
1272. A printhead module according to claim 1262 configured to receive dot data to which a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier has been applied, the nozzles being disposed on 5 the printhead module, the method comprising the steps of: determining the rotational displacement; determining at least one correction factor that at least partially compensates for the ink dot displacement; and using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement 10
1273. A printhead module according to claim 1262 configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with 15 the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1),..., nozzle position x], wherein nozzle positionx is at or adjacent the centre of the set of nozzles.
1274. A printhead module according to claim 1262 configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that 20 comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: (a). providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b). providing a fire signal to the next inward pair of nozzles in each set; (c). in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and 25 (d). in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle.
1275. A printhead module according to claim 1262 having been manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to 30 form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed.
1276. A printhead module according to claim 1262 including: 35 at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1465
1277. A printhead module according to claim 1262 installed in a printer comprising: a printhead comprising at least the first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and 5 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead.
1278. A printhead module according to claim 1262 installed in a printer comprising: 10 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are 15 configured such that no dot data passes between them.
1279. A printhead module according to claim 1262 installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer 20 than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. 25
1280. A printhead module according to claim 1262 installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; 30 at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller. 35
1281. A printhead module according to claim 1262 in communication with a printer controller for supplying dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1466 least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead 5 modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module.
1282. A printhead module according to claim 1262 in communication with a printer controller for supplying 10 dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold. 15 1283. A printhead module according to claim 1262 in communication with a printer controller for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the 20 sequence ftom each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. 25 1284. A printhead module according to claim 1262 in communication with a printer controller for outputting to a printhead module: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being 30 configured to output at least some of the control data and at least some of the dot data for the at least two inks.
1285. A printhead module according to claim 1262 including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 35 SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1467
1286. A printhead module according to claim 1262 in communication with a printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and 5 a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number, wherein the printer controller is selectively configurable to supply dot data for the first and second modes.
1287. A printhead module according to claim 1262 in communication with a printer controller for supplying 10 data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan.
1288. A printhead module according to claim 1262 used in conjunction with a printer controller for supplying 15 one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a). a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b). a fire signal is provided to the next inward pair of nozzles in each set; 20 (c). in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. 25 1289. A printhead module according to claim 1262 used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), ... , nozzle position x], 30 wherein nozzle positionx is at or adjacent the centre of the set of nozzles.
1290. A printhead module according to claim 1262 in communication with a printer controller for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second 35 row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1468 nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing.
1291. A printhead module according to claim 1262 in communication with a printer controller for supplying 5 dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position 10 where the faulty nozzle would otherwise have printed it
1292. A printhead module according to claim 1262 in communication with a printer controller for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. 15
1293. A printhead module according to claim 1262 including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at 20 least one of the other groups of the nozzles.
1294. A printhead module according to claim 1 being capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and 25 a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number.
1295. A printhead comprising a plurality of printhead modules according to claim 1262 the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of.the modules, 30 wherein each type is determined by its geometric shape in plan.
1296. A printhead module according to claim 1262 including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position 35 n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1469
1297. A printhead module according to claim 1262 including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: 5 in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle.
1298. A printhead module according to claim 1262 for receiving dot data to be printed using at least two 10 different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data.
1299. A printhead module according to claim 1262 including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a 15 direction normal to that of a pagewidth to be printed.
1300. A printhead module according to claim 1262 comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module 20 being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print' media are printed to by nozzles from the second pair of rows.
1301. A printhead module according to claim 1262 in communication with a printer controller for providing 25 data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 30
1302. A printhead module according to claim 1262 having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. 35
1303. A printhead module according to claim 1262 comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1470 configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 5 1304. A printhead module according to claim 1262 comprising a plurality of the rows, the printhead module being configured to fire each nozzle in each row simultaneously with the nozzle or nozzles at the same position in the other rows.
1305. A printhead module according to claim 1262 including a plurality of pairs of the rows, each pair of rows 10 including an odd row and an even row, the odd and even rows in each pair being offset from each other in both x and y directions relative to an intended direction of print media movement relative to the printhead, the printhead module being configured to cause firing of at least a plurality of the odd rows prior to firing any of the even rows, or vice versa. 15 1306. A printhead module according to claim 1305, wherein all the odd rows are fired before any of the even rows are fired, or vice versa.
1307. A printhead module according to claim 1305, wherein all the odd rows, or the even rows, or both, are fired in a predetermined order. 20
1308. A printhead module according to claim 1307, configurable such that the predetermined order is selectable from a plurality of predetermined available orders.
1309. A printhead module according to claim 1305, wherein the predetermined order is sequential. 25
1310. A printhead module according to claim 1309, configurable such that the predetermined order can commence at any of a plurality of the rows.
1311. A printhead module comprising at least first and second rows configured to print ink of a similar type or 30 color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second rows are fired such that some dots output to print media are printed to by nozzles from the first row and at least some other dots output to print media are printed to by nozzles from the second row. 35 SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1471
1312. A printhead module according to claim 1311, controllable such that either of the nozzles in each aligned pair of nozzles in the first and second rows can be selected to output ink for a selected dot to be printed on the print media. 5 1313. A printhead module according to claim 1312, wherein, in the event a nozzle in the first row is faulty, the corresponding nozzle in the second row is selected to output ink for a dot for which the faulty nozzle would otherwise have output ink.
1314. A printhead module according to claim 1312, including a plurality of sets of the first and second rows. 10
1315. A printhead module according to claim 1314, wherein each of the sets of the first and second rows is configured to print in a single color or ink type.
1316. A printhead module according to claim 1315, wherein the first and second rows in at least one of the sets 15 are separated by one or more rows from the other set or sets.
1317. A printhead module according to claim 1311, wherein each of the rows includes an odd sub-row and an even sub-row, the odd and even sub-rows being offset with respect to each other in a direction of intended print media travel relative to the printhead. 20
1318. A printhead module according to claim 1317, wherein the odd and even sub-rows are transversely offset relative to each other.
1319. A printhead module according to claim 1311, configured such that the first and second rows are fired 25 alternately.
1320. A printhead comprising a plurality of printhead modules according to claim 1311.
1321. A printhead according to claim 1320, the printhead being a pagewidth printhead. 30
1322. A printhead module according to claim 1311, configured to receive dot data to which a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier has been applied, the nozzles being disposed on the printhead module, the method comprising the steps of: 35 determining the rotational displacement; determining at least one correction factor that at least partially compensates for the ink dot displacement; and SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1472 using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement.
1323. A printhead module according to claim 1311, configured to receive dot data to which a method of 5 expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle positionx is at or adjacent the centre of the set of nozzles. 10
1324. A printhead module according to claim 1311, configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: 15 (a). providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b). providing a fire signal to the next inward pair of nozzles in each set; (c). in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 20
1325. A printhead module according to claim 1311, having been manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is 25 left-handed.
1326. A printhead module according to claim 1311, including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, 30 wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers.
1327. A printhead module according to claim 1311, installed in a printer comprising: a printhead comprising at least the first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and 35 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1473
1328. A printhead module according to claim 1311, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; 5 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 10 1329. A printhead module according to claim 1311, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot 15 data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module.
1330. A printhead module according to claim 1311, installed in a printer comprising: 20 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and 25 the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller.
1331. A printhead module according to claim 1311, in communication with a printer controller for supplying 30 dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead 35 modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement and supply the dot data to the printhead module. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1474
1332. A printhead module according to claim 1311, in communication with a printer controller for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or 5 adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold.
1333. A printhead module according to claim 1311, in communication with a printer controller for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a 10 plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired 15 before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles.
1334. A printhead module according to claim 1311, in communication with a printer controller for outputting to a printhead module: 20 dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 25 1335. A printhead module according to claim 1311, including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
1336. A printhead module according to claim 1311, in communication with a printer controller for supplying 30 print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; 35 wherein the printer controller is selectively configurable to supply dot data for the first and second modes. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1475
1337. A printhead module according to claim 1311, in communication with a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 5
1338. A printhead module according to claim 1311, used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: 10 (a). a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b). a fire signal is provided to the next inward pair of nozzles in each set; (c). in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each 15 set have been fired, and then the central nozzle is fired.
1339. A printhead module according to claim 1311, used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a 20 fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
1340. A printhead module according to claim 1311, in communication with a printer controller for supplying 25 dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by 30 nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing.
1341. A printhead module according to claim 1311, in communication with a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of 35 the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1476 corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
1342. A printhead module according to claim 1311, in communication with a printer controller for receiving 5 first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead.
1343. A printhead module according to claim 1311, including: at least one row of print nozzles; 10 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. -1344. A printhead module according to claim 1 being capable of printing a maximum of n of channels of print 15 data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. 20 1345. A printhead comprising a plurality of printhead modules according to claim 1311, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan.
1346. A printhead module according to claim 1311, including at least one row that comprises a plurality of sets 25 of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 30 1347. A printhead module according to claim 1311, including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and 35 in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1477
1348. A printhead module according to claim 1311, for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data. 5 1349. A printhead module according to claim 1311, including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
1350. A printhead module according to claim 1311, having a plurality of rows of nozzles configured to extend, 10 in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. 15
1351. A printhead module according to claim 1311, in communication with a printer controller for providing data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift 20 register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
1352. A printhead module according to claim 1311, having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond 25 to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold.
1353. A printhead module according to claim 1311, comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second 30 rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 35 SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1478
1354. A printer controller for providing data to a printhead module that includes: at least one row of print nozzles; 5 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
1355. A printer controller according to claim 1354, wherein there is a one to one correspondence between the 10 nozzles and respective elements of the first and second shift registers.
1356. A printer controller according to claim 1355, wherein each of the shift registers supplies dot data to about half of the nozzles in a row. 15 1357. A printer controller according to claim 1354, including at least one pair of rows of the nozzles, the rows in each pair being offset in a direction parallel to the rows by half the intra-row nozzle spacing.
1358. A printer controller according to claim 1357, wherein each of the at least two shift registers supplies dot data to at least some of the nozzles in at least the pair of rows. 20
1359. A printer controller according claim 1354, including a plurality of the rows configured to print using at least two ink channels, the nozzles for each of the ink channels being fed the dot data from at least one pair of first and second registers. 25 1360. A printer controller according to claim 1359, wherein the printhead module forms part of a printhead.
1361. A printer controller according to claim 1359, wherein the printhead includes a plurality of the printhead modules and the printer controller is configured to supply data to a plurality of the modules. 30 1362. A printer controller according to claim 1360, wherein the printhead is a pagewidth printhead comprising a plurality of the printhead modules.
1363. A printer controller according to claim 1354, for implementing a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational 35 displacement of a printhead module relative to a carrier, the nozzles being disposed on the printhead module, the method comprising the steps of: determining the rotational displacement; SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1479 determining at least one correction factor that at least partially compensates for the ink dot displacement; and using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement. 5 1364. A printer controller according to claim 1354 for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of 10 the set of nozzles.
1365. A printer controller according to claim 1354, for implementing a method of expelling ink from a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: 15 (a). providing a fire signal to nozzles at a first and nth position in each set of nozzles; (b). providing a fire signal to the next inward pair of nozzles in each set; (c). in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 20
1366. A printer controller according to claim 1354, manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to fonn bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is 25 left-handed.
1367. A printer controller according to claim 1354, for supplying data to a printhead module including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, 30 wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers.
1368. A printer controller according to claim 1354, installed in a printer comprising: a printhead comprising at least a first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and 35 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the printhead. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1480
1369. A printer controller according to claim 1354, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; 5 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 10 1370. A printer controller according to claim 1354, installed in a printer comprising; a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot 15 data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module.
1371. A printer controller according to claim 1354, installed in a printer comprising: 20 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and 25 the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller.
1372. A printer controller according to claim 1354, for supplying dot data to at least one printhead module and 30 at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead 35 modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and supply the dot data to the printhead module. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 .1481
1373. A printer controller according to claim 1354, for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printer 5 controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold.
1374. A printer controller according to claim 1354, for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a plurality of rows of nozzles configured to 10 extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row, wherein the 15 printer controller is configured to provide one or more control signals that control the order of firing of the nozzles.
1375. A printer controller according to claim 1354, for outputting to a printhead module: dot data to be printed with at least two different inks; and 20 control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks.
1376. A printer controller according to claim 1354, for supplying data to a printhead module including at least 25 one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
1377. A printer controller according to claim 1354, for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable 30 into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. 35 SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1482
1378. A printer controller according to claim 1354, for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 5 1379. A printer controller according to claim 1354, for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a). a fire signal is provided to nozzles at a first and nth position in each set of nozzles; (b). a fire signal is provided to the next inward pair of nozzles in each set; 10 (c). in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. 15 1380. A printer controller according to claim 1354, for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or 20 adjacent the centre of the set of nozzles.
1381. A printer controller according to claim 1354, for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel 25 relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. 30 1382. A printer controller according to claim 1354, for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints 35 an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1483
1383. A printer controller according to claim 1354, for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead. 5 1384. A printer controller according to claim 1354, for supplying data to a printhead module including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 10
1385. A printer controller according to claim 1354, for supplying data to a printhead capable of printing a maximum of n of channels of print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, 15 wherein the first number is greater than the second number.
1386. A printer controller according to claim 1354, for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 20
1387. A printer controller according to claim 1354, for supplying data to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], 25 wherein nozzle positionx is at or adjacent the centre of the set of nozzles.
1388. A printer controller according to claim 1354, for supplying data to a printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and 30 nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. 35 1389. A printer controller according to claim 1354, for supplying data to a printhead module for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1484 printhead module including a communication input for receiving the dot data for the at least two colors and the control data.
1390. A printer controller according to claim 1354, for supplying data to a printhead module including at least 5 one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
1391. A printer controller according to claim 1354, for supplying data to a printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each 10 row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. 15
1392. A printer controller according to claim 1354, for supplying data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows 20 are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows.
1393. A printer controller according to claim 1354, for supplying data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal 25 sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold.
1394. A printer controller according to claim 1354, for supplying data to a printhead module comprising a 30 plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 35 SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1485
1395. A printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify operation of the nozzles in response to the temperature rising above a first threshold. 5
1396. A printhead module according to claim 1395, configured to modify the operation of the nozzles at or adjacent the at least one thermal sensor, such that operation of nozzles not at or adjacent the at least one thermal sensor is not modified. 10 1397. A printhead module according to claim 1396, wherein each thermal sensor is associated with a predetermined group of the nozzles, the nozzles in the predetermined group being those for which the operation is modified.
1398. A printhead module according to claim 1397, wherein each thermal sensor is associated with a single 15 nozzle.
1399. A printhead module according to claim 1398, wherein the modification includes preventing operation of the nozzle. 20 1400. A printhead module according to claim 1399, wherein the modification includes preventing operation of the nozzle for a predetermined period.
1401. A printhead module according to claim 1399, wherein the modification includes preventing operation of the nozzle until the temperature drops below a second threshold. 25
1402. A printhead module according to claim 1401, wherein the second threshold is lower than the first threshold.
1403. A printhead module according to claim 1402, wherein the second threshold is the same as the first 30 threshold.
1404. A printhead module according to claim 1395, wherein the temperature is not determined explicitly by the at least one thermal sensor or the module. 35 1405. A printhead module according to claim 1395, wherein the printhead module is a thermal inkjet printhead module and each of the nozzles includes a thermal ink ejection mechanism. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1486
1406. A printhead module according to claim 1405, wherein the thermal sensor comprises at least part of one of the thermal inkjet mechanisms.
1407. A printhead module according to claim 1406, wherein the thermal sensor comprises a heating element. 5
1408. A printhead module according to claim 1407, wherein the thermal sensor determines the temperature by determining a resistance of the heating element.
1409. A printhead module according to claim 1395, configured to: 10 output thermal information from the at least one thermal sensor to a controller; and receive control information back from the controller, the control information being indicative of the modification to make to the operation of the one or more nozzles.
1410. A printhead module according to claim 1395, further including a plurality of data latches, the data latches 15 being configured to provide dot data to respective ones of the nozzles, at least some of the data latches being configured to receive thermal signals from respective ones of the thermal sensors during an acquisition period.
1411. A printhead module according to claim 1406, wherein the data latches are configured to form a shift register, the shift register being configured to: 20 shift the print data in during a print load phase; sample the signals from the thermal sensors during a temperature load phase; and shift the thermal signals out during an output phase.
1412. A printhead module according to claim 1411, wherein the output phase coincides with a subsequent print 25 load phase.
1413. A printhead module according to claim 1408, further including logic circuitry configured to perform a bitwise operation on: each thermal signal as it is clocked out of the shift register; and each piece of dot data to be clocked into the shift register, such that when a thermal signal is indicative of a thermal problem with a nozzle, the 30 logic circuitry prevents loading of data that would cause firing of that nozzle.
1414. A printhead module according to claim 1413, wherein the logic circuitry includes an AND circuit that receives as inputs the dot data and the thermal signal corresponding to the nozzle for which the dot data is intended, an output of the AND circuit being in communication with an input of the shift register. 35
1415. A printhead module according to claim 1395, configured to receive dot data to which a method of at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1487 rotational displacement of a printhead module relative to a carrier has been applied, the nozzles being disposed on the printhead module, the method comprising the steps of: determining the rotational displacement; determining at least one correction factor that at least partially compensates for the ink dot displacement; and 5 using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement.
1416. A printhead module according to claim 1395, configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that 10 comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle positionx is at or adjacent the centre of the set of nozzles. 15 1417. A printhead module according to claim 1395, configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: (a). providing a fire signal to nozzles at a first and nth position in each set of nozzles; 20 (b). providing a fire signal to the next inward pair of nozzles in each set; (c). in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired, and (d). in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle. 25 1418. A printhead module according to claim 1395, having been manufactured in accordance with a method of manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. 30
1419. A printhead module according to claim 1395, including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 35
1420. A printhead module according to claim 1395, installed in a printer comprising: SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1488 a printhead comprising at least the first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the 5 printhead.
1421. A printhead module according to claim 1395, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; 10 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 15 1422. A printhead module according to claim 1395, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other' and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot 20 data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module.
1423. A printhead module according to claim 1395, installed in a printer comprising: 25 a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and 30 the second controller; and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data received from the first printer controller.
1424. A printhead module according to claim 1395, in communication with a printer controller for supplying 35 dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the printhead module relative to a carrier, the printer being configured to: SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1489 access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and 5 supply the dot data to the printhead module.
1425. A printhead module according to claim 1395, in communication with a printer controller for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or 10 adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold.
1426. A printhead module according to claim 1395, in communication with a printer controller for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a 15 plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired 20 before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles.
1427. A printhead module according to claim 1395, in communication with a printer controller for outputting to a printhead module: 25 dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks. 30 1428. A printhead module according to claim 1395, including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
1429. A printhead module according to claim 1395, in communication with a printer controller for supplying 35 print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: a first mode, in which the printhead module is configured to receive data for a first number of the channels; and SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1490 a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number, wherein the printer controller is selectively configurable to supply dot data for the first and second modes. 5 1430. A printhead module according to claim 1395, in communication with a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 10 1431. A printhead module according to claim 1395, used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a). a fire signal is provided to nozzles at a first and nth position in each set of nozzles; 15 (b). a fire signal is provided to the next inward pair of nozzles in each set; (c). in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. 20
1432. A printhead module according to claim 1395, used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the 25 sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles.
1433. A printhead module according to claim 1395, in communication with a printer controller for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type 30 or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead 35 module for printing. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1491
1434. A printhead module according to claim 1395, in communication with a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the 5 dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
1435. A printhead module according to claim 1395, in communication with a printer controller for receiving 10 first data and manipulating the first data to produce dot data to be printed, the print controller including at least two serial outputs for supplying the dot data to at least one printhead.
1436. A printhead module according to claim 1395, including: at least one row of print nozzles; 15 at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
1437. A printhead module according to claim 1395 being capable of printing a maximum of n of channels of 20 print data, the printhead being configurable into: a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. 25 1438. A printhead comprising a plurality of printhead modules according to claim 1395, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan.
1439. A printhead module according to claim 1395, including at least one row that comprises a plurality of sets 30 of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), . nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 35 1440. A printhead module according to claim 1395, including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1492 signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire 5 the central nozzle.
1441. A printhead module according to claim 1395, for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data, 10
1442. A printhead module according to claim 1395, including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed. 15 1443. A printhead module according to claim 1395, having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that 20 the nozzles of each row are all fired before the nozzles of each subsequent row.
1444. A printhead module according to claim 1395, comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the 25 printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows.
1445. A printhead module according to claim 1395, in communication with a printer controller for providing 30 data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles. 35
1446. A printhead module according to claim 1395, comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1493 rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it. 5 1447. A printhead module according to claim 1414, further including a logic circuit accepting as inputs a masking signal and the thermal signal corresponding to the nozzle for which the dot data is intended, the logic circuit outputting the thermal signal to the input of the AND circuit in reliance on a value of the masking signal.
1448. A printhead module according to claim 1447, wherein the value of the masking signal enables masking 10 of the thermal signal for at least one nozzle position, including the nozzle for which the current dot data is intended.
1449. A printhead module according to claim 1447, wherein the value of the masking signal enables masking of the thermal signal for a plurality of nozzle positions corresponding to a region of the printhead associated the 15 nozzle for which the current dot data is intended.
1450. A printhead module according to claim 1447, wherein the value of the masking signal enables masking of the thermal signal for all of the nozzle positions of the printhead. 20
1451. A printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, and being configured such that, in the event a nozzle in the first row is faulty, a corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position 25 where the faulty nozzle would otherwise have printed it.
1452. A printhead module according to claim 1451, wherein each nozzle in the first row is paired with a nozzle in the second row, such that each pair of nozzles is aligned in an intended direction of print media travel relative to the printhead module. 30
1453. A printhead module according to claim 1452, including a plurality of sets of the first and second rows.
1454. A printhead module according to claim 1453, wherein each of the sets of the first and second rows is configured to print in a single color or ink type. 35 SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1494
1455. A printhead module according to claim 1451, wherein each of the rows includes an odd and an even sub row, the odd and even sub-rows being offset with respect to each other in a direction of print media travel relative to the printhead in use. 5 1456. A printhead module according to claim 1455, wherein the odd and even sub-rows are transversely offset with respect to each other.
1457. A printhead comprising a plurality of printhead modules according to claim 1452. 10 1458. A printhead comprising a plurality of printhead modules according to claim 1454.
1459. A printhead according to claim 1457, the printhead being a pagewidth printhead.
1460. A printhead module according to claim 1451, configured to receive dot data to which a method of at least 15 partially compensating for errors in ink dot placement by at least one of a plurality of nozzles due to erroneous rotational displacement of a printhead module relative to a carrier has been applied, the nozzles being disposed on the printhead module, the method comprising the steps of: determining the rotational displacement; determining at least one correction factor that at least partially compensates for the ink dot displacement; and 20 using the correction factor to alter the output of the ink dots to at least partially compensate for the rotational displacement.
1461. A printhead module according to claim 1451, configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that 25 comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 30 1462. A printhead module according to claim 1451, configured to receive dot data to which a method of expelling ink has been applied, the method being applied to a printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising the steps of: (a). providing a fire signal to nozzles at a first and nth position in each set of nozzles; 35 (b). providing a fire signal to the next inward pair of nozzles in each set; (c). in the event n is an even number, repeating step (b) until all of the nozzles in each set has been fired; and SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1495 (d). in the event n is an odd number, repeating step (b) until all of the nozzles but a central nozzle in each set have been fired, and then firing the central nozzle.
1463. A printhead module according to claim 1451, having been manufactured in accordance with a method of 5 manufacturing a plurality of printhead modules, at least some of which are capable of being combined in pairs to form bilithic pagewidth printheads, the method comprising the step of laying out each of the plurality of printhead modules on a wafer substrate, wherein at least one of the printhead modules is right-handed and at least another is left-handed. 10 1464. A printhead module according to claim 1451, including: at least one row of print nozzles; at least two shift registers for shifting in dot data supplied from a data source to each of the at least one rows, wherein each print nozzle obtains dot data to be fired from an element of one of the shift registers. 15 1465. A printhead module according to claim 1451, installed in a printer comprising: a printhead comprising at least the first elongate printhead module, the at least one printhead module including at least one row of print nozzles for expelling ink; and at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first and second printer controllers are connected to a common input of the 20 printhead.
1466. A printhead module according to claim 1451, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region; 25 at least first and second printer controllers configured to receive print data and process the print data to output dot data to the printhead, wherein the first printer controller outputs dot data only to the first printhead module and the second printer controller outputs dot data only to the second printhead module, wherein the printhead modules are configured such that no dot data passes between them. 30 1467. A printhead module according to claim 1451, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot 35 data to the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second printhead module; and the second printer controller outputs dot data only to the second printhead module. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1496
1468. A printhead module according to claim 1451, installed in a printer comprising: a printhead comprising first and second elongate printhead modules, the printhead modules being parallel to each other and being disposed end to end on either side of a join region, wherein the first printhead module is longer 5 than the second printhead module; at least first and second printer controllers configured to receive print data and process the print data to output dot data for the printhead, wherein: the first printer controller outputs dot data to both the first printhead module and the second controller, and the second printer controller outputs dot data to the second printhead module, wherein the dot data output by the second printer controller includes dot data it generates and at least some of the dot data 10 received from the first printer controller.
1469. A printhead module according to claim 1451, in communication with a printer controller for supplying dot data to at least one printhead module and at least partially compensating for errors in ink dot placement by at least one of a plurality of nozzles on the printhead module due to erroneous rotational displacement of the 15 printhead module relative to a carrier, the printer being configured to: access a correction factor associated with the at least one printhead module; determine an order in which at least some of the dot data is supplied to at least one of the at least one printhead modules, the order being determined at least partly on the basis of the correction factor, thereby to at least partially compensate for the rotational displacement; and 20 supply the dot data to the printhead module.
1470. A printhead module according to claim 1451, in communication with a printer controller for supplying dot data to a printhead module having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or 25 adjacent at least one of the nozzles, the printer controller being configured to modify operation of at least some of the nozzles in response to the temperature rising above a first threshold.
1471. A printhead module according to claim 1451, in communication with a printer controller for controlling a printhead comprising at least one monolithic printhead module, the at least one printhead module having a 30 plurality of rows of nozzles configured to extend, in use, across at feast part of a printable pagewidth of the printhead, the nozzles in each row being grouped into at least first and second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired 35 before the nozzles of each subsequent row, wherein the printer controller is configured to provide one or more control signals that control the order of firing of the nozzles. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1497
1472. A printhead module according to claim 1451, in communication with a printer controller for outputting to a printhead module: dot data to be printed with at least two different inks; and control data for controlling printing of the dot data; 5 the printer controller including at least one communication output, each or the communication output being configured to output at least some of the control data and at least some of the dot data for the at least two inks.
1473. A printhead module according to claim 1451, including at least one row of printhead nozzles, at least one row including at least one displaced row portion, the displacement of the row portion including a component in a 10 direction normal to that of a pagewidth to be printed.
1474. A printhead module according to claim 1451, in communication with a printer controller for supplying print data to at least one printhead module capable of printing a maximum of n of channels of print data, the at least one printhead module being configurable into: 15 a first mode, in which the printhead module is configured to receive data for a first number of the channels; and a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number; wherein the printer controller is selectively configurable to supply dot data for the first and second modes. 20 1475. A printhead module according to claim 1451, in communication with a printer controller for supplying data to a printhead comprising a plurality of printhead modules, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 25 1476. A printhead module according to claim 1451, used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that: (a). a fire signal is provided to nozzles at a first and nth position in each set of nozzles; 30 (b). a fire signal is provided to the next inward pair of nozzles in each set; (c). in the event n is an even number, step (b) is repeated until all of the nozzles in each set has been fired; and (d). in the event n is an odd number, step (b) is repeated until all of the nozzles but a central nozzle in each set have been fired, and then the central nozzle is fired. 35
1477. A printhead module according to claim 1451, used in conjunction with a printer controller for supplying one or more control signals to a printhead module, the printhead module including at least one row that comprises SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1498 a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, the method comprising providing, for each set of nozzles, a fire signal in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), ... , nozzle position x], wherein nozzle position x is at or adjacent the centre of the set of nozzles. 5
1478. A printhead module according to claim 1451, in communication with a printer controller for supplying dot data to a printhead module comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the printhead module being configurable such 10 that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows, the printer controller being configurable to supply dot data to the printhead module for printing. 15 1479. A printhead module according to claim 1451, in communication with a printer controller for supplying dot data to at least one printhead module, the at least one printhead module comprising a plurality of rows, each of the rows comprising a plurality of nozzles for ejecting ink, wherein the printhead module includes at least first and second rows configured to print ink of a similar type or color, the printer controller being configured to supply the dot data to the at least one printhead module such that, in the event a nozzle in the first row is faulty, a 20 corresponding nozzle in the second row prints an ink dot at a position on print media at or adjacent a position where the faulty nozzle would otherwise have printed it.
1480. A printhead module according to claim 1451, in communication with a printer controller for receiving first data and manipulating the first data to produce dot data to be printed, the print controller including at least 25 two serial outputs for supplying the dot data to at least one printhead.
1481. A printhead module according to claim 1451, including: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift 30 register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at least one of the other groups of the nozzles.
1482. A printhead module according to claim 1451 being capable of printing a maximum of n of channels of print data, the printhead being configurable into: 35 a first mode, in which the printhead is configured to receive print data for a first number of the channels; and a second mode, in which the printhead is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1499
1483. A printhead comprising a plurality of printhead modules according to claim 1451, the printhead being wider than a reticle step used in forming the modules, the printhead comprising at least two types of the modules, wherein each type is determined by its geometric shape in plan. 5
1484. A printhead module according to claim 1451, including at least one row that comprises a plurality of sets of n adjacent nozzles, each of the nozzles being configured to expel ink in response to a fire signal, such that, for each set of nozzles, a fire signal is provided in accordance with the sequence: [nozzle position 1, nozzle position n, nozzle position 2, nozzle position (n-1), ... , nozzle position x], wherein nozzle positionx is at or adjacent the 10 centre of the set of nozzles.
1485. A printhead module according to claim 1451, including at least one row that comprises a plurality of adjacent sets of n adjacent nozzles, each of the nozzles being configured to expel the ink in response to a fire signal, the printhead being configured to output ink from nozzles at a first and nth position in each set of nozzles, 15 and then each next inward pair of nozzles in each set, until: in the event n is an even number, all of the nozzles in each set has been fired; and in the event n is an odd number, all of the nozzles but a central nozzle in each set have been fired, and then to fire the central nozzle. 20 1486. A printhead module according to claim 1451, for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data.
1487. A printhead module according to claim 1451, including at least one row of printhead nozzles, at least one 25 row including at least one displaced row portion, the displacement of the row portion including a component in a direction normal to that of a pagewidth to be printed.
1488. A printhead module according to claim 1451, having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, the nozzles in each row being grouped into at least first and 30 second fire groups, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein the nozzles are fired row by row such that the nozzles of each row are all fired before the nozzles of each subsequent row. 35 1489. A printhead module according to claim 1451, comprising at least first and second rows configured to print ink of a similar type or color, at least some nozzles in the first row being aligned with respective corresponding nozzles in the second row in a direction of intended media travel relative to the printhead, the SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1500 printhead module being configurable such that the nozzles in the first and second pairs of rows are fired such that some dots output to print media are printed to by nozzles from the first pair of rows and at least some other dots output to print media are printed to by nozzles from the second pair of rows. 5 1490. A printhead module according to claim 1451, in communication with a printer controller for providing data to a printhead module that includes: at least one row of print nozzles; at least first and second shift registers for shifting in dot data supplied from a data source, wherein each shift register feeds dot data to a group of nozzles, and wherein each of the groups of the nozzles is interleaved with at 10 least one of the other groups of the nozzles.
1491. A printhead module according to claim 1451, having a plurality of nozzles for expelling ink, the printhead module including a plurality of thermal sensors, each of the thermal sensors being configured to respond to a temperature at or adjacent at least one of the nozzles, the printhead module being configured to modify 15 operation of the nozzles in response to the temperature rising above a first threshold.
1492. A first entity configured to authenticate a digital signature supplied by a second entity, wherein one of the entities includes a base key and the other of the entities includes a variant key and a bit-pattern, the variant key being based on the result of applying a one way function to the base key and the bit-pattern, the digital signature 20 having been generated by the second entity using its key to digitally signing at least part of data to be authenticated, the first entity being configured to: (a). receive the digital signature from the second entity; (b). receive the data; and (c). authenticate the digital signature based on the received data and the first entity's key. 25
1493. A first entity according to claim 1492,including the base key, the first entity being configured to receive, from the second entity, the bit-pattern, wherein (c) includes: generating the variant key from the bit-pattern and the base key; and authenticating the digital signature using the generated variant key. 30
1494. A first entity according to claim 1493,the first entity storing information, wherein the data is indicative of a request to be performed on the information.
1495. A first entity according to claim 1494,wherein the information is a value. 35
1496. A first entity according to claim 1493,wherein the data is indicative of a read instruction. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1501
1497. A first entity according to claim 1493,wherein the data is indicate of a write instruction, the data being indicative of new information to be written.
1498. A first entity according to claim 1493,wherein the data is indicative of a function to be applied to the 5 information.
1499. A first entity according to claim 1498,wherein the function is a decrement or increment function.
1500. A first entity according to claim 1493,wherein the data is indicative of a value stored in the second entity. 10
1501. A first entity according to claim 1493,the first entity being configured to send a request to the second entity, the data being returned in response to the request.
1502. A first entity according to claim 1501,wherein the data is indicative of a value stored in the second entity. 15
1503. A first entity according to claim 1501,the first entity being configured to digitally sign at least some of the request with the base key.
1504. A first entity according to claim 1492,wherein the first entity has the base key. 20
1505. A first entity according to claim 1503,the first entity storing information, wherein the data is indicative of a request to be performed on the information.
1506. A first entity according to claim 1504,wherein the information is a value. 25
1507. A first entity according to claim 1503,wherein the data is indicative of a read instruction.
1508. A first entity according to claim 1503,wherein the data is indicate of a write instruction, the data being indicative of new information to be written. 30
1509. A first entity according to claim 1503,wherein the data is indicative of a function to be applied to the information.
1510. A first entity according to claim 1508,wherein the function is a decrement or increment function. 35
1511. A first entity according to claim 1503,wherein the data is indicative of a value stored in the second entity. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1502
1512. A first entity according to claim 1510,the first entity being configured to send a read request to the second entity, the data being returned in response to the request.
1513. A first entity according to claim 151 1,wherein the data is indicative of a value stored in the second entity. 5
1514. A first entity according to claim 1511 ,the first entity being configured-to digitally sign at least some of the request with the base key.
1515. A first entity according to claim 1492,including: 10 a first bit-pattern a non-volatile memory storing resource data, a first base key for use with at least a first variant key; a second variant key for use with a second base key, the second variant key being the result of a one way function applied to: the second base key; and the first bit-pattern or a modified bit-pattern based on the first bit-pattern. 15
1516. A first entity according to claim 1492,configured for use in a method of enabling or disabling a verification process of a first entity in response to a predetermined event, the first entity having at least one associated bit-pattern and at least one variant key, each of the variant keys having been generated by applying a one way function to: a base key; and one or more of the at least one bit-patterns, respectively; or one or more 20 alternative bit patterns, each of the alternative bit-pattems being based on one or the at least one bit-patterns, the method including the method including: (a). determining that the predetermined event has happened; and (b). enabling or disabling at least one of the first variant keys in response the predetermined event. 25
1517. A first entity according to claim 1492,for use in a system for enabling authenticated communication between a first entity and at least one other entity, the system including a second entity, wherein: the first entity and the second entity share transport keys; and 30 the second entity includes at least one authentication key configured to be transported from the second entity to the first entity using the transport keys, the authentication key being usable to enable the authenticated communication by the first entity. 35 1518. A first entity according to claim 1492,configured for use in a method of storing a first bit-pattern in non volatile memory of a device, the method comprising: SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1503 (a). applying a one way function to a second bit-pattern associated with the device, thereby to generate a first result; (b). applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and 5 (c). storing the second result in the memory, thereby indirectly storing the first bit-pattern.
1519. A first entity according to claim 1492,configured for use in a method of storing a bit-pattern in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: 10 (a). determining a first memory location; and (b). storing the bit-pattern at the first memory location; wherein the first memory locations are different in at least a plurality of the respective devices.
1520. A first entity according to claim 1492,configured for use in a method of storing at least one functionally 15 identical code segment in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: (a). determining a first memory location; and (b). storing a first of the at least one code segments in the memory at the first memory location; wherein the first memory location is different in at least a plurality of the respective devices. 20
1521. A first entity according to claim 1492,configured for implementing a method for providing a sequence of nonces (RO, R1, R2, ... ) commencing with a current seed of a sequence of seeds (xl, x2, x3,...), the method comprising: (a). applying a one-way function to the current seed, thereby to generate a current nonce; (b) outputting the 25 current nonce; (b). using the current seed to generate a next seed in a sequence of seeds, the seed so generated becoming the current seed; and (c). repeating steps (a) to (c) as required to generate further nonces in the sequence of nonces. 30 1522. A first entity according to claim 1492,configured for implementing a method of storing multiple first bit patterns in non-volatile memory of a device, the method comprising, for each of the first bit-patterns to be stored: (a). applying a one way function to a third bit-pattern based on a second bit-pattern associated with the device, thereby to generate a first result; (b). applying a second function to the first result and the first bit-pattern, thereby to generate a second result; 35 and (c). storing the second result in the memory, thereby indirectly storing the first bit-pattern;wherein the third bit-patterns used for the respective first bit-patterns are relatively unique compared to each other. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1504
1523. A first entity including: a first bit-pattern a non-volatile memory storing resource data, a first base key for use with at least a first variant key; 5 a second variant key for use with a second base key, the second variant key being the result of a one way function applied to: the second base key; and the first bit-pattern or a modified bit-pattern based on the first bit-pattern.
1524. A first entity according to claim 1523,wherein the first variant key is stored in a second entity. 10 1525. A first entity according to claim 1523,wherein the second base key is stored in a third entity.
1526. A first entity according to claim 1523,configured to receive a request from any of a plurality of second entities, the request being indicative of at least one operation to be performed on the resource data, each of the second entities having an associated bit-pattern and one of the first variant keys, the first variant key in each of 15 second entities being based on the result of applying a one way function to the first base key and the associated bit-pattern of that second entity, the first entity being configured to: (a). receive the request from one of the second entities; (b). perform the at least one operation in the request, thereby to generate a response; (c). use the first base key to digitally sign at least part of the response, thereby to generate a digital signature; 20 and (d). send the response and the'digital signature to the second entity from which the request was received, such that the second entity can verify the at least part of the response using its variant key.
1527. A first entity according to claim 1526,configured to, prior to (b), receive the associated bit-pattern from 25 the second entity that makes the request in (a), wherein (c) includes: (i) using the first base key and the associated bit-pattern received from the second entity to generate the first variant key of the second entity making the request in (a); and (ii) using the first variant key generated in (i) to perform the signing of at least part of the response the response. 30
1528. A first entity according to claim 1523,configured to receive a request from any of one or more third entities, the request being indicative of at least one operation to be performed on the resource data, each of the one or more third entities having the second base key, the first entity being configured to: (a). receive the request from the one of the third entities; 35 (b). perform the at least one operation in the request, thereby to generate a response; (c). use the second variant key to digitally sign at least part of the response, thereby to generate a digital signature; and SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1505 (d). send the response and the digital signature to the third entity from which the request was received, such that the third entity can verify the at least part of the response using its base key.
1529. A first entity according to claim 1528,configured to send the first bit-pattern to the third entity that makes 5 the request in (e), such that the third entity can: (i) use the second base key and the bit-pattern received from the first entity to generate the second variant key; and (ii) use the second variant key generated in (i) to perform the verification. 10 1530. A first entity according to claim 1526,configured to receive a request from any of one or more third entities, the request being indicative of at least one operation to be performed on the resource data, each of the one or more third entities having the second base key, the first entity being configured to: (a). receive the request from the one of the third entities; (b). perform the at least one operation in the request, thereby to generate a response; 15 (c). use the first variant key to digitally sign at least part of at least the response, thereby to generate a digital signature; and (d). send the response and the digital signature to the third entity from which the request was received, such that the third entity can verify at least part of the response using its base key. 20 1531. A first entity according to claim 1530,configured to send the first bit-pattern the third entity that makes the request in (a), such that the third entity can: (i) use the second base key and the bit-pattem received from the first entity to generate the second variant key; and (ii) use the second variant key generated in (i) to perform the verification. 25
1532. A first entity according to claim 1530,wherein the second and third entities have different permissions in relation to the operations they can perform on the resource data, the permissions being defined based which of the first and second base key and variant key combinations is used for the verification. 30 1533. A first entity according to claim 1532,wherein the first base and variant key combination provides a higher permission to perform an operation on the resource data than the second base key and variant key combination.
1534. A first entity according to claim 153 1,wherein the second and third entities have different permissions in 35 relation to the operations they can perform on the resource data, the permissions being defined based which of the first and second base key and variant key combinations is used for the verification. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1506
1535. A first entity according to claim 1534, wherein the first base and variant key combination provides a higher permission to perform an operation on the resource data than the second base key and variant key combination. 5 1536. A first entity according to claim 1523, configured to receive a request from any of a plurality of second entities, the request being indicative of at least one operation to be performed on the resource data, each of the second entities having an associated bit-pattern and one of the first variant keys, the first variant key in each of second entities being based on the result of applying a one way function to the first base key and the associated bit-pattern of that second entity, the first entity being configured to: 10 (a). receive the request from one of the second entities; (b). receive the bit-pattern associated with the entity from which the request was received; (c). receive a digital signature from the entity from which the request was received, the digital signature having been generated by digitally signing at least part of the request using the variant key; (d). generate the variant key of the entity from which the request sent, by applying the one way function to 15 the first base key and the received bit pattern; and (e). verify the request by digitally signing at least part of the request using the variant key generated in (d) and comparing the produced signature against the signature received in (d).
1537. A first entity according to claim 1523,configured to receive a request from any of one or more third 20 entities, the request being indicative of at least one operation to be performed on the resource data, each of the one or more third entities having the second base key, the first entity being configured to: (a). receive the request from the one of the third entities; (b). receive a digital signature from the third entity from which the request was received, the digital signature having been generated by the third entity signing at least part of the request using the second variant key; 25 (c). verify the at least part of the request by digitally signing at least part of the request using the second variant key and comparing the produced signature against the signature received in (g).
1538. A first entity according to claim 1537, configured to send the first bit-pattern to the third entity that makes the request in (f), such that the third entity can: 30 (i) use the second base key and the bit-pattern received from the first entity to generate the second variant key; and (ii) use the second variant key generated in (i) to digitally sign at least part of the request; and (iii) send the request for receipt by the first entity in (a). 35 1539. A first entity according to claim 1536, configured to receive a request from any of one or more third entities, the request being indicative of at least one operation to be performed on the resource data, each of the one or more third entities having the second base key, the first entity being configured to: SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1507 (a). receive the request from the one of the third entities; (b). receive a digital signature from the third entity from which the request was received, the digital signature having been generated by the third entity signing at least part of the request using the second variant key; (c). verify the at least part of the request by digitally signing at least part of the request using the second 5 variant key and comparing the produced signature against the signature received in (g).
1540. A first entity according to claim.1539, wherein the second and third entities have different permissions in relation to the operations they can perform on the resource data, the permissions being defined based which of the first and second base key and variant key combinations is used for the verification. 10
1541. A first entity according to claim 1540, wherein the first base and variant key combination provides a higher permission to perform an operation on the resource data than the second base key and variant key combination. 15 1542. A first entity according to claim 1523,wherein the resource data represents a physical property.
1543. A first entity according to claim 1542, wherein the physical property is a remaining amount of a physical resource. 20 1544. A first entity according to claim 1543, wherein the resource is a consumable resource.
1545. A first entity according to claim 1544, wherein the resource entity is physically attached to a reservoir or magazine that holds the consumable resource. 25 1546. A first entity according to claim 1545, wherein the resource is a fluid.
1547. A first entity according to claim 1546, wherein the fluid is ink.
1548. A first entity according to claim 1530,wherein the operation includes a read, in which the resource data is 30 read by the entity making the request.
1549. A first entity according to claim 1523,wherein the operation includes write, in which the resource data is modified by the entity making the request. 35 1550. A first entity according to claim 1523,wherein the operation includes decrementing, in which the resource is decremented by the entity making the request. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1508
1551. A first entity according to claim 1523,wherein the one way function is a hash function.
1552. A first entity according to claim 1551, wherein the one way function is SHAL. 5 1553. A second entity configured for use with the first entity of claim 1523.
1554. A second entity configured for use with the first entity of claim 1526.
1555. A second entity configured for use with the first entity of claim 1536. 10
1556. A third entity configured for use with the first entity of claim 1528.
1557. A third entity configured for use with the first entity of claim 1530. 15 1558. A third entity configured for use with the first entity of claim 1537.
1559. A first entity according to claim 1523,configured to authenticate a digital signature supplied by a second entity, wherein one of the entities includes a base key and the other of the entities includes a variant key and a bit pattern, the variant key being based on the result of applying a one way function to the base key and the bit 20 pattern, the digital signature having been generated by the second entity using its key to digitally signing at least part of data to be authenticated, the first entity being configured to: (a). receive the digital signature from the second entity; (b). receive the data; and (c). authenticate the digital signature based on the received data and the first entity's key. 25
1560. A first entity according to claim 1523,configured to implement a method of enabling or disabling a verification process of a first entity in response to a predetermined event, the first entity having at least one associated bit-pattern and at least one variant key, each of the variant keys having been generated by applying a 30 one way function to: a base key; and one or more of the at least one bit-patterns, respectively; or one or more alternative bit patterns, each of the alternative bit-patterns being based on one or the at least one bit-patterns, the method including the method including: (a). determining that the predetermined event has happened; and 35 (b). enabling or disabling at least one of the first variant keys in response the predetermined event. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1509
1561. A first entity according to claim 1523,configured for usein a system for enabling authenticated communication between a first entity and at least one other entity, the system including a second entity, wherein: the first entity and the second entity share transport keys; and the second entity includes at least one authentication key configured to be transported from the second entity to 5 the first entity using the transport keys, the authentication key being usable to enable the authenticated communication by the first entity.
1562. A first entity according to claim 1523,configured to implement a method of storing a first bit-pattern in 10 non-volatile memory of a device, the method comprising: (a). applying a one way function to a second bit-pattern associated with the device, thereby to generate a first result; (b). applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and 15 (c). storing the second result in the memory, thereby indirectly storing the first bit-pattern.
1563. A first entity according to claim 1523,configured to implement a method of storing a bit-pattern in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: 20 (a). determining a first memory location; and (b). storing the bit-pattern at the first memory location; wherein the first memory locations are different in at least a plurality of the respective devices. 25 1564. A first entity according to claim 1523,configured to implement a method of storing at least one functionally identical code segment in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: (a). determining a first memory location; and (b). storing a first of the at least one code segments in the memory at the first memory location; wherein the 30 first memory location is different in at least a plurality of the respective devices.
1565. A first entity according to claim 1523,configured to implement a method for providing a sequence of nonces (RO, R1, R2, ... ) commencing with a current seed of a sequence of seeds (xl, x2, x3,...), the method 35 comprising: (a). applying a one-way function to the current seed, thereby to generate a current nonce; (b) outputting the current nonce; SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1510 (b). using the current seed to generate a next seed in a sequence of seeds, the seed so generated becoming the current seed; and (c). repeating steps (a) to (c) as required to generate further nonces in the sequence of nonces. 5
1566. A first entity according to claim 1523,configured to implement a method of storing multiple first bit patterns in non-volatile memory of a device, the method comprising, for each of the first bit-patterns to be stored: (a). applying a one way function to a third bit-pattern based on a second bit-pattern associated with the device, thereby to generate a first result; 10 (b). applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and (c). storing the second result in the memory, thereby indirectly storing the first bit-pattern; wherein the third bit-patterns used for the respective first bit-patterns are relatively unique compared to each other. 15 1567. A method of enabling or disabling a verification process of a first entity in response to a predetermined event, the first entity having at least one associated bit-pattern and at least one variant key, each of the variant keys having been generated by applying a one way function to: a base key; and one or more of the at least one bit patterns, respectively; or one or more alternative bit patterns, each of the alternative bit-patterns being based on one or the at least one bit-patterns, the method including 20 the method including: (a). determining that the predetermined event has happened; and (b). enabling or disabling at least one of the first variant keys in response the predetermined event.
1568. A method according to claim 1567, wherein step (a) includes disabling at least one of the variant keys,, 25 such that the disabled at least one variant key can no longer be used to digitally sign information in that entity.
1569. A method according to claim 1567, wherein step (a) includes disabling at least one of the variant keys, such that the disabled at least one variant key can no longer be used to verify information signed by one or more respective base keys related to the disabled at least one variant key in that entity. 30
1570. A method according to claim 1567, wherein the step of disabling the at least one variant key includes modifying a status of a flag associated with that at least one variant key.
1571. A method according to claim 1567, wherein the step of disabling the at least one variant key includes 35 deleting that at least one variant key. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1511
1572. A method according to claim 1567, wherein the step of disabling the at least one variant key includes modifying that at least one variant key
1573. A method according to claim 1567, wherein the event is a predetermined point in time being reached or 5 passed.
1574. A method according to claim 1567, wherein the first entity includes a plurality of the variant keys, the plurality of variant keys being based on the result of a one way function applied to: a respective one of a corresponding plurality of base keys; and one of the at least one bit-patterns or one of the at least one alternative 10 bit-patterns, the method including the steps of: determining that a predetermined event related to one of the variant keys has happened; and enabling or disabling at least one of the plurality of variant keys with which the predetermined event is associated.
1575. A method according to claim 1567, wherein the plurality of base keys has a corresponding sequence of 15 predetermined events associated with them, the method including the steps of: (a). determining that one of the predetermined event has happened; and (b). enabling or disabling the variant key in the sequence corresponding to predetermined event that is determined to have happened. 20 1576. A method according to claim 1575, wherein the variant keys are disabled in the order of the sequence of predetermined events.
1577. A method according to claim 1576, wherein the sequence of events is chronological. 25 1578. A method according to claim 1577, wherein each of the events includes a time being reached.
1579. A method according to claim 1578, wherein the step of determining that one of the events has happened includes receiving a time from a trusted source. 30 1580. A method according to claim 1579, wherein the time is a date.
1581. A method according to claim 1580, wherein the date is determined with a resolution of a month.
1582. A method according to claim 1568, wherein the predetermined event includes detection of compromise 35 of one or more of the keys, the method including disabling the one or more variant keys corresponding to the one or more keys that were compromised. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1512
1583. A method according to claim to claim 1568, wherein the predetermined event includes suspect compromise of one or more of the keys, the method including disabling the one or more variant keys corresponding to the one or more keys that were suspected of being compromised. 5 1584. A method of manufacturing second entities for use in the verification process with the first entity of claim 1567, each of the first entities including at least first and second variant key, the first variant key having been generated by applying a one way function to a first base key and a first bit-pattern, and the second variant key having been generated by applying a one way function to a second base key and a second bit-pattern, the method comprising the steps of: 10 manufacturing a plurality of second entities for use with the first entities, each of the second entities including at least the first base key; and upon the first variant key being disabled in response to one of the predetermined event, manufacturing a plurality of third entities for use with the first entities, each of the third entities including at least the second base key. 15 1585. A method according to claim 1567, wherein the first variant key is automatically disabled in response to a predetermined event.
1586. A method according to claim 1585, further including the step of causing the first variant key to be disabled. 20
1587. A method according to claim 1586, wherein the first variant key is disabled in response to a time being reached.
1588. A method according to claim 1582, wherein at least some of the first entities have one or more further 25 variant keys, each of the respective further variant keys having been generated by applying a one way function to respective further base keys and bit-patterns, each of the variant keys being enabled or disabled in response to respective predetermined events, the method comprising the step of manufacturing a sequence of sets of second entities, each set of the second entities being manufactured such that the variant key corresponding to its base key is enabled for the verification process during the life of that set. 30
1589. A method according to claim 1588, wherein the predetermined events are selected such that the variant keys corresponding with the base keys of more than one of the sets are enabled at once.
1590. A method according to claim 1567, using a first entity configured to authenticate a digital signature 35 supplied by a second entity, wherein one of the entities includes a base key and the other of the entities includes a variant key and a bit-pattern, the variant key being based on the result of applying a one way function to the base SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1513 key and the bit-pattern, the digital signature having been generated by the second entity using its key to digitally signing at least part of data to be authenticated, the first entity being configured to: (a). receive the digital signature from the second entity; (b). receive the data; and 5 (c). authenticate the digital signature based on the received data and the first entity's key.
1591. A method according to claim 1567, using a first entity including: a first bit-pattern 10 a non-volatile memory storing resource data, a first base key for use with at least a first variant key; a second variant key for use with a second base key, the second variant key being the result of a one way function applied to: the second base key; and the first bit-pattern or a modified bit-pattern based on the first bit-pattern. 15
1592. A method according to claim 1567, using a system for enabling authenticated communication between a first entity and at least one other entity, the system including a second entity, wherein: the first entity and the second entity share transport keys; and the second entity includes at least one authentication key configured to be transported from the second entity to 20 the first entity using the transport keys, the authentication key being usable to enable the authenticated communication by the first entity.
1593. A method according to claim 1567, including storing a first bit-pattern in non-volatile memory of a device, the method comprising: 25 (a). applying a one way function to a second bit-pattern associated with the device, thereby to generate a first result; (b). applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and (c). storing the second result in the memory, thereby indirectly storing the first bit-pattern. 30
1594. A method according to claim 1567, including storing a bit-pattern in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: (a). determining a first memory location; and 35 (b). storing the bit-pattern at the first memory location; wherein the first memory locations are different in at least a plurality of the respective devices. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1514
1595. A method according to claim 1567, including storing at least one functionally identical code segment in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: (a). determining a first memory location; and (b). storing a first of the at least one code segments in the memory at the first memory location; wherein the 5 first memory location is different in at least a plurality of the respective devices.
1596. A method according to claim 1567, including providing a sequence of nonces (RO, R1, R2,...) commencing with a current seed of a sequence of seeds (xl, x2, x3,...), the method comprising: (a). applying a one-way function to the current seed, thereby to generate a current nonce; (b) outputting the 10 current nonce; (b). using the current seed to generate a next seed in a sequence of seeds, the seed so generated becoming the current seed; and (c). repeating steps (a) to (c) as required to generate further nonces in the sequence of nonces. 15 1597. A method according to claim 1567, including storing multiple first bit-patterns in non-volatile memory of a device, the method comprising, for each of the first bit-patterns to be stored: (a). applying a one way function to a third bit-pattern based on a second bit-pattern associated with the device, thereby to generate a first result; (b). applying a second function to the first result and the first bit-pattern, thereby to generate a second result; 20 and (c). storing the second result in the memory, thereby indirectly storing the first bit-pattern; wherein the third bit-patterns used for the respective first bit-patterns are relatively unique compared to each other.
1598. A system for enabling authenticated communication between a first entity and at least one other entity, 25 the system including a second entity, wherein: the first entity and the second entity share transport keys; and the second entity includes at least one authentication key configured to be transported from the second entity to the first entity using the transport keys, the authentication key being usable to enable the authenticated communication by the first entity. 30
1599. A system according to claim 1598, wherein the transport keys include: a first transport key in the first entity; and a second transport key in the second entity. 35 1600. A system according to claim 1599, wherein the first and second transport keys are the same. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1515
1601. A system according to claim 1600, wherein the second transport key is a base key and the first transport key is a variant key, the variant key having been generated by applying a one way function to the base key and a first bit-pattern. 5 1602. A system according to claim 1601, wherein the first bit-pattern is stored in the first entity.
1603. A system according to claim 1600, wherein each of the first and second transport keys is a second bit pattern stored in the first and second entities during manufacture of the system or its components. 10 1604. A system according to claim 1603, wherein the second bit-pattern was determined randomly or pseudo randomly.
1605. A system according to claim 1604, wherein the second bit-pattern was generated using a stochastic -process or mechanism. 15
1606. A system according to claim 1598, wherein the authentication key enables authenticated communication between the first and second entities.
1607. A system according to claim 1606, wherein the authentication key provides the first entity with 20 permission to request performance of at least one operation on at least one value in the second entity.
1608. A system according to claim 1598, wherein the authentication key enables authenticated communication between the first entity and one or more entities other than the second entity. 25 1609. A system according to claim 1608, wherein the authentication key is a variant key.
1610. A system according to claim 1608, wherein the one or more entities include the base key corresponding to the authentication key. 30 1611. A plurality of systems, each being in accordance with claim 1609, wherein the variant key in each system is relatively unique compared to the variant keys in the other systems.
1612. A system according to claim 1598, wherein the authentication key is.a third bit-pattern that was determined randomly or pseudo-randomly. 35
1613. A system according to claim 1612, wherein the third bit-pattern was generated using a stochastic process or mechanism. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1516
1614. A system for enabling authenticated communication between a first entity and at least one other entity, the system including a second entity, wherein: the first entity and the second entity share additional transport keys; 5 the second entity and each of the at least one other entities share transport keys; and the second entity includes at least one authentication key configured to be transported from the second entity to the first entity using the first transport keys and to each of the at least one other entities using the respective additional shared transport keys, such that the authentication keys, once transported to the first and at least one other entities, enable verified communication therebetween. 10
1615. A system according to claim 1614, wherein each pair of transport keys is different from the other pairs of transport keys.
1616. A system according to claim 1614, wherein the authentication key is the first transport key. 15
1617. A system according to claim 1614, wherein the authentication key is the additional transport key for one of the at least one other entities.
1618. A system according to claim 1614, wherein the authentication key is not the same as any of the transport 20 keys.
1619. A system according to claim 1614, wherein the authentication key is a variant key, the variant key having been generated by applying a one way function to a base key and a first bit-pattern. 25 1620. A system according to claim 1619, wherein the first transport key is a bit-pattern stored in the first and second entities during manufacture of the system or its components.
1621. A system according to claim 1620, wherein the bit-pattern was determined randomly or pseudo randomly. 30
1622. A system according to claim 1621, wherein the bit-pattern was generated using a stochastic process or mechanism.
1623. A method of manufacturing a system having at least first and second entities, method comprising the 35 steps of: providing the first and second entities with transport keys; and providing the second entity with at least one authentication key; SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1517 the system being configured to enable transport of the at least one authentication key from the second entity to the first entity using the transport keys, the authentication key being usable to enable the authenticated communication by the first entity. 5 1624. A method according to claim 1623, wherein the transport keys include: a first transport key in the first entity; and a second transport key in the second entity.
1625. A method according to claim 1624, wherein the first and second transport keys are the same. 10
1626. A method according to claim 1625, wherein the second transport key is a base key and the first transport key is a variant key, the variant key having been generated by applying a one way function to the base key and a first bit-pattern. 15 1627. A method according to claim 1626, wherein the first bit-pattern is stored in the first entity.
1628. A method according to claim 1625, wherein each of the first and second transport keys is a second bit pattern stored in the first and second entities during manufacture of the system or its components. 20 1629. A method according to claim 1628, wherein the second bit-pattern was determined randomly or pseudo randomly.
1630. A method according to claim 1629, wherein the second bit-pattern was generated using a stochastic process or mechanism. 25
1631. A method according to claim 1623, wherein the authentication key enables authenticated communication between the first and second entities.
1632. A method according to claim 1623, wherein the authentication key enables authenticated communication 30 between the first entity and one or more entities other than the second entity.
1633. A method according to claim 1623, wherein the authentication key is a third bit-pattern that was determined randomly or pseudo-randomly. 35 1634. A method according to claim 1633, wherein the third bit-pattern was generated using a stochastic process or mechanism. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1518
1635. A method for enabling authenticated communication between a first entity and at least one other entity in a system including a second entity, wherein: the first entity and the second entity share first transport keys; the second entity and each of the at least one other entities share additional transport keys; and 5 the second entity includes at least one authentication key; the method including the steps of: transporting the authentication key from the second entity to the first entity using the first transport keys, and to each of the at least one other entities using the respective shared additional transport keys, such that the authentication keys, once transported to the first and at least one other entities, enable verified communication 10 therebetween.
1636. A method according to claim 1635, wherein each pair of transport keys is different from the other pairs of transport keys. 15 1637. A method according to claim 1635, wherein the authentication key is the first transport key.
1638. A method according to claim 1635, wherein the authentication key is one of the additional transport keys.
1639. A method according to claim 1635, wherein the authentication key is not the same as any of the transport 20 keys.
1640. A method according to claim 1635, wherein the authentication key is a variant key, the variant key having been generated by applying a one way function to a base key and a first bit-pattern. 25 1641. A method according to claim 1640, wherein the first transport key is a bit-pattern stored in the first and second entities during manufacture of the system or its components.
1642. A method according to claim 1641, wherein bit-pattern was determined randomly or pseudo-randomly. 30 1643. A method according to claim 1642, wherein the bit-pattern was generated using a stochastic process or mechanism.
1644. A system according to claim 1598, including a first entity configured to authenticate a digital signature supplied by a second entity, wherein one of the entities includes a base key and the other of the entities includes a 35 variant key and a bit-pattern, the variant key being based on the result of applying a one way function to the base key and the bit-pattern, the digital signature having been generated by the second entity using its key to digitally signing at least part of data to be authenticated, the first entity being configured to: SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1519 (a). receive the digital signature from the second entity; (b). receive the data; and (c). authenticate the digital signature based on the received data and the first entity's key. 5
1645. A system according to claim 1598, including a first entity including: a first bit-pattern a non-volatile memory storing resource data, a first base key for use with at least a first variant key; 10 a second variant key for use with a second base key, the second variant key being the result of a one way function applied to: the second base key; and the first bit-pattern or a modified bit-pattern based on the first bit-pattern.
1646. A system according to claim 1598, configured to implement a method of enabling or disabling a 15 verification process of a first entity in response to a predetermined event, the first entity having at least one associated bit-pattern and at least one variant key, each of the variant keys having been generated by applying a one way function to: a base key; and one or more of the at least one bit-patterns, respectively; or one or more alternative bit patterns, each of the alternative bit-patterns being based on one or the at least one bit-patterns, the method including 20 the method including: (a). determining that the predetermined event has happened; and (b). enabling or disabling at least one of the first variant keys in response the predetermined event.
1647. A system according to claim 1598, configured to implement a method of storing a first bit-pattern in non 25 volatile memory of a device, the method comprising: (a). applying a one way function to a second bit-pattern associated with the device, thereby to generate a first result; (b). applying a second function to the first result and the first bit-pattem, thereby to generate a second result; and 30 (c). storing the second result in the memory, thereby indirectly storing the first bit-pattern.
1648. A system according to claim 1598, configured to implement a method of storing a bit-pattern in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: (a). determining a first memory location; and 35 (b). storing the bit-pattern at the first memory location; wherein the first memory locations are different in at least a plurality of the respective devices. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1520
1649. A system according to claim 1598, configured to implement a method of storing at least one functionally identical code segment in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: (a). determining a first memory location; and 5 (b). storing a first of the at least one code segments in the memory at the first memory location;wherein the first memory location is different in at least a plurality of the respective devices.
1650. A system according to claim 1598, configured to implement a method of providing a sequence of nonces (RO, R1, R2, ... ) commencing with a current seed of a sequence of seeds (xl, x2, x3,...), the method comprising: 10 (a). applying a one-way function to the current seed, thereby to generate a current nonce; (b) outputting the current nonce; (b). using the current seed to generate a next seed in a sequence of seeds, the seed so generated becoming the current seed; and (c). repeating steps (a) to (c) as required to generate further nonces in the sequence of nonces. 15
1651. A system according to claim 1598, configured to implement a method of storing multiple first bit patterns in non-volatile memory of a device, the method comprising, for each of the first bit-patterns to be stored: (a). applying a one way function to a third bit-pattern based on a second bit-pattern associated with the device, thereby to generate a first result; 20 (b). applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and (d). storing the second result in the memory, thereby indirectly storing the first bit-pattern;wherein the third bit-patterns used for the respective first bit-patterns are relatively unique compared to each other. 25
1652. A method of storing a first bit-pattern in non-volatile memory of a device, the method comprising: (a). applying a one way function to a second bit-pattern associated with the device, thereby to generate a first result; (b). applying a second function to the first result and the first bit-pattern, thereby to generate a second result; 30 and (c). storing the second result in the memory, thereby indirectly storing the first bit-pattern.
1653. A method according to claim 1652, wherein the one way function is more cryptographically secure than the second function. 35
1654. A method according to claim 1653, wherein the second function is a logical function. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1521
1655. A method according to claim 1654, wherein the logical function is an XOR function.
1656. A method according to claim 1653, wherein the one way function is a hash function. 5 1657. A method according to claim 1653, wherein the one way function is SHAl.
1658. A method according to claim 1652, wherein the first bit-pattern is a key.
1659. A method according to claim 1652, further including the step of storing one or more code segments in the 10 memory, the code segments being configured to run on a processor of the device, thereby enabling the device to: apply the one way function to the second bit-pattern, thereby to generate the first result; apply a third function to the first result and the second result, thereby to generate the first bit-pattern;wherein the third function is the inverse of the second function. 15 1660. A method according to claim 1659, wherein the third function and the second function are the same.
1661. A method according to claim 1652, wherein the second bit-pattern was generated randomly or pseudo randomly. 20 1662. A method according to claim 1652, the method further including the step, performed prior to step (a), of determining the second bit-pattern.
1663. A method according to claim 1662, wherein determining the second bit-pattern includes generating the second bit-pattern randomly or pseudo-randomly. 25
1664. A method according to claim 1662, wherein determining the second bit-pattern includes generating the second bit-pattern based on a stochastic process or mechanism.
1665. A method according to claim 1662, wherein determining the second bit-pattern includes selecting the 30 second-bit pattern from an existing list or sequence of second bit-patterns.
1666. A method of storing a first bit-pattern in non-volatile memory of each of a plurality of devices, the method comprising, for each of the devices: (a). applying a one way function to a second bit-pattern associated with the device, thereby to generate a first 35 result; (b). applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1522 (c). storing the second result in the non-volatile memory, thereby indirectly storing the first bit pattern;wherein the second bit-patterns of the respective devices are relatively unique with respect to each other.
1667. A method according to claim 1666, wherein the one way function is more cryptographically secure than 5 the second function.
1668. A method according to claim 1667, wherein the second function is a logical function.
1669. A method according to claim 1668, wherein the logical function is an XOR function. 10
1670. A method according to claim 1667, wherein the one way function is a hash function.
1671. A method according to claim 1667, wherein the one way function is SHAL. 15 1672. A method according to claim 1666, wherein the first bit-pattern is a key.
1673. . A method according to claim 1666, wherein step (c) comprises, for each device: (a). determining a first memory location; and (b). storing the second result at the first memory location; wherein the first memory locations are different in 20 at least a plurality of the respective devices.
1674. A method according to claim 1673, wherein step (d) includes randomly selecting the first memory location. 25 1675. A method according to claim 1674, wherein step (a) includes selecting the first memory location based on a stochastic process or mechanism.
1676. A method according to claim 1673, wherein step (a) includes selecting the first memory location from an existing list or sequence of memory locations. 30
1677. A method according to claim 1666, further including the step of storing one or more code segments in the device, the code segments being configured to run on a processor of the device, thereby enabling the device to: apply the one way function to the second bit-pattern, thereby to generate the first result; and apply a third function to the first result and the second result, thereby to generate the first bit-pattern; wherein the 35 third function is the inverse of the second function.
1678. 27, A method according to claim 1677, wherein the third function and the second function are the same. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1523
1679. A method according to claim 1677, wherein the second bit-patterns have characteristics associated with random numbers. 5 1680. A method according to claim 1679, wherein the second bit-pattern was generated randomly or pseudo randomly.
1681. A method according to claim 1679, the method further including the step, performed prior to step (a), of determining the second bit-pattern. 10
1682. A method according to claim 1681, wherein determining the second bit-pattern includes generating the second bit-pattern randomly or pseudo-randomly.
1683. A method according to claim 1681, wherein determining the second bit-pattern includes generating the 15 second bit-pattern based on a stochastic process or mechanism.
1684. A device manufactured in accordance with the method of claim 1652.
1685. A device manufactured in accordance with the method of claim 1659. 20
1686. A device manufactured in accordance with the method of claim 1666.
1687. A device manufactured in accordance with the method of claim 1677. 25 1688. A device having an associated second bit-pattern, and non-volatile memory, the non-volatile memory indirectly storing a first bit-pattern in the form of a second result, the second result being generated by: (a). applying a one way function to the second bit-pattern, thereby to generate a first result; and (b). applying a second function to the first result and the first bit-pattern, thereby to generate the second result. 30
1689. A device according to claim 1688, further including a processor, the processor being configured to run one or more code segments that: apply the one way function to the second bit pattern, thereby to generate the first result; and apply a third function to the first result and the second result, the third function being the inverse of the second 35 function, thereby to generate the first bit-pattern.
1690. A device according to claim 1689, wherein the third function and the second function are the same. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1524
1691. A device according to claim 1689, wherein the one or more code segments, when run on the processor, use the first bit-pattern in a cryptographic process. 5 1692. A device according to claim 1691, wherein the cryptographic process is digital signing.
1693. A device according to claim 1688, wherein the one way function is more cryptographically secure than the second function. 10 1694. A device according to claim 1688, wherein the second function is a logical function.
1695. A device according to claim 1688, wherein the logical function is an XOR function.
1696. A device according to claim 1688, wherein the one way function is a hash function. 15
1697. A device according to claim 1688, wherein the one way function is SHAL.
1698. A device according to claim 1688, wherein the first bit-pattern is a key. 20 1699. A device according to claim 1688, wherein the second bit-pattern was generated randomly or pseudo randomly.
1700. A device according to claim 1699, wherein the second bit-pattern was generated using a stochastic process or mechanism. 25
1701. A method according to claim 1652, implemented in a first entity configured to authenticate a digital signature supplied by a second entity, wherein one of the entities includes a base key and the other of the entities includes a variant key and a bit-pattern, the variant key being based on the result of applying a one way function to the base key and the bit-pattern, the digital signature having been generated by the second entity using its key to 30 digitally signing at least part of data to be authenticated, the first entity being configured to: (a). receive the digital signature from the second entity; (b). receive the data; and (c). authenticate the digital signature based on the received data and the first entity's key. 35 1702. A method according to claim 1652, implemented in a first entity including: a first bit-pattern a non-volatile memory storing resource data, SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1525 a first base key for use with at least a first variant key; a second variant key for use with a second base key, the second variant key being the result of a one way function applied to: the second base key; and the first bit-pattern or a modified bit-pattern based on the first bit-pattern. 5 1703. A method according to claim 1652, for enabling or disabling a verification process of a first entity in response to a predetermined event, the first entity having at least one associated bit-pattern and at least one variant key, each of the variant keys having been generated by applying a one way function to: a base key; and one or more of the at least one bit-patterns, respectively; or one or more alternative bit patterns, each of the alternative bit-patterns being based on one or the at least one bit-patterns, the method including 10 the method including: (a). determining that the predetermined event has happened; and (b). enabling or disabling at least one of the first variant keys in response the predetermined event. 15 1704. A method according to claim 1652, implemented in a system for enabling authenticated communication between a first entity and at least one other entity, the system including a second entity, wherein: the first entity and the second entity share transport keys; and the second entity includes at least one authentication key configured to be transported from the second entity to the first entity using the transport keys, the authentication key being usable to enable the authenticated 20 communication by the first entity.
1705. A method according to claim 1652, for storing a bit-pattern in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: (a). determining a first memory location; and 25 (b). storing the bit-pattern at the first memory location;wherein the first memory locations are different in at least a plurality of the respective devices.
1706. A method according to claim 1652, for storing at least one functionally identical code segment in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: 30 (a). determining a first memory location; and (b). storing a first of the at least one code segments in the memory at the first memory location; wherein the first memory location is different in at least a plurality of the respective devices.
1707. A method according to claim 1652, for providing a sequence of nonces (RO, R1, R2, ... ) commencing 35 with a current seed of a sequence of seeds (xl, x2, x3,...), the method comprising: (a). applying a one-way function to the current seed, thereby to generate a current nonce; (b) outputting the current nonce; SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1526 (b). using the current seed to generate a next seed in a sequence of seeds, the seed so generated becoming the current seed; and (c). repeating steps (a) to (c) as required to generate further nonces in the sequence of nonces. 5 1708. A method according to claim 1652, for storing multiple first bit-patterns in non-volatile memory of a device, the method comprising, for each of the first bit-patterns to be stored: (a). applying a one way function to a third bit-pattern based on a second bit-pattern associated with the device, thereby to generate a first result; (b). applying a second function to the first result and the first bit-pattern, thereby to generate a second result; 10 and (c). storing the second result in the memory, thereby indirectly storing the first bit-pattern; wherein the third bit-patterns used for the respective first bit-patterns are relatively unique compared to each other.
1709. A method of storing a bit-pattern in each of a plurality of devices, each of the devices having a memory, 15 the method comprising, for each device: (a). determining a first memory location; and (b). storing the bit-pattern at the first memory location;wherein the first memory locations are different in at least a plurality of the respective devices. 20 1710. A method according to claim 1709, wherein step (a) includes randomly selecting the first memory location.
1711. A method according to claim 1710, wherein step (a) includes selecting the first memory location based on a stochastic process or mechanism. 25
1712. A method according to claim 1709, wherein step (a) includes selecting the first memory location from an existing list or sequence of memory locations.
1713. A method according to claim 1709, wherein the memory is non-volatile memory. 30
1714. A method according to claim 1713, the method further comprising storing one or more code segments in the memory of each device, the one or more code segments including data indicative of the first memory location at which the bit-pattern is stored on that device. 35 1715. A method according to claim 1709, wherein the first memory locations of the devices are selected such that, from device to device, there is no overlap of the positions of at least some of the bits, bytes or characters of the devices' respective bit-pattem. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1527
1716. A method according to claim 1709, wherein the first memory locations of the devices are selected such that, from device to device, positions of at least some of the bits, bytes or characters of the devices' respective bit patterns overlap. 5
1717. A method according to claim 1709, wherein the first memory locations of the devices are selected such that, from device to device, bit, byte or character positions of the devices' respective bit-patterns are shuffled, rotated or otherwise ordered differently. 10 1718. A method according to claim 1716, wherein the first memory locations of the devices are selected such that, from device to device, bit, byte or character positions of the devices' respective bit-patterns are shuffled, rotated or otherwise ordered differently.
1719. A method according to claim 1709, comprising: 15 applying a function to the first bit pattern and a second bit pattern, thereby to generate a result; and storing the result in the first memory location, thereby indirectly storing the first bit-pattern.
1720. A method according to claim 1719, wherein the second bit-pattern is stored with the device. 20 1721. A method according to claim 1720, wherein the second bit-pattern is stored in the device in a non volatile manner.
1722. A method according to claim 1719, wherein the function is a logical function. 25 1723. A method according to claim 1722, wherein the logical function is an XOR function.
1724. A method according to claim 1723, wherein the first bit-pattern is a key.
1725. A method according to claim 1719, wherein the second bit pattern was generated randomly. 30
1726. A method according to claim 1725, comprising randomly selecting the second bit-pattern.
1727. A method according to claim 1726, comprising selecting the second bit-pattern based on a stochastic process or mechanism. 35
1728. A method according to claim 1719, comprising selecting the second bit-pattern from an existing list or sequence of bit-patterns. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1528
1729. A method according to claim 1719, wherein the first memory locations of the devices are selected such that, from device to device, there is no overlap of the positions of at least some of the bits, bytes or characters of the devices' respective results. 5
1730. A method according to claim 1719, wherein the first memory locations of the devices are selected such that, from device to device, positions of at least some of the bits, bytes or characters of the devices' respective results overlap. 10 1731. A method according to claim 1719, wherein the first memory locations of the devices are selected such that, from device to device, bit, byte or character positions of the devices' respective results are shuffled, rotated or otherwise ordered differently.
1732. A method according to claim 1730, wherein the first memory locations of the devices are selected such 15 that, from device to device, bit, byte or character positions of the devices' respective results are shuffled, rotated or otherwise ordered differently.
1733. A method according to claim 1719, wherein the respective second bit-patterns are stored at a second memory location of each of the respective devices, wherein the second memory locations are different in at least a 20 plurality of the respective devices.
1734. A method according to claim 1733, wherein the second memory locations of the devices are selected such that, from device to device, there is no overlap of the positions of at least some of the bits, bytes or characters of the devices' respective second bit-patterns. 25
1735. A method according to claim 1733, wherein the second memory locations of the devices are selected such that, from device to device, positions of at least some of the bits, bytes or characters of the devices' respective second bit-patterns overlap. 30 1736. A method according to claim 1733, wherein the second memory locations of the devices are selected such that, from device to device, bit, byte or character positions of the devices' respective second bit-patterns are shuffled, rotated or otherwise ordered differently.
1737. A method according to claim 1735, wherein the second memory locations of the devices are selected 35 such that, from device to device, bit, byte or character positions of the devices' respectives second bit-patterns are shuffled, rotated or otherwise ordered differently. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1529
1738. A method according to claim 1733, the method further comprising storing one or more code segments in the memory of each device, the one or more code segments including data indicative of the second memory location at which the second bit-pattem is stored on that device. 5 1739. A method according to claim 1709, further comprising, for each device: determining a second memory location; and storing, at the second memory location, a result of applying a function to the bit-pattern;wherein the second memory locations are different in at least a plurality of the respective devices. 10 1740. . A method according to claim 1739, wherein the function is a logical operation.
1741. A method according to claim 1739, wherein the function is a bit inversion operation.
1742. A method according to claim 1739, wherein step (a) includes randomly selecting the second memory 15 location.
1743. A method according to claim 1742, wherein step (a) includes selecting the second memory location based on a stochastic process or mechanism. 20 1744. A method according to claim 1739, wherein step (a) includes selecting the second memory location from an existing list or sequence of memory locations.
1745. A method according to claim 1739, wherein the memory is non-volatile memory. 25 1746. A method according to claim 1745, the method further comprising storing one or more code segments in the memory of each device, the one or more code segments including data indicative of the second memory location at which the result is stored on that device.
1747. A method according to claim 1746, wherein the second memory locations of the devices are selected 30 such that, from device to device, there is no overlap of the positions of at least some of the bits, bytes or characters of the devices' respective results.
1748. A method according to claim 1746, wherein the second memory locations of the devices are selected such that, from device to device, positions of at least some of the bits, bytes or characters of the devices' 35 respective results overlap. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1530
1749. A method according to claim 1739, wherein the second memory locations of the devices are selected such that, from device to device, bit, byte or character positions of the devices' respective results are shuffled, rotated or otherwise ordered differently. 5 1750. A method according to claim 1748, wherein the second memory locations of the devices are selected such that, from device to device, bit, byte or character positions of the devices' respective results are shuffled, rotated or otherwise ordered differently.
1751. A device having a bit-pattern stored in it in accordance with the method of claim 1709. 10
1752. A device having a bit-pattern and a result stored in it in accordance with the method of claim 1719.
1753. A device having a bit-pattern and a result stored in it in accordance with the method of claim 1729. 15 1754. A plurality of devices having respective bit-patterns stored in them in accordance with the method of claim 1709.
1755. A plurality of devices having respective bit-patterns and results stored in them in accordance with the method of claim 1719. 20
1756. A plurality of devices having respective bit-patterns and results stored in them in accordance with the method of claim 1729.
1757. A device having a bit-pattern stored in it in accordance with the method of claim 1709. 25
1758. A device having a bit-pattern and a result stored in it in accordance with the method of claim 1719.
1759. A device having a bit-pattern and a result stored in it in accordance with the method of claim 1729. 30 1760. A plurality of devices having respective bit patterns stored in them in accordance with the method of claim 1709.
1761. A plurality of devices having a bit-pattern and a result stored in them in accordance with the method of claim 1719. 35
1762. A plurality of devices having a bit-pattern and a result stored in them in accordance with the method of claim 1729. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1531
1763. A method according to claim 1709, implemented in a first entity configured to authenticate a digital signature supplied by a second entity, wherein one of the entities includes a base key and the other of the entities includes a variant key and a bit-pattern, the variant key being based on the result of applying a one way function 5 to the base key and the bit-pattern, the digital signature having been generated by the second entity using its key to digitally signing at least part of data to be authenticated, the first entity being configured to: (a). receive the digital signature from the second entity; (b). receive the data; and (c). authenticate the digital signature based on the received data and the first entity's key. 10
1764. A method according to claim 1709, implemented in a first entity including: a first bit-pattern a non-volatile memory storing resource data, a first base key for use with at least a first variant key; 15 a second variant key for use with a second base key, the second variant key being the result of a one way function applied to: the second base key; and the first bit-pattern or a modified bit-pattern based on the first bit-pattern.
1765. A method according to claim 1709, for enabling or disabling a verification process of a first entity in response to a predetermined event, the first entity having at least one associated bit-pattern and at least one variant 20 key, each of the variant keys having been generated by applying a one way function to: a base key; and one or more of the at least one bit-patterns, respectively; or one or more alternative bit patterns, each of the alternative bit-patterns being based on one or the at least one bit-patterns, the method including the method including: (a). determining that the predetermined event has happened; and (b). enabling or disabling at least one of the first variant keys in response the predetermined event. 25
1766. A method according to claim 1709, implemented in a system for enabling authenticated communication between a first entity and at least one other entity, the system including a second entity, wherein: the first entity and the second entity share transport keys; and 30 the second entity includes at least one authentication key configured to be transported from the second entity to the first entity using the transport keys, the authentication key being usable to enable the authenticated communication by the first entity.
1767. A method according to claim 1709, for storing a first bit-pattem in non-volatile memory of a device, the 35 method comprising: (a). applying a one way function to a second bit-pattern associated with the device, thereby to generate a first result; SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1532 (b). applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and (c). storing the second result in the memory, thereby indirectly storing the first bit-pattern. 5
1768. A method according to claim 1709, for storing at least one functionally identical code segment in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: (a). determining a first memory location; and (b). storing a first of the at least one code segments in the memory at the first memory location;wherein the 10 first memory location is different in at least a plurality of the respective devices.
1769. A method according to claim 1709, for providing a sequence of nonces (RO, Rl, R2, ... ) commencing with a current seed of a sequence of seeds (xl, x2, x3,...), the method comprising: (a). applying a one-way function to the current seed, thereby to generate a current nonce; (b) outputting the 15 current nonce; (b). using the current seed to generate a next seed in a sequence of seeds, the seed so generated becoming the current seed; and (c). repeating steps (a) to (c) as required to generate further nonces in the sequence of nonces. 20 1770. A method according to claim 1709, for storing multiple first bit-patterns in non-volatile memory of a device, the method comprising, for each of the first bit-patterns to be stored: (a). applying a one way function to a third bit-pattern based on a second bit-pattern associated with the device, thereby to generate a first result; (b). applying a second function to the first result and the first bit-pattern, thereby to generate a second result; 25 and (c). storing the second result in the memory, thereby indirectly storing the first bit-pattern; wherein the third bit-patterns used for the respective first bit-patterns are relatively unique compared to each other.
1771. A method of storing at least one functionally identical code segment in each of a plurality of devices, 30 each of the devices having a memory, the method comprising, for each device: (a). determining a first memory location; and (b). storing a first of the at least one code segments in the memory at the first memory location; wherein the first memory location is different in at least a plurality of the respective devices. 35 1772. A method according to claim 1771, wherein at least one of the code segments in each of the devices includes an initial instruction, the initial instruction being located at an initial instruction location, the initial instruction location being the same in all the devices. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1533
1773. A method according to claim 1772, wherein the initial instruction in each device is indicative of the first memory location of that device. 5 1774. A method according to claim 1773, wherein the initial instruction is indicative of the first memory location by including an explicit reference to the memory location.
1775. A method according to claim 1774, wherein the initial instruction is indicative of the first memory location by including an implicit reference to the memory location. 10
1776. A method according to claim 1775, wherein the implicit reference is a pointer to a location at which the address of the first memory location is stored.
1777. A method according to claim 1776, wherein the implicit reference is a pointer to a register that holds the 15 address of the first memory location.
1778. A method according to claim 1771, wherein step (a) includes randomly selecting the first memory location. 20 1779. A method according to claim 1778, wherein step (a) includes selecting the first memory location based on a stochastic process or mechanism.
1780. A method according to claim 1771, wherein step (a) includes selecting the first memory location from an existing list or sequence of memory locations. 25
1781. A method according to claim 1771, each device including at least one additional memory location, each of the at least one code segments being located at the first memory location or one of the additional memory locations, wherein each of the code segments includes at least one instruction that is indicative of one of the at least one additional memory locations or of the first memory location, and wherein at least one of the additional 30 memory locations corresponding to one of the code segments is different in at least a plurality of the respective devices.
1782. A method according to claim 1781, wherein the at least one instruction is indicative of the additional or first memory location by including an explicit reference to the memory location. 35
1783. A method according to claim 1782, wherein the at least one instruction is indicative of the additional or first memory location by including an implicit reference to the memory location. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1534
1784. A method according to claim 1783, wherein the implicit reference is a pointer to a location at which the address of the additional or first memory location is stored. 5 1785. A method according to claim 1784, wherein the implicit reference is a pointer to a register that holds the address of the additional or first memory location.
1786. A method according to claim 1783, wherein the implicit reference is an index into an address table wherein the address table holds the location of the additional or first memory location. 10
1787. A method according to claim 1771, wherein the memory is non-volatile memory.
1788. A method according to claim 1781, wherein the memory is non-volatile memory. 15 1789. A method according to claim 1771, implemented in a first entity configured to authenticate a digital signature supplied by a second entity, wherein one of the entities includes a base key and the other of the entities includes a variant key and a bit-pattern, the variant key being based on the result of applying a one way function to the base key and the bit-pattern, the digital signature having been generated by the second entity using its key to digitally signing at least part of data to be authenticated, the first entity being configured to: 20 (a). receive the digital signature from the second entity; (b). receive the data; and (c). authenticate the digital signature based on the received data and the first entity's key.
1790. A method according to claim 1771, implemented in a first entity including: 25 a first bit-pattern a non-volatile memory storing resource data, a first base key for use with at least a first variant key; a second variant key for use with a second base key, the second variant key being the result of a one way function applied to: the second base key; and the first bit-pattern or a modified bit-pattern based on the first bit-pattern. 30
1791. A method according to claim 1771, for enabling or disabling a verification process of a first entity in response to a predetermined event, the first entity having at least one associated bit-pattern and at least one variant key, each of the variant keys having been generated by applying a one way function to: a base key; and one or 35 more of the at least one bit-patterns, respectively; or one or more alternative bit patterns, each of the alternative bit-patterns being based on one or the at least one bit-patterns, the method including the method including: (a). determining that the predetermined event has happened; and SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1535 (b). enabling or disabling at least one of the first variant keys in response the predetermined event
1792. A method according to claim 1771, implemented in a system for enabling authenticated communication 5 between a first entity and at least one other entity, the system including a second entity, wherein: the first entity. and the second entity share transport keys; and the second entity includes at least one authentication key configured to be transported from the second entity to the first entity using the transport keys, the authentication key being usable to enable the authenticated communication by the first entity. 10
1793. A method according to claim 1771, for storing a first bit-pattern in non-volatile memory of a device, the method comprising: (a). applying a one way function to a second bit-pattern associated with the device, thereby to generate a first 15 result; (b). applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and (c). storing the second result in the memory, thereby indirectly storing the first bit-pattern. 20
1794. A method according to claim 1771, for storing a bit-pattern in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: (a). determining a first memory location; and (b). storing the bit-pattern at the first memory location; wherein the first memory locations are different in at 25 least a plurality of the respective devices.
1795. A method according to claim 1771, for providing a sequence of nonces (RO, R1, R2, ... ) commencing with a current seed of a sequence of seeds (xl, x2, x3,...), the method comprising: (a). applying a one-way function to the current seed, thereby to generate a current nonce; (b) outputting the 30 current nonce; (b). using the current seed to generate a next seed in a sequence of seeds, the seed so generated becoming the current seed; and (c). repeating steps (a) to (c) as required to generate further nonces in the sequence of nonces. 35 1796. A method according to claim 1771, for storing multiple first bit-patterns in non-volatile memory of a device, the method comprising, for each of the first bit-patterns to be stored: SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1536 (a). applying a one way function to a third bit-pattern based on a second bit-pattern associated with the device, thereby to generate a first result; (b). applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and 5 (c). storing the second result in the memory, thereby indirectly storing the first bit-pattern; wherein the third bit-patterns used for the respective first bit-patterns are relatively unique compared to each other.
1797. A method for providing a sequence of nonces (RO, R1, R2, ... ) commencing with a current seed of a sequence of seeds (xl, x2, x3,...), the method comprising: 10 (a). applying a one-way function to the current seed, thereby to generate a current nonce; (b) outputting the current nonce; (b). using the current seed to generate a next seed in a sequence of seeds, the seed so generated becoming the current seed; and (c). repeating steps (a) to (c) as required to generate further nonces in the sequence of nonces. 15
1798. A method according to claim 1797, wherein xl is generated based on an initial seed x0, the initial seed having been generated by a random number generator.
1799. A method according to claim 1798, the initial seed xO having been generated based on a stochastic 20 process.
1800. A method according to clain 1799, wherein the next seed is generated from the current seed on the basis of a second function. 25 1801. A method according to claim 1800, wherein the second function is less cryptographically strong than the one way function.
1802. A method according to claim 1801, wherein the second function is additive. 30 1803. A method according to claim 1797, wherein the second function is a linear feedback shift register function.
1804. A method according to claim 1797, wherein the one way function is a hash function. 35 1805. A method according to claim 1797, wherein the hash function is SHAL. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1537
1806. A device for generating a sequence of nonces (RO, R1, R2, ... ), the device including: memory for storing a current seed of a sequence of seeds (xl, x2, x3,...)' a processor configured to: (a). apply a one way function to the current seed to generate a current nonce; and (b). use the current seed to generate a next seed in the sequence of seeds, the seed so generated becoming the 5 current seed; and (c). storing the current seed in memory.
1807. A device according to claim 1806, configured to generate x1 in the seed sequence based on an initial seed xO, the initial seed being stored in a non-volatile manner in the device. 10
1808. A device according to claim 1806, wherein xO was generated by a random number generator.
1809. A device according to claim 1808, the initial seed xO having been generated based on a stochastic process. 15
1810. A device according to claim 1806, wherein the processor is configured to generate the next seed by applying a second function to the current seed.
1811. A deviQe according to claim 1810, wherein the second function is less cryptographically strong than the 20 one way function.
1812. A device according to claim 1811, wherein the second function is additive.
1813. A device according to claim 1806, wherein the second function is a linear feedback shift register 25 function.
1814. A device according to claim 1806, wherein the memory is non-volatile.
1815. A device according to claim 1813, wherein the memory is flash memory. 30
1816. A device according to claim 1806, wherein the device comprises one or more integrated circuits.
1817. A device according to claim 1806, wherein the device comprises a monolithic integrated circuit. 35 1818. A device according to claim 1806, wherein the one way function is a hash function.
1819. A device according to claim 1818, wherein the hash function is SHAl. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1538
1820. A method of manufacturing a series of devices, each of the devices being in accordance with claim 10 and including a non-volatile memory, the method comprising: (a). generating a bit-pattern on the basis of a random or pseudo random process; 5 (b). storing the bit-pattem in a non-volatile manner in the device; wherein the device is configured to use the bit-pattern as an initial current seed, and to store subsequent generated seeds in the non-volatile memory.
1821. A method according to claim 1820, wherein the step of storing the bit-pattern in a non-volatile manner includes storing the value in a place other than in the non-volatile memory. 10
1822. A method according to claim 1821, wherein the bit-pattern is stored in non-erasable form.
1823. A method according to claim 1820, including the step of storing a program on the device, the program including the one way function for generating the current nonce from the current seed. 15
1824. A method according to claim 1823, wherein the one way function is a hash function.
1825. A method according to claim 1823, wherein the one way function is non-compressing. 20 1826. A method according to claim 1824, wherein the hash function is SHA1
1827. A method according to claim 1797, implemented in a first entity configured to authenticate a digital signature supplied by a second entity, wherein one of the entities includes a base key and the other of the entities includes a variant key and a bit-pattern, the variant key being based on the result of applying a one way function 25 to the base key and the bit-pattern, the digital signature having been generated by the second entity using its key to digitally signing at least part of data to be authenticated, the first entity being configured to: (a). receive the digital signature from the second entity; (b). receive the data; and (c). authenticate the digital signature based on the received data and the first entity's key. 30
1828. A method according to claim 1797, implemented in a first entity including: a first bit-pattern a non-volatile memory storing resource data, 35 a first base key for use with at least a first variant key; a second variant key for use with a second base key, the second variant key being the result of a one way function applied to: the second base key; and the first bit-pattern or a modified bit-pattern based on the first bit-pattern. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1539
1829. A method according to claim 1797, for enabling or disabling a verification process of a first entity in response to a predetermined event, the first entity having at least one associated bit-pattern and at least one variant 5 key, each of the variant keys having been generated by applying a one way function to: a base key; and one or mor of the at least one bit-patterns, respectively; or one or more alternative bit patterns, each of the alternative bit-patterns being based on one or the at least one bit-patterns, the method including the method including: (a). determining that the predetermined event has happened; and (b). enabling or disabling at least one of the first variant keys in response the predetermined event. 10
1830. A method according to claim 1797, implemented in a system for enabling authenticated communication between a first entity and at least one other entity, the system including a second entity, wherein: the first entity and the second entity share transport keys; and 15 the second entity includes at least one authentication key configured to be transported from the second entity to the first entity using the transport keys, the authentication key being usable to enable the authenticated communication by the first entity.
1831. A method according to claim 1797, for storing a first bit-pattern in non-volatile memory of a device, the 20 method comprising: (a). applying a one way function to a second bit-pattern associated with the device, thereby to generate a first result; (b). applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and 25 (c). storing the second result in the memory, thereby indirectly storing the first bit-pattern.
1832. A method according to claim 1797, for storing a bit-pattern in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: 30 (a). determining a first memory location; and (b). storing the bit-pattern at the first memory location; wherein the first memory locations are different in at least a plurality of the respective devices.
1833. A method according to claim 1797, for storing at least one functionally identical code segment in each of 35 a plurality of devices, each of the devices having a memory, the method comprising, for each device: (a). determining a first memory location; and SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1540 (b). storing a first of the at least one code segments in the memory at the first memory location; wherein the first memory location is different in at least a plurality of the respective devices. 5 1834. A method according to claim 1797, for storing multiple first bit-patterns in non-volatile memory of a device, the method comprising, for each of the first bit-pattems to be stored: (a). applying a one way function to a third bit-pattern based on a second bit-pattern associated with the device, thereby to generate a first result; (b). applying a second function to the first result and the first bit-pattern, thereby to generate a second result; 10 and (c). storing the second result in the memory, thereby indirectly storing the first bit-pattern; wherein the third bit-patterns used for the respective first bit-patterns are relatively unique compared to each other.
1835. A method of storing multiple first bit-patterns in- non-volatile memory of a device, the method 15 comprising, for each of the first bit-patterns to be stored: (a). applying a one way function to a third bit-pattern based on a second bit-pattern associated with the device, thereby to generate a first result; (b). applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and 20 (c). storing the second result in the memory, thereby indirectly storing the first bit-pattern;wherein the third bit-patterns used for the respective first bit-patterns are relatively unique compared to each other.
1836. A method according to claim 1835, wherein step (c) comprises: (d). determining a first memory location; and 25 (e). storing the second result at the first memory location.
1837. A method according to claim 1836, wherein step (d) includes randomly selecting the first memory location. 30 1838. A method according to claim 1837, wherein step (d) includes selecting the first memory location based on a stochastic process or mechanism.
1839. A method according to claim 1836, wherein step (d) includes selecting the first memory location from an existing list or sequence of memory locations. 35
1840. A method according to claim 1835, wherein each third bit-pattern is generated from the second bit pattern by removing, adding or changing one or more bits, bytes or characters of the second bit-pattern. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1541
1841. A method according to claim 1840, wherein each third bit-pattern is generated from the second bit pattern by adding an index of one or more bits, bytes or characters to the second bit-pattern, the index having been added at any position of the identifier, including being appended before or after the identifier, or being distributed 5 within the identifier.
1842. A method according to claim 1841, wherein the index added to the second bit-pattern for the respective second bit-patterns is derived from a series of indices. 10 1843. A method according to claim 1842, including the step of generating the index as required.
1844. A method according to claim 1835, wherein the one way function is more cryptographically secure than the second function. 15 1845. A method according to claim 1835, wherein the second function is a logical function.
1846. A method according to claim 1845, wherein the logical function is an XOR function.
1847. A method according to claim 1835, wherein the one way function is a hash function. 20
1848. A method according to claim 1835, wherein each of the first bit-patterns is a key.
1849. A method according to claim 1835, further including the step of storing one or more code segments in the memory, the code segments being configured to run on a processor of the device, thereby enabling the device to, 25 for each of first bit-patterns to be retrieved: generate the third-bit pattern corresponding to the first bit pattern to be retrieved; apply the one way function to the third bit-pattern, thereby to generate the first result; and apply a third function to the first result and the second result corresponding to the first bit-pattern to be retrieved, thereby to generate that first bit-pattern; 30 wherein the third function is the inverse of the second function.
1850. A method according to claim 1849, wherein the third function and the second function are the same.
1851. A method according to claim 1835, wherein the second bit-pattern was generated randomly or pseudo 35 randomly. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1542
1852. A method according to claim 1835, the method further including the step, performed prior to step (a), of determining the second bit-pattern.
1853. A method according to claim 1852, wherein determining the second bit-pattern includes generating the 5 second bit-pattern randomly or pseudo-randomly.
1854. * A method according to claim 1852, wherein determining the second bit-pattern includes generating the second bit-pattern based on a stochastic process or mechanism. 10 1855. A method according to claim 1852, wherein determining the second bit-pattern includes selecting the second-bit pattern from an existing list or sequence of bit-patterns.
1856. A method of storing multiple first bit-patterns in non-volatile memory of each of a plurality of devices, the method comprising, for each of the first bit-patterns to be stored: 15 (a). applying a one way function to a third bit-pattern based on a second bit-pattern associated with the device, thereby to generate a first result; (b). applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and (c). storing the second result in the memory, thereby indirectly storing the first bit-pattern; wherein the third 20 bit-patterns used for the respective first bit-patterns in each device are relatively unique with respect to each other, and the second bit-patterns of the respective devices are relatively unique with respect to each other.
1857. A method according to claim 1835, wherein step (c) comprises, for each device: (d). determining a first memory location; and 25 (e). storing the second result at the first memory location.
1858. A method according to claim 1857, wherein step (d) includes randomly selecting the first memory location. 30 1859. A method according to claim 1858, wherein step (d) includes selecting the first memory location based on a stochastic process or mechanism.
1860. A method according to claim 1857, wherein step (d) includes selecting the first memory location from an existing list or sequence of memory locations. 35 SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1543
1861. A method according to claim 1857, wherein the first memory locations of the devices are selected such that, from device to device, there is no overlap of the positions of at least some of the bits, bytes or characters of the devices' respective second results. 5 1862. A method according to claim 1857, wherein the first memory locations of the devices are selected such that, from device to device, positions of at least some of the bits, bytes or characters of the devices' respective second results overlap.
1863. A method according to claim 1857, wherein the first memory locations of the devices are selected such 10 that, from device to device, bit, byte or character positions of the devices' respective second results are shuffled, rotated or otherwise ordered differently.
1864. A method according to claim 1863, wherein the first memory locations of the devices are selected such that, fmm device to device, bit, byte or character positions of the devices' respective second results are shuffled, 15 rotated or otherwise ordered differently.
1865. A method according to claim 1856, wherein for each device, each third bit-pattern is generated from the second bit-pattern by removing, adding or changing one or more bits, bytes or characters of the second bit-pattern. 20 1866. A method according to claim 1865, wherein for each device, each third bit-pattern is generated from the second bit-pattern by adding an index of one or more bits, bytes or characters to the second bit-pattern, the index having been added at any position of the identifier, including being distributed within the identifier.
1867. A method according to claim 1866, wherein the index added to the second bit-pattern for the respective 25 second bit-patterns is derived from a series of indices.
1868. A method according to claim 1867, including the step, for each device, of generating the index as required. 30 1869. A method according to claim 1856, wherein the one way function is more cryptographically secure than the second function.
1870. A method according to claim 1856, wherein the second function is a logical function. 35 1871. A method according to claim 1870, wherein the logical function is an XOR function.
1872. A method according to claim 1856, wherein the one way function is a hash function. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1544
1873. A method according to claim 1856, wherein each of the first bit-patterns is a key.
1874. A method according to claim 1856, further including the step of storing one or more code segments in the 5 memory of each device, the code segments being configured to run on a processor of each device, thereby enabling each device to, for each of first bit-patterns to be retrieved: generate the third-bit pattern corresponding to the first bit pattern to be retrieved; apply the one way function to the third bit-pattern, thereby to generate the first result; and apply a third function to the first result and the second result corresponding to the first bit-pattem to be retrieved, 10 thereby to generate that first bit-pattern; wherein the third function is the inverse of the second function.
1875. A method according to claim 1874, wherein the third function and the second function are the same. 15 1876. A method according to claim 1856, wherein the second bit-pattern for each device was generated randomly or pseudo-randomly.
1877. A method according to claim 1876, wherein the second bit-pattern for each device was generated based on a stochastic process or mechanism. 20
1878. A device manufactured in accordance with the method of claim 1835.
1879. A device manufactured in accordance with the method of claim 1849. 25 1880. A plurality of devices manufactured in accordance with the method of claim 1856.
1881. A plurality of devices manufactured in accordance with the method of claim 1874.
1882. A method according to claim 1835, implemented in a first entity configured to authenticate a digital 30 signature supplied by a second entity, wherein one of the entities includes a base key and the other of the entities includes a variant key and a bit-pattern, the variant key being based on the result of applying a one way function to the base key and the bit-pattern, the digital signature having been generated by the second entity using its key to digitally signing at least part of data to be authenticated, the first entity being configured to: (a). receive the digital signature from the second entity; 35 (b). receive the data; and (c). authenticate the digital signature based on the received data and the first entity's key. SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1545
1883. A method according to claim 1835, implemented in a first entity including: a first bit-pattern a non-volatile memory storing resource data, 5 a first base key for use with at least a first variant key; a second variant key for use with a second base key, the second variant key being the result of a one way function applied to: the second base key; and the first bit-pattern or a modified bit-pattern based on the first bit-pattern. 10 1884. A method according to claim 1835, for enabling or disabling a verification process of a first entity in response to a predetermined event, the first entity having at least one associated bit-pattern and at least one variant key, each of the variant keys having been generated by applying a one way function to: a base key; and one or more of the at least one bit-patterns, respectively; or one or more alternative bit patterns, each of the alternative bit-patterns being based on one or the at least one bit-patterns, the method including the method including: 15 (a). determining that the predetermined event has happened; and (b). enabling or disabling at least one of the first variant keys in response the predetermined event.
1885. A method according to claim 1835, implemented in a system for enabling authenticated communication 20 between a first entity and at least one other entity, the system including a second entity, wherein: the first entity and the second entity share transport keys; and the second entity includes at least one authentication key configured to be transported from the second entity to the first entity using the transport keys, the authentication key being usable to enable the authenticated communication by the first entity. 25
1886. A method according to claim 1835, for storing a first bit-pattern in non-volatile memory of a device, the method comprising: (a). applying a one way function to a second bit-pattern associated with the device, thereby to generate a first 30 result; (b). applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and (c). storing the second result in the memory, thereby indirectly storing the first bit-pattern. 35
1887. A method according to claim 1835, for storing a bit-pattern in each of a plurality of devices, each of the deviceS having a memory, the method comprising, for each device: SUBSTITUTE SHEET (RULE 26) RO/AU WO 2005/120835 PCT/AU2004/000706 1546 (a). determining a first memory location; and (b). storing the bit-pattern at the first memory location; wherein the first memory locations are different in at least a plurality of the respective devices. 5 1888. A method according to claim 1835, for storing'at least one functionally identical code segment in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device: (a). determining a first memory location; and (b). storing a first of the at least one code segments in the memory at the first memory.location; wherein the first memory location is different in at least a plurality of the respective devices. 10
1889. A method according to claim 1835, for providing a sequence of nonces (RO, R1, R2, ... ) commencing with a current seed of a sequence of seeds (xl, x2, x3,...), the method comprising: (a). applying a one-way function to the current seed, thereby to generate a current nonce; (b) outputting the current nonce; 15 (b). using the current seed to generate a next seed in a sequence of seeds, the seed so generated becoming the current seed; and (c). repeating steps (a) to (c) as required to generate further nonces in the sequence of nonces. SUBSTITUTE SHEET (RULE 26) RO/AU
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2004
- 2004-05-27 WO PCT/AU2004/000706 patent/WO2005120835A1/en active Application Filing
- 2004-05-27 EP EP10193974A patent/EP2301753B1/en not_active Expired - Lifetime
- 2004-05-27 PT PT101939742T patent/PT2301753E/en unknown
- 2004-05-27 AU AU2004320526A patent/AU2004320526B2/en not_active Ceased
- 2004-05-27 EP EP04734974A patent/EP1765595B1/en not_active Expired - Lifetime
- 2004-05-27 DE DE602004031888T patent/DE602004031888D1/en not_active Expired - Lifetime
- 2004-05-27 CA CA002567724A patent/CA2567724A1/en not_active Abandoned
- 2004-05-27 AT AT04734974T patent/ATE501857T1/en not_active IP Right Cessation
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2009
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- 2012-11-20 CY CY20121101116T patent/CY1113337T1/en unknown
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