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AU2003250361A1 - Processor for performing arithmetic operations in composite operands - Google Patents

Processor for performing arithmetic operations in composite operands

Info

Publication number
AU2003250361A1
AU2003250361A1 AU2003250361A AU2003250361A AU2003250361A1 AU 2003250361 A1 AU2003250361 A1 AU 2003250361A1 AU 2003250361 A AU2003250361 A AU 2003250361A AU 2003250361 A AU2003250361 A AU 2003250361A AU 2003250361 A1 AU2003250361 A1 AU 2003250361A1
Authority
AU
Australia
Prior art keywords
processor
arithmetic operations
performing arithmetic
composite operands
operands
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003250361A
Other versions
AU2003250361A8 (en
Inventor
Mohammed Benaissa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Sheffield
Original Assignee
University of Sheffield
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Sheffield filed Critical University of Sheffield
Publication of AU2003250361A1 publication Critical patent/AU2003250361A1/en
Publication of AU2003250361A8 publication Critical patent/AU2003250361A8/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/724—Finite field arithmetic
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G06F9/30014—Arithmetic instructions with variable precision
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3812—Devices capable of handling different types of numbers
    • G06F2207/382—Reconfigurable for different fixed word lengths
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3828—Multigauge devices, i.e. capable of handling packed numbers without unpacking them
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
    • G06F2207/7209—Calculation via subfield, i.e. the subfield being GF(q) with q a prime power, e.g. GF ((2**m)**n) via GF(2**m)

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Computing Systems (AREA)
  • Algebra (AREA)
  • Probability & Statistics with Applications (AREA)
  • Error Detection And Correction (AREA)
AU2003250361A 2002-06-14 2003-06-11 Processor for performing arithmetic operations in composite operands Abandoned AU2003250361A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB0213683A GB2389678A (en) 2002-06-14 2002-06-14 Finite field processor reconfigurable for varying sizes of field.
GB0213683.6 2002-06-14
PCT/GB2003/002481 WO2003107177A2 (en) 2002-06-14 2003-06-11 Processor

Publications (2)

Publication Number Publication Date
AU2003250361A1 true AU2003250361A1 (en) 2003-12-31
AU2003250361A8 AU2003250361A8 (en) 2003-12-31

Family

ID=9938576

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003250361A Abandoned AU2003250361A1 (en) 2002-06-14 2003-06-11 Processor for performing arithmetic operations in composite operands

Country Status (3)

Country Link
AU (1) AU2003250361A1 (en)
GB (1) GB2389678A (en)
WO (1) WO2003107177A2 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7594261B2 (en) 2005-02-08 2009-09-22 Microsoft Corporation Cryptographic applications of the Cartier pairing
US7702098B2 (en) 2005-03-15 2010-04-20 Microsoft Corporation Elliptic curve point octupling for weighted projective coordinates
US7680268B2 (en) 2005-03-15 2010-03-16 Microsoft Corporation Elliptic curve point octupling using single instruction multiple data processing
DE102005041102A1 (en) * 2005-08-30 2007-03-15 Siemens Ag Method for scalar multiplication of points on an elliptic curve
US8180047B2 (en) 2006-01-13 2012-05-15 Microsoft Corporation Trapdoor pairings
KR100896269B1 (en) 2006-12-05 2009-05-08 한국전자통신연구원 Simd parallel processor with simd/sisd/row/column opertaion modes
US8923510B2 (en) * 2007-12-28 2014-12-30 Intel Corporation Method and apparatus for efficiently implementing the advanced encryption standard
GB2458665B (en) * 2008-03-26 2012-03-07 Advanced Risc Mach Ltd Polynomial data processing operation
GB2497070B (en) 2011-11-17 2015-11-25 Advanced Risc Mach Ltd Cryptographic support instructions
US10409615B2 (en) * 2017-06-19 2019-09-10 The Regents Of The University Of Michigan Configurable arithmetic unit

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5001662A (en) * 1989-04-28 1991-03-19 Apple Computer, Inc. Method and apparatus for multi-gauge computation
US5210710A (en) * 1990-10-17 1993-05-11 Cylink Corporation Modulo arithmetic processor chip
EP1302848B1 (en) * 1994-12-01 2006-11-02 Intel Corporation A microprocessor having a multiply operation
US6092094A (en) * 1996-04-17 2000-07-18 Advanced Micro Devices, Inc. Execute unit configured to selectably interpret an operand as multiple operands or as a single operand
US6009450A (en) * 1997-12-24 1999-12-28 Motorola, Inc. Finite field inverse circuit

Also Published As

Publication number Publication date
GB2389678A (en) 2003-12-17
WO2003107177A2 (en) 2003-12-24
GB0213683D0 (en) 2002-07-24
WO2003107177A3 (en) 2004-10-07
AU2003250361A8 (en) 2003-12-31

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase