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AU2002228866A1 - High bandwidth multi-phase clock selector with continuous phase output - Google Patents

High bandwidth multi-phase clock selector with continuous phase output

Info

Publication number
AU2002228866A1
AU2002228866A1 AU2002228866A AU2886602A AU2002228866A1 AU 2002228866 A1 AU2002228866 A1 AU 2002228866A1 AU 2002228866 A AU2002228866 A AU 2002228866A AU 2886602 A AU2886602 A AU 2886602A AU 2002228866 A1 AU2002228866 A1 AU 2002228866A1
Authority
AU
Australia
Prior art keywords
high bandwidth
clock selector
bandwidth multi
continuous phase
phase output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002228866A
Inventor
Keith Bassett
Benjamin Tang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Primarion Inc
Original Assignee
Primarion Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Primarion Inc filed Critical Primarion Inc
Publication of AU2002228866A1 publication Critical patent/AU2002228866A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H03L7/0996—Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
AU2002228866A 2000-11-13 2001-11-13 High bandwidth multi-phase clock selector with continuous phase output Abandoned AU2002228866A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US24804200P 2000-11-13 2000-11-13
US60/248,042 2000-11-13
PCT/US2001/047050 WO2002039585A2 (en) 2000-11-13 2001-11-13 High bandwidth multi-phase clock selector with continuous phase output

Publications (1)

Publication Number Publication Date
AU2002228866A1 true AU2002228866A1 (en) 2002-05-21

Family

ID=22937406

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002228866A Abandoned AU2002228866A1 (en) 2000-11-13 2001-11-13 High bandwidth multi-phase clock selector with continuous phase output

Country Status (3)

Country Link
US (1) US6621312B2 (en)
AU (1) AU2002228866A1 (en)
WO (1) WO2002039585A2 (en)

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US7164742B2 (en) * 2002-10-31 2007-01-16 Intel Corporation Deskew architecture
US20050063506A1 (en) * 2003-09-23 2005-03-24 Sony Corporation Method and system for jitter correction
US7046072B2 (en) * 2004-03-03 2006-05-16 Atheros Communications, Inc. Commutating phase selector
US8155018B2 (en) * 2004-03-03 2012-04-10 Qualcomm Atheros, Inc. Implementing location awareness in WLAN devices
US7516029B2 (en) * 2004-06-09 2009-04-07 Rambus, Inc. Communication channel calibration using feedback
US8228110B1 (en) 2004-12-06 2012-07-24 Marvell International Ltd. Low power, low voltage phase interpolator
US7158443B2 (en) * 2005-06-01 2007-01-02 Micron Technology, Inc. Delay-lock loop and method adapting itself to operate over a wide frequency range
TWI316329B (en) * 2006-04-26 2009-10-21 Realtek Semiconductor Corp Phase selector, data receiving device, data transmitting device utilizing phase selector and clock-selecting method
JP4983178B2 (en) * 2006-09-15 2012-07-25 富士通株式会社 Differential quadrature phase-shift keying optical receiver circuit
US7551012B2 (en) * 2007-03-27 2009-06-23 Mosaid Technologies Incorporated Phase shifting in DLL/PLL
US8355478B1 (en) 2009-05-29 2013-01-15 Honeywell International Inc. Circuit for aligning clock to parallel data
US8294500B1 (en) * 2009-10-27 2012-10-23 Altera Corporation Multi-phase interpolators and related methods
US9020087B2 (en) * 2012-05-15 2015-04-28 Exar Corporation All digital burst-mode clock and data recovery (CDR)
JP6024489B2 (en) * 2013-01-31 2016-11-16 富士通株式会社 Clock recovery circuit and clock data recovery circuit
EP3420637A4 (en) * 2016-03-03 2019-03-13 Qualcomm Incorporated Method for robust phase-locked loop design
CN113539327B (en) * 2021-07-09 2024-08-13 中国科学院上海微系统与信息技术研究所 Device for realizing quick logic calculation of phase change memory unit and data retrieval method
CN116743121B (en) * 2023-08-16 2023-10-27 沐曦集成电路(上海)有限公司 Clock selection system for digital frequency synthesizer

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5034967A (en) 1988-11-14 1991-07-23 Datapoint Corporation Metastable-free digital synchronizer with low phase error
US5179303A (en) * 1991-10-24 1993-01-12 Northern Telecom Limited Signal delay apparatus employing a phase locked loop
US5485490A (en) 1992-05-28 1996-01-16 Rambus, Inc. Method and circuitry for clock synchronization
CA2130268C (en) 1992-12-23 2000-05-16 Yoav Goldenberg Digitally controlled phase shifter
US5521499A (en) * 1992-12-23 1996-05-28 Comstream Corporation Signal controlled phase shifter
US5355035A (en) 1993-01-08 1994-10-11 Vora Madhukar B High speed BICMOS switches and multiplexers
US5561692A (en) 1993-12-09 1996-10-01 Northern Telecom Limited Clock phase shifting method and apparatus
AU1841895A (en) * 1994-02-15 1995-08-29 Rambus Inc. Delay-locked loop
US5475344A (en) 1994-02-22 1995-12-12 The Board Of Trustees Of The Leland Stanford Junior University Multiple interconnected ring oscillator circuit
US5570294A (en) 1994-03-11 1996-10-29 Advanced Micro Devices Circuit configuration employing a compare unit for testing variably controlled delay units
US5502750A (en) * 1994-06-15 1996-03-26 Pericom Semiconductor Corp. Digital jitter attenuator using selection of multi-phase clocks and auto-centering elastic buffer for a token ring network
US5552745A (en) 1994-09-21 1996-09-03 International Business Machines Corporation Self-resetting CMOS multiplexer with static output driver
JP2771464B2 (en) * 1994-09-29 1998-07-02 日本電気アイシーマイコンシステム株式会社 Digital PLL circuit
US5644604A (en) 1994-11-14 1997-07-01 Hal Computer Systems, Inc. Digital phase selector system and method
JPH08321827A (en) 1995-03-20 1996-12-03 Fujitsu Ltd Data identification device and optical receiver using the device
EP0783797B1 (en) 1995-07-21 2003-11-05 Koninklijke Philips Electronics N.V. A wireless digital communication device, and a pulse shaping network
US6400735B1 (en) * 1998-06-22 2002-06-04 Xilinx, Inc. Glitchless delay line using gray code multiplexer
US6289068B1 (en) * 1998-06-22 2001-09-11 Xilinx, Inc. Delay lock loop with clock phase shifter
US6229344B1 (en) 1999-03-09 2001-05-08 Vitesse Semiconductor Corp. Phase selection circuit

Also Published As

Publication number Publication date
WO2002039585A2 (en) 2002-05-16
US20020056854A1 (en) 2002-05-16
WO2002039585A3 (en) 2002-12-05
US6621312B2 (en) 2003-09-16

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