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AU2002221394A1 - Method and apparatus for reducing latency in a memory system - Google Patents

Method and apparatus for reducing latency in a memory system

Info

Publication number
AU2002221394A1
AU2002221394A1 AU2002221394A AU2139402A AU2002221394A1 AU 2002221394 A1 AU2002221394 A1 AU 2002221394A1 AU 2002221394 A AU2002221394 A AU 2002221394A AU 2139402 A AU2139402 A AU 2139402A AU 2002221394 A1 AU2002221394 A1 AU 2002221394A1
Authority
AU
Australia
Prior art keywords
memory system
reducing latency
latency
reducing
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
AU2002221394A
Inventor
Nagi Nassief Mekhiel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mosaid Technologies Inc
Original Assignee
Mosaid Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CA2327134A external-priority patent/CA2327134C/en
Application filed by Mosaid Technologies Inc filed Critical Mosaid Technologies Inc
Publication of AU2002221394A1 publication Critical patent/AU2002221394A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0884—Parallel mode, e.g. in parallel with main memory or CPU

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AU2002221394A 2000-11-30 2001-11-28 Method and apparatus for reducing latency in a memory system Withdrawn AU2002221394A1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CA2327134A CA2327134C (en) 2000-11-30 2000-11-30 Method and apparatus for reducing latency in a memory system
CA2327134 2000-11-30
US09/725,461 US6587920B2 (en) 2000-11-30 2000-11-30 Method and apparatus for reducing latency in a memory system
PCT/CA2001/001686 WO2002044904A2 (en) 2000-11-30 2001-11-28 Method and apparatus for reducing latency in a memory system

Publications (1)

Publication Number Publication Date
AU2002221394A1 true AU2002221394A1 (en) 2002-06-11

Family

ID=25682262

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002221394A Withdrawn AU2002221394A1 (en) 2000-11-30 2001-11-28 Method and apparatus for reducing latency in a memory system

Country Status (3)

Country Link
US (1) US6587920B2 (en)
AU (1) AU2002221394A1 (en)
WO (1) WO2002044904A2 (en)

Families Citing this family (16)

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Publication number Priority date Publication date Assignee Title
US6892279B2 (en) * 2000-11-30 2005-05-10 Mosaid Technologies Incorporated Method and apparatus for accelerating retrieval of data from a memory system with cache by reducing latency
US20020099910A1 (en) * 2001-01-23 2002-07-25 Shah Emanuel E. High speed low power cacheless computer system
US6804750B2 (en) * 2002-01-22 2004-10-12 Micron Technology, Inc. Technique for reducing memory latency during a memory request
US6769047B2 (en) * 2002-03-21 2004-07-27 Intel Corporation Method and system for maximizing DRAM memory bandwidth through storing memory bank indexes in associated buffers
JP4208541B2 (en) * 2002-09-30 2009-01-14 キヤノン株式会社 Memory control device
JP3800164B2 (en) * 2002-10-18 2006-07-26 ソニー株式会社 Information processing device, information storage device, information processing method, and information processing program
JP4934267B2 (en) * 2003-10-17 2012-05-16 パナソニック株式会社 Compiler device
JP4656862B2 (en) 2004-05-28 2011-03-23 ルネサスエレクトロニクス株式会社 Semiconductor device
US7941585B2 (en) * 2004-09-10 2011-05-10 Cavium Networks, Inc. Local scratchpad and data caching system
US7594081B2 (en) 2004-09-10 2009-09-22 Cavium Networks, Inc. Direct access to low-latency memory
US20060056234A1 (en) * 2004-09-10 2006-03-16 Lowrey Tyler A Using a phase change memory as a shadow RAM
EP1794979B1 (en) 2004-09-10 2017-04-12 Cavium, Inc. Selective replication of data structure
US7571188B1 (en) * 2004-09-23 2009-08-04 Sun Microsystems, Inc. Cache abstraction for modeling database performance
US20080133864A1 (en) * 2006-12-01 2008-06-05 Jonathan Randall Hinkle Apparatus, system, and method for caching fully buffered memory
DE102009022207B4 (en) 2009-05-20 2015-06-18 Institut für Rundfunktechnik GmbH Peer-to-peer transmission system for data streams
US10783083B2 (en) 2018-02-12 2020-09-22 Stmicroelectronics (Beijing) Research & Development Co. Ltd Cache management device, system and method

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US5226147A (en) * 1987-11-06 1993-07-06 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device for simple cache system
US5233702A (en) 1989-08-07 1993-08-03 International Business Machines Corporation Cache miss facility with stored sequences for data fetching
JP2777247B2 (en) * 1990-01-16 1998-07-16 三菱電機株式会社 Semiconductor storage device and cache system
US5261066A (en) 1990-03-27 1993-11-09 Digital Equipment Corporation Data processing system and method with small fully-associative cache and prefetch buffers
US5488709A (en) 1990-06-27 1996-01-30 Mos Electronics, Corp. Cache including decoupling register circuits
JPH04233642A (en) * 1990-07-27 1992-08-21 Dell Usa Corp Processor which performs memory access in parallel with cache access and method used therrfor
JP3599334B2 (en) * 1991-08-16 2004-12-08 マルティチップ テクノロジー， インコーポレイテッド High performance dynamic memory system
DE69324508T2 (en) 1992-01-22 1999-12-23 Enhanced Memory Systems, Inc. DRAM with integrated registers
JP2775549B2 (en) 1992-05-08 1998-07-16 三菱電機株式会社 Associative memory cell and associative memory circuit
US5640531A (en) 1993-06-22 1997-06-17 Unisys Corporation Enhanced computer operational system using auxiliary mini-cache for enhancement to general cache
TW358907B (en) 1994-11-22 1999-05-21 Monolithic System Tech Inc A computer system and a method of using a DRAM array as a next level cache memory
JPH08335390A (en) * 1995-06-08 1996-12-17 Mitsubishi Electric Corp Dynamic semiconductor memory
US5655105A (en) 1995-06-30 1997-08-05 Micron Technology, Inc. Method and apparatus for multiple latency synchronous pipelined dynamic random access memory
US5710905A (en) 1995-12-21 1998-01-20 Cypress Semiconductor Corp. Cache controller for a non-symetric cache system
US5875451A (en) 1996-03-14 1999-02-23 Enhanced Memory Systems, Inc. Computer hybrid memory including DRAM and EDRAM memory components, with secondary cache in EDRAM for DRAM
JP3429948B2 (en) 1996-04-10 2003-07-28 株式会社日立製作所 Controller for embedded CPU
US5778435A (en) 1996-05-30 1998-07-07 Lucent Technologies, Inc. History-based prefetch cache including a time queue
US5900011A (en) 1996-07-01 1999-05-04 Sun Microsystems, Inc. Integrated processor/memory device with victim data cache
US6167486A (en) 1996-11-18 2000-12-26 Nec Electronics, Inc. Parallel access virtual channel memory system with cacheable channels
US6065099A (en) 1997-08-20 2000-05-16 Cypress Semiconductor Corp. System and method for updating the data stored in a cache memory attached to an input/output system
JP3092558B2 (en) * 1997-09-16 2000-09-25 日本電気株式会社 Semiconductor integrated circuit device
US6122714A (en) 1997-10-24 2000-09-19 Compaq Computer Corp. Order supporting mechanisms for use in a switch-based multi-processor system
US6279082B1 (en) 1998-10-14 2001-08-21 Telefonaktiebolaget Lm Ericsson (Publ) System and method for efficient use of cache to improve access to memory of page type

Also Published As

Publication number Publication date
US6587920B2 (en) 2003-07-01
US20020095559A1 (en) 2002-07-18
WO2002044904A2 (en) 2002-06-06
WO2002044904A3 (en) 2003-01-03

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