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ATE223084T1 - Signalverarbeitungssystem und -verfahren - Google Patents

Signalverarbeitungssystem und -verfahren

Info

Publication number
ATE223084T1
ATE223084T1 AT99108349T AT99108349T ATE223084T1 AT E223084 T1 ATE223084 T1 AT E223084T1 AT 99108349 T AT99108349 T AT 99108349T AT 99108349 T AT99108349 T AT 99108349T AT E223084 T1 ATE223084 T1 AT E223084T1
Authority
AT
Austria
Prior art keywords
data
time period
cycle time
output
processing system
Prior art date
Application number
AT99108349T
Other languages
English (en)
Inventor
Ralf Berninger
Original Assignee
Mitsubishi Electric Europ B V
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Europ B V filed Critical Mitsubishi Electric Europ B V
Application granted granted Critical
Publication of ATE223084T1 publication Critical patent/ATE223084T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Communication Control (AREA)
  • Image Processing (AREA)
AT99108349T 1999-04-28 1999-04-28 Signalverarbeitungssystem und -verfahren ATE223084T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP99108349A EP1049024B1 (de) 1999-04-28 1999-04-28 Signalverarbeitungssystem und -verfahren

Publications (1)

Publication Number Publication Date
ATE223084T1 true ATE223084T1 (de) 2002-09-15

Family

ID=8238066

Family Applications (1)

Application Number Title Priority Date Filing Date
AT99108349T ATE223084T1 (de) 1999-04-28 1999-04-28 Signalverarbeitungssystem und -verfahren

Country Status (3)

Country Link
EP (1) EP1049024B1 (de)
AT (1) ATE223084T1 (de)
DE (1) DE69902628T2 (de)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4079456A (en) * 1977-01-24 1978-03-14 Rca Corporation Output buffer synchronizing circuit having selectively variable delay means
US4638451A (en) * 1983-05-03 1987-01-20 Texas Instruments Incorporated Microprocessor system with programmable interface
JPH0683578A (ja) * 1992-03-13 1994-03-25 Internatl Business Mach Corp <Ibm> 処理システム、及びデータスループット制御方法
US5752073A (en) * 1993-01-06 1998-05-12 Cagent Technologies, Inc. Digital signal processor architecture

Also Published As

Publication number Publication date
EP1049024B1 (de) 2002-08-28
EP1049024A1 (de) 2000-11-02
DE69902628T2 (de) 2003-04-03
DE69902628D1 (de) 2002-10-02

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Legal Events

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