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ATE148242T1 - Priorisierung von mikroprozessoren in multiprozessorrechnersystemen - Google Patents

Priorisierung von mikroprozessoren in multiprozessorrechnersystemen

Info

Publication number
ATE148242T1
ATE148242T1 AT93924899T AT93924899T ATE148242T1 AT E148242 T1 ATE148242 T1 AT E148242T1 AT 93924899 T AT93924899 T AT 93924899T AT 93924899 T AT93924899 T AT 93924899T AT E148242 T1 ATE148242 T1 AT E148242T1
Authority
AT
Austria
Prior art keywords
bus
priority
bus master
host bus
host
Prior art date
Application number
AT93924899T
Other languages
English (en)
Inventor
Roger E Tipley
Michael Moriarty
Mark Taylor
Original Assignee
Compaq Computer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compaq Computer Corp filed Critical Compaq Computer Corp
Application granted granted Critical
Publication of ATE148242T1 publication Critical patent/ATE148242T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)
  • Bus Control (AREA)
  • Exchange Systems With Centralized Control (AREA)
AT93924899T 1992-10-02 1993-09-24 Priorisierung von mikroprozessoren in multiprozessorrechnersystemen ATE148242T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/955,499 US5535395A (en) 1992-10-02 1992-10-02 Prioritization of microprocessors in multiprocessor computer systems

Publications (1)

Publication Number Publication Date
ATE148242T1 true ATE148242T1 (de) 1997-02-15

Family

ID=25496899

Family Applications (1)

Application Number Title Priority Date Filing Date
AT93924899T ATE148242T1 (de) 1992-10-02 1993-09-24 Priorisierung von mikroprozessoren in multiprozessorrechnersystemen

Country Status (7)

Country Link
US (1) US5535395A (de)
EP (1) EP0664031B1 (de)
AT (1) ATE148242T1 (de)
AU (1) AU5440894A (de)
CA (1) CA2145316A1 (de)
DE (1) DE69307717T2 (de)
WO (1) WO1994008301A1 (de)

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US5872941A (en) * 1996-06-05 1999-02-16 Compaq Computer Corp. Providing data from a bridge to a requesting device while the bridge is receiving the data
US5903906A (en) * 1996-06-05 1999-05-11 Compaq Computer Corporation Receiving a write request that allows less than one cache line of data to be written and issuing a subsequent write request that requires at least one cache line of data to be written
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US6021480A (en) * 1996-06-05 2000-02-01 Compaq Computer Corporation Aligning a memory read request with a cache line boundary when the request is for data beginning at a location in the middle of the cache line
US6075929A (en) * 1996-06-05 2000-06-13 Compaq Computer Corporation Prefetching data in response to a read transaction for which the requesting device relinquishes control of the data bus while awaiting data requested in the transaction
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US6073199A (en) * 1997-10-06 2000-06-06 Cisco Technology, Inc. History-based bus arbitration with hidden re-arbitration during wait cycles
US6496881B1 (en) 1999-03-11 2002-12-17 Compaq Information Technologies Group, L.P. Method and apparatus for disabling a processor in a multiprocessor computer
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US6499090B1 (en) 1999-12-28 2002-12-24 Intel Corporation Prioritized bus request scheduling mechanism for processing devices
EP1164493B1 (de) 2000-06-16 2005-11-30 STMicroelectronics S.r.l. Arbitrierungsverfahren mit variablen Prioritäten, zum Beispiel für Verbindungsbussen, und entsprechendes System
US20030131201A1 (en) * 2000-12-29 2003-07-10 Manoj Khare Mechanism for efficiently supporting the full MESI (modified, exclusive, shared, invalid) protocol in a cache coherent multi-node shared memory system
US7389332B1 (en) 2001-09-07 2008-06-17 Cisco Technology, Inc. Method and apparatus for supporting communications between nodes operating in a master-slave configuration
US7421478B1 (en) 2002-03-07 2008-09-02 Cisco Technology, Inc. Method and apparatus for exchanging heartbeat messages and configuration information between nodes operating in a master-slave configuration
US7200610B1 (en) 2002-04-22 2007-04-03 Cisco Technology, Inc. System and method for configuring fibre-channel devices
US7165258B1 (en) * 2002-04-22 2007-01-16 Cisco Technology, Inc. SCSI-based storage area network having a SCSI router that routes traffic between SCSI and IP networks
US7415535B1 (en) * 2002-04-22 2008-08-19 Cisco Technology, Inc. Virtual MAC address system and method
US7188194B1 (en) * 2002-04-22 2007-03-06 Cisco Technology, Inc. Session-based target/LUN mapping for a storage area network and associated method
US7587465B1 (en) * 2002-04-22 2009-09-08 Cisco Technology, Inc. Method and apparatus for configuring nodes as masters or slaves
US7433952B1 (en) 2002-04-22 2008-10-07 Cisco Technology, Inc. System and method for interconnecting a storage area network
US7240098B1 (en) 2002-05-09 2007-07-03 Cisco Technology, Inc. System, method, and software for a virtual host bus adapter in a storage-area network
US7831736B1 (en) 2003-02-27 2010-11-09 Cisco Technology, Inc. System and method for supporting VLANs in an iSCSI
US7295572B1 (en) 2003-03-26 2007-11-13 Cisco Technology, Inc. Storage router and method for routing IP datagrams between data path processors using a fibre channel switch
US7433300B1 (en) 2003-03-28 2008-10-07 Cisco Technology, Inc. Synchronization of configuration data in storage-area networks
US6976132B2 (en) * 2003-03-28 2005-12-13 International Business Machines Corporation Reducing latency of a snoop tenure
US7904599B1 (en) 2003-03-28 2011-03-08 Cisco Technology, Inc. Synchronization and auditing of zone configuration data in storage-area networks
US7526527B1 (en) 2003-03-31 2009-04-28 Cisco Technology, Inc. Storage area network interconnect server
US7366854B2 (en) * 2003-05-08 2008-04-29 Hewlett-Packard Development Company, L.P. Systems and methods for scheduling memory requests utilizing multi-level arbitration
US7451208B1 (en) 2003-06-28 2008-11-11 Cisco Technology, Inc. Systems and methods for network address failover
JP4421459B2 (ja) * 2004-11-30 2010-02-24 株式会社東芝 無線通信装置及び無線通信方法
US7392353B2 (en) * 2004-12-03 2008-06-24 International Business Machines Corporation Prioritization of out-of-order data transfers on shared data bus
US20090138683A1 (en) * 2007-11-28 2009-05-28 Capps Jr Louis B Dynamic instruction execution using distributed transaction priority registers
US8886918B2 (en) * 2007-11-28 2014-11-11 International Business Machines Corporation Dynamic instruction execution based on transaction priority tagging
US8706936B2 (en) 2011-11-14 2014-04-22 Arm Limited Integrated circuit having a bus network, and method for the integrated circuit

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JPH0810445B2 (ja) * 1990-09-21 1996-01-31 インターナショナル・ビジネス・マシーンズ・コーポレイション 動的バス調停方法及び装置
US5148112A (en) * 1991-06-28 1992-09-15 Digital Equipment Corporation Efficient arbiter
US5265223A (en) * 1991-08-07 1993-11-23 Hewlett-Packard Company Preservation of priority in computer bus arbitration

Also Published As

Publication number Publication date
AU5440894A (en) 1994-04-26
DE69307717D1 (de) 1997-03-06
DE69307717T2 (de) 1997-07-17
WO1994008301A1 (en) 1994-04-14
US5535395A (en) 1996-07-09
EP0664031B1 (de) 1997-01-22
CA2145316A1 (en) 1994-04-14
EP0664031A1 (de) 1995-07-26

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties