NL8702484A - DEVICES COUPLED BY A LOAD. - Google Patents

Description

A'v VO * VO 9354

Devices coupled by a load.

The invention relates to load coupled devices and more particularly it can be applied to serial operating registers.

The use of charge-coupled devices has been described by W.S. Boyle and G.D. Smith in an article entitled "Charge Coupled Semiconductor Devices," Bell System Technical Journal, April 1970, biz. 5S7 and by G.F. Amelio, M.F. Tompsett, G.E. Smith in an article "Experimental Verification of the Charge Coupled Device Concept" biz. 593 from the same magazine and in an article by M.F. Tompsett, 10 G.F. Amelio and G.E. Smith "Charge Coupled 8-Bit Shift Register",

Applied Physics Letters, Vol. 17, 3, p. 111, August 1970 in which articles are discussed in charge coupled semiconductor devices. Charges are stored in potential wells created on the surface of a semiconductor and voltages 15 are used to displace the charges along this surface. More specifically, these charges are minority carriers stored at the silicon (Si) silicon dioxide (SiO 2) interfaces of MOS capacitors. They are transferred from one capacitor to another capacitor on the same substrate by manipulating the voltages across the capacitors.

The invention can be applied in a circuit comprising a substrate of a semiconductor material of one conductivity type.

According to a preferred embodiment of the invention, the circuit further includes a source of charge carriers and includes a region of a different conductivity type in contact with the substrate, and members located close to the source to form a potential well in the substrate, into which carriers of the source may flow. Furthermore, the circuit includes means coupled to the source to control the flow of charge carriers from the source to the potential well, and means to bias the source in reverse to the substrate.

According to another preferred embodiment of the invention, the circuit comprises means which respond to a single pulse for "A".

w '4. ..' *% • t * -2- creating a potential well in the substrate, which is considerably deeper on one edge of the well than on the opposite edge of the well.

According to another embodiment of the invention, the circuit comprises a number of rows of a relatively thin insulating layer formed on the substrate, each such row defining a length of the substrate along which charges are to be propagated. Furthermore, the circuit is provided with a number of electrode members, which lie next to each other along the length of the row. Each such member establishes an asymmetric potential source in the substrate which is considerably deeper in the portion of the well opposite the desired direction in which the signal propagates along the length of its row than the portion. from the well facing away from the desired direction in which the signal propagates.

Furthermore, the circuit is provided with means for supplying one phase of a two phase shear voltage to alternating electrode members of each row and supplying the second phase of shear voltage to the other electrode members of each row.

According to another preferred embodiment of the invention 20, the circuit includes first and second spaced regions which contact the substrate, both regions being formed of a conductivity type semiconductor material different from that of the substrate, means for holding the first region at a potential such that it is available as an acceptor of minority charge carriers and a control electrode which is spaced from the substrate and extends between the regions to flow the minority charge carriers from control the second to the first area. Furthermore, the circuit includes means coupled to the substrate to place a minority charge carrier on the portion of the substrate on which the second region is located, while an output terminal is connected to the second region to which a signal can be scanned, and means for supplying a signal to the control electrode of a sensor to pass a charge contained in the area to the first area, after which the second area is reset to a reference voltage level.

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According to another preferred embodiment of the invention, the circuit is provided with two charge-coupled debt registers, means for simultaneously shifting charge signals through one of the registers and shifting complements of these charge signals through the other of the registers. Furthermore, the circuit is provided with a differential signal detector, which is coupled to one input terminal with a stage of one of the registers and to the other input terminal with a corresponding stage from the other of the shift registers.

According to another preferred embodiment of the invention, the circuit comprises first and second regions in the substrate which are relatively shortly spaced, which are of opposite conductivity type to the substrate, members coupled to the second region to establish a conduction path in the substrate during the one time interval which extends from the second region to a reference voltage source (V +) to reset the second region to a reference voltage source. Furthermore, an electrode member is coupled to the second region and to the portion of the substrate extending between the first and second regions to reset the first region to a voltage level during a second time interval.

According to another embodiment of the invention, a charge can be propagated at a high speed from a voltage well in a substrate below one electrode to an area of the substrate below an adjacent electrode. The electrodes are spaced apart from each other, which is no greater than the distance of the electrodes from the substrate, and a depletion depth is established in the substrate below the adjacent electrode, which can be compared with the electrode width.

The invention will be further described with reference to the drawings. Herein: fig. 1 shows schematically, partly in block form, and partly in section, a part of the system in which the invention is applied; Figures 2 and 3 show block diagrams of various systems in which the invention has been applied; v i * * »-4-? & FIG. 4 is a sectional view showing the input end of a shift register according to an embodiment of the invention; FIG. 5 waveforms contained in the circuit of FIG. 4; 6a-6e potential wells formed in response to 5 different voltages applied to the circuit of FIG. 4; Fig. 7 schematically shows in cross section another form of the entrance end of the system in which the invention is applied; FIG. 8 waveforms used during the operation of the circuit of FIG. 7; FIG. 9 is a more realistic sectional view through a portion of a shift register according to an embodiment of the invention; Fig. 10 is a schematic sectional view through another embodiment of a shift register in which the invention is applied; Fig. 11 is a more realistic cross-sectional view of the shape of the invention shown in Fig. 10; fig. 12 shows a cross-sectional view of another form of a shift register in which the invention is applied; Fig. 13 shows both waveforms and voltage wells and this figure is used in explaining the operation of the circuitry of Figs. 9-12; Fig. 14 is a top view and partly schematic view 25 'of a two-dimensional shift register system according to another embodiment of the invention; fig. 15 and 16 cross-sections according to the lines XV-XV and XVI-XVI of fig. 14; fig. 17 a top view and partly schematic view of another form of a two-dimensional shift register system, in which the invention Figures 18 and 19 are cross-sectional views along lines XVIII-XVIII and XIX-XIX of Figure 17, Figure 20 shows a top view of another form of a shift register in which the invention is applied; Fig. 21 is a top plan view of a portion of a multi-channel shift register in which the invention has been applied, Fig. 22 is a sectional view taken on the line XXII - XXII of f Fig. 21; Fig. 23 is a top plan view of part of another form of shift register in which the invention is applied; FIG. 24 is a section along line XXIV - XXIV of FIG. 23; Fig. 25 is a top plan view of a portion of another form of a shift register in which the invention is applied; 26, 27 and 28 are sectional views along lines XXVI - XXVI, XXVII - XXVII and XXVIII - XXVIII, respectively, of Fig. 25; Fig. 29 is a schematic sectional view through a form of a coupling structure, in which the invention has been applied to a three-phase slide fermenter system, ie a construction form around the output end of the one register with the input end of the second register. to link; Figure 30 shows the charge propagation in the circuit of Figure 29; FIG. 31 waveforms used in the circuit of FIG. 25; Fig. 32 is a schematic sectional view showing another form of a coupling structure in which the invention has been applied; now for a four phase shift register system; FIG. 33 waveforms used during the operation of the circuit of FIG. 32; Fig. 34 is a cross section of another form of a coupling chain, in which the invention is applied; FIG. 35 waveforms used during the operation of the circuit of FIG. 34; FIG. 36 helps to explain in more detail the operation of the circuit shown in FIG. 34; Fig. 37 more realistically illustrates another form of a link circuit employing the invention, now a four phase shift system circuit; Figures 38 and 39 are sectional views showing changes in the input circuit of the receiving register of Figure 37; Fig. 40 shows a cross-section of another form of a coupling circuit, in which the invention is applied, which circuit is fed by a two-phase voltage source; Fig. 41 waveforms used during the operation of the circuit of Fig. 40; Fig. 42 is a top view showing how the circuit of Fig. 40 can be designed; Fig. 43 is a sectional view through another form of a link circuit fed by a two phase power supply; FIG. 44 waveforms used during the operation of the circuit of FIG. 43; FIG. 45 is a top view showing how the circuit of FIG. 43 can be designed; Fig. 46 is a block shape and schematic representation of another form of a coupling chain in which the invention is applied; Fig. 47 is a block diagram showing a circuit circuit coupling circuit as shown in Fig. 21; Fig. 48 is a cross-sectional and schematic representation of the actual construction of the circuit of Fig. 47; Fig. 49 is a schematic representation of another form of the circuit of Fig. 47; Fig. 50 is a cross-sectional and schematic representation of another form of a coupling chain in which the invention is applied; Fig. 51 is a schematic representation showing both a circuit for the. 25 shows coupling the output end of one register to the input end of the other register as input-output circuits for the system; 52a-h help to explain in more detail a method of manufacturing the above-described systems.

Before the invention will be described in detail, a generalized explanation of a complete system is given first. In this explanation, a serial memory consisting of a plurality of shift registers which can act as a circulating memory is used as an example. This discussion is followed by a more detailed discussion of (1) the input end of the system, (2) the center of the system, (3) the coupling between the system's shift registers, (4 ) the output end of the system, (5) general considerations regarding the implementation of the load-coupled shift chains, (6) considerations regarding the very fast operation and (7) manufacturing methods.

In order to facilitate the illustration, the common substrate 10 of Fig. 1 is shown in two parts. The substrate is formed from a semiconductor, for example, from n-type silicon. Other alternatives are possible, which will be discussed later. A thin film insulating material, such as a film formed from silicon dioxide (SiO2), is applied to the parts of the surface of the semiconductor substrate under which the charge signals travel. The actual thickness can be from 500 - 2000 &. The. other areas of the silicon surface (not shown) may be covered with a layer of SiO 2 with a thickness of perhaps 10,000 A or 15 thicker.

A number of conductive plates or electrodes 14-0, 14-1, 14-2 ...

14- (n + 1) formed of a metal, for example aluminum, are placed on the silicon dioxide layer. A source of charge carriers is disposed in the substrate 10 and close to the control plate or electrode 14-0, and another member provided with a charge carrier collector is located in the substrate close to the control plate 14- (n + 1). The source and members are only shown as rectangles in Figure 1.

Their actual construction is shown in the following drawings and will be discussed later. The entire construction acts as a shift register in a manner which will be briefly discussed.

A second shift register equal to the first is placed near the first shift register. It contains a minority carrier source S ^ / a number of conductive plates 16-0, 16-1, 15-2 etc., which are placed on the silicon dioxide surface 12 and a member C ^, which can have the same construction and function as the member C ^, which is located near the control plate 16- (n + 1).

The output terminal 18 of the first shift register is connected to the input circuit of the second shift register by a signal regenerating circuit. This signal regenerating circuit may contain a single connection between the two registers represented by the broken line 171 or may alternatively be an external circuit represented by the block 19 between the two registers. registers is linked. The output line 18-1 of the second shift register may be coupled to the input terminal of the next shift register (not shown). This coupling can be accomplished in the same manner as that previously discussed. Also, the output line 18-1 can be coupled via a regenerating circuit to the charge carrier source to obtain a circulating memory. As a third alternative or additionally, the output line 18-1 may be the output terminal of the system. These various alternatives are briefly discussed with reference to Figures 2 and 3.

The information supplied to the serial memory of FIG. 1 can be propagated from stage to stage by a multiple supply a 3, 4 or higher phase signal, but preferably it is a 2 phase voltage source, since this allows the construction of the memory 15 can be more compact and faster under certain circumstances. By nature, however, using a 2-phase voltage source does not provide one-way signal propagation.

Furthermore, the device of Fig. 1 includes several DC voltage biasing means. These are not shown in Figure 1, but are shown in later Figures and their function will be discussed with reference to these Figures.

Before discussing the operation of the device of FIG. 1, it is recommended to consider the general theory of operation of the cargo coupled devices. When a negative 2.5 voltage pulse is applied to a plate or electrode, such as 14-2, a so-called deep depletion region is formed in the portion of the n-type substrate located immediately below this electrode. In other words, the supplied negative voltage pulse majority carriers, in the case of an n-type substrate, eject electrons from the surface of the substrate directly below the electrode, such as 14-2. This creates a voltage well on the n-type silicon surface corresponding to the induced depletion region. The depth of the potential well is proportional to the square of the depth of the depletion region. The higher the specific resistance of the substrate, the greater the depletion depth for a voltage pulse of a given amplitude. The thicker the layer of silicon dioxide below the electrode, the shallower the depletion depth for a given voltage amplitude supplied to the electrode.

Any voltage well formed on the surface of the silicon substrate will tend to collect minority carriers (in this case, holes). If available from no other place, they will come from the substrate itself. In this case, the supports are thermally generated and are mainly supplied by a surface generation process. They form an inversion layer on the surface of the silicon substrate in which the voltage well is formed in a time of the order of one second. In other words, the potential well established under the electrode in response to a negative voltage pulse is "naturally" filled with minority carriers.

The magnitude of the charge, which can be collected in such a potential well, is equal to the charge required to replace the number of 15 "exposed" immovable ions (ions, which previously gave up charge) in the deep depletion region plus the charge. additional charge collected in response to the capacitance between the substrate and the electrode.

In the preferred embodiment, shown in Fig. 1, the thermal generation of charge carriers does not depend on the charge input into a potential well as a signal. Instead, a source is used, which source can have a heavily doped p + region located in the substrate, as will be discussed in more detail later. In response to a voltage V applied to the control plate 14-0, which voltage is more negative than the source potential and a negative voltage applied to the electrode 14-1, the leading edge of which can overlap the trailing edge of the voltage -V (or simply by applying a voltage pulse to the electrode 14-0, which in time coincides with the voltage applied to the electrode 14-1), an inversion layer is formed between the source and the potential well, which is created under the electrode 14 -1. Charge carriers move from the source through this inversion layer or "channel" established under the electrode 14-0 into the potential well below the electrode 14-1 very quickly in a time of the order of one to 35 tens of nanoseconds with an appropriate implementation of the circuit.

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The passage of this charge can be controlled via the control plate 14-0 and alternatively, in addition, the source itself can be pulsed, as will be discussed briefly.

The storage of the charge under an electrode or plate may represent the presence of a binary digit (bit) such as "1". The absence of charge carriers in the area of a substrate under an electrode may represent the storage of the bit "0". Other alternatives are also possible and will be briefly described later.

In the device of FIG. 1, charges are transferred from one potential well to the next, ie, from the area of the substrate under one electrode to the area of the substrate under the next adjacent electrode, by multiple phase voltages. In other words, the transfer takes place under the influence of an electric field, which can be called a running field. Another mechanism, which may be involved in the transfer of charge from "capacitor" to "capacitor" (where a capacitor can be considered to be an electrode, such as 14-1, the region of the n-type semiconductor substrate below this electrode and the silicon dioxide layer separating the two) is diffusion, which in the case of charge-coupled device normally also leads to an induced running field As will be discussed briefly below, to work very quickly the charge-coupled chain designed to operate under the influence of the running field instead of diffusion.

When a charge reaches the last electrode 14-n of the shift register, it can be scanned and the scanned signal used is used to control the passage of the charge to the input stages to the next register. The transfer involves a control plate 14- (n + 1) and the construction in the member C1.

The function of the member is to sense the presence of charge, which is brought about by a voltage level, which can regenerate the signal in the second shift register and displace the charge signal from the first shift register. For example, a floating connection may be used to couple a signal to the control plate 16-0, to enable or disable the transfer of charge to the region '/ hi.

-11- under the electrode 16-1 when a corresponding negative voltage pulse is applied to the plate 16-1 from the source 20. This connection is represented by the broken line 171 or by 18, 19. In the former case, the connection is such that the complement 5 of the bit present at 14-n is transferred to the area below 16-1. In the latter case, either the bit or its complement can be transferred. All this will be discussed in more detail later.

Fig. 2 schematically shows a form which a system of shift registers can take. The shift registers are connected to each other via signal regenerating chains, so that one large ring is obtained. These are useful in many data processing applications, such as large capacity serial memories and large circulating memories of this type can also be used as refresh memories for cathode ray tube displays; in communication applications and in video processing applications. The circuit of Fig. 2 is also schematically shown as an input-output circuit 20 / which includes means for receiving new information and means for supplying information to be output. Chain specialties are shown and will be discussed later.

The system of Fig. 3 is arranged in different ways.

Kier each pair of shift registers forms a ring, which, depending on the size of the shift register, can store, for example, 32 - 256 bits. The signal regenerating and control circuits 21 may be provided with decoders which address the signals on address lines and the control units which respond to signals present on the control lines.

The chains can be of the same type as used in a memory.

They can be used to allow reading of the bits stored in a loop. As an alternative, the various registers connected as a ring can be considered to be analogous to tracks of a drum memory and reading the bits in parallel. It should be noted that, although not explicitly shown here, in FIG. 2, the multiple phase voltage source is included.

Although not specifically mentioned in the following text, the charge-coupled structures and chains to be described can also be used in random access, charge-storage, memory and self-scanned photo-scanning systems. In the latter application, the light signal (instead of an electrical impulse) can be used as the charge carrier source for the charge coupled shift register. In the two-phase constructions which will be described in detail later, the light input signal can be applied to the polysilicon electrodes and the system can function as a self-scanned photo-scanning system. In these applications, if an analog output signal is desired, it can be obtained from a common drain region, which is fed by parallel charge-coupled 1 (X peeled shift registers, which shift the signal in one direction only. A simple choice of the desired row in the array is possible if one of the multiple phase voltages is supplied unconditionally, while the other of these voltages is supplied only to the selected row This one phase is varied between a DC voltage level, forming a shallow potential well and a voltage, whereby a deep well is formed, so that the electrodes receiving this one phase always have a potential well which fluctuates between two levels. The carriers generated by light are thus collected at these electrodes and, if desired, they can be stored carriers in a row) are shifted to an output terminal by the addition to the row of the other phase (s).

Entry end of the system

In the prior art, the charge carrier source (S1 in FIG. 1) for the charge coupled shift register was described as 25; a control electrode PN junction (for an n-type substrate, a p + region), which operated with the substrate potential. During the operation of the shift register, the signal charge of this p + region was transferred to the first potential well by applying a negative pulse (corresponding to V of Fig. 1) to the control electrode, such as 14-0 in Fig. 1. controlling the magnitude of the charge to be input into the first potential well, it was necessary to accurately control the magnitude and duration of this applied voltage.

In charge-coupled devices, during the propagation of the charge from the source to the potential well hangs under the first storage plate (such as 14-1 in Fig. 1) and later from the area of the substrate under one storage plate to the area of the substrate Under the next plate, the flow velocity of the charge depends on the amount by which the potential well of the next adjacent plate is to be filled. For example, if a charge is present under the plate 14-2 (Fig. 1) and this charge begins to flow in the "empty" depletion region below the plate 14-3, the charge initially flows very quickly. As the charge fills the area under plate 14-3 to an increasing degree, the longer it becomes more difficult to enter additional charges. The reason for this lies in the fact that when the well becomes full, the surface potential of the well becomes closer to that of the substrate (the difference in potential decreases). In addition, it has been found that if an attempt is made to completely fill each well from the previous one, a particular charge tends to remain in the previous well. This residual charge in the case where the next bit to be transferred to the previous well is a 0 (absence of charge) adversely affects the signal-to-noise ratio since it tends to make a stored 0 look like a saved 1. This effect is cumulative and with a large number of stages it becomes quite serious.

One aspect of the preferred embodiment resides in the means for obtaining a desired degree of partial filling of the first potential well (the well below the plate 14-1) substantially independent of the magnitude of the voltage applied to the control electrode 14- 0 (as long as the amplitude of the control pulse V is sufficient

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large). The details of how this is done are given briefly after the construction is described.

Reference is now made to Fig. 4. The charge carrier source consists of a conductive line formed in the n-type silicon substrate. This construction can be made by diffusing a substantial amount of p-type material, such as boron, into a limited area of the substrate. This makes this region of the substrate relatively highly conductive and a good source of positive charge carriers. The n-type silicon substrate is kept at an increased voltage, for example +5 volts. The reason for this is to depletion the surface of the silicon adjacent to the silicon dioxide layer, the surface along which the charge carriers representing the signal are moved during the operation of the register. The purpose of this pretension is -14-

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eliminate signal loss resulting from surface recombinations by making it impossible for the majority carriers (in this example electrons) of the silicon substrate to surface to reset the traps for the minority carriers 5 (in in this case holes), which represent the signal.

In order to achieve the potential well filling control, the source is not tied to the same potential as the substrate, but instead is reverse biased to an extent of, for example, -5 volts relative to ground (-10 volts 10 relative to the substrate). As will be seen briefly, this biasing in the opposite direction, together with the selection of pulses V and φ ^ with an appropriate amplitude and timing, ensures that the potential well established below the first plate 14-1 is only up to predetermined level is filled, which can only be a fraction of the capacity of this potential well.

In the following discussion of the operation of the portion of the system shown in FIG. 4, reference will be made to FIGS. 5 and 6a-6e. The resting potential states, i.e., the states for time tQ of FIG. 5 are as shown in FIG.

20 6a. The well below the source region S ^, which region is at -5 volts, is deeper than the region under plates 14-0 and 14-1, so that the charge carriers remain in S.

When a negative voltage pulse V, such as the pulse having an amplitude of -10 volts, is applied to the plate 14-0, a. inversion layer, 23 in Fig. 6b. This layer extends from the p + region along the surface of the silicon substrate below the control electrode 14-0. This inversion layer or the conduction channel is analogous to the conduction channel which is formed when the driving electrode of a metal oxide semiconductor (MOS) transistor is biased in the forward direction. The condition necessary to form the conduction channel is that the negative voltage applied to the control electrode 14-0 is more negative than the bias voltage at which the source electrode is held by an amount that the n-type threshold voltage V exceeds substrate. This threshold voltage V is the same parameter as the similarly designated parameter in the metal oxide semiconductor transistor technique. The conductivity of the rrta β · "** .. .. x x ΐ ϊ 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 is is is is is is is is is is is is is is is is is is is is is is is is is is is is is is is is is is is is” is is is is is is is is is is is is is is is is is is is is is is is is is is is is waarin waarin waarin waarin waarin, waarin, waarin waarin,,,,,, waarin waarin waarin, waarin,,,,,,, waarin waarin waarin,, waarin waarin, waarin waarin, waarin waarin waarin waarin waarin by waarin waarin is

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The input pulse V must occur simultaneously with the φ pulse, 0 x in order to transfer the charge signal in the first potential well.

5. The following example illustrates the case where the trailing edge of pulse V overlaps the leading edge of pulse φ and the pulse V ein-O i o before the pulse ends.

As shown in Fig. 5, at the time t ^, while the driving voltage V is still present, the leading edge of the negative pulse I φ ^ applied to the first plate 14-1 occurs. This pulse can be more negative than the control pulse and is shown in the present example to have an amplitude of -15 volts. The resulting operation is shown schematically in Fig. 6c. The negative voltage applied to plate 14-1 allows a potential well to enter. the area of the 'sub-15 street below this plate. The minority carriers, in this case positive charges, then flow from the source through the induced conduction channel 23 below the control electrode 14-0 to the potential well below the electrode 14-1. This charge current only continues until the surface potential under the first electrode 14-1 reaches the potential of the source (provided that sufficient time of the order of nanoseconds is allowed for this process).

If the difference between the source voltage and the control voltage V is

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is large (in this example 5 volts are used, but a smaller voltage difference would also be suitable) the first potential well can be filled to the desired level. This desired level can only be a fraction of the capacity of the potential well and, unlike the prior art, can be precisely controlled without requiring precise control either of the duration or the amplitude of the control pulse.

FIG. 6d shows the operation at the time t ^, which falls after the termination of the control pulse V_, but before the termination of the pulse. First, it is noted that when the control electrode 14-0 is at 0 volts, i.e., more positive than the source S ^, the conduction channel has a high impedance. Stated another way, the charge carriers stored in the potential well below the first store 14-1 see a potential hill which prevents their escape back to the source. Therefore, these charges - 16 - remain stored under plate 14-1 until shifted to the next plate 14-2 by the next voltage phase. This will be discussed briefly.

The foregoing description relates to writing 5 and 1 in the first stage of the shift register. To write a 0, no voltage pulse is applied to the control plate 14-0 during the period t ^ - t. The result is that as long as the surface potential under the control electrode is more positive (actually less negative in this example) (by about one volt) than the potential at which the source is maintained, no charge from the source to the first potential well will be transferred. (The one volt value provides a more than sufficient potential barrier to prevent charge transfer through the diffusion process and also provides a safety factor to account for variations in the parameters of the device).

The above described operation is shown in a number of figures. Fig. 6a still represents the quiescent state of the circuit. At a time between a tQ and the situation is still as shown in Fig. 6a. Since the control plate 14-0 is still biased in reverse direction to the source, no inversion region is formed below the plate 14-0. At a time such as t the situation is as shown in Fig. 6e. Although a potential well has been established below the first plate 14-1, no charge carriers can flow from this source into this voltage well due to the fact that the control plate is still at 0 volts. As noted previously, no charge below plate 14-1 represents the storage of a 0.

A second form of an input circuit according to the invention is shown in Fig. 7. The difference between this circuit and the circuit of Fig. 4 consists in that in the circuit of Fig. 7 the source is normally biased in reverse direction ( to -15 volts relative to the substrate, -20 volts to ground in this example), that is, in its quiescent state, the source does not act as a source of minority charge carriers for potential wells with larger surface potentials than the source. After all, such a bias can be the source region as a drain (drain electrode) for the charge wire. /. V -I '.J' 4 i t -17- gers which are present in a potential well. The source can be "turned on" by applying a voltage pulse to the source at an appropriate time, as shown in FIG. 8.

During the operation of the device of Fig. 7, in the absence of an impulse, the impulses and φ ^ transfer a 0 (no charge) to the potential well under the first storage plate 14-1. In the presence of a positive pulse V during the pulses φ. and V, however, a w 1 c 1 is stored under the first plate 14-1.

The timing of the pulses of FIG. 7 shown in FIG. 8 is important. At time tQ, the pulse is applied to the storage plate 14-1. This creates a potential well under the first plate 14-1. Shortly after the start of the pulse φ ^, that is, at the time t, the control pulse V starts. This creates a potential well Xc under the electrode 14-0, which is connected to the potential well 15 under the control electrode 14-1. Since no charges are available yet, no inversion layer or a guide channel is formed yet.

Shortly after this at time t2, the positive pulse is applied to source S1. This pulse can have an amplitude of 10 volts, so that V has a swing from -15 volts to -5 volts. The conditions are now exactly the same as shown in Fig. 6c - a conduction channel is formed from to the potential source under the electrode 14-1 and the positive minority charge carriers flow from the source and partially fill the potential well under the plate 14-1 to the pre known fraction of its capacity. The trailing edges of the pulses occur as shown in Fig. 8, the pulse V terminating before the other c pulses, in order to prevent reverse flow of charge, ie back from the partially filled well below 14 -1 to the source S ^.

An important feature of the circuit of FIG. 7 is that the timing at which charges are input can be precisely controlled by timing pulses V and V with the pulse sequence shown in FIG. 8. control. Generally, the pulse provides the timing, while the source potential determines the level at which the first potential well is filled (or "" "emptied).

In this general case, the timing is such that the entire pulse occurs within both the pulse and the pulse.

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In the embodiments of the input circuits discussed so far, a signal such as V is used as the control signal.

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However, it is easily possible to implement logic on the input signals. For example, the first two plates, designated 14-0 and 14-1 in Figure 4, may be the control plates, which may be designated 14-01 and 14-02. Here, the signals applied to the two control plates can represent two information bits and in this case the two control plates will simulate the AND function. If desired, the first electrode 14-01 can receive a relatively longer signal and the electrode 14-02 can receive a shorter signal, which coincides with the signal supplied to 14-01. Here, one or both signals may represent information or the first signal, i.e. the longer signal, may represent information and the shorter signal may be a timing or strobe pulse.

Alternatively, the two input signals may be the signals and Vc of FIG. 7, this first signal being applied to the source and the second signal to the control electrode 14-0. Here the positive going pulse V can represent 1 and the negative going pulse V can also represent 1 and with this convention the circuit c 20 also performs the AND function.

Generally, in charge coupled circuits, as discussed above, multiple input gate operation can be accomplished by coincidentally applying a number of negative pulses to a corresponding number of drivers and a positive pulse at source S1. An OR function can be realized by using a number of sources, all of which supply a charge input to the first potential well (below electrode 14-1) in parallel. Here, a positive pulse applied to a source electrode coinciding with the unconditionally supplied positive going control pulse V will couple a charge c signal to the first potential well. Other alternatives are also possible.

It is also possible to operate the input circuit such that charges of different sizes represent bits 1 and 0, respectively. Input signals at these two levels can be obtained by using the DC voltage level of the signal supplied to the control electrode 14-0 to generate the 0 at a lower

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w. ...: - j - »fi -19- charge level than the 1 input or by controlling the potential of the source such that the first potential well is filled at a lower level for 0 and at a higher level for 1 or by a combination of these methods.

5 The middle section of the system

The transfer of charge from below an electrode, such as 14-1 (Fig. 4), to below an adjacent electrode, such as 14-2, occurs by applying a negative voltage pulse to the electrode 14-2, while increasing the amplitude of the voltage pulse. reduced.

As a result, while the potential well under the electrode 14-1 is made shallower, the potential well under the electrode 14-2 is made deeper and the charge overflows from the shallow to the deeper well. The use of overlapping clock pulses is common for 2, 3, 4 and higher phase operated charge coupled chains. However, it is noted in passing that non-overlapping clock pulses may be used in connection with the two-phase operation (and also in three- and four-phase operation), if certain conditions are met, as will be briefly discussed.

In an arrangement, as shown in Fig. 1, there is no problem with one-way signal propagation if the source 20 is a three or higher phase source. In these cases, when charge is transferred, for example, from below the electrode 14-2 to below the electrode 14-3 (Fig. 1), no negative voltage pulse is applied to the electrode 14-1. Therefore, the very shallow potential well below the electrode 14-1 (the only such well will be present due to a DC bias voltage between the electrode and the substrate) acts as a barrier to the charge current in the reverse direction, so that only the forward direction for the charge current is available when the source 20 provides three or more phases.

Such a one-way charge current is not present in the case of a two-phase source. In order to obtain a one-way charge current here, special techniques must be used, as discussed below.

One aspect of the preferred embodiment resides in the fact that, according to the invention, special electrode structures have been found, which can be made relatively inexpensive to achieve that the charge flows in one direction with two phase voltages. In general, each electrode does not consist of a single plate, but of two plates which overlap each other. In terms of operation, a device shown in Fig. 9 depends mainly on the geometry of the electrodes and more particularly mainly on the distance of one electrode from two further from the substrate than the other electrode. The second device, schematically shown in Fig. 10 and more realistically shown in Fig. 11, depends mainly on a voltage offset maintained between the two electrodes of each 10 pair. A third alternative is to combine the geometry of Fig. 9 with the stress offset of Fig. 11. An embodiment of the invention is shown in Fig. 12.

In all of the above cases, the construction is such that an asymmetric depletion region is formed below an electrode pair in response to a negative potential (or potentials) supplied thereto. The direction of the asymmetry of the depletion region is such that a charge introduced herein will accumulate at the leading edge of the depletion region, since the potential well at this region is considerably deeper than in the rest of the region.

Reference will now be made to Fig. 9. Each electrode corresponding to 14-1, 14-2, etc. in Fig. 1 consists of two electrodes overlapping each other. One of the electrodes consists of a metal, for example, aluminum and is shown with 26-1, 26-2 etc. and the other electrode of each pair consists of a p + polysilicon region, such as -25 'as shown at 28-1, 28- 2, etc., which is directly electrically connected to the aluminum alloy electrode. The term "polysilicon" refers to a polycrystalline form of silicon. This is obtained by depositing the silicon at an elevated temperature or by depositing amorphous silicon, then heating to 900 ° C or more for ten or more minutes, to change the amorphous structure to a polycrystalline structure.

(The use of polysilicon material is known per se in MOS technology.) The polysilicon electrode of each pair is closer to the n-type silicon substrate than the aluminum electrode of this pair. Each aluminum electrode, such as 26-2, overlaps the leading edge of the associated polysilicon electrode 28-2 and also overlaps the trailing edge of the polysilicon electrode 28-1 of the previous pair.

The overlapping polysilicon-aluminum electrode construction allows a very short distance between each aluminum electrode and the two poly-silicon electrodes it overlaps. However, typical dimensions are given later, although it may be noted here that such a distance may be 1,000 Å or less. In addition, the manufacturing techniques used to make the structure, which will be discussed in detail later, allow for self alignment of the aluminum electrodes with respect to the poly-1Q silicon electrodes. The only critical alignment has to do with the etching of the aluminum electrodes above the polysilicon electrodes. The manufacturing technique also allows the two different thicknesses of the channel oxide (a and b in Fig. 9) to be easily obtained.

During the operation of the circuit of FIG. 9, for example, when a negative voltage pulse is applied to the electrode pair 26-2, 28-2, the depletion region created is asymmetrical, as shown by the broken line 30. This area is considerably deeper under the electrode 28-2 than under the aluminum electrode 28-2 to which it belongs. There are two reasons for this. One is that the electrode 28-2 is more tightly coupled to the n-type silicon due to the shorter distance to the n-type silicon. This leads to a smaller voltage drop across the silicon dioxide under the electrode 23-2 (the area c) than under the electrode 26-2 (the area 25b), creating a deeper potential well under the polysilicon electrode 28-2 than under the aluminum electrode 26-2 .. The other reason is that the work function for pr polysilicon used on n-type substrates is lower than that for aluminum with about 1 volt. This implies that for a given negative voltage applied to a polysilicon electrode it will repel a greater number of electrons from the adjacent region of the substrate than an aluminum electrode of the same size, which is the same distance from the substrate and to which the same voltage is applied.

Since the main function of the aluminum electrode is to provide a barrier to the charge current when a phase voltage applied to two electrodes is made more positive (in reality less negative) during which time the charge "overflows" to the potential well below the next electrode pair, the "active region" (the portion closest to the substrate having the dimension k) of this electrode is made shorter than the corresponding dimension c of the polysilicon electrode.

Such a construction leads to a faster transfer time and to the possibility of a greater packing density. This size (which is approximately equal to the distance k between two adjacent polysilicon electrodes) can be as small as 2.5 microns or less using the known metal oxide semiconductor manufacturing technology.

As discussed above, the unidirectional charge transfer in a two-phase construction is obtained, as shown in Figure 9, by applying asymmetric potential wells to successive electrode pairs in the manner described. In order to obtain a relatively large asymmetry in these wells without having to have very large differences between the two thicknesses (at b and c respectively) of the silicon dioxide layer, it is desirable to have silicon substrates with a relatively lower specific resistance, such as 20 use a specific resistance of less than 3 ohm-centimeter and preferably in the range of 1 ohm-centimeter. However, a substrate with a slightly greater specific resistance can be used if a relatively large substrate bias for +10 volts or more is used. Greater bias of the substrate in combination with the two thicknesses of the oxide causes a deeper potential well below the electrode which is a shorter distance from the surface of the substrate.

During the operation of the construction shown in Fig. 9, it is assumed that a positive charge accumulates in the deeper portion 30 of the well 30, as indicated at 31 in response to a negative pulse φ ^. Towards the trailing edge of this pulse, a negative pulse is applied to the next electrode pair 26-3, 28-3 (time t ^ in Figure 13). In response to the coincidence of the last portion of the pulse φ2 and the first portion 35 of the pulse Φ, the charge 31 will tend to flow to the right, where the sequence of events is as shown in Fig. 13.

f * -23-

When the potential well under the electrode 28-2 becomes shallower, the potential well under the electrode pair 26-3, 23-3 becomes deeper and the charge present at 31 overflows into this potential well and collects under the electrode 28-3.

Although it is true that coinciding with the supply of the φ ^ pulse to the electrode pair 26-3, 28-3, this same pulse is applied to the previous electrode pair 26-1, 28-1, the flow of charge into the opposite direction is prevented by the potential barrier, which is present under the aluminum electrode 26-2. Just before the pulse is applied, all of the charge under the aluminum electrode 26-2 is stored in the deeper well under the electrode 28-2 (time t ^ in Figure 13). Therefore, when the negative pulse continues and the Φ2 pulse begins to die (time t ^ in Figure 13), the charge in this deeper portion of the potential well will overflow in the forward direction, the direction in which the stored positive charge "sees" the more negative potential, and is prevented from moving in the opposite direction through the potential hill (the less negative voltage) it sees in this direction.

Furthermore, it may be noted at this point that if the construction of FIG. 9 is operated with a sufficiently large bias voltage supplied to the substrate so that the charge signal in the deeper potential well can be maintained by the bias voltage alone, the two phase voltage pulses then do not overlap. Such a lead can lead to simpler signal regenerating circuits, as will be described later.

Typical dimensions for the construction of Fig. 9 are by way of example:

a = 1,000 A b = 2,000 A.

30 c = 10 - 13 microns' (ji) d = 3,000 - 10,000 A e = 7.5 - 12.5 microns f = 500 - 1,000 A g = 3,000 - 10,000 A 35 h = greater than 100 microns j = 5 - 7.5 micron J i i -24- k = 2.5-5 micron 1 = 2.5 micron

The dimensions (except for b in Fig. 11) are the same for the structures of Figs. 11 and 12.

FIG. 10 schematically shows a second way of creating asymmetric depletion zones. Again, each store corresponding to 14-2, 14-3, etc. of FIG. 1 consists of two very short spaced electrodes, such as 30-la and 30-lb, between which a fixed DC offset, which is indicated schematically by the battery 32. In response to a clock pulse, such as a pulse, the first electrode of each pair, for example, 30-1, is not made as negative as the second electrode, such as 30-lb of each pair. In practice, the voltage offset can be achieved in one of a number of conventional ways in the multi-15 phase power supply. As a simple example, the voltage applied to the electrode 30-1A can be taken from one point along a voltage divider and the voltage applied to the electrode 30-1A can be taken from another point along the voltage divider. The effect of the voltage offset is to obtain an asymmetric potential well, as indicated by the broken line 34, which schematically shows the situation for the voltage.

A cross-section and partial schematic view of a practical embodiment of the device according to Fig. 10 is shown in Fig. 11. The construction is very similar to that of Fig. 9, 25, however the aluminum electrodes 30-1a, 30-2a , etc. are at the same distance from the substrate as the polysilicon electrodes 30-lb, 30-2b, etc., i.e. a = b.

Although the asymmetric depletion region is obtained in a different manner in FIG. 1 than in FIG. 9, the operation of the construction of FIG. 11 in response to the two phase voltage pulses is very similar to that of the construction of FIG. 9. Operation is shown in Figure 13.

The construction shown in cross-section in Fig. 12 combines the features of both Fig. 9 and Fig. 11. In view of the previous explanation, Fig. 12 need not be discussed in detail.

r i -25-

In the various constructions discussed above, for an empty potential potential well (a well that has not yet collected charge carriers) for a given voltage drop across the silicon dioxide, the specific resistance of the substrate is higher the deeper the well is, as has been implied. which is formed. When a potential well is filled with movable charges, more and more of the voltage supplied by the electrode responsible for the well is consumed as a voltage drop across the silicon dioxide. This promotes the asymmetry of the potential well. However, mathematical calculations regarding the electric fields in charge-coupled circuits indicate that the lower the specific resistance of the substrate, the smaller is the fringed electric field generated at an electrode and as will be discussed later. current theory, that the smaller the fringed field, the slower the charge shift rate that can be obtained. Therefore, in certain applications, an advantage can be obtained by using substrates with a higher specific resistance. The embodiments of the invention, shown in Figs. 11 and 12, which depend for the potential well asymmetry on the DC voltage offset between the two electrodes of a pair, enable the latter type of construction, i.e. they make it possible that the asymmetric potential wells are formed using substrates of higher specific resistance. For example, an operation appears to be feasible using two phase voltages and substrates with specific resistances of, for example, 10 ohm.cm and above to utilize the construction of Figures 11 and 12 of the dimensions discussed earlier and with a DC voltage. jump off, for example, 5 volts.

Fig. 14 shows a portion of a two dimensional charge coupled capacitor array using two electrodes as described in connection with FIG. 9. (Two dimensional implies more than the single row of electrodes.) The aluminum electrodes 40-1a , 40-2a, etc. take a zig-zag path in one sense and the polysilicon electrodes 40-lb, 40-2b, etc. take a zig-zag path 35 in the opposite sense. This means, for example, that in the upper region of the construction, the right hand of the electrode 40-la is coupled to its associated 40-lb electrode on the right edge of the electrode 40-la and on the left edge of the 40-lb electrode, while in the center of the construction the left edge of the 40-la electrode is coupled to the right edge of the 40-lb electrode. The reason for doing the construction in this way is to cause the charges to move in one direction (to the right) in the upper thin film region, as discussed in more detail briefly, and the charges to move in the opposite direction (to the left). moving the adjacent thin film region.

10; The polysilicon electrodes 40-lb (and the aluminum electrodes) also follow a zig-zag path in the third size, that is, in the size in and out of the paper of Fig. 14. Thus, in the top portion of the figure, there is an electrode such as 40-lb is very close to the substrate and is therefore coupled to it. In the next region, the distance between the electrode 40-lb and the substrate is relatively far, to effectively decouple the electrode 40-lb from the substrate. The Si02 thin film may have a depth of, for example, 500-2,000 A and the thick film may be deeper than 10,000 A. These different thin film and thick film areas are indicated on the right-hand side of Fig. 14. Each electrode, such as 40-1a, is electrically connected directly to its associated electrode, such as the 40-lb electrode. These connections are shown schematically in FIG. 14 by the diagonal, crossed lines.

The construction of the top thin film region along IX-IX 25. of Fig. 14 is similar to that shown in section in Fig. 9 (however, reference numerals are different). The zig-zag structure in the third dimension (in and out of the paper in Fig. 14) of the polysilicon and aluminum electrodes and the connection of an aluminum electrode with its associated polysilicon electrode are shown in section 30-XV and XVI-XVI in FIG. 14. These cross sections are shown in FIGS. 15 and 16, respectively. All three figures can be referred to in the following discussion of the operation.

For the purpose of this discussion, it is believed that in response to an impulse, a charge at A FIG. 14 has accumulated in the upper shift register below the 40-lb, 40-lb-electrode electrode. It should be noted that the construction of this electrode ... · ..,

i I

The pair is similar to that discussed in connection with Fig. 9 such that the potential well is asymmetrical. In response to the phase 2 pulse, the charge stored under electrode 40-lb moves to the right and is stored at 3 under electrode 40-2b of the next 5 electrode pair 40-2a, 40-2b. In response to the next φ ^ impulse, this charge continues to move to the right and is stored at C under the electrode 4Q-3b of the pair 40-3a, 40-3b etc. When a charge reaches the end of the shift register (not shown in Fig. 14), a charge regenerating circuit (shown and discussed later IQ) feeds a charge or its complement (depending on the regenerating chain used) into the next shift register. The direction in which the charge signal flows is indicated by the broken line 42.

For the purpose of the present explanation, it is assumed that this charge has arrived at phase E under the electrode 40-4b of the pair 40-4a, 40-4b during phase 1 time (during the negative pulse φ ^). It would be understood that the asymmetry direction of the potential well is now reversed. At E, the aluminum electrode 40-4a is to the right of its associated electrode 40-4b, while at D 20, the aluminum electrode 40-4a is to the left of its associated electrode 4Q-4b. Therefore, in response to the next impulse, the charge stored at Ξ will move to the left towards F.

From the above it will be clear that with the construction of fig. 14 it is possible to arrange a number of shift registers on a single substrate (as schematically shown in fig. 2), which show the operation of one, very long shift register simulate. As already noted and as will be briefly discussed, means connecting the output terminal of each shift register to the input terminal of the next shift register may be integrated on the same substrate as the registers. Regarding size versus storage capacity, if each storage location occupies an area of, for example, 4 - 50 microns, it is possible to have a 10 bit register on a substrate with an area of 2.5 mm x 2.5 mm.

The manufacturing process, which will be discussed later, is similar to that used in the manufacture of silicon control MOS field effect transistors and is well known. Each warehouse is

A I

-28- requires only a single element (a single charge storage capacitor) at each site as opposed to the requirement, for example, of 4 or 6 transistors per site, used in many memories now commercially available.

A second embodiment of a two-dimensional construction is shown in Fig. 17. It contains an n-type silicon substrate 43, a silicon dioxide layer 44, which is thick in certain areas and thin in others, and p + type polysilicon lines 65 - 69, which are on the silicon dioxide. The cross-sectional views of Figures 18 and 19 will help the reader visualize the construction. The thin film region (section IX'-IX ', is similar in section to Fig. 9).

The last part of the construction, which is on the top surface of Fig. 17, contains the aluminum lines 50 and 52. These extend to the interdigital construction, for example 15 in one case lips 53 - 58, and in another case lips 59-63 as a second example. Line 50 is connected to the voltage source and line 52 is connected to the voltage source. The line 50 is connected to alternating polysilicon electrodes 66 and 68 and the line 52 is connected to alternating polysilicon electrodes 65, 67 and 69 in both cases in the same manner as already discussed with reference to Fig. 14.

For example, at a storage location, a phase-1 pair of electrodes would be the lip 75 and the electrode 68; the next electrode pair, a phase-2 pair, consisting of the lip 56 and the electrode 67; the next pair is a phase-1 pair and consists of the lip 74 and the electrode 66, etc.

During the operation of the device of FIG. 17, if a charge is originally stored under the electrode pair 75-78 during a phase-1 pulse, during the next phase-2 pulse, the charge will move to the left under the move electrode pair 56-67; during the next phase impulse, the charge will continue to move to the left and will be stored below the electrode pair 74, 66, etc. Therefore, the stored charge will be stored along the line IX'-IX '. propagate to the left. On the other hand, it is clear that for the next shift register, which is bounded by lips 53, 60, 55, etc., each stored charge is "f". In other words, as in the embodiment of Figure 9, if each set of lips along a horizontal line is considered a shift register, the two phase negative voltage pulses applied to the electrodes 50 and 52 charges will be in opposite directions. propagate directions in successive registers.

A shift register, which is provided with the construction of fig.

11 or FIG. 12 is shown in FIG. 20. It includes a common conductor 90 connected to interdigital tabs 91, 92, 93, 10 each consisting of one electrode of a pair. The polysilicon electrode 94 is the second electrode of the pair 91, 94; the polysilicon electrode 95 is the second electrode of the pair 92, 95. The polysilicon electrodes 94 and 95 are directly connected to the aluminum conductor 98 at 96 and 97. The phase 2 electrodes are similar in construction and symmetrical with the phase-1 electrodes and are positioned as shown.

As in the previous devices discussed previously, the portion of the structure of FIG. 20 on which stored charges propagate at XI'-XI 'contains a thin film silicon dioxide region.

The cross section along this thin film region resembles that of Fig. 11. Alternatively, the cross section may be as shown in Fig. 12. The operation of the shift register of Fig. 20 is quite similar to that of the previously discussed embodiments.

The construction of Fig. 20 is somewhat inefficient from the viewpoint of packaging density. Extra space is required for conductors 98 and 98 ". Nevertheless, modifications of this construction, as shown in Fig. 21, are useful and economical. In this figure, in the region 100, each polysilicon electrode, such as 104b, forms a plurality of stores rather than a single such location. This is shown in Figure 22, which is a section taken along line XXII-XXII of Figure 21.

During the operation of the device shown in Fig. 21, there are a plurality of source electrodes (not shown) which input a number of charges into the first "electrode pair" corresponding to one information byte. For example, each polysilicon electrode of a pair of eight or more silicon dioxide thin film regions 104 of FIG. 22 may contain,

M t. S

. : j ~} i ï -30- under which 8 bits of information can be stored respectively.

For example, these bits, indicated by the presence or absence of charge, are shifted one byte at a time from one electrode pair to another electrode pair. For example, they (8 bits) can be shifted 5 from the electrode pair 104-la, 104-lb 'to the electrode pair 104-2a, 1C4-2b, in which case at least the a electrode is the aluminum electrode on the surface and the b electrode the polysilicon electrode.

If an attempt is made to transmit a signal along a relatively long polysilicon line located a short distance from a silicon substrate, there will be a significant delay in signal transmission. The reason for this is that the polysilicon line has a relatively high sheet resistance on the order of 10 - 20 ohms per square, so that the line looks like a resistor capacitor transfer or delay line, the "capacitor" being the divided capacitance between the line and the substrate. The solution to this problem in the devices of Figs. 20 and 21 is to use a number of relatively short polysilicon lines, such as 94 and 95 of Fig. 20, all of which are connected in parallel with a relatively good conducting line, such as the aluminum line 98, which is quite a distance (10,000 A or more) from the substrate.

The device of Fig. 23 solves the above-mentioned problem in a different way, whereby no extra space is required. Kier, the shift register consists of an interdigital construction similar to that shown in FIG. 20 and sectioned in FIG. 11, and the polysilicon portion also includes an interdigital construction. The conductor analogous to 98 of FIG. 20 consists of a length of polysilicon line, such as 106, which, in its entirety, lies below the corresponding aluminum line 108. The distance f (fig. 24) between these two lines may be of the order of 500 - 1,000 Å, which is less than or comparable to the distance a (fig. 11) between the polysilicon line and the substrate in the thin silicon dioxide area. The distance between the polysilicon line 106 and the substrate in the thick silicon dioxide region (dimension q, Fig. 24) may be of the order of 10,000 Å or more.

The result of the above geometry is that the capacitance between the polysilicon line and the aluminum electrode is considerable; λ

f '; «B

i t -31- is made larger than that between the polysilicon line and the substrate.

The reason for this is that there is a much larger area of polysilicon which is a small distance from the aluminum than there is a comparable distance from the substrate. In addition, as noted above, the construction may be such that the polysilicon line closest to the silicon substrate is 1,000-2,000 A, while the size may be 500 A.

The coupling between an aluminum line and its corresponding polysilicon line can also be increased in other ways. For example, the silicon dioxide layer of FIG. 24 can be replaced by, for example, a 500Å thick layer of silicon nitride or other dielectric material, which has a higher dielectric constant than silicon dioxide. As another alternative, the silicon dioxide layer 15 can be replaced with a fairly thinly doped oxide, which tends to form a PN junction at the surface of the polysilicon, thereby measuring direct short circuits due to the pinholes, due to the very thin oxide can be formed, which can be less than 500 A.

With the structure, arranged as discussed above, the aluminum lines seen from an AC voltage standpoint are coupled to the respective polysilicon lines. Thus, for example, when an impulse is applied to line 108 ', it is capacitively coupled "instantaneously" to polysilicon line 1061, while simultaneously the two lines are voltage to each other in the manner previously discussed in connection with each other. have staggered with earlier embodiments.

A two-dimensional system operating according to the principles discussed in connection with Figures 23 and 24 is shown in Figure 25.

This system has substantially the same packing density as the device of Figure 17 and it uses a voltage offset, as in the construction, discussed in connection with this Figure and Figures 11 and 12. As in previous devices, there are thin silicon dioxide film and thick silicon dioxide film areas. Such thin film areas are present, for example, at XI-XI in Fig. 25. The cross-section at these. bidding can be as shown in Fig. 11 or as shown in λ '·; 1} -32- Fig. 12. The thick film areas are located between the thin film areas. Two cross sections along lines XXVII-XXVII and XXVIII-XXVIII, respectively, shown in Figures 27 and 28, are both the thick and thin film areas.

An additional feature of interest in FIG. 25 is the manner in which the two phase voltages are conducted to the lips of the system. For example, if the phase 1 voltage is taken, it is conducted directly through the aluminum conductor 116 to the alternative aluminum lines 118, 120, 124. The more negative phase-1 voltage is conducted through 10th aluminum conductor 126 to polysilicon line 128 along the entire extent of this line. This direct connection is more clearly shown in Figure 26, which is a section taken along line XXVI-XXVI of Figure 25. The long polysilicon line 128 is connected in parallel with the polysilium lines 118a, 120a, 124a. A similar construction 15 is used for the phase-2 voltage.

In the device of Fig. 25, as well as in the device of Fig. 23, the capacitance between each aluminum line, such as 118, and the corresponding polysilicon line, such as the line 118a, is made much larger than that between the polysilicon line and the substrate. The reason for this is the relatively small distance between lines 118 and 118a over a relatively large surface area just as discussed in connection with Fig. 23.

The operation of the device of Fig. 25 will be apparent from what has already been discussed in connection with Fig. 23. A charge 25- can be entered into a shift register in the manner discussed in connection with the input end of the system. Once present in a shift register, this charge moves in one direction (to the right) in the topmost shift register; it moves in the opposite direction (to the left) in the next shift register, etc. The links between the registers contain regenerating chains, which will be discussed briefly. Coupling between adjacent system shift registers

Fig. 29 is a sectional view of the coupling between the output end of one register and the input end of a second register. For the purpose of the present discussion, the plates or electrodes 14- (n-1), 14-n, 16-0, etc. are simply shown as X * -33- as single elements. Their actual construction may be similar to that already discussed in connection with Figures 9, 11 and 12 and will be discussed and illustrated later. The substrate 10 is an ordinary substrate and the silicon dioxide layer 12 is also an ordinary layer.

The new construction of Fig. 29, not shown before, includes a floating area or junction F and a drain D, both of which are formed in the substrate. These are highly doped p + silicon regions equal to the source S ^ shown in Figures 4 and 7. The floating junction F and the drain D correspond to the source and the drain electrodes of a metal oxide semiconductor MOS-, respectively. transistor and the electrode 14- (n + 1) corresponds to the control electrode of such a transistor. The drain D is connected to a voltage supply V, which supplies a voltage of a value, for example -10 volts.

The input end of the next shift register is provided with a source S2 and a control electrode 17, the function and structure of which are the same as that of the source and control electrode 14-0, which are shown in previous figures, respectively. The function of the electrode 17, controlled by the voltage pulse, is to provide the timing for the transfer of the charge signal from the source 52 to the potential well below the first electrode 16-1. As previously described, this potential well below the first electrode of the second shift register can be charged with charge in a previously known magnitude such that its surface voltage approaches the voltage of the source 5, ie the voltage of the power supply V ^, which can have a value such as -5 volts.

Fig. 29 also shows some of the capabilities in the system.

These are defined below and their significance in the operation of the system will be briefly discussed later.

30 = capacitance between electrode 14-n and

the floating junction F

C, = the capacitance between the reset electrode b

14- (n + 1) and the junction F

C3 = the capacitance between the junction F and the substrate 10 C4 = the capacitance between the control electrode 16-0 and the substrate 10 S -. * *. 3 tl -34- = the capacitance between the substrate 10 and the conductor 140, which connects the junctions F to the control electrode 16-0 C = C + C, + C '+ C. + C_ = the total effective F ab 3 4 5 5 capacity of the floating junction F.

The operation of the system of Fig. 29 will be discussed first for the case where the capacities are considerably less than C. Furthermore, for the purpose of this explanation, it will be assumed that the shift registers are operated with a 3 phase voltage source, as this is one of the more simple operating modes. The operation of other structures with 4-phase voltage sources and 2-phase voltage sources will be described later.

The waveforms used during the operation of the circuit of Figure 29 are shown in Figure 31. Fig. 30 schematically illustrates the potential wells that are formed and the manner in which charge is transferred in response to the feeding of the waveform of FIG. 31.

Fig. 30 (a) shows the operation during the φ2 impulse (time

t of Fig. 31). A reset pulse V, which is preferably more negative X R.

20 is then the supply voltage V coincides with the negative φ2 pulse.

Fig. 30 (a) shows that a charge 142 is collected in the potential well below the electrode 14- (n-1) in response to the φ2 pulse. Coinciding

has the -15 volt V pulse applied to the reset electrode R.

14- (n + 1) a low impedance channel, schematically indicated by 144 between the source F and the drain electrode D, which resets the region F to a reference voltage close to the value of V ^, while the charge accumulated in F during the previous cycle is transferred to the drain electrode D.

Fig. 30 (b) shows the situation after the phase-2 pulse has ended -30 and the phase-3 pulse φ ^ has started. The time can be from Fig. 31. The charge previously present under the electrode 14- (nl) spilled into the combined potential well under the electrode 14-n and the junction F. In the example given, the well under the electrode 14-n is deeper than that under the electrode F (14-n is at -15 volts and F is at about -10 volts), so that the charge tends to collect in the former region of the potential source, as shown. During this time t0, the return voltage V is 0 volts. Therefore, no potential barrier has been established under the return electrode or, in other words, the channel between the junction. F and the drain D is in its high impedance state. If man considers F as a source, the electrode 14- (n + 1) is a control electrode and D is a drain electrode, all of this from a MOS transistor. transistor is turned off, and none of the charge passes to D.

When the next impulse occurs, the situation is as shown in Fig. 30 (c). This figure shows that after the positive transition of the impulse φ. (as at time t in Fig. 31), the

J

charge, if present under an electrode 14-n, will be transferred to the floating junction F. Assuming that the charge is present at the floating junction F, the potential of this floating junction becomes relatively positive (it actually becomes less negative).

.15 When this floating junction is directly connected to the control electrode 16-0, it applies this control electrode to a relatively positive voltage, so that the potential well below this electrode becomes very shallow. This shallow potential well acts as a voltage barrier. During this same period, as for example of Fig. 31, the pulse is applied. This pulse allows a conduction channel to extend from the supply electrode S, which is at a voltage of -5 volts, after an area of the substrate below the electrode 17. When the control electrode 16-0 is at a considerably more positive voltage than V ^ -5 volts, the voltage of the conductive channel, the charges from the source cannot flow into the potential well created under the electrode 16-1 by the negative φ ^ voltage pulse applied to this electrode.

The case where the last bit stored in the first register is 0 instead of 1 is shown in Figure 3.0 (d).

A 0 is stored here under the electrode 14-n during the pulse. The floating junction F therefore remains negative to a degree of roughly -10 volts, the voltage at which it was charged during the φ pulse. This voltage applied to the control electrode 16-0 is in the forward direction, so that during the pulse a conductive channel 35 146 extends from the source to the region of the substrate, just below the electrodes 17 and 16-0 to the potential source, which is brought to i * -36 under the first electrode 16-1 by the -15 volt pulse. This allows the positive charge carriers available at the source to flow to the potential well below the electrode 16-1 until the surface potential of the well begins to approach the potential of the source. Thus, in response to a 0 stored under the last plate 14-n of the first shift register, a 1 is transferred to the first plate 16-1 of the next shift register.

To summarize what has been discussed so far, during the φ pulse, a charge specifying bit 1 can be stored under electrode 14- (n-1) 10 '. During the φ ^ pulse, bit 1 is transferred to the potential well under the electrode 14-n. During the impulse, the absence of a charge, which is an indication of bit 0, is stored under the first electrode 16-1 of the next shift register. It is therefore clear that when the last bit in the first register is 1, its complement 0 is shifted into the second shift register. The discussion further showed that when the last bit in the first register is 0, its complement 1 is shifted into the second shift register.

The circuit of FIG. 32 is the same as that in FIG. 29, however, a 4-phase voltage source is used instead of a 3-phase voltage source. Using a 4-phase voltage source instead of a 3-phase voltage source simplifies the tempering somewhat since the φ ^ pulse can be applied to the electrode 14- (n + 1) instead of the VR pulse.

During the operation of the embodiment of Fig. 32

during the φ ^ impulse (time t ^ of Fig. 33) a charge, if present, moves under the electrode 14- (n-2). The same pulse applied to the electrode 14- (n + 1) forms an inversion layer between the floating junction area F and the drain electrode D, whereby the area 30 F discharges the positive charge which it may have accumulated during the previous cycle and a negative assume voltage level of about -10 volts. During the φ ^ pulse, the charge present under the plate 14- (n-2) is moved to the area of the substrate under the plate 14- (n-1). During the φ impuls impulse (time t ^ of FIG. 33), the charge 35 is moved to the area below the plate 14-n and may begin to collect at the floating area F. The transfer of cargo in F

,,: · Λ t. -37- is completed towards the end of the impuls pulse, and this brings the control electrode 16-0 to a relatively positive value with respect to the potential 3 ^, if F has accumulated a positive charge representing the bit 1 and a negative value, if the area F remains negative, representing the bit 0.

During the φ negative pulse applied to the electrode 16-1, the control voltage pulse V is applied to the electrode 17.

This takes place at time t of Fig. 33. Depending on whether the electrode 16-0 is relatively negative or relatively positive with respect to 3 ^, the conducting channel will or will not extend from source S2 to the potential well below the electrode 16-1. In other words, the positive carriers available at the region will or will not pass to the region of the voltage well below the electrode 16-1.

In the above discussion, the operation of the system with overlapping pulses was considered. Such action causes the charge transfer from one well to the next, by lowering the surface potential of a subsequent well while increasing the potential of the well containing the charge to be transferred, forcing its charge to flow into the next potential well. By using a relatively large substrate bias V, such as 10-15 volts bias, it is possible to operate the system with multiple phase pulses which do not overlap. Under such conditions, the control pulse V can be replaced by a corresponding pulse from the multi-phase voltage pulses. In this case, whether or not the control pulse V will be eliminated will depend entirely on how quickly the charge can be transferred from below the electrode 14-n to the area below the floating area F. If this charge transfer is sufficiently fast (occupies a shorter interval than the interval between the non-overlapping pulses and (Fig. 29), proper operation is obtained.

Returning to Fig. 29, if the capacities are Ca and more than a small fraction of the value of the total capacity of the floating F region, the operation of the output circuit may differ significantly from the operation just discussed. First

1 J

-38- the effect of the capacity C will be considered. If the value b of this capacitance cannot be neglected compared to the total capacitance C, then at the trailing edge of the reset pulse V, applied to the electrode 14- (n + 1), where the positive going voltage-5 transition occurs, this positive transition is capacitively coupled to the region F, resulting in a positive step in the potential of F. The result of this is that at the end of this reset pulse V, the region F is at a higher (more positive ) legs-

R

will then be (the DC voltage at which the drain region D10 is maintained). Since all eligible chains should have the value of as small as possible, the size of the overlap between the electrode 14 ~ (n + 1) and the floating area F should be minimal. One way to achieve the minimum overlap is to use a "self-aligned polysilicon port", as shown at 14- (n + 1) '15 in Figure 37. This can be done by the procedure to be described later.

While the presence of the capacitance is to be avoided, the capacitance C can be advantageously used to achieve a different mode of operation of the output circuit. The circuit can be schematically represented in exactly the same manner as Figure 29 for the case of a 3-phase charge-coupled shift register, however, the negative timing control voltage pulse V_ can be eliminated.

During operation, the main difference between this shape of the circuit and that already described in connection with Fig. 29 consists in that due to the relatively large capacitive coupling C, the potential of the floating F region has a negation ci follow the voltage swing of the overlapping electrode 14-n, which is controlled by the φ ^ voltage pulse. Therefore, during the impulse, the F region becomes relatively strongly negative. It is therefore possible to directly use the floating region potential F to use the passage of charge from the source to the first potential well (under electrode 16-1) of the second shift register.

In other words, if no charge is present under the electrode 14-n during a negative φ ^ pulse, indicating the storage of the bit 0, the floating region F will keep the control electrode 35 16-0 sufficiently negative to allow charge to flow from the source to the area below the electrode 16-1, during t. * -39- the time during which the leading edge of the negative pulse φ- ^ overlaps the trailing edge of the negative pulse i, on the other hand, if, during the φ pulse, a positive charge is present, which is 1 below the plate 14- n Adjusts, the floating F region becomes sufficiently positive: to allow the flow of charge out; prevent the source to the area under the electrode 16-1 during the next impulse. All this is possible without the need for the additional timing control pulse 7.

There are a number of other circuit operation properties that can be benefited from when there is a significant capacitance at C. At the end of the φ imouls (time t_, Fig. 31), the positive voltage swing of φ ^ esn yields positive voltage step to the region F, which tends to reset the process of returning F to the reference voltage '-J to change. This effect can be used to simplify the output circuit in two ways. Firstly, the reset pulse V can be replaced by a DC voltage level, for example ground level (since the substrate is at a voltage +7) or a slightly more negative potential, such as 7 ,. Second, the construction of the output circuit can be simplified by operating the reset electrode 14- (n + 1), as well as the drain D and the source electrode with the same potential, for example. Finally, a special control waveform 7 of FIG. 35 can be used to promote chain operation.

A circuit combining the above characteristics is shown in Fig. 34. The common voltage V at which the electrodes D and 3 ^ are held may be -5 volts, while the substrate 10 may be biased to +5 volts.

In the following description of the operation of the circuit of Fig. 34, reference is made to Figs. 34, 35 and 36. At time t7, a charge may be present under the electrode 14- (n-2). The composite wave power V is at its most positive value, which can be d earth. In response to this positive impulse, the floating region F, which, as will be remembered, is capacitively coupled to the electrode 14-n by some significant value of the capacitance C, is also made relatively positive. As a result, the region F acts as a relatively strongly forward biased supply electrode of an MOS transistor and any charge which may have been collected therefor is channeled through the channel region below the electrode 14- (n + 1). ) transferred to the drain electrode D. During the process, the electrode F reaches a negative value, which is not as negative as -5 volts. The actual value is -5 volts + Vfc, where V is the threshold voltage discussed earlier. The configuration of the potential wells at time t is shown in Fig. 36 (a).

Then the impulse occurs and the charge present under the electrode 14- (n-2) is transferred to the area of the substrate under the electrode 14- (n-1). This part of the operation takes place without complications and is not shown in Fig. 36.

10.- At time t, the control voltage V is at its most negative value. The negative impulse has started and the φ ^ impulse is ending. Assuming that the φ ^ pulse has a maximum negative value of -15 volts, the actual voltage present at the electrode 14- (n-1) at this time is about -8 volts. The potential wells currently established are as shown in Fig. 36 (b). The charge previously present in the potential well below the electrode 14- (nl) flows into the potential well below the electrodes 14-n and in F. The capacitive coupling between the electrode 14-n and the region F has the region F given a more negative value than the electrode 14-n, since F was originally negative and was about -5 volts. Therefore, the deepest potential well is located in the region F, and if the charge was originally stored under the electrode 14- (n-2) it finally collects in the region F. Furthermore, it can be noted that the drain electrode D 25 .. negative if the region F and further, since since the electrode 14- (n + 1) is at a distance from the substrate, the surface potential below is slightly less negative than that of the drain electrode D.

During the above time period, the φ ^ pulse is in.

This pulse is applied elsewhere in the array to, for example, plate 16-3 of Figure 34 to propagate a charge previously stored under plate 16-2 to plate 16-3. If desired, instead of using the control voltage V, it would be possible to supply the φ_ pulse 3. «j to the electrode 14-n, as discussed earlier, however, no such versatile control is obtained from the charge transfer and signal regeneration, as will be shown briefly.

i -41-

At the time the impulse is in. During this same period, the voltage V is increased 3.

to a value between 0 and -15 volts. The action value used is a function of chain parameters, such as the size of the capacitance C (Fig. 29) and other distributed chain capacities.

The increase in the value of Y & to -Y makes the potential well below the electrode F slightly shallower, but it still remains sufficiently deep to prevent most of the charge from passing at F to the area D. The value of -V is chosen such that in the case where charge at F representing the hit 1 is present, the voltage at 16-0 prevents the charge from the supply electrode & 0 to the region below 16- 1 flows. This set of conditions is at (c) in FIG.

3ö is displayed. The value of the voltage must also be such that in the absence of the charge at F, which indicates storing the bit 0, a conductive channel region is established under the electrode 16-0, 11 such that the charge is from the source transfer to the area under the electrode 10-1. This situation is shown at (d) in Fig. 36.

The circuit of FIG. 3½ is particularly attractive when it is equipped with MOS devices (F, -4- (η + 1.), D) of the promotion type, which have low threshold voltages. Furthermore, it should be noted that other embodiments of the invention, previously described, advantageously use special waveforms, such as V of Fig. 35, to control the electrode 30 overlapping the floating junction area F.

This allows for better control of the tempering of the potential developed at the floating region F and also allows the potential to be shifted at F to a more negative value t * -42- (when F is a charge of below an electrode such as 1 ^ - (n-2) (Fig. 3 * 0) and after a less negative value -V in Fig. 35i selected to provide the desired signal regeneration threshold level, when the potential well below the first storage electrode 10-1 of the next register is ready to accept a charge, this means that the positive step & V at Va (capacitively coupled with F) is also an additional control to ensure that when the region of 10. the substrate near F is charged to the extent permissible, the voltage at F (applied to the electrode 16-0) will cut off the flow of charge from the supply electrode 32 to the region below the first storage electrode 16-1 * 15 shows Fig. 37 more realistically the actual construction which can be used for the portion of the system schematically shown in FIG. 29. However, it is noted that here and elsewhere the thickness of the electrodes (their vertical dimensions) are not shown to scale and that they are drawn in a much larger ratio than the horizontal (length) dimensions of the electrodes. This same construction and the alternatives of Figs. 38, 39 and k0 are also suitable for the construction shown schematically in Figs. 32 and 3.

Fig. 37 depicts a silicon gate embodiment of the phase-coupled charge coupled system previously described with reference to Figs. 32 and 33. Fig. 3 ^ shows the bottom of the two shift registers of Figs. , 37 in a modified version.

Here, the signal regeneration is effected by the coincidence of two control pulses V and V. In this case, the c3 voltage pulse V provides the timing to input the charge into the second c shift register. The control impulse determines whether or not 35 and how much charge is to be transferred to the first potential well τ t -43 from the second hidden nut.

The selective tempering of these two surges and reeas was described in the section dealing with the input end of the system. Fig. 39 is a generalized representation of the input end of a register similar to that of Fig. 38, but intended for a 2 phase operation, The signal regeneration in a specific, similar 2 phase charge coupled system is described in more detail later with reference to FIGS. H2, hj and kk,

Returning to fig. 38

Here, just as in the case of the system, shown in. 37, 39 and 0 0, the floating region F is connected to an aluminum electrode 10-0, which is of the self-aligned type and which can be made such that it has a relatively small capacity relative to the substrate 10 has. Although the electrode 16-0 is located a relatively small distance from the additional control electrodes 17 - a polysilicon electrode, in the region 170, this region 170 is very small on the order of half a micron. Therefore, the presence of the electrode 17 does not contribute significantly to the capacity of the electrode 16-0. For the remainder of the overlapped portion, area 171 *, the silicon dioxide can be made relatively thick on the order of several thousand angstroms (the drawing is not to scale). This relatively large distance over a relatively large area means that the capacitance in this region is relatively small. The aforementioned polysilicon electrode 17 is located between the aluminum electrode 16-0 and the supply electrode ö2 *.

It should be noted that in the case of the four-phase system, as described with reference to FIG., Using still polysilicon and aluminum electrodes, and an output stage, similar to that of FIG. the floating region p · of the first register can be connected to the electrode 17 of the second register, shown in Fig. 37, In this case the voltage is applied to 16-0, & 2 to 5 16-1, to 96-2 and to 16-3

All of the above-described constructions for the input end of the second register can be used at the input end of the first and all other registers. In other words, the constructions shown schematically in Figures k and 7 may be practical, as shown in one or more of the three figures discussed last,

Fig. k0 shows a version of the coupling chain suitable for the 2-phase operation, wherein, as previously described with reference to Fig. 3k, the overlapping capacity C is a relatively large fraction of the total capacity C_ of the floating • junction is F. The construction is similar in many respects to that already discussed. The waveforms used during the operation of the circuit are shown in FIG.

During operation, the negative voltage pulse V occurs during the negative 4. pulse. This discharges any charge carrier which may be accumulated in the floating region F 'and the floating region F' assumes a negative potential close to that of the voltage source V1. During the next ib0 pulse, any charge collected under the electrode pair 14- (nl) a, 14- (nl) b is transferred to the area below the electrode 1 ^ -n and the floating area F. Shortly after the start of the negative pulse, the negative control pulse V occurs and this makes a conductive

O

channel formed under the polysilicon electrode 17, effectively expanding the source region. Now the 35. charge from or not to the first potential well i. * -45- under the electrode lö-i strcisen, which depends on whether the electrode 16-0 betrelckelijlc is negative (no positive charge at F) or relatively positive (indicating the bit 1 stored at i4-n and F) compare is not the potential of the source S1.

Fig. 42 is a plan view of a portion of a two dimensional shift register system, a portion of which is shown in section in FIG. 4q. In order to facilitate the reader's understanding of Fig. 42, parts in Fig. 42 corresponding to those in Fig. 4o are given the same reference numerals. The saving in the embodiment, which is possible with a 2-phase operation, is shown in Fig. 42.

Another form of a 2 phase coupling chain is shown in Fig. K3. Here, the last electrode of the first shift register consists of an electrode pair 1 ^-na, 14 ~ na instead of the single electrode of Fig. B0. In addition, the first electrode 10-1 of the second shift register is controlled by a phase 1 pulse instead of a phase 2 pulse. In addition, the timing waveforms of FIG. Are slightly different from those used for the circuit of FIG. 40,

During the operation of the circuit of Fig. 43, the reset pulse occurs during the pulse

25 v and the floating electrode is reset to R

reference negative voltage level. When the next 42 impulse occurs, the charge is optionally transferred under the electrode pair 14- (nl) a, 14- (hl) b to the potential well below the electrode pair 14-na, 14-nb and 30, hence the charge flows into the potential well below the floating electrode F if during the pulse the electrode F is at a more negative potential than the electrode pair 14-na, 14-na.

The charge transfer from the last potential well of the shift register to the floating area F is completed during the trailing edge of tb.

At this time, during the pulse V (which occurs during the first portion of the negative pulse 4), a conductive channel extends from the source to below. 5 electrode 17 out. At the same time, if the floating electrode F is relatively negative, the charge of S2 flows through this channel region and through the channel region formed under the electrode 16-0 to the potential well below the electrode 16-1 established by 4. On the other hand, if the electrode 16-0 is relatively positive, indicating the storage of a 1 at the floating electrode F, a barrier is established below the electrode 16-0 and no charge of S2 flows to the potential well under the electrode ló-1.

Shortly after the control pulse V has ended and still during the negative pulse 4. ^, the reset pulse V occurs to reset the floating electrode X \ F, i.e. to bring it to its reference potential. At this time, however, no charge 20 can flow from the source, since Vc is at ground potential, creating a barrier to charge transfer from the source,

Fig. 45 is a plan view of a portion of a two-dimensional ion shift registers count el, 25 as shown in part in FIG. 43, Here again the saving in implementation speaks for itself.

While not shown, it will be appreciated that various other permutations and combinations of the various devices described may be used. To give just one example, it is clear that the simplified construction of Fig. 34 can be used in the 2-phase version of the shift register.

Briefly, it is returned to FIG. 4o. As noted previously, the con- v> -47- 3: ruc; ie var, the signal regenerating stage can be somewhat simplified, such as? from the embodiment shown in FIG. 42 at <t, if the circuit is depleted to operate without the reset control voltage pulse V. This circuit modification is schematically shown by the broken line connecting the electrode 14- (n + 1) to the same power source as is used for the drain electrode D. In a preferred embodiment of the invention, a common power supply gβίο uses D, l4- (n + 1) and S2 in the same manner as previously indicated in Fig. 34 for the case of a 3 phase system.

In the hitherto shown embodiment of the invention, each shift register receives the complements of the bits stored in the previous shift register. The circuit schematically shown in FIG. 46 allows each shift register to supply the bits themselves to the next shift register. The floating electrode F instead of being directly connected to the control electrode 16-0 of the next register is thereby connected across an inverter I. In other respects, the operation is the same as that discussed previously. The inverter can also be used in the various other discussed embodiments of the invention. In practice, the inverter can be made from metal-oxide-semiconductor devices integrated in the same substrate as the rest of the system or alternatively it can be a circuit outside the substrate.

In the embodiment of the invention shown in Fig. 21, a number of bits are transferred in parallel in the region 11. When discussing this figure, it was noted that this number of bits may be an information byte. More particularly, an advantageous effect can be achieved if, moreover, the β-48 complement of the byte is transferred in a falling manner.

Thus, an ait type system includes n pairs of charge coupled shift registers (wherein n is an integer, which in the case of limitation is 1, which is 5 normally β or 8, and which may be a significantly larger number). A shift register of each pair stores the bits and the other the complements of the bits, and each such pair can be connected to a balance detector, as shown in Figures 4-7.

An important advantage of working in this way is that the signal can be detected without having to reach a certain threshold level. For reliable operation of the balance detector it is only necessary that there is a sufficient amplitude difference between the two input signals, one representing bit 1 and the other representing bit O. Another advantage of using a balance detection device is, as will be briefly discussed with reference to Fig. 49, the relative ease at which new information can be input to the storage loop and output information from the storage loop. obtained. The reason for this is the additional signal amplification, which is available, which allows the balance detector to be located some distance from the charge-coupled shift registers.

An embodiment of the balance detection scheme is shown in Fig. 48. It is assumed that the top left register 14- (n + 1) stores 14-n etc. bits and that the top right register 14a (n + 1) stores 1), 14a-n etc. stores complements of the bits. In practice, these two registers are arranged side by side and the bits and their complements move in the same sequence, however here they are shown simply converging for convenience.

3.5

The balance detector is provided with two transistors 200, 201, which are the same substrate as the rest of the system. integrated. Furthermore, use is made of the output constructions of the two shift registers as the load device or "spring tines" 5 for the two cross-coupled transistors 200, 201. Thus, the balance detector consists, in alliance, of a four-transistor, flip-flop, two of which transistors act as load resistors and are part of the output circuit of the shift registers.

XG During the operation of the systems of FIG. 3, during the pulse, V can be made relatively strongly negative and V equal to V can be made, ° 1

As a result, the floating areas F- and F „discharge any charge that one of them may have collected and are reset to a vessel close to -V ^. Therefore, terminals 202 and 203 become close to -V at the same negative potential. and when V is made zero (V remains at -V ^), all four transistors are cut off and the F, and F regions are in an open chain.

JL. c.

The transfer of the charge signal to the F1 and F1 regions establishes the state that the flip-flop will assume when it is energized again or, in other words, when the four-transistor flip-flop is in an active state, condition.

The flip-flop is reclassified by first making V_positive G1 more (actually less negative) and then (or coincidentally) reducing it to a negative potential in order to transistor loads (f ^, 14— (n + 1), D and Fg144a (n + 1), D) in the chain, more precisely, Viets can be made more positive than the reset portion of the cycle, however it is still being set at a potential sufficiently negative that the two load transistors are still in their conducting state. The control voltage i 1 -50- V is made relatively positive with respect to V; 1 '4 it can be increased, for example, to or a slightly more positive potential (the actual value chosen for V will depend on the voltages, desired at 202 and 203)

As noted above, the state the flip-flop assumes will depend on the values of the bits stored in the two shift registers. For example, if the bit is stored under Γ0. -the electrode pair 14-n is 0 during the impulse (no charge), F ^ remains relatively negative. Accordingly, there will be a charge under the electrode pair 14a-n, so that at the end of the impuls2 pulse this charge will be transferred to F F and F „will be relatively positive. The relatively negative voltage at 202 will unbalance the flip-flop, and when the flip-flop is energized again, the result will be to make the transistor 201 conductive, and therefore the relatively positive voltage at 203 will cause transistor 200 is cut off. The difference in voltage between F- ^ and F ^ determines the new state when the flip-flop is energized again. Therefore, the clamp 202 will be relatively negative close to the value ~ V ^ minus the voltage drop from D to F ^. while the point 203 will be at a relatively positive value, close to the potential V,

Ci which can be the same as.

During the impulse, the information stored at 202 and 203j associated with the control electrodes 16-0 and 16a-0 will coincide with a negative

selective pulse V applied to electrodes 17 and 17a O

be supplied, have a guide channel under the electrode 16-0 and no guide channel under the electrode 16a-Q. I.e. after the start of the impulse, * Li s Jr -51- warm the flip-flop before the new toe edge is sensed, the acid pulse V- is made negative, * and the charge from 32 to the area below the storage plate ió-1. Since the electrode 10a-0 is relatively positive with respect to V, no charge transfer from the source 3i to the region below the storage plate 10a-i takes place.

Fig. 49 shows in a more schematic manner an alternative device. The construction 13 of the upper ea lower shift registers is the same as that of Fig. 48 and only the floating junctions F, and the electrodes 10-10 and 10-0 are shown. In this embodiment, the floating junctions are not used as a load element and for the balance detector. The transistors 200 and 201 are the same as those of Fig. 48. In addition, however, there are separate transistors 204 and 205i whose purpose is to amplify the signals present at F1 and Fn, respectively. In addition, there are transistors 207 and 208 which have the dual task of operating as transistor loads for the flip-flop 200, .201 and as a means of inputting new information into the flip-flop. It may further be noted that new information in the circuit of FIG. 48 may be input by two transistors, such as 207 and 208, shown in FIG. 49.

During the operation of the device of FIG. 4Q, the flip-flop is first reset by making both transistors 207 and 208 conductive (EXT = EXT = V, while J2i = IN ^ = certain negative value, for example -V, of flS-43), The transistors 207 eh 208 4- ___ are then turned off, for example by making EXT = EXT = ground, while Vq is also equal to -V ^, so that the transistors 200 and 201 are turned off. Hence, both points 202 and 203 are on the same reference potency (-Reset).

-52-

At the time when the flip-flop is reset and the charge signal is available at F1 and F1, a negative pulse V, which is more negative 0 2, is applied to the drain electrodes of transistors 2½ and 20p. For example, if Ui (the voltage at F ^) is relatively negative and IN (the voltage at F2) is relatively positive, transistor 204 will conduct more than transistor 203 * This will unbalance the flip-flop so that at the same way as be-10. for the circuit of Fig. 48, when the flip-flop is energized again (first by returning the voltages IN '= IN to -V ^ and then returning to V ^) the flip-flop will be in a new state in which the voltage difference 15 between points 202 and 203 will be an amplified version of the voltage difference originally present between F1 and F2.

New information can be added to the bottom registers via transistors 207 and 208 in a manner used, for example, in a P-M0S

memory system. The EXT and EXT signals perform the function of the word dialing pulses, while the IN 'and IX signals perform the function of the bit signals which input new information. The external input signals can set the flip-flop to the desired state in the absence of the control input pulse V1.

L 2

The external signals may also be given a sufficient amplitude to overcome any signal which may be present at Fn and F-30 during Vn. In other words, the operation is the same as that described in connection with Fig. 48. This means that during the regeneration process of the information, transistors 207 and 208 perform the function of the load devices in the flip-flop, which are in the circuit of Fig. 48 were part of the. ï η. * -53- output consonation of the complementary shift registers.

Therefore, the features discussed above in Figs. Id and 49 are the flip-flops used to convert suitable charge-coupled information into static information unbeaten in a flip-flop. For example, when a byte and its complement to charge-coupled shift registers, such as in FIG. 21, are transferred to an output terminal of this array, there may be n flip-flops 13, as shown in FIGS. 48 and 49, where n is the number of bits in a byte. These n bits can easily be slipped into any suitable form of memory. For example, the signal regenerating flip-flop, as in Fig. 49, with additional transistors 204 and 20p for amplifying the signal taken from F and F0 can act as a semiconductor memory, which can be used as a buffer storage between the charges coupled memory loops and external circuits · 21 In the systems of FIGS. 43 and 49, the input information is scanned at the floating junctions such as F ^ and F ^. It is noted that the system may also operate using floating aluminum electrodes such as 14 -n of FIG. p0 to capacitively couple signals to the flip-flop. The change in capacitance of such floating electrodes as a function of the charge signal will become apparent from the description which will be given briefly of the operation of the circuit of FIG. PQ.

52 Although FIGS. 47-49 are presented for the present discussion in terms of a 2-phase device, it will be appreciated that the techniques described also apply to 3-4 and higher phase, a load of propagating circuits.

In the discussion that has so far taken place 4 * -54-, the link between two registers was provided with a floating junction area, such as F, F, etc.

This floating junction region is located in an n-type substrate and consists of a p + region. It is also possible to use the signal sensing member a floating aluminum electrode as shown in Fig. 50. Here the floating aluminum electrode 1-n at the output end of one register coupled to a control electrode 10 0 at the input end of the next register.

During the operation of the system of FIG. 50, a four-phase device 1, it is assumed that the electrode 14-n is reset by the negative control pulse V- to a certain voltage which is not as negative as and is in a open circuit (leave floating) by removing the control pulse V. This creates a potential well under the electrode 14-n. At the time of the charge, the charge (or no charge) is transferred to the region of the substrate under the last storage electrode 14- (n-1) 20. Currently, a charge is assumed to be present, during the trailing edge of the 4 ^ pulse overlapping the negative 4 ^ pulse, since the potential well is made shallower under the electrode 14- (nl), the one contained therein charge into the potential well below the floating aluminum electrode 14 ~ n. As is apparent in this technique, increasing the charge in the potential well below the electrode 1U-n increases the effective capacitance between the electrode 14-n and the substrate, since a solid charge prior to these floating electrodes increases to has been brought about, this reduces df at the electrode llt - n and therefore at the voltage present at 16-0,

When the 4 ^ pulse is finished, the charge transfer to the potential well below the -55 electrode 14-n is completed. and at this time, the aega-11ave control pulse V1 is supplied to the elextroda 17. hu are the oas conditions appropriate to allow charge to flow from 3 through the conduction channel on the electrode 17 and depending on whether the electrode 16-0 is negative or positive relative to the potential of the source 5 ^ or not to flow to the potential well below the storage electrode 10-1.

Under ideal conditions and when a perfect dielectric-silicon dioxide layer with no leakage is assumed, a solid charge in the electrode 14-n can be maintained by the capacitive voltage dividing action. For the purpose of the present discussion, a relatively large DC voltage source V15, and a relatively small capacitor is assumed in the circuit to achieve this goal. However, in practice, even a dielectric material which is equally good as silicon dioxide a finite, specific resistance, which will generally attempt to make the reference voltage of the electrode 1n under these conditions dependent on the previous state of the shift register. In addition, these floating electrodes will develop a slow voltage if the conductivity of these two capacitors is not accurately proportional to their respective capacities and further errors would be introduced. In order to avoid such problems and also avoid the need for a relatively high DC voltage source, according to the invention a reset voltage means, for example defMOS device F, Vc, is provided to reset the electrode 14-n to a k reference level. Whenever the negative control pulse V occurs, the floating aluminum electrode 14-n is reset to the voltage of. Although, if desired, a negative pulse V can be applied during every 35 µms, in reality, the electrode 1k-α does not need to be reset as often. If desired, it can be reset, for example, synchronously with a negative impulse, for example, every millisecond.

Another feature of the circuit of FIG. 10 is that the voltage of the electrode 10-O can be modulated by an external voltage source through a coupling capacitor, which is indicated by broken lines. The control voltage Vc 10 can be synchronous with the control voltage V. The purpose of this is to shift the level of the voltage present at 16-0 to a suitable level, for example in one case to completely close off the channel under the electrode 16-0 and in another case to strongly close this channel 15 conductive. This indeed corresponds to what has already been described for the case where there is a significantly overlapping capacity G.

a

An alternative to the above-described reset means is to keep the floating electrode 1 to 20 at a fixed reference voltage by connecting this electrode to a power source terminal through a relatively large value resistor indicated by broken lines with Rc. This resistor can be in the form of a relatively thin strip of polysilicon film 25 of the same composition used for the poly-silicon electrodes.

Exit of the system

Fig. 51 schematically shows a form of an input-output circuit for the system according to the invention. This figure also shows the use of charge-coupled logic circuits. This circuit is designed for the 2 phase embodiments, however, similar circuits can be used for the 3 and higher phase embodiments.

The portion of the circuit containing *> -57- ca eie.ctro <ie; i iU- (r-2), i4- (ni) etc. in the top 11 '' 'er b5' "eeite, may be at the end of the xa. "0 -. 3" s: the array and contains the switching electrodes 16-2 and 10-1, etc. 5 validated at the first half of the first register of the system, together they form part of a closed loop.

It is desirable to allow the information to be easily recalculated to have impulses V. esnbepaalüe tepa-xLG __ ° active value with respect to the source 3 and VT1T is. * XVLG- be positive with respect to the source 3 ^, for example i3, <as the latter are at earth potential.

The electrodes 17a, 10a-10, 10a-1, and 10a-2 represent the input end of a shift register to remove wet output from the above system 15, which may be closed loop. In short, this register of the system works as follows. The output is obtained only when the negative control tube train V (supplied to the electrode 17a) is present. V pulses are relatively negative IC pulses and V is relatively positive, new information can

Input in closed loop system under the control of the input signal. Incidentally, the function of the control pulse and V V, and V is equal to that of the timing pulse of Fig. 4o.

For the purpose of this description, it is assumed that the voltage source V ^ representing the potentials of 3, 3, and 3. controls -5V will be. The sources S0, 3 ^ and may consist of the same single source region, but in order to obtain an additional control 72 over the operation of the output stage, separate control voltages can be applied to the sources S0, S0 and in a manner, for example, already was described in connection with fig. 7

The operation of the closed loop will already be clear. from the previous discussions, for example the discussion of the circuit of FIG. bo (with the proviso that d d2 in FIG. kö in FIG. pl).

During the negative impulse, the complement of the bit stored in the last stage of the last shift register is shifted into the first stage (16-1) of the first shift register. During the next impulse the bit, stored parent 16 —1, advance to the left to the potential well below the electrode pair 16-210.

At the leading edge of this & 2 pulse and the trailing edge of the pulse, which is finishing, the positive charge, which is present at F, runs

X

into the potential well established under 14ma, 11mb. It should be noted that F ^ is a small distance from 1 ^ - (n-1), and the aluminum electrode 1 ^ 4-n overlaps this distance. The electrode 1k-1 acts as a control electrode during the trailing edge of the pulse, to prevent a charge at 20 F 1 from propagating back to 1U- (n-1). When 4 ^ decreases, the potential well below the electrode 1 ^ -η decreases and, concomitantly, the potential well below the electrode pair 14-ma and 1 ^ -mb increases, causing this charge transfer. The charge transfer from F ^ to 25 Fo stops when the electrode F reaches the potential of & in the three-stage voltage, i.e. (-15 volts + V). This is the reset or reference voltage for F ^.

At the beginning of the & 2 pulse, F0 is at a negative voltage V close to 30 + b2 (assuming a strong capacitive coupling of ϋ> 2 with F2), since it has already been reset as previously described, therefore the positive charge carriers collected in the potential well under F2. The potential of F ^ is, if no charge is transferred from 35, + 2> 2, assuming, s * -59-that -e.pacit32.-c var, the electrode i ^ -mb. is considerably larger v. n the capacity of F, relative to the substrate pope ae capacity of the egg process 16a-0. Incidentally, the potential of F2 + will be d2, where the * -XA.ouaicg depends on the capacitance between the electrode i'r-ffib and the total capacitance of? 2 «.

The above discharge current, if connected to exx, zidz to a positive change in the potential at s2 and since it is connected to ia-Q, tou a corresponding voltage change at 16a-0.

The laava ^ uenoemae electrode is the control electrode for another housing register 16a-1, lóa-2 etc.

If the control voltage is relatively negative with respect to the beam during the & 2 time, the charge will continue to propagate through the guide vane below 17a. Depending on whether xoa-0 is relatively negative (no charge at F0) or relatively 1x jk positive with respect to S2 (charge present at? 2), the charge will or will not go to the first potential source, the one pass electrode 1a-1. After this, this information propagates to the right. On the other hand, if it is relatively positive, for example, is at ground potential, then no information from F can pass to the 100-2 register.

After the termination of V, the impulse terminates while the impulse is still in progress and the two-second arming impulse impulse Vb occurs. This impulse causes C2 the region of the substrate under the control electrode 1 ^ - (n + 1) to act as a conduction channel and each charge at Fn is fed through this channel to the drain D. After the charges are transferred, the second floating electrode F0 becomes one. negative value, close to that of reset by the control pulse Y. V ^, can have a certain value, 2 for example -5 volts · i £ -60-

When it is desired to enter new information into the slide fermenter, the electrode '17 is made relatively positive with respect to, ie, it is brought to a potential, for example, arcipotential, and a relatively negative impulse or impulse train is applied to 17 -b supplied. The relative positive * voltage leaves the electrode 1? prevent the progression of charge carriers from the source to the potential well below the electrode 10-1, regardless of the potential at 16-0. Therefore, if geexi information is input at V_v, VriT, _ indeed will enter a 0 in JJN bÜL / Kjr the shift register in response to each pulse, effectively erasing the successive bits stored in the shift register systems e1.

15 New information can be entered

by applying a corresponding voltage V to the control electrode lób-0, coinciding with the pulse V.

Ki) Cr which is supplied to 17-b during each negative pulse. If V is negative during the ά impulse,

J-ti X.

20, the supply electrode transfers charge to the potential well below the electrodes 10-1 and 1b-1. These two electrodes are essentially the same electrode, a common electrode, shown separately for convenience in the drawing, which electrode is capable of charging either through the channel, controlled by the electrodes 17 and 10, or through the channel controlled by receive electrodes 17-b and lób-0. If, on the other hand, \ r. is relatively positive.

IN

for example, at ground potential during the negative pulse VREG ', then a potential barrier is established under the electrode 30 lób-0 and no charge is transferred from to the potential well, which is established by & under the electrode lób-1, ló-1 brought.

The purpose of the special stage, consisting of the electrodes 14-ma and 14-mb and the F2 region 35, is to make it possible to obtain an output signal, -51-x.

Gap .: e: half a period is delayed from the output signal, wet is available at the first shift register solar. additional capacitive load of the first output stage, The construction of this special output stage 5 can be extended to a multi-stage construction, each stage consisting of 14-ma, l4-mb, F0, which successive stages are controlled by successive phases. This new and improved construction is useful as a so-called "bucket brigade" circuit, as described by p. L. J. Sangster, Integrated MOS and Bipolar

Analog Delay Lines using Bucket-Brigade Capacitor Storage ", ISSCC Digest Technical Papers, biz. Jk, 1970 * Such bucket brigade circuits are made using a standard p-MOS process. The new construction according to fig. Pi is made using self-aligning silicon gate techniques, which will be discussed later, and allows the construction of considerably more compact circuits, it further provides a method of measuring the capacitance of the electrode (electrode 14-mb) which diffuses the overlapping floating junctions, making them more reproducible Another feature of this circuit is the virtual elimination of the unwanted inter-stage redemption capability, the latter being possible because the floating junction regions are diffused, whereby the silicon gates, such as 14 -ma and 14 - (^ ni-1) in the case shown in Fig. 51 »if the mask are used.

The new "bucket brigade" shift registries, which can also be used as a self-scanned photo-scan system, can be made in the same way as two-phase charge-coupled shift registers, using two thicknesses of channel dioxide to obtain of the asymmetric potential wells, as shown in FIG.

- 14 of 17 «New new bucket brigade constructions

£ U

-62- the two different thicknesses of the channel oxide are not essential for operation, but can be used as an additional control over the respective values of the silicon gate and the aluminum capacities 5 in optimizing the design of these switches. 1ingen.

During operation of the above bucket-brigade circuit, charges representing information are biased between oppositely biased floating junctions, such as area F

in Fig. 51 under the control of the two-phase clock voltage pulses, such as ch0, which are transmitted in parallel, the self-aligned polysilicon gates, such as 14 ~ ma, overlap the floating junction regions, such as F2.

General Considerations Regarding Design of Cargo Coupled Sliding Shackles__

A number of factors that must be taken into account when designing the circuits discussed above have been previously addressed.

Taking FIG. 0 as an example, the energy source serves to drive the floating region F at a given reference voltage YT. The power supply voltage - 25. V1 (combined with (Fig. 29), if present) determines the amount of charge applied to the potential well below the first storage electrode 16-1.

supplied. The potential V of the floating area F

£ is the voltage applied to the control electrode 16-0.

When = V ^ p (no charge signal present at F) then the charge made available at S2 can be transferred to the potential well below 16-1 at an appropriate time. On the other hand, the value of V,

F

when charge is present, it is sufficient to flow charge 35 from S2 to the well below 16-1. ± e "prevent".

• ck -63-

This value should be more positive than λ (-V ^ +> where _V "is the threshold value associated with, 10 - G" For the present purposes, it is assumed that V of FIG.

Uq volaoence is negative, so that a highly conductive bead under electrode 17 is produced *

From the above it is clear that by judicious choice of the values of V ^ and V, an appropriate value of V can be obtained in one case (no charge at F) to allow a charge in a desired amount flows from 3 ^ to the potential well below 16-1 and otherwise (charge at F) to prevent charge from S0 from flowing to the potential well below lo-1 * The voltage swing at F - the magnitude of the deviation of 15 y from V. , can be increased by increasing the magnitude of (± n fig * 4o), forming a deeper potential source at F and when charges are present more such charges are collected thereby causing a greater positive swing of V_ £ 20,

In discussing Fig. 29, the various distributed capacitances of the circuit were input * The total capacitive load C of the floating region F is; - 23 CF = ° a + Cb + C3 + Ck + C5

The change in voltage 4. V_ caused at F due to the charge transfer Q. is to F. t

For a substrate with a relatively high specific resistance, the main contributions can be

formed by G and G ^. Therefore, in this environment ^ V a D F

can be significantly increased for ..a given Q, by C.

* ... cL

and to a minimum. This implies a short dimension of fig. Ko (assuming that the .capacity

Jh * '-64- • ε us s and 17 and 1.6-0 is relatively low in fig. I + o) and a minimal overlap between l-n -n and F, as shown for example in fig. ^ 3 Discussed in connection with Fig. A3, somewhat more complicated tapering signals are needed and it may sometimes be desirable to sacrifice some of the voltage gain for the sake of simplification of the timing and other considerations. The effect on the operation of the circuit as a result of increasing the capacitance at C has already been discussed,

The operating speed attainable with the charge-coupled shift registers described above depends in part on the time required to transfer a charge from one potential well to the next potential well. This charge transfer can be performed in three different ways: 1, Diffusion, 20 2, Using a self-induced running field, which is due to the gradient of the surface potential due to an uneven charge distribution in or between the two potential wells, and 3 · By an externally induced loop field, which is a result of the fringed field between the two electrodes.

Computer calculations relating to 3 have shown that for one. substrate with a sufficiently high specific resistance, the self-aligned electrode structures discussed above which allow the separation between two adjacent electrodes to be equal to or less than the distance of an electrode from the substrate can be made such that the full charge transfer mainly in response to the fringed field and in a time of the order of ij. * -65- & -TO o z t a of nanoseconds is performed. On the other hand, the above mentioned mechanism 2, which can be considered.

a rd.susseecnainsRis with a coefficient of diffusion is proportional to the Is.dxngsdxch'ckexd te, until the charge transmit in a similar manner to the discharge of a withstand capacitance (RC) transmission line. lighter in contrast, with the mechanism 2, the charge transfer becomes. progressively slower than the RC time our aunt as a function of the amount of charge removed from the potential .10 · Pu “. In the absence of 3 mentioned above, which is expected to be at a great distance from each other · 8 · 8 ·? and / or long electrodes, when the potential well becomes empty, the charge transfer mechanism begins to depend entirely on the diffusion of charge carriers, independent of their concentration, with a characteristic time constant 1.2.

of tt - where L is the elctrod e length e and D is the diffusion coefficient in crn / sec. In cases 1 and 2, the charge transfer efficiency (the degree of charge transfer completeness) is expected to be inversely proportional to the operating frequency. In method 3 editer, a full charge transfer can essentially take place in a single transit time of the charge carriers and this implies an extremely fast operation as well as a full charge transfer. Therefore, while the mechanism 2 can significantly contribute to the initial charge transfer, a complete and rapid charge transfer is possible only in the presence of the mechanism 3.

When the depletion depths can be compared to or greater than the electrode lengths 30 Li and the separation between the electrodes is equal to or less than da thickness of the silicon dioxide layer, the effective charge transfer time t due to the fringed field can be substrate with infinite specific resistance were approximated by: 3b tc = / U cv T7FZ ^ j. τ -66- where the above equation is derived from Ξ. = 2 Jï'a. On V (2)

L

t = L / \ c .ui; (3) / min where = the electric field, present under the 5 electrode (see independent) 2 = the mobility = 250 cm / volt-sec for n-type silicon.

represents the difference between the voltages applied to two adjacent charge-coupled electrodes. The equation was derived for a 3-phase charge-coupled shift register, when the &? voltage increased, voltage increased and voltage was 0. The charge was transferred from the potential well under a & 2 electrode to the potential well under the 15 electrode. At the time of interest, the values of the voltages applied to these two electrodes were 4 ^ = 0 volts, volts and = -2V volts, which is A? =? makes.

a = the thickness of the silicon dioxide, i.e. the distance of an electrode from the substrate.

Although in the above case the value of B. was obtained analytically (by an accurate solution of the potential field equation), such analytical methods cannot be applied when it comes to finite specific resistance. This requires computer calculations, which involve approximations (the solution of Poisson's equations). From such numerical solutions of 50 the potential field of charge-coupled constructions, taking into account the finite X. * -67- specifically: © resistance of the substrate, ie taking into account the space discharge of the area of exchange, the following has emerged. For a configuration of electrodes, where L - 4 micron (yu), 5 the distance f between electrodes = 0.2yU, a = 2.000 S, specific resistance of the substrate p = 20 ohra-ca and the voltages, present on three adjacent electrodes 7 and 12 volts respectively, the minimum fringed field on the surface of the silicon substrate (the field which contributes to the charge transfer) is 2.5 x dO "^ volts / cm. This comes with a transit time - time it takes for the charge to move from the potential well ... to the next, 0, 5n, sec. Kei f ran j evormx - field L = 10 yU with all other factors the same, is 4 x 10 volts / cm, corresponding with a transit time of 10η.sec.

The fringe variation void eeiiSr-p (and the runtime increases accordingly) when the depletion depth becomes smaller than the electrode length L. The size of the franformed field is among other things a function of the electrode voltage (the greater the voltage between the electrodes and the greater their absolute value, the greater the field), the specific resistance p of the substrate (the greater p, the greater the fringed field for a given electrode voltage) and the dimension a (the smaller. a, the larger the fringe-shaped field for a given electrode voltage. It was found that when the depth of charge becomes less than 6a, the fringe-shaped field begins to decay very quickly. take with the reduction of the specific resistance of the substrate. The condition where the depletion depth is equal to 6a corresponds to the situation where the effective thickness of the silicon dioxide (which is equal to about 3a) equals 1 / 2xd> the effective depletion depth * The above condition— 35 the corresponds to the situation when the voltage drop -68- ί. V.

- '"Pr the silicon dioxide is equal to the voltage across the depletion depth of the silicon»

Another method of increasing the fringed field for a solid electrode construction in the case of a relatively low specific resistance of the substrate is to operate the two-phase structures with a relatively large substrate bias. A large substrate bias through the. increasing the depletion depth of IQ · the potential wells lead to larger fringed fields »

For example, from the numerical solutions of the potential fields, it appears that for substrate doping of 5 χ.,. ΙΟ '* "' *“ 3 cm (which corresponds - with a specific resistance of 0.8 ohm-cm for an n-type substrate) and electrodes, which are 15 k microns long and separated by a distance of 0.2 microns on 2,000 channel oxide, the minimum fringe-shaped field is 300 volts / cm for phase voltages of 2, 7 and 12 volts. However, for the same construction, the minimum fringed field increased to 1,200 volts / cm 2Ό for phase voltage and from 12, 1.7 and 22 volts. This means that in this case the minimum fringed field is increased by a factor of four when the substrate bias.

ning from V = +2 volts is changed to V .: = +12 volts. ii N

The structures according to the invention can be used to achieve very fast operation. * The overlapping electrode construction allows the adjacent electrode h to be placed close together. The distance between the electrodes f (see Fig. 9) can be made very small from 30 -1,000 £ or less (i.e., 0.1 µU or less). The length L.

(Fig. 9) can be small, 13 yU or less - perhaps as small as 5 yU, as is the length k (Fig. 9), which can be 2-5 yU. The short length k is easily obtained using the self-35 aligned silicon gate technique *

• 5 X

-69-

Coniputer analyte, discussed briefly above, indicates that the use of a substrate having a relatively high specific resistance.

(10 or more ohm-cm) may yield bit rates of the order of 5 bits per second or more. In particular, high packing density circuits, such as are desired for serial memory applications, are best obtained by using two phase constructions for the charge coupled circuits. Of these constructions, the construction, which uses only the two thicknesses of the silicon dioxide and without stress offset (as shown in Fig. 9), uses a substrate with a relatively low specific resistance, for example, a substrate with a specific resistance in the order of magnitude from three to. one ohm-cm. These registers are intended to operate in H Q * h £ t range from 10 'to 10 bit per second. To achieve higher bit rates with these constructions, a relatively high substrate bias voltage V, for example, +10 volts or more may be used. · To obtain bit rates greater than 10, preference is given to the two- phase constructions that use staggered DC voltages (as shown in Figure 11), since they can be made with substrates with a high (as well as a low) specific resistance.

Another factor to consider when determining the working speed. ness. of the circuits discussed above, the response time of the signal regenerating circuits (circuits as discussed with reference to, for example, FIG.

37-i * 0), this should take into account the time required to reset the floating junction F to a reference potential, as well as the time required to transfer charge to the floating junction and the time required to place charge in the first potential well £ Τ '-70- of the next register (the well below electrode 10-1) under the control of the floating junction. The charge transfer in the floating junction can in principle be as fast as the time it takes to transfer charge between two adjacent potential wells. The time required to reset the floating junction to the reference potential (the potential Y ^) can be compared to the charge transfer time and can be accelerated by using a sufficiently large reset pulse VR. The residual factor, n.l * the time it takes to transfer charge to the potential well below the electrode lé-1, is the major limitation in the response time of the signal regenerating circuit. However, this is not a serious limitation, since it can be shown that for a voltage of two volts or more, this charge transfer time can be on the order of several nanoseconds.

Manufacturing Methods The following discussion of the fabrication techniques that can be used in the manufacture of the described charge-coupled devices relates to processes known per se in integrated chain engineering.

Therefore, the description has been somewhat shortened and known steps such as cleaning the platelets, applying photoresist, quenching the channel oxide, alloying the silicon with aluminum contacts and other procedures used are self-explanatory and not discussed in detail.

Reference is now made to Fig. 52.

As shown in Fig. 52a, a thick silicon dioxide layer 2hO (about 10,000 2 thick) is grown thermally on the silicon substrate 2h2. As shown in Fig. 52b, then the portion of the silicon becomes dioxyde, on which the electrodes and the diffused

-V '/ "t V

-71- 'regions D, F and will be formed, etched away.

Then, as shown in Fig. 52c, a thin one.

layer 244 of silicon dioxide (perhaps 500 Å - 2,000 µL thick) grown thermally on the substrate.

As shown in Fig. 52d, a polysilicon layer 246 (about 3,000-5,000 R thick) is then deposited ectaxially over the silicon wafer '242 over both the thin and thick silicon dioxide regions. Then, a mask is used to define the regions of the substrate on which the p + regions will be formed by removing all the polysilicon not used for the control electrodes. Briefly, a photoresist can be applied through this mask and parts of the polysilicon 15 and silicon dioxide bounded by the uncured regions are etched on the photoresist to leave the construction shown in Fig. 52e. areas 248-250 of the substrate. It then becomes a source of p + material. As drill 20 uses, to form the PN junctions, as shown in Fig. 521 *. In this operation, it is noted that the polysilicon areas and, in the other places, the thick silicon dioxide are used as the diffusion mask,

After the above steps, a second, thin, silicon dioxide layer 2,000, 6,000, 2 thick can be applied over the entire sample as shown in FIG. 52g. The function of this oxide is to serve as the dielectric isolation between the polysilicon and the aluminum electrodes, in particular the different phase tokens. This oxide can also be applied before the supply electrodes and drain electrodes are applied. Another mask can then be used to define the etched areas in Fig. 52h. Then find it. etching to leave the polysilicon portions of each electrode pair, as shown at 252-257. Tn fiar. 52h, the d + region in the <5> -72- * substrate may be the supply electrode, the floating region F and the drain electrode D. The electrode 250 may be the control electrode, which is used to connect the floating electrode F to the reset the voltage of the drain electrode D »

The other steps of the process will speak for themselves and will not be explained in more detail. First, an additional silicon dioxide layer is thermally grown or applied to obtain the desired IQ. thickness of the channel oxide under the aluminum electrodes and to insulate the polysilicon electrodes. Subsequently, openings are made with another mask on the p + regions in the substrate and on locations on the polysilicon, which require connection to aluminum conductors or electrodes to be applied later. A continuous aluminum layer can then be applied over the sample. Then, another mask can be used to define the aluminum electrodes. Then parts of the aluminum can be etched away to define the aluminum electrode construction.

During the step shown in Fig. 52h, a portion of the silicon dioxide channel region Zkk can be etched if desired. Whether or not this is done depends on how close it is desired to apply the aluminum electrode 25 to the substrate. If it is desired that the aluminum electrode be as close to the substrate as the polysilicon electrode, parts of the layer should be 2hb in association with the next layer. silicon dioxide is etched away, which will be applied. On the other hand, if the aluminum electrodes are to be more distant from the silicon substrate than the polysilicon electrodes, etching can be stopped, as shown in FIG. 52h.

According to a second manufacturing method, essentially the same construction can be used, but without? * 73- self-aligned diffusion are made by changing the order of cie treatments * In this case, the regions in the n-type substrate can be formed to grow the thick silicon dioxide (before the step 5 shown in Fig. 52 a). As the thick oxide is grown, the p + regions will now be driven deeper into the substrate. In addition, with this technique, one of the masks can be used both for etching the polyisilicon electrodes 252-257 and the polyisilicon control electrode 258. .

While in most of this specification specific materials have been mentioned to further illustrate the invention, it is. clearly, these are just examples. In many cases, other materials than those mentioned may be used. For example, although it is now believed that silicon is a preferred substrate material, for example, other materials such as germanium or gallium arsenide may be used instead. Furthermore, even in the case of silicon, in certain cases preference may be given to p-type substrates instead of n-type substrates,

In p-type substrates, the charge carriers are electrons and their mobility is about twice that of holes 25 and this implies that faster charge coupled structures can be manufactured in this way. Additionally, instead of using poly silicon and aluminum for electrodes, other materials such as poly silicon and one of the molybdenum, or molybdenum gold or platinum-titanium goub, or tungsten aluminum or aluminum silicon alloys or any of a number of such metals are used instead. It is also possible to replace the polyilicon using the two-layer metallization technology. An example is the use of anodized aluminum for the first metal layer (aluminum oxycle in this case. one of the insulators are between this metal electrode and the second electrode of the pair) * Although silicon dioxide has many advantageous properties, other insulating materials such as aluminum oxide and silicon nitride can be used on silicon substrates and many other high quality dielectrics can be used on substrates that are not silicon substrates *

Obviously, the exemplary dimensions apply to the case of systems made using integrated circuit techniques, such as using contact or projection pressures to develop the photoresist. The same type of constructions can be made considerably smaller in size, which means that it can be made to have a much faster performance by using a scanning electron beam to expose the photoresist , or even for making the electrodes directly. Here, alignment between the different layers of the structure can be automated using feedback techniques and a digital computer for control. Before using this manufacturing technique, electrode length measurements are obtained in the order of one micron (10 µm) or less.

/ '*, ft -s f

Claims (5)

1. Shaft guide device of the. charge-coupled type, comprising a substrate, of a semiconductor material of a first gel-array type, characterized by a first and a second surface of the substrate spaced apart, both of which are formed from a semiconductor material of a. second gel-sliding type, the second region comprising an electrically floating region: by means for keeping the first region at a given potential; by control electrodes oc spaced from the substrate and located between the first and second regions; by means for storing a charge near the second area; by means for transferring at least a portion of the stored charge to the second area; by an output line connected to the second region to which output signal can be measured related to the charge transferred to the second region and by means of applying a signal to the control electrodes to control the floating second selectively reset the area to a reference potential. 2. Haul guide device according to claim 1, characterized in that the output line is also connected to another control electrode. 3. A semiconductor device according to claim 2, characterized in that "the other control electrode is spaced" from the substrate. 4. A semiconductor device according to claim 1.1, characterized in that the output line is connected to the gate electrode of the MOS field effect transistor. 5. Semiconductor device according to claim 4. characterized in that the MOS field effect transistor has two regions of. the second conductivity type on the surface of the substrate.