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NL2022578A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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Publication number
NL2022578A
NL2022578A NL2022578A NL2022578A NL2022578A NL 2022578 A NL2022578 A NL 2022578A NL 2022578 A NL2022578 A NL 2022578A NL 2022578 A NL2022578 A NL 2022578A NL 2022578 A NL2022578 A NL 2022578A
Authority
NL
Netherlands
Prior art keywords
solder material
material layer
solder
semiconductor device
electrode
Prior art date
Application number
NL2022578A
Other languages
Dutch (nl)
Other versions
NL2022578B1 (en
Inventor
Nakagawa Masao
Kuwano Ryoji
Shinotake Yohei
Nishimura Hideki
Original Assignee
Shindengen Electric Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Mfg filed Critical Shindengen Electric Mfg
Publication of NL2022578A publication Critical patent/NL2022578A/en
Application granted granted Critical
Publication of NL2022578B1 publication Critical patent/NL2022578B1/en

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
    • B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
    • B23K35/0233—Sheets, foils
    • B23K35/0238—Sheets, foils layered
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
    • B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
    • B23K35/0244—Powders, particles or spheres; Preforms made therefrom
    • B23K35/025—Pastes, creams, slurries
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
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    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00—Articles made by soldering, welding or cutting
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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Abstract

A method of manufacturing a semiconductor device according to the present invention includes: an assembled body forming step of forming an assembled body 50 where a solder material 44 having a structure where a first solder material layer 41 disposed on a surface of an electrode 24 and containing a flux, a second solder material layer 42 disposed on a surface of an electrode connecting member 32 and containing a flux, and a third solder material layer 43 disposed between the first solder material layer 41 and the second solder material layer 42 and containing no flux are stacked is disposed between the electrode 24 and the electrode connecting member 32, and a substrate 10, a semiconductor chip 20 and a lead 30 are disposed in a state where the electrode 24 and the electrode connecting member 32 opposedly face each other with a solder material 44 sandwiched therebetween; and a joining step of joining the electrode 24 and the electrode connecting member 32 to each other via the solder 40. According to the method of manufacturing a semiconductor device of the present invention, a semiconductor device whose reliability is minimally lowered can be manufactured and, at the same time, it is possible to prevent the joining step from becoming cumbersome.

Description

DESCRIPTION
Title of the Invention: METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Technical Field [0001]
The present invention relates to a method of manufacturing a semiconductor device. Background Art [0002]
Conventionally., there has been known a method of manufacturing a semiconductor device where the semiconductor device is manufactured by joining a semiconductor chip and a lead to each other via a solder (for example, see patent literature 1).
[0003]
As shown in Fig. 9, a conventional semiconductor device 900 described in patent literature 1 includes: a substrate 910 having a semiconductor chip mounting surface 912; a semiconductor chip 920 mounted on the semiconductor chip mounting surface 912, the semiconductor chip 920 having a collector electrode 922 formed on a surface of the semiconductor chip 920 which opposedly faces the semiconductor chip mounting surface 912, and an emitter electrode 924 (electrode) and a gate electrode 926 both formed on a surface of the semiconductor chip 920 on a side opposite to the surface w hich opposedly faces the semiconductor chip mounting surface 912, the gate electrode 926 disposed at a position spaced apart from the emitter electrode 924; and a lead 930 having an electrode connecting member 932 which is joined to the emitter electrode 924 via a solder 940.
[0004]
In the conventional semiconductor device 900, the electrode connecting member 932 is joined to the emitter electrode 924 via the solder 940. That is, the semiconductor chip 920 and the lead 930 are directly joined to each other only via the solder 940 (without via an interposing member such as a w ire). Accordingly, the semiconductor device 900 has a large current capacitance and hence, the semiconductor device 900 is a semiconductor device suitably used in electronic equipment (for example, a power source) which uses a large current.
[0005]
The conventional semiconductor device 900 is manufactured by the following manufacturing method (conventional method of manufacturing a semiconductor device). That is, tiie conventional method of manufacturing a semiconductor device includes: an assembled body forming step of forming an assembled body where a substrate 910, a semiconductor chip 920 and a lead 930 are disposed in a state where an emitter electrode 924 and an electrode connecting member 932 opposedly face each other with a solder material sandwiched therebetween; and a joining step of
-) joining the emitter electrode 924 and the electrode connecting member 932 to each other via a solder 940 by solidifying the solder material after melting the solder material.
Citation List
Patent Literatu re [0006]
PTL 1: JP 2010-123686 A
PTL 2: JP 2017-199809 A
Summary of Invention
Technical Problem [0007]
In general, there has been known that, to relax a stress (for example, a .thermal stress) acting on a solder between a semiconductor chip and a lead, it is effective to keep a thickness of the solder at a fixed thickness or more (see patent literature 2, for example).
[0008]
However, when a solder material containing a flux (cream solder in a paste form, for example) is used as the soider material 944, a thickness of the soider material 944 before the joining step becomes excessively large (see Fig. 10(a)). Accordingly, when the lead 930 is disposed on the solder material 944, the solder material 944 collapses and hence, there is a concern that the solder material 944 projects to an undesired place thus giving rise to a drawback that reliability of a manufactured semiconductor device may be lowered (see Fig. 10(b)).
[0009]
On the other hand, when a solder material containing no flux (pellet solder) is used as the solder material 944, an oxide formed on a surface of the solder material cannot be removed by the flux. Accordingly, to prevent lowering of a joining strength between a soider and a semiconductor chip or a joining strength between the soider and a lead, it is necessary to perform the joining step under a particular condition (under a hydrogen atmosphere or the like) thus giving rise to a drawback that the joining step becomes cumbersome.
[0010]
The present invention has been made to overcome the above-mentioned drawbacks, and it is an object of the present invention to provide a method of manufacturing a semiconductor device where a semiconductor device whose reliability’ is minimally lowered can be manufactured and, at the same time, it is possible to prevent a joining step from becoming cumbersome.
Solution to Problem [0011] [1] A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device where a semiconductor device includes: a substrate having a semiconductor chip mounting surface; a semiconductor chip mounted on the semiconductor chip mounting surface and having an electrode formed on a surface on a side opposite to a surface which opposedly faces the semiconductor chip mounting surface; and a lead having an electrode connecting member which is joined to the electrode via a solder. The method of manufacturing a semiconductor device includes: an assembled body forming step of forming an assembled body where a solder material having a structure where a first solder material layer disposed on a surface of the electrode and containing a flux, a second solder material layer disposed on a surface of the electrode connecting member and containing a flux, and a third solder material layer disposed between the first solder material layer and the second solder material layer and containing no flux are stacked is disposed between the electrode and the electrode connecting member, and the substrate, the semiconductor chip and the lead are disposed in a state where the electrode and the electrode connecting member opposedly face each other with the solder material sandwiched therebetween; and a joining step of joining the electrode and the electrode connecting member to each other via the solder by solidifying the solder material after melting the solder material.
[0012]
In this specification,, “solder material” means a solder before an object is joined in the joining step.
[0013] [2] In the method of manufacturing a semiconductor device according to the present invention, it is preferable that both of the first solder material layer and the second solder material layer be made of a solder material in a paste form, and the third solder material layer be formed of a solder material in a solid form, [0014] [3] In the method of manufacturing a semiconductor device according to the present invention, it is preferable that, in the assembled body forming step, a thickness of the third solder material layer may fall within a range of 60% to 90% inclusive of a thickness of the solder material.
[0015] [4] Tn the method of manufacturing a semiconductor device according ίο the present invention, it is preferable that, in the assembled body forming step, a composition of the third solder material layer be equal to a composition of the first solder material layer excluding a flux component and a composition of the second solder material layer exclud ing a flux component, [0016] [5] In the method of manufacturing a semiconductor device according to the present invention, it is preferable that,, in the assembled body forming step, the assembled body be formed such that the first solder material layer and the third solder material layer are disposed on the second electrode, the second solder material layer is disposed on the electrode connecting member and, thereafter, the third solder material layer and the second solder material layer are made to overlap with each other. [0017] [6] In the method of manufacturing a semiconductor device according to the present invention, it is preferable that, in the assembled body forming step, the assembled body be formed such that the first solder material layer, the third solder material layer and the second solder material layer are disposed on the semiconductor chip in this order and. thereafter, the second solder material layer and the electrode connecting member of the lead be made to overlap with each other.
[0018] [7] In the method of manufacturing a semiconductor device according to the present invention, it is preferable that, a thickness of the solder be 300pm or more.
[0019] [8] In the method of manufacturing a semiconductor device according to the present invention, it is preferable that, in the assembled body forming step, tire first solder material layer and the second solder material layer be disposed using a dispenser.
Advantageous Effects of Invention [0020]
In the method of manufacturing a semiconductor device according to the present invention, in the assembled body forming step, the solder material having the third solder material layer disposed between the first solder material layer and the second solder material layer and containing no flux is disposed between the electrode and the electrode connecting member. With the use of such a method, in the third solder material layer containing no flux, there is no vaporization of a flux at the time of performing the joining step (at the time of a reflow) and hence, there is no possibility' that a thickness of the third solder material layer becomes small after the joining step attributed to vaporization of the a flux whereby it is unnecessary to make a thickness of a solder material (a whole solder material formed of the first to third solder material layers) excessively large before the joining step (it is sufficient to set the thickness of the solder material before the joining step to a thickness slightly larger than the thickness of the solder after the joining step). Accordingly, even when the lead is disposed on the solder material, the solder material minimally collapses and hence, it is possible to prevent the solder material from projecting to an undesired place. As a result, it is possible to manufacture a semiconductor device whose reliability is minimally lowered.
[0021]
In the method of manufacturing a semiconductor device according to the present invention, in the assembled body forming step, the solder material having the third solder material layer disposed between the first solder material layer and the second solder material layer and containing no flux is disposed between the electrode and the electrode connecting member. With the use of such a method, a semiconductor device where a thickness of the solder is kept at a fixed thickness or more can be manufactured. Accordingly., a stress (for example, a thermal stress) which acts on a solder between the semiconductor chip and the lead can be relaxed. Also from this point of view, it is possible to manufacture a semiconductor device whose reliability· is minimally lowered. [0022]
In the method of manufacturing a semiconductor device according to the present invention, in the assembled body forming step, the solder material having the first solder material layer disposed on the surface of the electrode and containing a flux and the second solder material layer disposed on the surface of the electrode connecting member of the lead and contain ing a flux is disposed betw een the electrode and the electrode connecting member. Accordingly, joining can be performed in a state where an impurity on surfaces of the electrode, tlie electrode connecting member and the third solder material layer can be removed by the a flux and hence, it is possible to manufacture a semiconductor device which exhibits a high adhesion strength betw een the solder and the semiconductor chip and a high adhesion strength between the solder and the lead. Accordingly, it is unnecessary' to perform a joining step under a particular condition (under a hydrogen atmosphere or the like) for preventing lowering of a joining strength between tlie solder and the semiconductor chip or a joining strength between the solder and the lead whereby it is possible to prevent the joining step from becoming cumbersome.
Brief Description of Draw ings [0023]
Fig. 1 is a view· showing a semiconductor device 1 according to an embodiment 1. Fig. 1(a) is a plan view of the semiconductor device 1, Fig. 1(b) is a cross-sectional view taken along a line A-A in Fig. 1 (a), and Fig. 1(c) is an enlarged cross-sectional view of an essential part of the semiconductor device 1. In Fig. 1(c), the illustration of a resin 80 is omitted for simplifying the description.
Fig. 2 is a flowchart of a method of manufacturing a semiconductor device according to the embodiment 1.
Fig. 3 is a view showing steps of the method of manufacturing a semiconductor device according to the embodiment 1. Fig. 3(a) is a view showing a substrate preparation step, and Fig. 3(b) is a view showing a semiconductor chip mounting step.
Fig. 4 is a view showing steps of the method of manufacturing a semiconductor device according to the embodiment 1. Fig. 4(a) is a view; showing a first solder material layer arrangement step. Fig. 4(b) is a view showing a second solder material layer arrangement step and a third solder material layer arrangement step.
Fig. 5 is a view showing steps of the method of manufacturing a semiconductor device according to the embodiment 1. Fig. 5(a) is a Hew showing a lead frame arrangement step. Fig. 5(b) is a view showing a joining step (reflow step), and Fig. 5(c) is a. view showing a wire bonding step.
Fig. 6 is a view showing steps of a method of manufacturing a semiconductor device according to an embodiment 2. Fig. 6(a) is a view showing a first solder material layer arrangement step. Fig. 6(b) is a view show ing a second solder material layer arrangement step and a third solder material layer arrangement step, and Fig. 6(c) is a view showing a lead frame arrangement step.
Fig. 7 is a view showing steps of a method of manufacturing a semiconductor device according to the modification 1. Fig. 7(a) is a view showing a semiconductor chip arrangement step. Fig. 7(b) is a view showing a first solder material layer arrangement step, a second solder material layer arrangement step and a third solder material layer arrangement step, and Fig. 7(c) is a view showing a lead frame arrangement step.
Fig. 8 is a view showing a semiconductor device 2 according to a modification 2. Fig. 8(a) is a perspective view of the semiconductor device 2, and Fig. 8(b) is a cross-sectional Hew taken along a line B-B in Fig. 8(a). In Fig. 8, symbols 10a, 10b indicate substrates, symbols 12a, 12b indicate semiconductor chip mounting surfaces, symbols 14a, 14b indicate insulating substrates, symbols 18a, 18b indicate heat-radiation metal plates, and symbols 40a, 40b indicate solders.
Fig. 9 is a cross-sectional view showing a conventional semiconductor device 900. In Fig. 9, symbol 946 indicates a solder, symbols 960, 962 indicate terminals, symbol 970 indicates a wire, and symbol 980 indicates a resin.
Fig. 10 is a view show ing a drawback which a conventional method of manufacturing a semiconductor device has. Fig. 10(a) is a view showing a mode of an assembled body before arranging a lead, and Fig. 10(b) is a Hew showing a mode of the assembled body after arranging the lead. Symbols 944, 945 indicate solder materials (solder materials in a paste form).
Description of Embodiments [0024]
Here inafter, a method of manufacturing a semiconductor device according to the present invention is described based on embodiments shown in the drawings. The respective drawings are schematic view s, and do not always strictly reflect actual sizes.
[0025] [Embodiment 1]
1. Configuration of semiconductor device 1 according to embodiment
The semiconductor device 1 according to the embodiment 1 is a semiconductor device where., to relax a stress (a thermal stress, for example) which acts on a solder between a semiconductor chip and a lead, a thickness of lire solder is maintained at a fixed thickness or more. As shown in Fig. 1, the semiconductor device 1 according to the embodiment includes a substrate 10, a semiconductor chip 20, leads 30, 62, 64, solders 40, 46, and a wire 70. These components are resin-sealed by a resin 80 except for a part of external connection terminals of the leads 30, 62. 64 and a part of a heat-radiation metal plate 18.
[0026]
The substrate 10 is a substrate having a semiconductor chip mounting surface 12. A suitable substrate (for example, a printed-circuit board) can be used as the substrate 10. However, in the embodiment 1, a direct copper bonding (DCB) substrate which has an insulating substrate 14, a circuit If? formed on one surface of the insulating substrate 14 and having a semiconductor chip mounting surface 12,. and a heat-radiation metal plate 18 formed on the other surface of the insulating substrate 14 is used. The heat-radiation metal plate 18 is exposed from the resin 80.
[0027]
The semiconductor chip 20 is an insulated gate bipolar transistor (IGBT) having a collector electrode 22 formed on one surface (a surface which opposedly faces the semiconductor chip mounting surface 12) and an emitter electrode 24 (electrode) and a gate electrode 26 formed on the other surface (a surface on a side opposite to a surface which opposedly faces the semiconductor chip mounting surface 12). The gate electrode 26 is disposed at a position spaced apart from the emitter electrode 24.
[0028]
The collector electrode 22 is joined to the semiconductor chip mounting surface 12 of the substrate 10 via the solder 46, and the collector electrode 22 is connected to the outside via the solder 46, the substrate 10 (the circuit 16) and the lead 64.
The emitter electrode 24 is joined to an electrode connecting member 32 of the lead 30 via the solder 40. and the emitter electrode 24 is connected to the outside via the solder 40 and the lead 30 (an external connecting terminal 34).
[0029]
The leads 30, 62, 64 are flat-plate-like metal members and are formed by cutting out portions of a lead frame. The leads 30, 62. 64 respectively have a larger cross-section than a wire so that a large electric current can flow through the leads 30, 62, 64.
The electrode connecting member 32 for connecting the lead 30 with the emitter electrode 24 is formed on one end portion of the lead 30, and an external connecting terminal 34 for connecting the lead 30 to the outside is formed on the other end portion of the lead 30.
One end portion of the lead 62 is connected to the gate electrode 26 via a wire 70, and the other end portion of the lead 62 forms a terminal for connection with the outside.
One end portion of the lead 64 is connected to the circuit 16 which is connected with the collector electrode 22, and the other end portion of the lead 64 forms a terminal for connection with the outside.
[0030]
The solders 40, 46 are made of an alloy or metal having conductivity and adhesiveness. The solders 40, 46 are formed by melting a solder material by heating and by solidifying a melted solder material.
The solder 40 joins the emitter electrode 24 and the electrode connecting member 32 to each other. A thickness (solder thickness) of the solder 40 is larger than a thickness of the solder 46 (the solder between the substrate 10 and the semiconductor chip 20). The thickness of the solder 40 is, for example, 300 gm or more, and is 500 gm, for example. A method of forming the solder 40 is described later.
The solder 46 joins the collector electrode 22 and the semiconductor chip mounting surface 12 to each other. The solder 40 is made of a solder material in a paste form (for example, a so-called cream solder) containing a flux, is disposed on the semiconductor chip mounting surface 12 of the substrate 10 by printing, and joins the substrate 10 and the semiconductor chip 20 to each other by heating using a reflow method. In the solder 46 between the substrate 10 and the semiconductor chip 20, no circumstance is found unlike the solder 40 between the semiconductor chip 20 and the lead 30 where a stress (for example, athermal stress) acting on the solder is relaxed and hence, when a thickness of the solder 46 is increased, a. conduction loss is increased. Accordingly, unl ike the solder 40 between the semiconductor chip 20 and the lead 30, it is preferable that the solder 46 between the substrate 10 and the semiconductor chip 20 have a relatively small thickness (setting a thickness of the solder to a fixed thickness or less).
[0031]
A suitable resin can be used as the resin 80.
[0032]
In the above-mentioned semiconductor device 1 of the embodiment 1, to relax a stress (for example, a thermal stress) which acts on the solder 40 between the semiconductor chip 20 and the lead 30, the solder 40 disposed between the semiconductor chip 20 and the lead 30 maintains a. fixed thickness or more.
In general, to join the semiconductor chip and the lead to each other, a solder material (for example, a so-called cream solder) which contains a flux for removing an impurity (oxide or the like) on a joining surface is used. However, with respect to the solder material which contains a flux, the flux is vaporized during a joining step (during a reflow) and hence, a thickness of the solder is decreased. Accordingly, to use such a solder material for manufacturing the semiconductor device 1 of the embodiment 1, it is necessary' to set a th ickness of a solder material before a joining step (before a reflow step) to a relatively large thickness.
However, when a thickness of a solder material is set relatively large, before a joining step (before a reflow step), there is a concern that when a lead is disposed on the solder material, the solder material collapses so that the solder material projects to an undesired place.
[0033]
In view of the above-mentioned circumstance, in the present invention, the following method of manufacturing a semiconductor device according to the embodiment 1 is used where a thickness of a solder after a joining step (after a reflow step) can be maintained at a fixed thickness or more, and it is possible to prevent an excessi ve increase of a thickness of a solder material before the joining step (before the reflow step).
[0034]
2. A method of manufacturing a semiconductor device according to the embodiment 1
As shown in Fig.2, the method of manufacturing a semiconductor device according to the embodiment 1 includes a substrate preparation step SI00, an assembled body forming step S200, a joining step S300, a wire bonding step S400, a resin sealing step S500, and a lead working step S600. [0035] (1) Substrate preparation step S I 00
In the substrate preparation step S100, the substrate 10 is prepared (see Fig.3 (a)). To be more specific, the substrate 10 is positioned and disposed on a predetermined jig.
[0036] (2) Assembled body forming step S200
In the assembled body forming step S200, an assembled body' 50 where the substrate 10, the semiconductor chip 20 and the lead 30 are disposed is formed in a state where the semiconductor chip mounting surface 12 of the substrate 10 and the collector electrode 22 of the semiconductor chip opposedly face each other with the solder material 45 sandwiched therebetween, and the emitter electrode 24 of the semiconductor chip 20 and the electrode connecting member 32 of the lead 30 opposedly face each other with the solder material 44 (see Fig.5 (a)) sandwiched therebetween (see Fig. 5(a)). The assembled body forming step S200 includes a semiconductor chip mounting step S2I0, a first solder material layer arrangement step S220, a third solder material layer arrangement step S230, a second solder material layer arrangement step S240, and a lead frame arrangement step S250.
[0037] (2-1) Semiconductor chip mounting step S210
In the semiconductor chip mounting step S210, the semiconductor chip 20 is mounted on the semiconductor chip mounting surface 12 of the substrate 10 via the solder material 45 (see Fig. 3(b)). To be more specific, firstly, the solder material 45 in a paste form (for example, a so-called cream solder) is printed on the semiconductor chip mounting surface 12 of the substrate 10. Next, the semiconductor chip 20 is mounted on the semiconductor chip mounting surface 12 in a state where the semiconductor chip mounting surface 12 and the collector electrode 22 of the semiconductor chip 20 opposedlv face each other w ith the solder material 45 sandwiched therebetween.
In the embodiment 1, the solder material 45 is printed on the semiconductor chip mounting surface 12. However, the solder material may be supplied in a suitable method such as supplying the solder material by a dispenser, supplying the solder material in the form of a w ire solder fed by a solder feeder or the like, supplying the solder material by making a melted solder material How onto the semiconductor chip mounting surface 12.
[0038]
Cream solder is a solder formed into a paste form w ith appropriate viscosity by adding a flux to powdery solder. A flux is a component which is vaporized at a high temperature. As a flux, resin-based a flux which uses a rosin, a modified rosin, a synthetic resin or the like as a main component is used. A thixotropic agent, an activator, a solvent for an activator, a dispersion stabilizing agent or the like may be added to a flux.
[0039] (2-2) First solder material layer arrangement step S220
In the first solder material layer arrangement step S220, the first solder material layer 41 made of a solder material in a paste fonn which contains a flux is arranged on the emitter electrode 24 of the semiconductor chip 20 (see Fig. 4(a)). In the first solder material layer arrangement step S220, for example, the first solder material layer 41 is arranged by supplying a solder material in a paste form (for example, a so-called cream solder) which contains a flux onto the emitter electrode 24 by a dispenser D. A thickness of the first solder material layer 41 may be a thickness sufficient for enabling joining of the third solder material layer 43 and the emitter electrode 24.
Various methods are considered as a method of supplying a solder material in a paste form. How ever, fine adjustment of an amount of solder and accuracy in a place to w h ich solder is supplied are necessary for supplying a solder material in a paste form onto the emitter electrode 24 and hence, it is preferable to supply a solder material in a paste fonn using a dispenser.
[0040] (2-3) Third solder material layer arrangement step S230
In the third solder material layer arrangement step S230, the third solder material layer 43 is arranged on the first solder material layer 41 (see lower side of Fig. 4(b)).
The third solder material layer 43 is a plate-like or a film-like soider material (a so-called plate solder) made of a solder material in a solid form which con tains no flux. A thickness of the third solder material layer 43 is a thickness which falls within a range of approximately 60% to 90% inclusive of a thickness of the solder material 44 (see Fig. 5(a)). The thickness of the third soider material layer 43 is a thickness which falls within a range of 75% to 95% of the soider 40 (a. solder after a reflow step). The thickness of the third solder material layer 43 is at least several times as large as a thickness of the first solder material layer 41. In the embodiment 1, the composition (mam components) of the third solder material layer 43 is equal to both the composition (main component) of the first solder material layer 41 from which a flux component is excluded and the composition (main component) of the second solder material layer 42 from which a flux component is excluded. However, the composition of the third solder material layer 43 may be equal to either one of the composition of the first solder material layer 41 or the composition of the second solder material layer 42, or the composition of the third solder material layer 43 may be different from the composition of the first solder material layer 41 and the composition of the second solder material layer 42.
[0041] (2-4) Second solder material layer arrangement step S240
In the second solder material layer arrangement step S240, the second solder material layer 42 made of a solder material in a paste form which contains a flux is arranged on the electrode connecting member 32 of the lead 30 (see upper side of Fig. 4(b)). To be more specific, with respect to the lead frame which forms the leads 30, 62, 64, on a surface of the electrode connecting member 32 which forms a portion of the lead frame which forms the lead 30, for example, the second solder material layer 42 is disposed by supplying a solder material in a paste form (for example, a so-called cream solder) which contains a flux by a dispenser. A thickness of the second solder material layer 42 has the same thickness as the first solder material layer 41, and may be a thickness sufficient for enabling joining of the third solder material layer 43 and the electrode connecting member 32. The second solder material layer arrangement step S240 may be performed in any stage provided that the stage is before the lead frame arrangement step S250.
[0042] (2-5) Lead frame arrangement step S250
In the lead frame arrangement step S250, the lead 30(lead frame) is disposed on the third solder material layer 43 which is disposed on the semiconductor chip 20 such that the second solder material layer 42 on the lead 30 is made to overlap with the third solder material layer (see Fig. 5(a)). At this stage of the operation, the leads 62, 64 in the lead frame are also disposed at predetermined positions. Tn this manner, the solder material 44 having the structure where the first solder material layer 41 disposed on the surface of the collector electrode 22 and containing a flux, the second solder material layer 42 disposed on the surface of the electrode connecting member 32 of the lead 30 and containing a flux, and the third solder material layer 43 disposed between the first solder material layer 41 and the second solder material layer 42 and containing no flux are stacked is disposed between the emitter electrode 24 and the electrode connecting member 32.
[0043]
With such a step, it is possible to form the assembled body 50 where the substrate 10, the semiconductor chip 20 and the lead 30 can be disposed in a state where the semiconductor chip mounting surface 12 of the substrate 10 and the emitter electrode 24 of the semiconductor chip opposedly face each other with the soider material 45 sandwiched therebetween, and the collector electrode of the semiconductor chip 20 and the electrode connecting member 32 of the lead 30 opposedly face each other with the soider material 44 sandwiched therebetween.
[0044] (3) Joining step (reflow step) S300
In joining step (reflow step) S300, the assembled body 50 is conveyed into and is heated by a reflow furnace (not shown in the drawings) so as to melt the solder materials 44,45. After melting the solder materials 44, 45, the soider materials 44, 45 are solidified and formed into the solders 40, 46 (see Fig. 5(b)). Accordingly, the semiconductor chip mounting surface 12 of the substrate 10 and the collector electrode 22 of the semiconductor chip 20 are joined to each other via the solder 46, and the emitter electrode 24 of the semiconductor chip 20 and the electrode connecting member 32 of the lead 30 are joined to each other via the solder 40. At this stage of the operation, a flux is vaporized from the first solder material layer 41 and the second solder material layer 42 which contain a flux and hence, a thickness of the first solder material layer 41 and a thickness of the second solder material layer 42 are decreased.
[0045] (4) Wire bonding step S400
Next, the gate electrode 26 and the lead (lead 62 shown in Fig. I) are connected to each other by the wire 70 (see Fig. 5(c)). A suitable wire is used as the wire 70.
[0046] (5) Resin sealing step S500 and lead working step S600
Next, the assembled body 50 is resin-sealed by the resin 80 except for the external terminals of the leads 30, 62, 64 and the metal plate 18 for heat radiation (resin sealing step S500, not shown in the drawings). Next, the leads 30, 62. 64 are separated from the lead frame by cutting, and working such as bending is applied to predetermined portions (lead working step S600, not shown in the drawings).
The semiconductor device I according to the embodiment 1 can be manufactured in accordance with the above-mentioned steps.
[0047]
3. Advantageous effects acquired by a method of manufacturing a semiconductor device of embodiment 1
In the method of manufacturing a semiconductor device according to the embodiment 1, in the assembled body forming step, the solder material 44 having the third solder material layer 43 disposed between the first solder material layer 41 and the second solder material layer 42 and containing no flux is disposed between the emitter electrode 24 and the electrode connecting member 32. With the use of such a method, in the third solder material layer 43 containing no flux, there is no vaporization of a flux at the time of performing the joining step (at the time of a reflow j and hence, there is no possibility that a thickness of the third solder material layer 43 becomes small after the joining step attributed to vaporization of the flux whereby it is unnecessary’ to make a thickness of the solder material 44 (a whole solder material formed of the first to third solder material layers) excessively large before the joining step (it is sufficient to set the thickness of the solder material 44 before the joining step to a value slightly larger than the thickness of the solder after the joining step). Accordingly, even when the lead 30 (lead frame) is disposed on the solder material 44, the solder material 44 minimally collapses and hence, it is possible to prevent the solder material 44 from projecting to an undesired place. As a result, it is possible to manufacture a semiconductor device whose reliability is minimally lowered.
[0048]
In the method of manufacturing a semiconductor device according to the present invention, in the assembled body forming step, the solder material 44 having the third solder material layer 43 disposed between the first solder material layer 41 and the second solder material layer 42 and containing no flux is disposed between the emitter electrode 24 and the electrode connecting member 32. With the use of such a method, a semiconductor device w here a thickness of the solder 40 is kept at a fixed thickness or more can be manufactured. Accordingly, a stress (for example, a thermal stress) which acts on the solder 40 between the semiconductor chip 20 and the lead 30 can be relaxed. Also from this point of view7, it is possible to manufacture a semiconductor device whose reliability is minimally lowered.
[0049]
In the method of manufacturing a semiconductor device according to the embodiment 1, in the assembled body forming step, the solder material 44 having the first solder material layer 41 disposed on the surface of the emitter electrode 24 and containing a flux and the second solder material layer 42 disposed on the surface of the electrode connecting member 32 of the lead 30 and containing a flux is disposed between the emitter electrode 24 and the electrode connecting member 32. Accordingly, joining can be performed in a state where an impurity on surfaces of the emitter electrode 24, the electrode connecting member 32 and the third solder material layer 43 is removed by the flux and hence, it is possible to manufacture a semiconductor device which exhibits a high joining strength between the solder 40 and the semiconductor chip 20 and a high joining strength between the solder 40 and the lead 30. Accordingly,, it is unnecessary' to perform a joining step under a particular condition (under a hydrogen atmosphere or the like) for preventing lowering of a joining strength between the solder 40 and the semiconductor chip 20 or a joining strength between the solder 40 and the lead 30 whereby it is possible to prevent the joining step from becoming cumbersome.
[0050]
In the method of manufacturing a semiconductor device according to the embodiment 1, both the first solder material layer 41 and the second solder material layer 42 are made of a solder material in a paste form having proper viscosity. Accordingly, it is possible to retain the first solder material layer 41 and the second solder material layer 42 on the emitter electrode 24 and on the electrode connecting member 32 (preventing the occurrence of a phenomenon that a solder or a flux falls down from the electrode because of having too small viscosity) and hence, handling of the first solder material layer 41 and the second solder material layer 42 can be facilitated. Further, the first solder material layer 41 and the second solder material layer 42 are respectively formed by mixing powdery solder and a flux at a proper rate and hence, it is possible to uniformly supply a flux to a joining surface.
[0051]
In the method of manufactu ring a semiconductor device according to the embod iment 1, the third solder material layer 43 is formed of a solder material in a solid form. Accordingly, even when the lead 30 is disposed on the solder material, the third solder material layer 43 minimally takes a collapsed shape and hence, it is possible to prevent solder from projecting to an undesired place with certainty .
[0052]
In the method of manufacturing a semiconductor device according to the embodiment 1, in the assembled body forming step, a thickness of the third solder material layer 43 falls within a range of 60% to 90% inclusive of a thickness of the solder material 44. That is, with respect to the solder material 44, a thickness of the solder material 44 minimally changes even when the lead is disposed on the solder material. Further, a rate of the third solder material layer 43 which minimally takes a collapsed shape in the solder material is large. Accordingly, even when the lead 30 is disposed on the solder material 44, it is possible to prevent the solder material from projecting to an undesired place with more certainty'. A thickness of the first solder material lay er 41 and a thickness of the second solder material layer 42 fall within a range of 10% to 40% inclusive of a thickness of the solder material 44. Accordingly, a rate that the solder material containing a flux occupies in the solder material 44 is small and hence, even when a flux is vaporized during a joining step (during a reflow ), an adverse effect exerted on a thickness of the solder after the joining step can be reduced.
[0053]
The reason that the thickness of the third solder material layer 43 is set to 60% or more is as follows. When the thickness of the third solder material layer 43 is less than 60% of the thickness of the solder material 44, there is a concern that the solder material is liable to take a collapsed shape in the joining step. The reason that the thickness of the third solder material layer 43 is set to less than 90% is as follows. When the thickness of the third solder material layer 43 is equal to or more than 90% of the thickness of tire solder material 44, there is a concern that a rate of the first solder material layer 41 and a rate of the second solder material layer 42 become small and hence, it becomes difficult to increase a joining strength by a flux in the first solde r material layer 41 and the second solder material layer 42. From the above-mentioned point of view, it is more preferable that the thickness of the third solder material layer 43 fall within a range of 65% to 85% inclusive of the thickness of the solder material 44.
[0054]
In the method of manufacturing a semiconductor device according to the embodiment 1. in the assembled body forming step, the thickness of the third solder material layer 43 falls within a range of 60% to 90% inclusive of the thickness of the solder material 44 and hence, a rate of the third solder material layer 43 containing no flux in the thickness of the solder material 44 is large. Accordingly, even when the solder material 44 is heated in the joining step (reflow step), it is possible to reduce a concern that solder scatters due to gasifying of a flux. As a result, short-circuiting or a connection failure attributed to scattered slug minimally occurs and hence, it is possible to manufacture a semiconductor device where reliability is minimally lowered.
[0055]
In the method of manufacturing a semiconductor device according to the embodiment I, in the assembled body forming step, the composition of the third solder material layer 43 is equal to the composition of the first solder material layer 41 from which a flux component is removed or the composition of the second solder material layer 42 from which a flux component is removed. Accordingly, the respective solder material layers are easily joined to each other, and a joining strength between the first solder material layer and the third solder material layer raid a joining strength between the second solder material layer and the third solder material layer after a joining step is further increased.
[0056]
In the method of manufacturing a semiconductor device according to the embodiment I, in the assembled body forming step, the assembled body 50 is formed in such a manner that the first solder material layer 41 and the third solder material layer 43 are disposed on the semiconductor chip 20, the second solder material layer 42 is disposed on the lead 30 and, thereafter, the third solder material layer 43 arid the second solder material layer 42 are made to overlap with each other.
Accordingly, the first solder material layer 41 and the second solder material layer 42 can be formed easily, and handling of the first solder material layer 41 and the second solder material layer 42 can be also facilitated.
[0057]
In the method of manufacturing a semiconductor device according to the embodiment 1, a thickness of the solder 40 is 300 pm or more. Accordingly, a stress (for example, a thermal stress) which acts on the solder 40 between the semiconductor chip 20 and the lead 30 can be relaxed and hence, a drawback such as the occurrence of a crack in the solder 40 minimally occurs. As a result, it is possible to manufacture a semiconductor device whose reliability is minimally lowered. From this point of view, to make the a bove-mentioned drawback min imally occur, it is prefera ble that a thickness of the solder 40 be 400 gm or more, and it is more preferable that a thickness of the solder 40 be 500 pm or more.
[0058]
In the method of manufacturing a semiconductor device according to the embodiment 1. in assembled body forming step S200, the first solder material layer 41 and the second solder material layer 42 are disposed using a dispenser. Accordingly, a solder in a paste form can be accurately and stably supplied and hence, it is possible to form the first solder material layer 41 and the second solder material layer 42 where a solder minimally projects and has small irregularity in thickness, [0059] [Embodiment 2]
A method of manufacturing a semiconductor device according to the embodiment 2 basically has substantially the same steps as the method of manufacturing a semiconductor device according to the embodiment 1. However, the method of manufacturing a semiconductor device according to the embodiment 2 differs from the method of manufacturing a semiconductor device according to the embodiment 1 with respect to the position where a second solder material layer is disposed. That is, in the method of manufacturing a semiconductor device according to the embodiment 2, in assembled body forming step, an assembled body 50 is formed such that, after first solder material layer arrangement step (see Fig. 6(a)), a first solder material layer 41, a third solder material layer 43 and a second solder material layer 42 are disposed on a semiconductor chip 20 (see Fig. 6(b)) and, thereafter, the second solder material layer 42 and a lead 30 (a lead frame on which leads 30, 62, 64 are formed) are made to overlap with each other (see Fig. 6(c)).
[0060]
In this man ner, the method of manufacturing a semiconductor device according to the embodiment 2 differs from the method of manufacturing a semiconductor device according to the embodiment 1 with respect to the position where the second solder material layer is disposed. However, in the same manner as the method of manufacturing a semiconductor device according to the embodiment 1, in the assembled body forming step, a. solder material 44 having the third solder material layer 43 disposed between the first solder material layer 41 and the second solder material layer 42 and containing no flux is disposed between an emitter electrode 24 and an electrode connecting member 32. With the use of such a method, in the third solder material layer 43 containing no flux, there is no vaporization of a flux at the time of performing the joining step (at the time of a reflow) and hence, there is no possibility that a thickness of the third solder material layer 43 becomes small after the joining step attributed to vaporization of a flux whereby it is unnecessary to malce a thickness of the solder material 44 (a whole solder material formed of the first to third solder material layers) excessively large before the joining step (it is sufficient to set the thickness of the solder material 44 before the joining step to a value slightly larger than the thickness of the solder after the joining step). Accordingly, even when the lead 30 is disposed on the solder material 44, the solder material 44 minimally collapses and hence, it is possible to prevent the solder material 44 from projecting to an undesired place. As a result, it is possible to manufacture a semiconductor device whose reliability is minimally lowered.
[0061]
In the method of manufacturing a semiconductor device according to the embodiment 2, in the assembled body forming step, the solder material 44 having the tliird solder material layer 43 disposed between the first solder material layer 41 and the second solder material layer 42 and containing no flux is disposed between the emitter electrode 24 and the electrode connecting member 32. With the use of such a method, a semiconductor device where a thickness of the solder 40 is kept at a fixed thickness or more can be manufactured. Accordingly, a stress (for example, a thermal stress) which acts on the solder 40 between the semiconductor chip 20 and the lead 30 can be relaxed. Also from this point of view, it is possible to manufacture a semiconductor device whose reliability' is minimally lowered.
[0062]
In the method of manufacturing a semiconductor device according to the embodiment 1, in the assembled body forming step, the solder material 44 having the first solder material layer 41 disposed on the surface of the emitter electrode 24 and containing a flux and the second solder material layer 42 disposed on the surface of the electrode connecting member 32 of the lead 30 and containing a flux is disposed between the emitter electrode 24 and the electrode connecting member 32. Accordingly, joining can be performed in a state where an impurity on surfaces of the emitter electrode 24, the electrode connecting member 32 and the third solder material layer 43 is removed by the flux and hence, it is possible to manufacture a semiconductor device which exhibits a high adhesion strength between the solder 40 and the semiconductor chip 20 and a high adhesion strength between the solder 40 and the lead 30. Accordingly, it is unnecessary' to perform a joining step under a particular condition (under a hydrogen atmosphere or the like) for preventing lowering of a joining strength between the solder 40 and the semiconductor chip 20 or a joining strength between the solder 40 and the lead 30 whereby it is possible to prevent the joining step from becoming cumbersome.
[0063]
In the method of manufacturing a semiconductor device according to the embodiment 2, the assembled body 50 is formed such that the first solder material layer 41. the third solder material layer 43 and the second solder material layer 42 are disposed on tlie semiconductor chip 20 and, thereafter, the second solder material layer 42 and the lead 30 are made to overlap with each other. Accordingly, the second solder material layer 42 and the third solder material layer 43 can be easily aligned with each other and hence, a semiconductor device can be easily manufactured. The third solder material layer 43 is a solder material in a solid form and hence, the second solder material layer 42 can be formed stably on the surface of the third solder material layer 43.
[0064]
The method of manufacturing a semiconductor device according to the embodimen t 2 has substantially the same steps as the method of manufacturing a semiconductor device according to the embodiment 1 except for the position where the second solder material layer is disposed. Accordingly, the method of manufacturing a semiconductor device according to the embodiment 2 acquires advantageous effects corresponding to the configurations in the method of manufacturing a semiconductor device according to the embodiment 2 which are equal to the configurations in the method of manufacturing a semiconductor device according to the embodiment 1 among all advantageous effects acquired by the method of manufacturing a semiconductor device according to the embodiment 1.
[0065]
Although the present invention has been described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments. Various modificati ons can be earned out in various modes without departing from the gist of the present invention, and the following modifications are also conceivable, for example.
[0066] (1) The materials, the shapes, the positions, the sizes and the like described in the above-mentioned embodiments are provided for an exemplifying purpose, and can be modified within a range where the advantageous effects of the present invention are not jeopardized.
[0067] (2) hi the above-mentioned embodiment 1, the assembled body 50 is formed such that the first solder material layer 41 and the third solder material layer 43 are disposed on the semiconductor chip 20 and, thereafter, the third solder material layer 43 and the second solder material layer 42 disposed on the surface of the lead 30 are made to overlap with each other. In the embodiment 2, the first solder material layer 41, the third solder material layer 43 and the second solder material layer 42 are disposed on the semiconductor chip 20 and, thereafter, the second solder material layer 42 and the lead 30 are made to overlap with each other. However, the present invention is not limited to such steps. For example, an assembled body 50 may be formed such that, after performing a semiconductor chip mounting step (see Fig. 7(a)), a solder material in a paste form is suppl led to one surface of a third solder material layer 43 and a first solder material layer 41 is disposed on the third solder material layer 43, and a solder material in a paste form is supplied to the other surface of the third solder material layer 43 and a second solder material layer 42 is disposed on the third solder material layer 43 thus forming a solder material 44 (see Fig. 7(b)) and, thereafter, the solder material 44 is disposed on an emitter electrode 24 of a semiconductor chip 20 and, thereafter, a lead 30(lead frame) is disposed on the solder material 44 (see Fig. 7(c)). Alternatively, an assembled body may be formed such tliat a second solder material layer 42, a third solder material layer 43 and a first solder material layer 41 are stacked on an electrode connecting member 32 of a lead 30 (after a solder material 44 is formed) and, thereafter, the solder material 44 and the lead 30 (lead frame) are disposed on an emitter electrode 24 of a semiconductor chip 20.
[0068] (3) In the above-mentioned respective embodiments, an IGBT is used as the semiconductor chip 20. However, the present invention is not limited to such a semiconductor chip. The semiconductor chip 20 may be any other semiconductor chips respectively having three terminals (for example. MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor)). The semiconductor chip 20 may be any other semiconductor chips each having two terminals (for example, diode). The semiconductor chip 20 may be any other semiconductor chips each having four or more terminals (for example, thyristor may be used as a semiconductor element having four terminals).
[0069] (4) In the above-mentioned respective embodiments, the semiconductor device having one semiconductor chip is exemplified as the semiconductor device of the present invention. However, the present invention is not limited to such a semiconductor device. For example, a semiconductor device having two semiconductor chips (see Fig. 8) may be used as the semiconductor device of the present invention, or a semiconductor device having three or more semiconductor chips may be used as the semiconductor device of the present invention.
[0070]
As the semiconductor device having two semiconductor chips, for example, a following semiconductor device where two semiconductor chips are connected to each other in cascode connection is named (see a semiconductor device 2 of modification 2 shown in Fig. 8). In the semiconductor device 2 of modification 2, an emitter electrode 24a of a first semiconductor chip 20a is electrically connected to a first lead 30a, a collector electrode 22a of the first semiconductor chip
20a is connected to a second lead 30b via a circuit 16a of a first substrate 10a, the collector electrode 22a of the first semiconductor chip 20a is electrically connected to an emitter electrode 24b of the second semiconductor chip 20b via a second lead 30b and, although not shown in the drawings, a collector electrode 22 b of the second semiconductor chip 20b is connected to a lead 66 via a circuit 16b. Also in the semiconductor device having such a configuration, a solder between the emitter electrode 24a of the first semiconductor chip 20a and the first lead 30a and a solder between the emitter electrode 24b of the second semiconductor chip 20b and the second lead 30b may be formed of a solder material formed by stacking a first solder material layer, a third solder material layer and a second solder material layer.
[0071] (5) In the above-mentioned respective embodiments, a so-called vertical-type semiconductor device where the collector electrode is disposed on one surface of the semiconductor chip, and the emitter electrode and the gate electrode are disposed on the other surface of the semiconductor chip is used as the semiconductor device of the present invention. However, the present invention is not limited to such a semiconductor device. For example, a so-called lateral-type semiconductor device which has all electrodes on a surface of a semiconductor chip on a side opposite to a substrate side may be used as the semiconductor device of the present invention.
[0072] (6) In the above-mentioned respective embodiments, in arranging the first solder material layer and the second solder material layer, a solder material is supplied using the dispenser. However, the present invention is not limited to such a method using the dispenser. For example, a solder material may be supplied by printing if it is available (this method being considered effective in arranging the second solder material layer 42 on the lead 30 in the embodiment 1 or the like, for example). A solder material may' be supplied in the form of a wire solder fed from a solder feeder or the like. A solder material may be supplied using other methods.
Reference Signs List [0073]
1: semiconductor device
10, 10a, 10b: substrate
12, 12a, 12b: chip mounting surface
14, 14a, 14b: insulating substrate
16, 16a, 16b: circuit
18, 18a, 18b: metal plate for heat radiation
20, 20a, 20b: chip
22. 22a, 22b: collector electrode (first electrode)
24, 24a, 24b: emitter electrode (second electrode)
26: gate electrode
30, 30a, 30b, 62, 64, 66: lead
32: electrode connecting member
34: external connection terminal
40, 40a, 40b, 46: solder
41: first solder material layer
42: second solder material layer
43: third solder material layer
44, 45: solder material
50: assembled body
70: wire
80: resin

Claims (7)

ConclusiesConclusions 1. Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij een halfgeleiderinrichting omvat:A method of manufacturing a semiconductor device wherein a semiconductor device comprises: een substraat met een halfgeleiderchip-montageoppervlak;a substrate with a semiconductor chip mounting surface; een halfgeleiderchip gemonteerd op het halfgeleiderchip-montageoppervlak en een elektrode heeft die is gevormd op een oppervlak aan een zijde tegenover een oppervlak dat tegengesteld richting het halfgeleiderchip-montageoppervlak is gericht;a semiconductor chip mounted on the semiconductor chip mounting surface and having an electrode formed on a surface on a side opposite to a surface facing opposite to the semiconductor chip mounting surface; en een bedrading (Engels: “lead) met een elektrodeverbindingslid dat is verbonden aan de elektrode via een soldering, de werkwijze voor het vervaardigen van een halfgeleiderinrichting omvattende: een geassembleerd lichaam-vormingsstap voor het vormen van een geassembleerd lichaam waarbij een soldeermateriaal een structuur heeft waarbij een eerste soldeermateriaallaag geplaatst op een oppervlak van de elektrode en een flux bevat, een tweede soldeermateriaallaag geplaatst op een oppervlak van het elektrodeverbindingslid en een flux bevat, een derde soldeermateriaallaag geplaatst tussen de eerste soldeermateriaallaag en de tweede soldeermateriaallaag en geen flux bevat zijn gestapeld en geplaatst tussen de elektrode en het elektrodeverbindingslid, en het substraat, de halfgeleiderchip en de bedrading zijn geplaatst in een toestand waarbij de elektrode en het elektrodeverbindingslid tegengesteld naar elkaar zijn gekeerd met het soldeermateriaal daartussen ingeklemd; en een verbindingsstap voor het aan elkaar verbinden van de elektrode en het elektrodeverbindingslid via de soldering middels het stollen van het soldeermateriaal na het smelten van het soldeermateriaal.and a lead with an electrode connection member connected to the electrode via a soldering, the method for manufacturing a semiconductor device comprising: an assembled body-forming step for forming an assembled body wherein a solder material has a structure wherein a first solder material layer placed on a surface of the electrode and containing a flux, a second solder material layer placed on a surface of the electrode connection member and containing a flux, a third solder material layer placed between the first solder material layer and the second solder material layer and no flux containing are stacked and placed between the electrode and the electrode connection member, and the substrate, the semiconductor chip and the wiring are placed in a state where the electrode and the electrode connection member are opposed to each other with the soldering material sandwiched between them; and a connecting step for connecting the electrode and the electrode connecting member to each other via the soldering by solidifying the solder material after melting the solder material. 2. Werkwijze voor het vervaardigen van een halfgeleiderinrichting volgens conclusie 1, waarbij beide van de eerste soldeermateriaallaag en de tweede soldeermateriaallaag zijn gemaakt van een soldeermateriaal in een pastavorm, en de derde soldeermateriaallaag is gevormd uit een soldeermateriaal in een vaste vorm.A method for manufacturing a semiconductor device according to claim 1, wherein both of the first solder material layer and the second solder material layer are made of a solder material in a paste form, and the third solder material layer is formed of a solder material in a solid form. 3. Werkwijze voor het vervaardigen van een halfgeleiderinrichting volgens conclusie 1 of 2, waarbij, in de geassembleerd lichaam-vormingsstap, een dikte van de derde soldeermateriaallaag binnen een bereik van 60% tot 90% valt inclusief een dikte van het soldeermateriaal.The method for manufacturing a semiconductor device according to claim 1 or 2, wherein, in the assembled body-forming step, a thickness of the third solder material layer falls within a range of 60% to 90% including a thickness of the solder material. 4. Werkwijze voor het vervaardigen van een halfgeleiderinrichting volgens een van de conclusies 1 - 3, waarbij in de geassembleerd lichaam-vormingsstap, een samenstelling van de derde soldeermateriaallaag gelijk is aan een samenstelling van ten minste een van een samenstelling van de eerste soldeermateriaallaag exclusief een fluxcomponent en een samenstelling van de tweede soldeermateriaallaag exclusief een fluxcomponent.A method for manufacturing a semiconductor device according to any of claims 1 to 3, wherein in the assembled body forming step, a composition of the third solder material layer is equal to a composition of at least one of a composition of the first solder material layer excluding a flux component and a composition of the second solder material layer excluding a flux component. 5. Werkwijze voor het vervaardigen van een halfgeleiderinrichting volgens een van de conclusies 1-4, waarbij, in de geassembleerd lichaam-vormingsstap, het geassembleerde lichaam zodanig wordt gevormd dat de eerste soldeermateriaallaag en de derde soldeermateriaallaag op de elektrode zijn geplaatst, de tweede soldeermateriaallaag op het elektrodeverbindingslid wordt geplaatst en, daama, de derde soldeermateriaallaag en de tweede soldeermateriaallaag met elkaar worden overlapt.A method for manufacturing a semiconductor device according to any of claims 1-4, wherein, in the assembled body-forming step, the assembled body is formed such that the first solder material layer and the third solder material layer are placed on the electrode, the second solder material layer is placed on the electrode connection member and, thereafter, the third solder material layer and the second solder material layer are overlapped with each other. 6. Werkwijze voor het vervaardigen van een halfgeleiderinrichting volgens een van de conclusies 1-4, waarbij in de geassembleerd lichaam-vormingsstap, het geassembleerde lichaam zodanig is gevormd dat de eerste soldeermateriaallaag, de derde soldeermateriaal laag en de tweede soldeermateriaallaag zijn geplaatst op de halfgeleiderchip en, daarna, de tweede soldeermateriaallaag en het elektrodeverbindingslid van de bedrading met elkaar worden overlapt.A method for manufacturing a semiconductor device according to any of claims 1-4, wherein in the assembled body-forming step, the assembled body is formed such that the first solder material layer, the third solder material layer and the second solder material layer are placed on the semiconductor chip and, thereafter, the second solder material layer and the electrode connection member of the wiring are overlapped with each other. Ί. Werkwijze voor het vervaardigen van een halfgeleiderinrichting volgens een van de conclusies 1-6, waarbij een dikte van de soldering 300μιη of meer is.Ί. A method for manufacturing a semiconductor device according to any of claims 1-6, wherein a thickness of the soldering is 300 µl or more. 8. Werkwijze voor het vervaardigen van een halfgeleiderinrichting volgens een van de conclusies 1-7, waarbij, in de geassembleerd lichaam-vormingsstap, de eerste soldeermateriaallaag en de tweede soldeermateriaallaag worden geplaatst met gebruik van een dispenser.A method for manufacturing a semiconductor device according to any of claims 1-7, wherein, in the assembled body-forming step, the first solder material layer and the second solder material layer are placed using a dispenser.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH113952A (en) * 1997-04-30 1999-01-06 Internatl Business Mach Corp <Ibm> Multilayered solder sealed band for semiconductor substrate and method thereof
JP2002261435A (en) * 2001-03-02 2002-09-13 Cimeo Precision Co Ltd Structure for laser diode sub-mount and its manufacturing method
JP2010123686A (en) 2008-11-18 2010-06-03 Renesas Technology Corp Semiconductor device and manufacturing method thereof
US20120001349A1 (en) * 2010-06-30 2012-01-05 Toyota Jidosha Kabushiki Kaisha Method of manufacturing semiconductor modules and semiconductor module
JP2017199809A (en) 2016-04-27 2017-11-02 三菱電機株式会社 Power semiconductor device

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3243834B2 (en) * 1992-05-26 2002-01-07 三菱電機株式会社 Solder material and joining method
JP3347279B2 (en) * 1997-12-19 2002-11-20 三菱電機株式会社 Semiconductor device and method of manufacturing the same
JP2001332686A (en) * 2000-05-19 2001-11-30 Sansha Electric Mfg Co Ltd Semiconductor module
JP4985129B2 (en) * 2007-06-12 2012-07-25 三菱電機株式会社 Bonded body, electronic module, and bonding method
JP2012049182A (en) * 2010-08-24 2012-03-08 Fuji Electric Co Ltd Method of manufacturing semiconductor device
JP2013183038A (en) * 2012-03-02 2013-09-12 Mitsubishi Electric Corp Semiconductor device
JP2014157858A (en) * 2013-02-14 2014-08-28 Fuji Electric Co Ltd Semiconductor device manufacturing method
TWI529880B (en) * 2013-06-19 2016-04-11 日月光半導體製造股份有限公司 Semiconductor device, semiconductor package and method for making the same
JP7033889B2 (en) * 2017-11-10 2022-03-11 三菱電機株式会社 Power semiconductor devices, manufacturing methods for power semiconductor devices, and power conversion devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH113952A (en) * 1997-04-30 1999-01-06 Internatl Business Mach Corp <Ibm> Multilayered solder sealed band for semiconductor substrate and method thereof
JP2002261435A (en) * 2001-03-02 2002-09-13 Cimeo Precision Co Ltd Structure for laser diode sub-mount and its manufacturing method
JP2010123686A (en) 2008-11-18 2010-06-03 Renesas Technology Corp Semiconductor device and manufacturing method thereof
US20120001349A1 (en) * 2010-06-30 2012-01-05 Toyota Jidosha Kabushiki Kaisha Method of manufacturing semiconductor modules and semiconductor module
JP2017199809A (en) 2016-04-27 2017-11-02 三菱電機株式会社 Power semiconductor device

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