NL2005730C2

NL2005730C2 - Photovoltaic cell and a method for producing such a photovoltaic cell.

Info

Publication number: NL2005730C2
Application number: NL2005730A
Authority: NL
Inventors: Lis Karen Nanver
Original assignee: Tempress Systems B V
Priority date: 2010-11-19
Filing date: 2010-11-19
Publication date: 2012-05-22
Also published as: WO2012067509A1; TW201222639A

Description

Photovoltaic cell and a method for producing such a photovoltaic cell Field of the invention

The present invention relates to a photovoltaic cell and a method of producing such 5 a photovoltaic cell.

Background of the invention

From the prior art, a solid state photovoltaic cell is known as to convert the energy of sunlight or another light source directly into electricity by the photovoltaic effect. In 10 general, the photovoltaic effect is described as the generation of a potential difference at the junction of two different materials when receiving energy from sunlight or other radiation.

The general processes of the photovoltaic effect comprises: 15 · generating the charge carriers due to the absorption of photons in the materials that form a junction; • separating the photo-generated charge carriers in the junction; • collecting the photo-generated charge carriers at the terminals of the junction.

20 Figure 1 schematically shows a cross-sectional view of a typical structure of a solid state photovoltaic cell from the prior art. In figure 1, a typical photovoltaic cell (or solar cell) 1 comprises a silicon substrate base layer 9 for generating photon-generated carriers, a silicon based emitter layer 7 arranged on top of the base layer 9 for collecting the photon-generated carriers, a front contact 3 connected to the emitter layer 7, a back 25 surface field (BSF) layer 11 arranged on the bottom of the base layer 9 for counteracting the diffusion of minority photon-generated carriers to reach a rear contact 15, the rear contact 15 connected to the BSF layer 11, an anti-reflection coating (ARC) layer 5 arranged on top of the emitter layer 7 for decreasing the reflection of light from the photovoltaic cell 1. The ARC layer 5 may serve as a passivation layer for passivating the 30 surface of the photovoltaic cell 1 and optionally acting as hydrogen source for bulk passivation.

Under certain circumstances the BSF layer 11 may serve as passivation layer. However, a passivation layer 13 may be arranged on the bottom of the BSF layer 11 for 2 passivating the surface of the photovoltaic cell 1 and reducing the surface recombination in the rear side.

Typically, the BSF layer 11 is made of, with the same type as the base layer, high doped n type material or p type material. An electric field is formed in the BSF layer 11 5 which introduces a barrier to minority photon-generated carriers to reach the rear contact 15, thus reduces the recombination in the rear contact 15.

An internal electric field formed by a p-n junction between the base layer 9 and the emitter layer 7 in the photovoltaic cell 1 that facilitates the separation of the photongenerated carrier pairs, i.e., electrons and holes.

10 The major obstacles of the photovoltaic cell in the prior art document are relatively low cell efficiency, which is limited by optical and electrical losses, and relatively high cell cost.

Summary of the invention 15 It is an objective of the invention to reduce or mitigate the disadvantages from the prior art.

This objective is achieved by a photovoltaic cell comprising: a semiconductor substrate having a first surface and a second surface; an emitter layer arranged on the first surface side of the semiconductor substrate; an anti-reflection coating 20 (ARC) layer arranged on top of the emitter layer; a back surface field (BSF) layer arranged on the second surface of the semiconductor substrate; a front contact arranged on the emitter layer; a rear contact arranged on the BSF layer wherein any one of the emitter layer and the BSF layers arranged on the first surface or the second surface, respectively, of the semiconductor substrate is formed by an amorphous boron layer.

25 According to an aspect of the invention, an amorphous boron-layer is applied on the first surface to form an emitter of a n-type photovoltaic cell.

Thereto, the amorphous boron-layer is contacted by a front-contact metal with relatively better electrical contact, i.e. provides relatively low contact resistance, and consequently relatively less metal is needed, which leaves more surface area for photon 30 collection. Thus, the Schottky-contact directly to the semiconductor emitter layer is eliminated, and the cell efficiency and the reliability of the emitter series resistance are improved.

3

Moreover, the emitter layer that can be contacted is formed uniformly over the whole front surface and no lithography is needed to place the contacts, for example on the regions that are more highly-doped than others. High doping is normally needed to give low contact resistance.

5 Furthermore, a p-n junction is formed at a relatively low temperature between the amorphous boron-layer and a first surface of a semiconductor substrate base layer of the n-type photovoltaic cell. Together with the amorphous boron layer, the p-n junction lowers the saturation current, i.e. dark current, and improves the electric power output of the photovoltaic cell.

10 When applying the amorphous boron layer as BSF layer, the processing cost is reduced by combining the back surface field (BSF) layer and the passivation layer as one layer. The production process of the photovoltaic cell is also simplified.

According to an aspect of the invention, there is provided a shallow boron-doped region in between the amorphous boron-layer and the semiconductor substrate base layer 15 of the n-type photovoltaic cell.

Advantageously, a considerable boron drive into the semiconductor substrate base layer, due to the relatively high boron-concentration gradient at the surface, improves the reproducibility of the photovoltaic cell.

According to an aspect of the invention, there is provided a photovoltaic cell as 20 described above, wherein the photovoltaic cell comprises a passivation layer, and the BSF layer and the passivation layer are combined as a single BSF and passivation layer.

According to an aspect of the invention, there is provided a photovoltaic cell as described above, wherein the single BSF and passivation layer is formed by amorphous boron.

25 According to an aspect of the invention, there is provided a photovoltaic cell as described above, wherein a boron-semiconductor material mixed layer is arranged between the amorphous boron layer and the semiconductor substrate layer of the photovoltaic cell.

According to an aspect of the invention, there is provided a photovoltaic cell as 30 described above, wherein the semiconductor substrate is a p-type semiconductor substrate and the emitter layer is a n-type emitter layer.

4

According to an aspect of the invention, there is provided a photovoltaic cell as described above, wherein the emitter layer is embodied by the amorphous boron layer, and the emitter layer is a p-type emitter layer.

According to an aspect of the invention, there is provided a photovoltaic cell as 5 described above, wherein a boron-semiconductor material mixed layer is arranged between the emitter layer and the semiconductor substrate layer of the photovoltaic cell.

According to an aspect of the invention, there is provided a photovoltaic cell as described above, wherein the semiconductor substrate is a silicon substrate.

According to an alternative aspect of the invention, there is provided a photovoltaic 10 cell as described above, wherein the semiconductor substrate is one selected from a germanium substrate, a silicon-carbide substrate and a diamond-like substrate or layer.

According to an aspect of the invention, there is provided a photovoltaic cell as described above, wherein the base layer contains one or more buried dot structures, the dot structures being formed from Si, Ge or an III-V compound.

15 According to an aspect of the invention, there is provided a method of manufacturing a photovoltaic cell, comprising: providing a p-type bulk doped semiconductor substrate with a first surface and a second surface opposite thereto; depositing and/or diffusing of a n-type emitter surface on top of the first surface; removing the native oxide on the second surface; forming a layer of 20 amorphous boron on top of the second surface such that an effective p++ layer is formed.

According to an aspect of the invention, there is provided a method as described above, further comprising: covering the first surface by an ARC/passivation layer; forming contacts on both surfaces and fire these at least through the ARC/passivation 25 layer.

According to an aspect of the invention, there is provided a method as described above, wherein the amorphous boron is formed at a temperature below about 700°C.

According to an aspect of the invention, there is provided a method as described above, wherein the formation temperature of the amorphous boron layer is between about 30 500°C and about 700°C.

According to an aspect of the invention, there is provided a method as described above, wherein the formation temperature of the amorphous boron layer is minimal 300°C.

5

According to an aspect of the invention, there is provided a method of manufacturing a photovoltaic cell, comprising: providing a n type semiconductor substrate with a first surface and a second surface opposite thereto; depositing and/or diffusing a n++-doped back surface field on top of the 5 second surface of the semiconductor substrate; removing the native oxide on the first surface; forming a layer of amorphous boron on top of the first surface such that an effective p-n junction is formed.

According to an aspect of the invention, there is provided a method as described above, further comprising: 10 covering the first surface by an ARC/passivation layer; depositing contacts on both surfaces and fire these at least through the ARC/passivation layer.

According to an aspect of the invention, there is provided a method as described above, wherein the amorphous boron is formed at a temperature below about 700°C. According to an aspect of the invention, there is provided a method as described 15 above, wherein the semiconductor substrate is one selected from a silicon substrate, a germanium substrate, a silicon carbide substrate and a diamond-like substrate or layer.

Brief description of the drawings

The invention will be explained in detail with reference to some drawings that are 20 only intended to show embodiments of the invention and not to limit the scope. The scope of the invention is defined in the annexed claims and by its technical equivalents.

The drawings show:

Figure 1 shows a cross-sectional view of a typical structure of a prior art p-type bifacial photovoltaic cell.

25 Figure 2 shows a cross-sectional view of an embodiment with an amorphous boron-layer arranged to a first surface of a semiconductor substrate of an n-type photovoltaic cell according to the invention.

Figure 3 shows a cross-sectional view of an embodiment with an amorphous boron-layer arranged to a second surface of a semiconductor substrate of a p-type photovoltaic cell 30 according to the invention.

Figure 4 shows a flow diagram of an example of a method for manufacturing a photovoltaic cell according to an embodiment of the invention.

6

Figure 5 shows a flow diagram of an example of a method for manufacturing a photovoltaic cell according to an embodiment of the invention.

Figure 6a shows the IV-characteristics of the photovoltaic cell with relatively high saturation current.

5 Figure 6b shows the IV-characteristics of the photovoltaic cell with relatively low saturation current.

Detailed description of embodiments

In figure 2, an embodiment of the invention with an amorphous boron layer 10 arranged to a first surface of a semiconductor substrate of a n-type photovoltaic cell is shown. A n-type photovoltaic cell 101 comprises a n-type semiconductor substrate base layer 109, with a first surface on top and a second surface on the bottom, for generating photon-generated carriers, an amorphous boron emitter layer 107 arranged on top of the n-type semiconductor substrate base layer 109 for collecting the photon-generated carriers, a 15 front contact 103 connected to the amorphous boron emitter layer 107, a n+ type back surface field (BSF) layer 111 arranged on the bottom of the base layer 109, a rear contact 115 connected to the BSF layer 111, an anti-reflection coating (ARC) layer 105 arranged on top of the amorphous boron emitter layer 107 for decreasing the reflection of light from the front side of the n-type photovoltaic cell 101. Further, a passivation layer 113 is 20 arranged on the bottom of the BSF layer 111 for passivating the surface of the photovoltaic cell 101 and reducing the surface recombination in the rear side.

The ARC layer 105 may also serve as passivation layer for passivating the surface of the photovoltaic cell 101 and optionally for acting as hydrogen source for bulk passivation.

25 The passivation layer 113 may also serve as anti-reflection coating layer for decreasing the reflection of light from the rear side of the n-type photovoltaic cell 101.

According to an embodiment of the invention, an interface with the function of a p-n junction is formed at relatively low temperature, e.g. below 700°C, or between about 500°C and about 700°C, or even down to about 300°C, between the amorphous boron 30 emitter layer 107 and the first surface of the semiconductor substrate base layer 109.

It is observed that already the presence of the interface between the amorphous boron layer and the n-type semiconductor substrate base layer, i.e., in case of practically no boron doping of the silicon substrate, provides the function of a p-n junction.

7

Note that, when the temperature is higher than 750°C, the amorphous boron emitter layer 107 may not be formed due to desorption of boron from the substrate surface and/or reaction with the semiconductor material. Also there may be a deeper boron doping profile into the n-type semiconductor substrate base layer 109. The thickness of the 5 amorphous boron emitter layer formed is typically in the nm-range up to about 1-10 nm.

The amorphous boron layer and the p-n junction suppress the electron injection from the n-type semiconductor substrate base layer 109, to further separate the electron-hole pairs, and thus lower the saturation current, i.e. dark current, and improve the electric power output of the photovoltaic cell 101.

10 According to an embodiment of the invention, the interface of the p-n junction is formed in a relatively low temperature, e.g. below 700°C, and is substantially damage-free, i.e. having relatively low defect density.

According to an embodiment of the invention, the front contact 103 and the rear contact 115 may be formed from metallic stacks, such as Aluminum (Al), Silver (Ag), 15 Nickel (Ni), Copper (Cu), or any conductive material compatible with solar technology.

The amorphous boron emitter layer 107 advantageously acts as a diffusion barrier layer between the n-type semiconductor substrate base layer 109 and the front contact 103. The diffusion barrier layer function may prevent a relatively destructive silicidation process made by the front contact metal and the semiconductor material. The silicidation 20 process may increase the emitter contact resistance due to the dopant depletion at the silicide-semiconductor interface. Thus, the direct contact between the amorphous boron emitter layer 107 and the front contact 103 provides a relatively low contact resistance and consequently relatively less metal coverage is needed, which provides more surface area for photon collection.

25 According to an embodiment, the thickness of the amorphous boron emitter layer 107 is about 3 nm, and the amorphous boron emitter layer 107 functions as a tunneling layer.

According to an embodiment of the invention, the n-type semiconductor substrate base layer 109 may further comprise a shallow boron-doped region emitter layer (not 30 shown in figure 2) in between the amorphous boron emitter layer 107 and the semiconductor substrate base layer 109. The shallow boron-doped region emitter layer is formed at a relatively lower temperature than what is normally used to drive-in dopants or to anneal/activate implanted dopants, e.g. below 700°C, or between about 500°C and 8 about 700°C, or down to about 300°C, when depositing the amorphous boron emitter layer 107 on top of the semiconductor substrate base layer 109.

Moreover, doping of the silicon substrate from the amorphous boron layer is more reliable than doping directly from the gas phase, also for diffusion temperatures above 5 700°C. For doping temperatures above 700°C which could be achieved by firing or a rapid thermal annealing step (RTA), it is advantageous to first deposit an amorphous boron layer below about 700°C. The high gradient in boron concentration at the silicon surface and the high total amount of boron atoms in the amorphous boron layer provides a relatively more effective p+ doping source. The shallow boron-doped region layer 10 provides a considerable doping of boron to the semiconductor substrate base layer 109 that improves the reproducibility of the emitter doping, due to the relatively high boron-concentration gradient at the surface of the semiconductor substrate base layer 109, i.e. at the interface with the amorphous boron emitter layer 107.

The shallow boron-doped region emitter layer further suppresses the minority 15 carrier (electrons) injection from the n-type semiconductor substrate base layer 109, to further separate the photon-generated electron-hole pairs, and thus improve the efficiency of electric power output. According to the invention, the amorphous boron layer is even more effective in suppressing the minority carrier (electron) injection.

Due to the fact that the shallow boron-doped region emitter layer is covered with the 20 amorphous boron emitter layer 107, the direct Schottky-contact between the shallow boron-doped region emitter layer and the front contacts 103 is eliminated.

According to a preferred embodiment, a doping temperature for driving boron into the n-type semiconductor substrate base layer 109 below about 700°C is selected. Therefore, a controllable thickness of the shallow boron-doped region emitter layer in the 25 n-type semiconductor substrate base layer 109 and a controllable thickness of the amorphous boron emitter layer 107 are formed in the nm-range, e.g. the thickness may be down to less than 1 nm.

According to an embodiment of the invention, a boron-silicon mixed layer may be formed between the amorphous boron emitter layer 107 and the semiconductor substrate 30 base layer 109. The boron-silicon mixed layer may be formed at a relatively low temperature, e.g. below 700°C, or between about 500°C and about 700°C, or down to about 300°C, when depositing the amorphous boron emitter layer 107 on top of the semiconductor substrate base layer 109.

9

According to an embodiment of the invention, the n-type semiconductor substrate base layer 109 may further comprise a blanket layer (not shown in figure 2). The blanket layer may comprise a plurality of buried dots, that may be quantum dots, of other material than the semiconductor material of the substrate, e.g. Germanium (Ge) or some types of 5 III-V compounds. The dots may be buried below an epitaxial layer of the same material as the substrate on which the amorphous boron layer is to be deposited. The dots may increase the efficiency of the photovoltaic cell 101 for absorbing energy from light sources with relatively high wavelength, e.g. using Germanium (Ge) for Infrared (IR) light, or from light sources with relatively low wavelength, e.g. using Gallium arsenide 10 (GaAs) for Ultraviolet (UV) light. The blanket layer is formed at a relatively low temperature, e.g. below 700°C.

Note that the dots are not stable above about 700°C as their material will intermix with the semiconductor material in the n-type semiconductor substrate base layer 109 at such a high temperature.

15 According to an embodiment of the invention, the semiconductor substrate base layer 109 is a silicon substrate base layer. In an alternative embodiment of the invention, the semiconductor substrate base layer 109 is a germanium substrate base layer.

In figure 3, an embodiment of the invention with an amorphous boron layer arranged to a second surface of a p-type semiconductor substrate of a photovoltaic cell is 20 shown. A photovoltaic cell 201 comprises a p-type semiconductor substrate base layer 209, with a first surface on top and a second surface on the bottom, for generating photongenerated carriers, an amorphous boron layer 211 arranged on the bottom of the p-type semiconductor substrate base layer 209, for providing an effective p++-doping for the p-type semiconductor substrate base layer 209 , a n-type emitter layer 207 arranged on top 25 of the p-type semiconductor substrate base layer 209 for collecting the photon-generated carriers, a front contact 203 connected to the n-type emitter layer 207, a rear contact 215 connected to the amorphous boron layer 211, an anti-reflection coating (ARC) layer 205 arranged on top of the emitter layer 207 for decreasing the reflection of light from the photovoltaic cell 201. Additionally, the ARC layer may serve as a passivation layer for 30 passivating the surface of the photovoltaic cell 201 and reducing the surface recombination at the front side.

10

Note that the amorphous boron layer 211 may serve also as a passivation layer for passivating the surface of the photovoltaic cell 201 and reducing the surface recombination.

According to an embodiment of the invention, the back surface field (BSF) layer 5 and passivation layer of the photovoltaic cell are implemented as one single amorphous boron layer 211, since the amorphous boron has passivating properties and provides a relatively more effective p+-doping to the p-type semiconductor substrate base layer 209.

According to an embodiment of the invention, an effective p++ layer (not shown in figure 3) is formed at relatively low temperature, e.g. below 700°C, or between about 10 500°C and about 700°C, or down to about 300°C, between the amorphous boron layer 211, i.e. p++-doping layer, and the second surface of the p-type semiconductor substrate base layer 209. This is due to the fact that, when the temperature is higher than 750°C, the amorphous boron layer 211 may not be formed and all the boron therein may be doped to the p-type semiconductor substrate base layer 209 due to desorption from the surface and 15 boron reaction with silicon. There will also be a deeper boron doping of the n-type semiconductor substrate base layer 209.

According to an embodiment of the invention, the interface of the amorphous boron layer 211 and the base layer 209 is formed at a relatively low temperature, e.g. below 700°C, and is substantially damage-free, i.e. with relatively low defect density. The lower 20 the formation temperature, the lower the thermally induced effects on other layers will be.

According to an embodiment of the invention, the p-type semiconductor substrate base layer 209 further comprises a shallow boron-doped region in between the amorphous boron layer 211 and the p-type semiconductor substrate base layer 209.

According to an embodiment of the invention, the p-type semiconductor substrate 25 base layer 209 may further comprise a shallow boron-doped region layer (not shown in figure 3) in between the amorphous boron layer 211 and the p-type semiconductor substrate base layer 209. The shallow boron-doped region layer is formed at a relatively lower temperature than what is normally used to drive-in dopants or to anneal/activate implanted dopants, e.g. below 700°C, or between about 500°C and about 700°C, or down 30 to about 300°C. This is due to the fact that, when the temperature is higher than 750°C, the amorphous boron layer 211 may not be formed due to desorption from the surface and boron reaction with the Si. There will also be a deeper boron doping of the n-type semiconductor substrate base layer 209.

11

Moreover, the doping temperature below 700°C is more reliable than the doping temperature above 700°C, due to the existence of the amorphous boron layer 211, which provides a relatively more effective p+ doping region.

The deposition of the amorphous boron layer produces an effective p++-doping of 5 the surface of the semiconductor substrate base layer 209, wherein the reproducibility is improved, due to the relatively high boron-concentration gradient at the surface of the semiconductor substrate base layer 209.

The shallow boron-doped region layer further suppresses the electron injection from the p-type semiconductor substrate base layer 209, to further separate the photon-10 generated carrier electron-hole pairs, and thus improve the efficiency of the electric power output.

According to a preferred embodiment, a doping temperature for driving boron into the silicon below about 700°C is selected. Therefore, the thickness of the shallow boron-doped region layer in the p-type semiconductor substrate base layer 209 is formed in a 15 controllable nm-range, and consequently a thickness of the amorphous boron layer 211 is created in the range of a few nm below about 10 nm, e.g. the thickness may be down to less than 1 nm.

According to an embodiment of the invention, a boron-silicon mixed layer can be formed between the amorphous boron layer 211 and the p-type semiconductor substrate 20 base layer 209. The boron-silicon mixed layer is formed at a relatively low temperature, e.g. below 700°C, or between about 500°C and about 700°C, or down to about 300°C.

According to an embodiment of the invention, the p-type semiconductor substrate base layer 209 may further comprise a blanket layer (not shown in figure 3). The blanket layer may comprise a plurality of buried dots, that can be quantum dots, of other material 25 that the semiconductor substrate, e.g. Germanium (Ge) or some type of III-V compounds. The dots may be buried below an epitaxial layer of the same material as the substrate on which the amorphous boron layer is to be deposited. The dots may increase the efficiency of the photovoltaic cell 201 for absorbing energy from light sources with relatively high wavelength, e.g. using Germanium (Ge) for Infrared (IR) light, or from light sources with 30 relatively low wavelength, e.g. using Gallium arsenide (GaAs) for Ultraviolet (UV) light. The blanket layer is formed at a relatively low temperature, e.g. below 700°C. This is due to the fact that the quantum dots are not stable above about 700°C as their material will 12 intermix with the semiconductor materials in the p-type semiconductor substrate base layer 209 at a relatively high temperature.

According to an embodiment of the invention, the semiconductor substrate base layer 209 is a silicon substrate base layer. In an alternative embodiment of the invention, 5 the semiconductor substrate base layer 209 is a germanium substrate base layer.

In Figure 4, a flow diagram of an example of a method for manufacturing a photovoltaic cell according to an embodiment as depicted in figure 3 is shown.

First, in action 301, a semiconductor substrate is provided. In an embodiment, the semiconductor substrate is a silicon (Si) substrate. In an alternative embodiment, the 10 semiconductor substrate is a germanium (Ge) substrate. The semiconductor substrate has a first surface and a second surface opposite thereto. For instance, a boron doped textured silicon wafer is provided.

Subsequently, in action 303, a n-type emitter surface is deposited and/or diffused on top of the first surface of the semiconductor substrate. For instance, this action can be 15 done by depositing a POy layer and drive-in by high-temperature diffusion of the phosphorous to ensure surface doping. The POy layer may be a phosphor glass formed from a gas containing POC13 or from sprayed H3P04, which is well known for the skilled person.

Subsequently, in action 304, the POy layer on at least the first surface is removed by 20 etching.

Subsequently, in action 305, the native oxide or POy layer on the second surface is removed. For instance, this action can be done by wet chemical etching using e.g. HF etchant.

Subsequently, in action 307, a layer of amorphous boron is deposited/formed on top 25 of the second surface in such a way that in the semiconductor substrate a layer of amorphous boron is formed and some boron is diffused into the substrate. The amorphous boron is deposited/formed at temperatures below about 700°C. An effective p+-doping of the c-Si has been demonstrated at temperatures down to 300°C, but lower temperatures should also be possible. Most experiments have been done at 500°C to 700°C. The 30 amorphous boron layer can be deposited on a silicon surface (in a process chamber) by using a silicon substrate with either: 13 • an oxygen-free silicon surface and an oxygen-free gas environment by supplying a relatively low concentration of boron-containing gas of about 1 -50 ppm; or • a silicon surface with a thin silicon-dioxide layer and an oxygen-free gas 5 environment by supplying a relatively high concentration of boron-containing gas (the supply gas being e.g. 2% B2H6 in argon or nitrogen) at a level of above about 100 ppm.. When using high concentration, a thick layer of amorphous boron is deposited and can be used to thermally drive-in boron.

It is noted that CVD processes may have a wide window of operation in which a 10 layer can be deposited. In an embodiment, the CYD process is an atmospheric process (760 Torr). Alternatively, the CVD process may be run at reduced pressure (e.g., 60 or 30 Torr).

It is noted that as will be appreciated by the skilled person, in a preferred setting of the CYD process, the growth rate of the amorphous boron layer is controlled by transport (i.e., 15 depletion) of boron-containing reactant in the gas phase.

Further, the CVD process may be an ALD (atomic layer deposition) process, or a PECVD (Plasma Enhanced CVD) or ICP-CVD (Inductive coupled plasma CVD).

Moreover, the deposition of the amorphous boron layer may be performed by evaporation. Additionally, the fabrication of the amorphous boron layer may be done in a 20 single semiconductor substrate process or a batch process for a plurality of semiconductor substrates.

Subsequently, in action 309, the first surface of the semiconductor substrate is covered by an ARC/passivation layer. For instance, this action can be done by depositing SiNx:H using Plasma-enhanced chemical vapor deposition (PECVD).

25 Finally, in action 311, the contacts on both surfaces of the semiconductor substrate are formed and/or annealed (heat-treated) at least through the ARC/passivation layer on both surfaces. For instance, this action can be done by screen printing contacts and firing these through a SiNx:H layer.

In figure 5, a flow diagram of an example of a method for manufacturing a 30 photovoltaic cell according to the embodiment as depicted in figure 2 is shown.

First, in action 401, a substrate is provided. The substrate has a first surface and a second surface opposite thereto. For instance, this action can be done by manufacturing a phosphorous doped textured silicon wafer.

14

Subsequently, in action 403, a n++-doped back surface field is deposited and/or diffused on top of the second surface of the semiconductor substrate. For instance, this action can be done by depositing a POy layer and drive-in by high-temperature diffusion of the phosphorous to ensure surface doping.

5 Subsequently, in action 404, the POy layer on the at least the second surface is removed by etching.

Subsequently, in action 405, native oxide on the first surface is removed. For instance, this action can be done by wet chemical etching using e.g. HF etchant.

Subsequently, in action 407, a layer of amorphous boron is deposited/formed on top 10 of the first surface of the silicon substrate in such a way that in said silicon substrate is effectively p+-doped. The amorphous boron is deposited at temperatures below about 700°C. Especially for the higher temperatures in this temperature range, a considerable doping of the c-Si is achieved (up to solid solubility, but in all cases/temperatures a layer that emits holes (effective p+-doping) is formed). In a process chamber, the amorphous 15 boron layer can be deposited on a silicon surface by using a silicon substrate with either: • an oxygen-free silicon surface and an oxygen free gas environment by supplying a relatively low concentration of boron-containing gas (e.g. at a concentration between 1 - 50 ppm); or • a silicon surface with a thin silicondioxide layer and an oxygen-free gas 20 environment by supplying a relatively high concentration of boron-containing gas (the supply gas being e.g. 2% B2H6 in argon or nitrogen) at a level of above about 100 ppm. .

Subsequently, in action 409, the first surface of the semiconductor substrate is covered by an ARC/passivation layer. For instance, this action can be done by 25 depositing SiNx:H or AlOx by Plasma-enhanced chemical vapor deposition (PECVD).

Subsequently, in action 410, the second surface of the semiconductor substrate is coated with an ARC/passivation layer , e.g. depositing SiNx:H by PECVD.

Finally, in action 411, the contacts on both surfaces of the semiconductor substrate are formed and/or annealed (heat-treated) at least through the ARC/passivation layer on 30 both the first and second surfaces of the semiconductor substrate (preferably not through the amorphous boron layer). For instance, this action can be done by screen printing contacts and annealing these through a SiNx:H layer on both the front side and the rear side of the photovoltaic cell.

15

It is noted that the amorphous boron layer may be deposited when applying a masking technique on a semiconductor surface to create a patterned amorphous boron layer on that semiconductor surface. In an embodiment, this allows to create p++ areas of amorphous boron on the second surface.

5 It is to be understood that the embodiments of the invention described hereinabove only show specific process flows and device structures. However, the amorphous boron layer may be used at different instances in the production process and may be applicable to other cell designs than addressed in this description.

In figure 6a, the I-V (current-voltage) characteristics of a photovoltaic cell with a 10 Schottky junction, or the I-V characteristics of a photovoltaic cell with a leaky pn- junction, or one with relatively high saturation current, is shown. In figure 6b, the I-V characteristics of a photovoltaic cell with a p-n junction, i.e. one with relatively low saturation current, is shown. In both figure 6a and 6b, the x-axis shows the current value of the photovoltaic cell and the y-axis shows the voltage value of the photovoltaic cell.

15 The I-V curve with a solid line shows the current-voltage relationship when the photovoltaic cell is in the illuminated status. The I-V curve with the dashed line shows the current-voltage relationship when the photovoltaic cell is in the dark status. The size of the shadowed rectangle area indicates the maximum output power value of the photovoltaic cell. When comparing figure 6a with figure 6b, it is observed that the I-V curve with the 20 dashed line shifts slightly from the left direction to the right direction. It implies that, in the dark status of photovoltaic cell, additional voltage source of the forward bias is needed in order to generate current. Moreover, it is observed that the size of the shadowed rectangle area depicted in figure 6b is greater than figure 6a. It implies that, in the illuminated status of photovoltaic cell, under the condition of the same current, the 25 photovoltaic cell with p-n junction has much higher voltages than the photovoltaic cell with Schottky contact, and thus generates more power. It also implies that the advantage of the boron layer by forming an effective p-n junction is of its low leakage and suppression of the surface recombination.

It is to be understood that the invention which is described above with reference to a 30 number of embodiments, is only limited by the annexed claims and its technical equivalents. In this document and in its claims, the verb "to comprise" and its conjugations are used in their non-limiting sense to mean that items following the word are included, without excluding items not specifically mentioned. In addition, reference to an element 16 by the indefinite article "a" or "an" does not exclude the possibility that more than one of the element is present, unless the context clearly requires that there be one and only one of the elements. The indefinite article "a" or "an" thus usually means "at least one".

5

Claims

A photovoltaic cell (101; 201) comprising: a semiconductor substrate (109; 209) with a first surface and a second surface; 5 an emitter layer (107; 207) disposed on the first surface of the semiconductor substrate; an anti-reflection coating (ARC) layer (105; 205) disposed on the emitter layer (107; 207); a back surface field layer (back surface field layer, BSF) (111; 211) disposed on the second surface of the semiconductor substrate; a front contact (103; 203) disposed on the emitter layer (107; 207); a rear contact (115; 215) disposed on the BSF layer (111; 211): wherein any one of the emitter layer (107) and the BSF layer (211) disposed on the first, second surface (109; 209), respectively of the semiconductor substrate is formed by an amorphous boron layer.

The photovoltaic cell (201) according to claim 1, wherein the photovoltaic cell comprises a passivation layer, and the BSF layer and the passivation layer are combined as a single BSF and passivation layer (211). 20

The photovoltaic cell of claim 2, wherein the single BSF and passivation layer (211) is formed by amorphous boron.

4. The photovoltaic cell (201) according to claim 2 or claim 3, wherein a blending layer of boron and semiconductor material is disposed between the layer of amorphous boron (211) and the semiconductor substrate layer (209) of the photovoltaic cell (201).

The photovoltaic cell (201) according to any of the preceding claims, wherein the semiconductor substrate (209) is a p-type semiconductor substrate and the emitter layer is an n-type emitter layer.

The photovoltaic cell (101) according to claim 1, wherein the emitter layer (107) is formed by the amorphous boron layer, and the emitter layer (107) is a p-type emitter layer.

The photovoltaic cell (101) according to claim 1, wherein a blending layer of boron and semiconductor material is disposed between the emitter layer (107) and the semiconductor substrate layer (109) of the photovoltaic cell (101).

The photovoltaic cell (101; 201) according to any one of the preceding claims, wherein the semiconductor substrate is a silicon substrate.

The photovoltaic cell (101; 201) according to any one of claims 1 to 7, wherein the semiconductor substrate is one selected from a germanium substrate, a silicon carbide substrate and a diamond-like substrate or layer.

The photovoltaic cell (101; 201), wherein the base layer contains one or more buried dot structures, which may be quantum dots, the dot structures being formed of Si, Ge, Si-Ge or an III-V component. 20

A method for manufacturing a photovoltaic cell, comprising: providing a p-type bulk doped semiconductor substrate with a first surface and a second opposite surface; applying and / or diffusing an n-type emitter surface to the first surface; removing natural oxide from the second surface; forming a layer of amorphous boron on the second surface in such a way that an effective p ++ layer is formed.

The method of claim 10, further comprising: covering the first surface by an ARC / passivation layer; forming contacts on both surfaces and heating them through at least the ARC / passivation layer.

The method of claim 11, wherein the amorphous drill is formed at a temperature of less than about 700 ° C.

The method of claim 11, wherein the formation temperature of the layer of amorphous boron is between about 500 ° C and about 700 ° C.

The method of claim 11, wherein the formation temperature of the layer of amorphous boron is at least 300 ° C. 10

A method for manufacturing a photovoltaic cell, comprising: providing an n-type semiconductor substrate with a first surface and a second opposite surface; applying and / or diffusing an n ++ doped rear surface field layer on the second surface of the semiconductor substrate; removing natural oxide from the first surface; forming a layer of amorphous boron on the first surface in such a way that an effective p-n junction is formed.

The method of claim 16, further comprising: covering the first surface by an ARC / passivation layer; applying contacts to both surfaces and heating them through at least the ARC / passivation layer.

The method of claim 16, wherein the layer of amorphous boron is formed at a temperature of less than about 700 ° C.

19. The method according to claim 11 or 16, wherein the semiconductor substrate is one selected from a silicon substrate, a germanium substrate, a silicon carbide substrate, and a diamond-like substrate or layer.